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An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing

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An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing Author Ivano Indino Supervisor Dr Ciaran MacNamee Submitted for the degree of Master of Engineering University of Limerick June 2017 ii Abstract An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing Ivano Indino Scan testing has been the preferred method used for testing large digital integrated circuits for many decades and many electronic design automation (EDA) tools vendors provide support for inserting scan test structures into a design as part of their tool chains. Although EDA tools have been available for many years, they are still hard to use, and setting up a design flow, which includes scan insertion is an especially difficult process. Increasingly high integration, smaller device geometries, along with the requirement for low power operation mean that scan testing has become a limiting factor in achieving time to market demands without compromising quality of the delivered product or increasing test costs. As a result, using EDA tools for power analysis of device behaviour during scan testing is an important research topic for the semiconductor industry. This thesis describes the design synthesis of the OpenPiton, open research processor, with emphasis on scan insertion, automated test pattern generation (ATPG) and gate level simulation (GLS) steps. Having reviewed scan testing theory and practice, the thesis describes the execution of each of these steps on the OpenPiton design block. Thus, by demonstrating how to apply EDA based synthesis and design for test (DFT) tools to the OpenPiton project, the thesis addresses one of the most difficult problems faced by any new user who wishes to use existing EDA tools for synthesis and scan insertion, namely, the enormous complexity of the tool chains and the huge and confusing volume of related documentation. The OpenPiton project was selected because it allows a user to implement design synthesis by simply adding standard cell library files, a good starting point for research based on scan test. Applying the design flow to a relatively small OpenPiton design block allows many overheads to be eliminated thereby making the flow easier to understand, but it is shown that the techniques can be easily migrated to larger OpenPiton design blocks including synthesis of multicore designs that can mimic today’s large commercial SOC (system on chips) for scan power issues. Additionally, in keeping with the emphasis on mitigating, the thesis shows how a design flow for the OpenPiton design block can be created using several EDA tools, with techniques to support power analysis or estimation being highlighted at various points in the flow. As a result of this work, readers should be able to set up an entire flow and reach a stage of data generation for scan power analysis in a shorter duration. This will allow engineers to focus on new approaches for scan power test mitigation and means that the re-iteration of the flow for data collection will become a much more manageable task. iii Declaration I hereby declare that this thesis is entirely my own work and does not contain material previously published by other author, except where due reference or acknowledgment has been made. Furthermore, I declare that it has not been submitted to any other university or higher education institution, or for any other academic award in this university. Signed: ________________________________________ Ivano Indino June 2017 iv Acknowledgements I would like to express my sincere gratitude to my advisor and supervisor Dr Ciaran MacNamee for the continuous support of my Masters research study, for his patience, motivation, and immense knowledge. His guidance helped me for both the time of research and the writing of this thesis. I could not have imagined having a better advisor and mentor for my Masters study. My sincere thanks also goes to Paul T. Donovan (my former Intel manager) that provided me with the opportunity to join his team allowing me to speed up my learning and gain the necessary knowledge to complete this study. I would also thank its entire team for all the support and training provided. Without their precious support it would have not been possible to conduct this research. Last but not the least, I would like to thank my family: my children for their patience and understanding throughout the writing of this thesis and my partner that believed in me. v I. Table of Contents 1 Scan testing: introduction .............................................................................................. 1 Introduction ............................................................................................................ 1 The importance of testing ........................................................................................ 1 Scope of this research ............................................................................................. 3 Motivation for this work ......................................................................................... 4 Difficulty of dealing with IP and proprietary data .................................................... 5 1.5.1 Why the need for an open-source and a mature project ..................................... 6 Outcomes, publication and conclusions ................................................................... 7 Organization of the thesis ........................................................................................ 8 2 IC Test, DFT techniques, scan testing and current research .......................................... 11 Introduction .......................................................................................................... 11 From functional test to scan testing ....................................................................... 11 Problems introduced by new technology nodes: from stuck at and at speed to a cell aware fault model ............................................................................................................ 13 Power consumption during scan testing ................................................................. 16 Design for testability techniques ........................................................................... 18 2.5.1 Ad-hoc techniques ......................................................................................... 19 2.5.2 Scan testing .................................................................................................... 20 2.5.3 BIST (built in self-test) .................................................................................. 22 Scan test architectures and application .................................................................. 23 Scan architectures ........................................................................................................ 23 2.6.1 Scan test techniques ....................................................................................... 24 2.6.2 Clock signals for scan testing ......................................................................... 26 Timing and power problems during scan testing .................................................... 29 Current research with respect to timing and power issues ...................................... 32 2.8.1 Test Power ..................................................................................................... 33 vi 2.8.2 Switching reduction schemes based on pattern generation .............................. 35 2.8.3 Schemes based on structural design elements ................................................. 36 Potential tools and methods to assess power violation issues during scan testing ... 38 Summary and conclusions ................................................................................. 40 3 Open-source project selection, synthesis and scan insertion ......................................... 43 Introduction .......................................................................................................... 43 Selecting an open-source project ........................................................................... 44 Generic synthesis and scan insertion flow using Synopsys DC .............................. 47 Standard cell libraries ............................................................................................ 52 Case study: synthesis and scan insertion Dynamic_node of OpenPiton .................. 53 3.5.1 Design compiler reference methodology ........................................................ 57 3.5.2 Alteration of the synthesis flow to add scan insertion to the design ................ 60 3.5.3 Synthesis implementation for Dynamic_node block of OpenPiton ................. 61 Conclusion ............................................................................................................ 64 4 ATPG environment setup and execution ...................................................................... 66 Introduction .......................................................................................................... 66 Scan configuration options .................................................................................... 67 Full chip ATPG vs hierarchical ATPG .................................................................. 70 Standard and low power scan patterns ................................................................... 72 The importance of fault models ............................................................................
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