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DRC Et LVS Pour La Conception Photonique Sur Sicilium Ruping Cao DRC et LVS pour la conception photonique sur sicilium Ruping Cao To cite this version: Ruping Cao. DRC et LVS pour la conception photonique sur sicilium. Autre. Université de Lyon, 2016. Français. NNT : 2016LYSEC009. tel-01499842 HAL Id: tel-01499842 https://tel.archives-ouvertes.fr/tel-01499842 Submitted on 1 Apr 2017 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. N° ordre : 2016LYSEC009 Thèse de l'Université de Lyon Délivrée par l’Ecole Centrale de Lyon Spécialité : Conception des Systèmes hétérogènes Soutenue publiquement le 25 Mars 2016 par Mme. Ruping Cao Préparée à l’Institut des Nanotechnologies de Lyon (INL) (UMR5270), Mentor Graphics Ireland Ltd French Branch DRC et LVS pour la Conception Photonique sur Silicium Ecole Doctorale Electronique, Electrotechnique, Automatique Composition du jury : Prof. Eric Cassan, Université Paris-Sud, en qualité de Président Dr. Marie-Minerve Louërat, Université Paris 6, en qualité de Rapporteur Prof. Dries Van Thourhout, Ghent University, en qualité de Rapporteur Dr. Charles Baudot, STMicroelectronics, en qualité d’Examinateur Prof. Ian O’Connor, Ecole Centrale de Lyon, en qualité de Directeur Alexandre Arriordaz, Mentor Graphics, en qualité d’Encadrant Abstract Silicon with its mature integration platform has brought electronic circuits to mass-market applications; silicon photonics will most probably follow this evolution. However, there are still many technological challenges to be addressed in order to realize silicon photonics technology. One of the key challenges is building a complete design environment interfaced with standard EDA tools; as in microelectronics, this would enable the creation of photonic libraries and photonic IP blocks. In this study, we focus on developing a physical verification (PV) flow for the silicon photonics technology. There are a number of components from the traditional CMOS IC physical verification world that can be borrowed. All, however, will require some modification due to the distinct nature of photonic circuits. We study the photonic circuit PV requirements, in comparison with those for traditional IC designs. The most significant limitation of current PV tools is to handle non- Manhattan layout designs. We adapt industrial standard PV tools to perform efficient and reliable design rule checking (DRC) that validates non-Manhattan like layout. We also propose methodologies and develop a layout versus schematic (LVS) checking flow specific to the non- Manhattan characteristics and photonic circuit verification requirements. The flow is capable of verifying photonic circuit layout implementation (or even manufactured silicon) with regard to the intended design. The developed flows are demonstrated with Mentor Graphics Pyxis design environment and Calibre® PV tool suit. As generic methodologies, they can also be in principle adopted in other EDA tool environments in order to verify the physical implementation of the photonic designs. Such a PV flow is essential for bringing the silicon photonics technology onto the real CMOS streamline. Résumé La plate-forme d'intégration silicium est arrivée à maturité, et a amené les circuits intégrés électroniques (IC) aux applications du marché de masse ; la photonique sur silicium va suivre probablement cette évolution. Pourtant, il y a encore de nombreux défis technologiques à relever pour réaliser la technologie photonique sur silicium. Parmi les principaux défis, il est essentiel de se concentrer sur la construction d'un environnement de conception complet interfacé avec les outils EDA standards ; comme dans la microélectronique, il permettrait la création de librairies photoniques et des blocs IP photoniques. Dans cette étude, nous nous concentrons sur l’adaptation et le développement du flot de vérification physique (PV, ou « physical verification ») pour la conception photonique sur silicium. Il y a un certain nombre de concepts de PV existant pour le CMOS traditionnel qui peuvent être empruntés. Tous, cependant, nécessiteront quelques modifications en raison de la nature distincte du circuit photonique. Nous étudions les exigences de PV pour les circuits photoniques, en comparaison avec celles de la conception de circuits intégrés traditionnels. La limitation la plus importante des outils de PV actuels est de traiter les layout « non-Manhattan ». Nous adaptons des outils industriels standards pour effectuer un « design rule checking » (DRC) 1 efficace et fiable qui valide les layout non-Manhattan. Nous proposons également des méthodologies et développons un flot « layout versus schematic » (LVS) spécifique aux caractéristiques non-Manhattan et aux exigences de vérification de circuits photoniques. Le flot est capable de vérifier le layout du circuit photonique (ou même le silicium fabriqué du circuit) en ce qui concerne la conception cible. Les flots développés sont démontrées avec les outils de Mentor Graphics – Pyxis (l’environnement de dessin) et Calibre® (les outils de PV). Comme les méthodologies génériques, ils peuvent aussi être en principe adoptés dans d'autres outils EDA afin d'effectuer la vérification de la réalisation de la conception du circuit photonique. Un tel flot de PV est essentiel pour amener la technologie photonique sur silicium sur la ligne de production réelle de CMOS. 2 Table of Contents Chapter 1 INTRODUCTION & BACKGROUND .................................................................. 8 1.1 Silicon Photonics ........................................................................................................ 8 1.1.1 Bringing light to the chip ...................................................................................... 8 1.1.2 Leveraging silicon platform for integrated photonics ............................................. 12 1.1.3 Challenges ahead .............................................................................................. 15 1.2 Design Tools for PIC................................................................................................. 17 1.2.1 CAD tools for photonic designs ........................................................................... 17 1.2.2 Leveraging EDA for photonic designs .................................................................. 20 1.2.3 The EDA methodology and the PDK .................................................................... 21 1.2.4 Review of current integrated design environments ................................................. 23 1.3 The PV Methodology ................................................................................................. 29 Chapter 2 PHYSICAL VERIFICATION FOR PHOTONIC DESIGNS – REQUIREMENTS AND LIMITATIONS ............................................................................................................. 32 2.1 Design Rule Checking ............................................................................................... 32 2.1.1 The non-Manhattan layout geometry .................................................................... 33 2.1.2 Curvilinear design in GDS format ........................................................................ 35 2.1.3 Dimensional measurement on snapped polygons ................................................... 35 2.1.4 DRC false error and missed error ........................................................................ 36 2.1.5 Handling advanced fabrication constraints ........................................................... 38 2.1.6 Density and fill insertion ..................................................................................... 39 2.2 Layout vs. Schematic Checking ................................................................................... 39 2.2.1 Curvilinear features in PICs ............................................................................... 41 2.2.2 Handling curvilinear data in standard layout format .............................................. 44 2.2.3 Representation of photonic device feature in standard netlist format ........................ 44 2.2.4 Representation of waveguide interconnect in standard netlist format........................ 45 2.2.5 Photonic device and connectivity definition ........................................................... 45 2.2.6 Device parameter comparison ............................................................................. 47 2.3 Design for Manufacturing .......................................................................................... 48 2.3.1 Process impact on photonic designs ..................................................................... 48 2.3.2 Lithographic checking ........................................................................................ 49 2.4 Considerations on Post-Layout Flow ........................................................................... 50 Chapter 3 DESIGN RULE CHECKING (DRC) .................................................................. 53 3.1 Solutions to DRC on Non-Manhattan Designs .............................................................. 53 3 3.1.1 Conditional
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