DOCSLIB.ORG

Synopsys Design Flow

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Synopsys Design Flow Digital IC Design Victor Grimblatt R&D Group Director © Synopsys 2012 1 SASE 2012 Agenda Introduction Electronic systems, an historic prospective Synopsys Design Flow © Synopsys 2012 2 Introduction © Synopsys 2012 3 Consumers Driving “Smart” Electronics Product Complexity / Capabilities 1980 1990 2000 2010 2020 © Synopsys 2012 4 Handset IC Market Value ($B) Mobile 100 80 60 40 20 0 2010 2011 2012 2013 2014 2015 Tablet IC Market Value ($B) 15 12 9 6 3 0 2010 2011 2012 2013 2014 2015 Source IBS, February 2011 $38B to $109B in non-memory ICs in 5 years! © Synopsys 2012 5 Microprocessor Sales Cloud Infrastructure: $80 $70 $60 $50 $40 Data, Data, Data $30 Billions $20 $10 $0 1992 1990 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012F 2014F Source: Data Center Knowledge 2011; P. Otellini, Intel, Investor Meeting 2010 Creation Transportation Global IP Traffic 1,200 Access 965.5 1,000 759.2 800 593.0 600 451.2 336.3 400 241.8 Access 200 Data IP Traffic, Exabytes 0 2010 2011F 2012F 2013F 2014F 2015F Source: Cisco Systems, VNI Global Mobile Data Traffic Forecast Update 2011 Access Data Storage 10 7.91 Manipulation Storage 8 6 4 1.8 2 0.8 1.227 0 2009 2010 2011 2012 2013 2014 2015 Source: Wikipedia, 2011; Google, Stockholder Meeting 2010 © Synopsys 2012 6 Smart Everything Grid Buildings Cars Toasters Dogs…? SW & E/E Software Lines of % Vehicle Code Cost Sensors 1970 100K <9% “Smart” Microprocessors Storage Example 1990 1M 33% Communication 2010 100M >40% © Synopsys 2012 7 Electronic Content in Systems Increases 30% 25% 20% 15% 10% Semiconductor Content Semiconductor 5% 0% Source: ST, TI, IC Insights © Synopsys 2012 8 Drivers of Innovation and Differentiation EDA + IP 2 Better Sooner Applications 3 Electronics ~$1.31T Semi $320.8B Cheaper EDA & IP $8.4B 1 Source: IC Insights, VDC Research, Synopsys Estimates © Synopsys 2012 9 What Drives the Drivers? Mobile Performance Power Cloud Power Infrastructure Performance “Smart” Power/Cost/Perf. Integration © Synopsys 2012 10 Advanced Designs and Tapeouts Source: Synopsys Global Technical Services © Synopsys 2012 11 Leading the Way at 32/28nm Design > 370 32/28nm Active Designs Source: Synopsys Global Technical Services © Synopsys 2012 12 Leading the Way at 22/20nm Design > 70 22/20nm Active Designs Source: Synopsys Global Technical Services © Synopsys 2012 13 Leading the Way at 16/14nm Design > 12 16/14nm Active Designs Source: Synopsys Global Technical Services © Synopsys 2012 14 Advanced Design Trends 56% of Respondents Currently Designing at 45nm or Below <20nm 100% 22/20nm 32/28nm 75% 45/40nm 65/55nm 90nm 50% 130nm 25% 180nm ≥250nm 0% 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 Source: 2011 Synopsys Global User Survey © Synopsys 2012 15 Advanced Design Trends Power Performance Requirements Drive Node Migrations Last Current Next 48% of “Next Designs” ≤ 32nm! “Next Design” is this Year! 35% 31% 30% 25% 20% 20% 15% 13% 13% 10% 5% 6% 5% 5% 4% 3% 0% ≥250nm 180 130 90 65/55 45/40 32/28 22/20 <20 Source: 2011 Synopsys Global User Survey © Synopsys 2012 16 Clock Frequency Trends Frequency is Increasing Over 1GHz 100% >2GHz 1-2GHz 80% 751MHz-1GHz 42% 60% 401-500MHz 301-400MHz 40% 201-300MHz 101-200MHz 20% 51-100MHz ≤50MHz 0% 2004 2005 2006 2007 2008 2009 2010 2011 Source: 2011 Synopsys Global User Survey © Synopsys 2012 17 Designs Are Growing More Complex Memory = 48% of Gate Count (on average) 30% 28% 20% 16% 13% 13% 12% 13% 12% 10% 10% 10% 9% 9% 9% 6% 7% 7% 6% 6% 6% 5% 4% 0% 1-100K 101-500K 501K-1M 1-2M 2-5M 5-10M 10-20M 20-50M 50-100M >100M Logic Memory Source: 2011 Synopsys Global User Survey © Synopsys 2012 18 Hardware/Software Development Costs Software Is Half of Time-to-Market App-Specific SW $2.50 Low-Level SW $2.00 OS Support Design Management $1.50 Post-silicon Validation Masks $M $1.00 Physical Design RTL Verification $0.50 RTL Development Spec Development $- IP Qualification 1 3 5 7 9 11 13 15 17 19 21 23 25 27 Months Source: IBS, Synopsys © Synopsys 2012 19 Electronic Systems, an Historic Prospective © Synopsys 2012 20 Key Innovations in Electronics: Audio/Video © Synopsys 2012 21 Key Innovations in Electronics: Audio/Video © Synopsys 2012 22 Key Innovations in Electronics: Audio/Video © Synopsys 2012 23 Key Innovations in Electronics: Audio/Video © Synopsys 2012 24 Key Innovations in Electronics: Audio/Video © Synopsys 2012 25 Key Innovations in Electronics: Audio/Video © Synopsys 2012 26 Key Innovations in Electronics: Audio/Video © Synopsys 2012 27 Key Innovations in Electronics: Audio/Video © Synopsys 2012 28 Key Innovations in Electronics: Audio/Video © Synopsys 2012 29 Key Innovations in Electronics: Audio/Video © Synopsys 2012 30 Key Innovations in Electronics: Audio/Video © Synopsys 2012 31 Key Innovations in Electronics: Audio/Video 2005 Sonos © Synopsys 2012 32 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 33 Going to a satellite not so far away! Apollo Guidance Computer, ~100 Microns, MIT 1961 10-3 MIPS © Synopsys 2012 34 Source: MIT, 1961 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 35 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 36 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 37 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 38 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 39 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 40 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 41 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 42 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 43 Key Innovations in Semiconductors © Synopsys 2012 44 Key Innovations in Semiconductors © Synopsys 2012 45 Once Upon a Time … April, 1961 first integrated circuit developed by Robert Noyce, from Fairchild Semiconductor © Synopsys 2012 46 Key Innovations in Semiconductors © Synopsys 2012 47 Key Innovations in Semiconductors © Synopsys 2012 48 Key Innovations in Semiconductors © Synopsys 2012 49 A Big Event … 4004, 10 Microns, Intel 1971 10-1 MIPS © Synopsys 2012 50 Source: 4004, Intel, 1971 Key Innovations in Semiconductors © Synopsys 2012 51 A 10,000X Improvement, Thanks To… “A Computer Code Entitled SCALD […] Speeds the Job” © Synopsys 2012 52 Source: Lawrence Livermore National Laboratory, Newsline, January 10th, 1979 Key Innovations in Semiconductors © Synopsys 2012 53 1961-1981, A 10,000X Improvement… S-1 Supercomputer, ~3 Microns, LLNL 1981 10 MIPS © Synopsys 2012 54 Source: Lawrence Livermore National Laboratory, 1983 Time Flies Away … DEC Alpha 21064, 64bits, 750 nm CMOS, 200Mhz 1991 300 DMIPS © Synopsys 2012 55 Source: Wikimedia Commons; Courtesy of A. Domic Key Innovations in Semiconductors © Synopsys 2012 56 Key Innovations in Semiconductors © Synopsys 2012 57 Key Innovations in Semiconductors © Synopsys 2012 58 Another Time Stamp … Itanium, 180 Nanometers, Intel 2001 ~25 GOPS © Synopsys 2012 59 Source: Intel, 2001 Key Innovations in Semiconductors © Synopsys 2012 60 1961-2011, A 100,000,000X Improvement… Ivy Bridge, 22 Nanometers, Intel 2011 100 GOPS ~160mm2, 1.4B transistors, 2.5-4GHz, 45-80W © Synopsys 2012 61 Source: M. Bohr, Intel, IDF 2011; S. Siers, Intel, ISSCC 2012; Sandra 2011 The Wireless Side in 2011: ST AP9540 CSI • Application processor for smart phones and tablets SGX544 SIA – Dual ARM Cortex A9 Periph3 @ 1.85GHz MMDSP C2C – Imagination GPU SGX544 @ 500MHz DDR CTRL0 – Dual 32 bits LPDDR2 PHY @ 533MHz DSS MCDE DDR0 • 32nm technology – 10 metal layers MMDSP • Advanced power A9 management HVA SVA – 10+ switchable power G1 Periph1 domains with multi- DDR CTRL1 voltage/multi-supply Periph2 scenarios DDR1 PHY © Synopsys 2012 62 62 Gordon E. Moore’s Law Twice the Number of Transistors for the Same Price, Every Two Years 0.5 = ~0.7 The Scaling Factor Area = 1 “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year ... Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit Area = 0.5 more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years.” Gordon E. Moore, Electronic Magazine, April 19th, 1965 © Synopsys 2012 63 Ley de Moore 16 15 14 13 12 11 10 9 8 7 6 OF THE OF NUMBER OF 2 5 4 LOG 3 2 1 COMPONENTSPER INTEGRATED FUNCTION 0 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 http://download.intel.com/museum/Moores_Law/Articles- Press_releases/Gordon_Moore_1965_Article.pdf Fuente: Electronics, 19 Abril, 1965 © Synopsys 2012 64 Wafer 1” – 1959 © Synopsys 2012 65 Wafer 300 mm © Synopsys 2012 66 Proyecciones para el 2000 en 1975 Moore no siempre tuvo razón © Synopsys 2012 67 Design - Layout © Synopsys 2012 68 EDA Back Then… CALMAGRAPHIC, Calma © Synopsys 2012 69 Source: D.E. Weisberg, The Engineering Design Revolution, 2008 (www.cadhistory.net) Design - Layout © Synopsys 2012 70 1970 – From Manual Layout to Manufacturing 33 MB Disk Plotter Digitizing Keyboard, Tablet Mainframe-500 lbs Table/Tablet and CRT 128k; 8-16 bit • Applicon- PCB & IC Digitizing, CAM* Mag Tape-Output • ComputerVision- Wiring, Mapping, Documentation, PCB • David Mann output for IC masks • Gerber for PCB artwork The Age of Photo-Mask Generation • Autotrol for digitizing the Gods SENSES * Computer Aided Manufacturing © Synopsys 2012 71 Design - Layout © Synopsys 2012 72 Basic Early CAD Applications Gridded
Load more

Recommended publications
  • An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing
    An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing Author Ivano Indino Supervisor Dr Ciaran MacNamee Submitted for the degree of Master of Engineering University of Limerick June 2017 ii Abstract An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing Ivano Indino Scan testing has been the preferred method used for testing large digital integrated circuits for many decades and many electronic design automation (EDA) tools vendors provide support for inserting scan test structures into a design as part of their tool chains. Although EDA tools have been available for many years, they are still hard to use, and setting up a design flow, which includes scan insertion is an especially difficult process. Increasingly high integration, smaller device geometries, along with the requirement for low power operation mean that scan testing has become a limiting factor in achieving time to market demands without compromising quality of the delivered product or increasing test costs. As a result, using EDA tools for power analysis of device behaviour during scan testing is an important research topic for the semiconductor industry. This thesis describes the design synthesis of the OpenPiton, open research processor, with emphasis on scan insertion, automated test pattern generation (ATPG) and gate level simulation (GLS) steps. Having reviewed scan testing theory and practice, the thesis describes the execution of each of these steps on the OpenPiton design block. Thus, by demonstrating how to apply EDA based synthesis and design for test (DFT) tools to the OpenPiton project, the thesis addresses one of the most difficult problems faced by any new user who wishes to use existing EDA tools for synthesis and scan insertion, namely, the enormous complexity of the tool chains and the huge and confusing volume of related documentation.
    [Show full text]
  • Package Designers Need Assembly-Level Lvs for Hdap Verification
    PACKAGE DESIGNERS NEED ASSEMBLY-LEVEL LVS FOR HDAP VERIFICATION TAREK RAMADAN MENTOR, A SIEMENS BUSINESS DESIGN TO SILICON WHITEPAPER www.mentor.com Package designers need assembly-level LVS for HDAP verification INTRODUCTION Contrary to what you might think, advanced integrated circuit (IC) packaging is real. Several leading foundries and outsourced assembly and test (OSAT) companies already offer high density advanced packaging (HDAP) services to their customers. The most common approaches currently offered by foundries/OSATs are the 2.5D-IC (interposer-based) style and fan-out wafer- level packaging (FO-WLP) approach (single die or multi die), as shown in Figure 1. Figure 1: The most common package styles currently in use are the 2.5D-IC and the FO-WLP. Because the interposer in a 2.5D-IC is similar to a traditional die (except that it doesn’t include active devices), IC design groups usually owns the 2.5D-IC design, which requires an IC-oriented design approach (Manhattan shapes in the layout database, SPICE/Verilog as the source netlist, etc.). In FO-WLP, IC package groups usually adopt design approaches that are based on spreadsheets (to capture the design intent), in-design manufacturing checks, and (traditionally) no automated layout vs .schematic (LVS) signoff. Automated LVS is not historically popular in the packaging world because the number of components and required I/Os is usually small, so a simple spreadsheet or bonding diagram is sufficient for an eyeball check. However, as HDAP evolves and its use expands, the need for an automated LVS-like flow to detect and highlight package connectivity errors has become apparent.
    [Show full text]
  • Introduction to Electronic Design Automation
    Design Automation? Introduction to Electronic Design Automation Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Spring 2013 1 2 Course Info (1/4) Course Info (2/4) Instructor Grading rules (raw score) Jie-Hong R. Jiang Homework 40% email: [email protected] Midterm 25% office: 242, EE2 Building Final Quiz 10% phone: (02)3366-3685 Project 25% office hour: 15:00-17:00 Fridays (Note that the final grade is based on grading on a curve.) TA Po-Ya Hsu Homework email: [email protected] discussions encouraged, but solutions should be written down individually and separately phone: (02)3366-3700 ext 6406 4 assignments in total office: 406, BL Hall late homework (20% off per day) office hour: 13:00-15:00 Mondays Midterm exam/final quiz in-class exam Email contact list NTU email addresses of enrolled students will be used for future contact Project Team or individual work on selected topics (CAD Contest problems / paper reading / Course webpage implementation / problem solving, etc.) http://cc.ee.ntu.edu.tw/~jhjiang/instruction/courses/spring13-eda/eda.html please look up the webpage frequently to keep updated Academic integrity: no plagiarism allowed 3 4 Course Info (3/4) Course Info (4/4) Prerequisite Objectives: Switching circuits and logic design, or by instructor’s consent Peep into EDA Main lecture basis Motivate interest Lecture slides and/or handouts Learn problem formulation and solving Textbook Have fun! Y.-W. Chang, K.-T. Cheng, and L.-T. Wang (Editors). Electronic Design Automation: Synthesis, Verification, and Test.
    [Show full text]
  • Cell Design Tutorial
    Cell Design Tutorial Cell Design Tutorial Product Version 4.4.6 June 2000 1990-2000 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 1-800-862-4522. All other trademarks are the property of their respective holders. Restricted Print Permission: This publication is protected by copyright and any unauthorized use of this publication may violate copyright, trademark, and other laws. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. This statement grants you permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used solely for personal, informational, and noncommercial purposes; 2. The publication may not be modified in any way; 3. Any copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement; and 4. Cadence reserves the right to revoke this authorization at any time, and any such use shall be discontinued immediately upon written notice from Cadence. Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence.
    [Show full text]
  • Asic Synthesis and Backend
    Getting to Work with OpenPiton Princeton University http://openpiton.org OpenPit ASIC SYNTHESIS AND BACKEND 2 Whats in the Box? • Synthesis – Synopsys Design Compiler • Static timing analysis (STA) – Synopsys Primetime • Formal equivalence checking (RVS) – Synopsys Formality • Place and route (PAR) – Synopsys IC Compiler • Layout versus schematic (LVS) – Mentor Graphics Calibre • Design rule checking (DRC) – Mentor Graphics Calibre • Coming soon: Gate-level simulation 3 Why is it Useful? • Research studies – Architecture, EDA, and other HW research • ASIC tapeout • Education 4 Piton ASIC • 25 tiles • Tested working in • IBM 32nm SOI silicon! • 36 mm2 (6mm x 6mm) • 1 GHz Target Frequency 5 Synthesis and Backend Flow 6 What do you need? • OpenPiton • Synopsys License – Tools and Reference Methodology (RM) • Mentor Graphics License – Calibre (for LVS and DRC only) • Standard cell library and process development kit 7 Getting Started • Download Synopsys-RM • Patch Synopsys-RM • Familiarize with directory structure and scripts • Port to process technology • Running the flow 8 Download Synopsys-RM • Synopsys Solvnet • See OpenPiton Synthesis and Backend Manual – Specify version – Specify settings • Broader support 9 Patching Synopsys-RM 10 Patching Synopsys-RM 10 Patching Synopsys-RM 10 Patching Synopsys-RM 10 Patching Synopsys-RM 11 Patching Synopsys-RM 11 Patching Synopsys-RM 11 Patching Synopsys-RM 11 Directory Structure and Scripts • All scripts written in Tcl • Two primary locations – Module generic scripts – Module specific scripts 12
    [Show full text]
  • DRC Et LVS Pour La Conception Photonique Sur Sicilium Ruping Cao
    DRC et LVS pour la conception photonique sur sicilium Ruping Cao To cite this version: Ruping Cao. DRC et LVS pour la conception photonique sur sicilium. Autre. Université de Lyon, 2016. Français. NNT : 2016LYSEC009. tel-01499842 HAL Id: tel-01499842 https://tel.archives-ouvertes.fr/tel-01499842 Submitted on 1 Apr 2017 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. N° ordre : 2016LYSEC009 Thèse de l'Université de Lyon Délivrée par l’Ecole Centrale de Lyon Spécialité : Conception des Systèmes hétérogènes Soutenue publiquement le 25 Mars 2016 par Mme. Ruping Cao Préparée à l’Institut des Nanotechnologies de Lyon (INL) (UMR5270), Mentor Graphics Ireland Ltd French Branch DRC et LVS pour la Conception Photonique sur Silicium Ecole Doctorale Electronique, Electrotechnique, Automatique Composition du jury : Prof. Eric Cassan, Université Paris-Sud, en qualité de Président Dr. Marie-Minerve Louërat, Université Paris 6, en qualité de Rapporteur Prof. Dries Van Thourhout, Ghent University, en qualité de Rapporteur Dr. Charles Baudot, STMicroelectronics, en qualité d’Examinateur Prof. Ian O’Connor, Ecole Centrale de Lyon, en qualité de Directeur Alexandre Arriordaz, Mentor Graphics, en qualité d’Encadrant Abstract Silicon with its mature integration platform has brought electronic circuits to mass-market applications; silicon photonics will most probably follow this evolution.
    [Show full text]
  • C 2011 Yuelin Du CHARACTERIZATION of the PERFORMANCE VARIATION for REGULAR STANDARD CELLS with PROCESS NON-IDEALITIES
    c 2011 Yuelin Du CHARACTERIZATION OF THE PERFORMANCE VARIATION FOR REGULAR STANDARD CELLS WITH PROCESS NON-IDEALITIES BY YUELIN DU THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical and Computer Engineering in the Graduate College of the University of Illinois at Urbana-Champaign, 2011 Urbana, Illinois Adviser: Professor Martin D. F. Wong ABSTRACT In IC manufacturing, the performance of standard cells often varies due to process non-idealities. Some research work on 2-D cell characterization shows that the timing variations can be characterized by the timing model. How- ever, as regular design rules become necessary in sub-45 nm node circuit design, 1-D design has shown its advantages and has drawn intensive re- search interest. The circuit performance of a 1-D standard cell can be more accurately predicted than that of a 2-D standard cell as it is insensitive to layout context. This thesis presents a characterization methodology to pre- dict the delay and power performance of 1-D standard cells. We perform lithography simulation on the poly gate array generated by dense line print- ing technology, which constructs the poly gates of inverters, and do statistical analysis on the data simulated within the process window. After that, circuit simulation is performed on the printed cell to obtain its delay and power per- formance, and the delay and power distribution curves are generated, which accurately predict the circuit performance of standard cells. In the end, the benefits of our cell characterization method are analyzed from both design and manufacturing perspectives, which shows great advantages in accurate circuit analysis and improving yield.
    [Show full text]
  • A Metamodel and Model-Based Design Rule Checking DSL for Verification and Validation of Electronic Circuit Designs
    A Metamodel and Model-based Design Rule Checking DSL for Verification and Validation of Electronic Circuit Designs Adrian Rumpold and Bernhard Bauer Institute of Computer Science, University of Augsburg, Germany Keywords: Domain-specific Modeling, Model-based Analysis, Model-based Testing and Validation, Systems Engineering, Electronic Design Automation, Design Rule Checking. Abstract: Development of embedded systems depends on both software and hardware design activities. Quality management of development artifacts is of crucial importance for the overall function and safety of the final product. This paper introduces a metamodel and model-based approach and accompanying domain-specific language for validation of electronic circuit designs. The solution does not depend on any particular electronic design automation (EDA) software, instead we propose a workflow that is integrated into a modular, general-purpose model analysis framework. The paper illustrates both the underlying concepts as well as possible application scenarios for the developed validation domain-specific language, MBDRC (Model-Based Design Rule Checking). It also discusses fields for further research and transfer of the initial results. 1 INTRODUCTION of a manual workflow within the software package — mostly only available as non free, proprietary Embedded hardware and computing have become software with the risk of vendor lock-in. pervasive aspects of modern technology, which This paper proposes a model-based solution to we encounter under a variety of different names: the
    [Show full text]
  • LVS Check for Photonic Integrated Circuits – Curvilinear Feature
    LVS Check for Photonic Integrated Circuits – Curvilinear Feature Extraction and Validation Ruping Cao∗, Julien Billoudet∗, John Ferguson∗, Lionel Couder∗, John Cayo∗, Alexandre Arriordaz∗, Ian O’Connor† ∗Mentor Graphics Corp. †Lyon Institute of Nanotechnology, Ecole´ Centrale de Lyon Abstract—This work is motivated by the demand of an II. LVS ON PHOTONIC DESIGNS electronic design automation (EDA) approach for the emerging ecosystem of the photonic integrated circuit (PIC) technology. A After a PIC layout passes through DRC, where physical reliable physical verification flow cannot be achieved without the manufacturability is checked against a set of design rules, it is adaption of the traditional EDA tools to the photonic design sent for LVS checking to determine if the circuit behaves as verification needs. We analyze how layout versus schematic desired – whether a layout implementation of a circuit matches (LVS) checking is performed differently for photonic designs, and propose an LVS flow that addresses the particular need the original schematic design. As part of the LVS job, electrical of curvilinear feature validation (curved path length and bend rule checking (ERC) searches for faulty or dangerous electrical curvature extraction). We show that it is possible to reuse and connections. An LVS check on photonic designs is mandatory extend the current LVS tools to perform such critical but non- for the same purpose. However, a dedicated LVS methodology traditional checks, which ensures a more reliable photonic layout is required due to the different verification requirement. implementation in term of functionality and circuit yield. Going forward, we propose possible future studies that can further improve the flows.
    [Show full text]
  • The Design of Standard Cell VLSI Circuits
    University of Central Florida STARS Retrospective Theses and Dissertations 1984 The Design of Standard Cell VLSI Circuits Randolph L. Abidin University of Central Florida Part of the Engineering Commons Find similar works at: https://stars.library.ucf.edu/rtd University of Central Florida Libraries http://library.ucf.edu This Masters Thesis (Open Access) is brought to you for free and open access by STARS. It has been accepted for inclusion in Retrospective Theses and Dissertations by an authorized administrator of STARS. For more information, please contact [email protected]. STARS Citation Abidin, Randolph L., "The Design of Standard Cell VLSI Circuits" (1984). Retrospective Theses and Dissertations. 4704. https://stars.library.ucf.edu/rtd/4704 THE DESIGN OF STANDARD CELL VLSI CIRCUITS BY RANDOLPH L. ABIDIN B.S., Stevens Institute of Technology, 1980 RESEARCH REPORT Submitted in partial fulfillment of the requirements for the degree. of Master of Science in the Graduate studies Program of the College of Engineering university of Central Florida Orlando, Florida Summer Term 1984 ABSTRACT There are basically three methods of designing very Large Scale Integrated (VLSI) circuits; Gate Array, Standard Cell, and Full Custom. The objective of this research is to design a VLSI circuit using the Standard Cell approach. A prime requisite for a successful design of these circuits is an integrated Computer Aided Design (CAD) system. The chip design requirements for an integrated CAD system are developed and their interrelationships are presented. As VLSI circuits grow in complexity, the problem of how to test them becomes more difficult. Two methods for testing are defined: 1.
    [Show full text]
  • Converging Photonics with EDA Approach: Validation of Layout
    ThP4 (Contributed) 17:30 - 18:30 Photonics Design with an EDA approach: Validation of Layout Waveguide Interconnects R. Cao∗, H. Hu∗, J. Ferguson∗, F. Pikus∗, J. Cayo∗, A. Arriordaz∗, E. Cassany, W. Bogaertsz, I. O’Connorx ∗Mentor Graphics Corp. yInstitute of Fundamental Electronics, Universite´ Paris-Sud zPhotonics Research Group, Ghent University – imec, Department of Information Technology xLyon Institute of Nanotechnology, Ecole´ Centrale de Lyon Abstract—This work demonstrates the use of commercial EDA resistance and capacitance extraction. However, waveguide toolsets for the measurement and validation of the layout of interconnect validation differs in two respects: 1)earlier flow waveguide interconnects and the integration into a dedicated integration is required, because the geometrical parameters silicon photonics physical design flow. of a waveguide interconnect must be considered to be not Tremendous progress has been made on development of only simulation parameters for the post-layout analysis of silicon photonics building blocks, but the next challenge will parasitic side effects, but must also be validated to avoid fatal be the realization of more complex systems that include many circuit failure, 2) a different extraction methodology must be devices and are integrated within complex CMOS mixed employed, due to the lack of existing algorithms for curvilinear electro-optical circuits [1] [2]. Seamless integration of pho- parameter computation. tonic integrated circuit (PIC) technology into existing silicon platforms requires a design flow that is compatible with current I. METHODOLOGY electronic design automation (EDA) tool suites. However, due A. Waveguide Interconnect Parameter Validation to differences in the physics between photonic and electronic As layout waveguide interconnect geometry must be val- circuits, a dedicated methodology for PIC design automa- idated for human errors that easily lead to optical signal tion must be developed to enable technology integration.
    [Show full text]
  • Introduction to Electronic Design Automation (EDA)
    901/33700 Introduction to Electronic Design Automation (EDA) 張耀文 原著 Yao-Wen Chang [email protected] http://cc.ee.ntu.edu.tw/~ywchang Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taipei 106, Taiwan Unit 1 1 NTUEE / Intro. EDA Administrative Matters ․Time/Location: Tuesday 2:20-5:20pm; EE-II 104 ․Instructor: Yao-Wen Chang, Chung-Yang Huang, Chien-Mo Li ․E-mail: {ywchang, ric, cmli}@cc.ee.ntu.edu.tw ․URL: http://cc.ee.ntu.edu.tw/~eda/Course/IntroEDA06 ․Office: BL-428; EE-II 444; EE-II 339 ․Office Hours: Contact Instructors ․Teaching Assistants ⎯ TBD ․Prerequisites: Computer Programming & logic design. ․Required Text: S. H. Gerez, Algorithms for VLSI Design Automation, John Wiley & Sons, 1999. ․References: Cormen, Leiserson, and Rivest, Introduction to Algorithms, 2nd Ed., McGraw Hill/MIT Press, 2001. ⎯ Other supplementary reading materials will be provided. Unit 1 2 NTUEE / Intro. EDA Course Objectives ․Study techniques for electronic design automation (EDA), a.k.a. computer-aided design (CAD). ․Study IC technology evolution and their impacts on the development of EDA tools ․Study problem-solving (-finding) techniques!!! S1 S2 S3 S4 S5 P1 P2 P3 P4 P5 P6 Unit 1 3 NTUEE / Intro. EDA Course Contents ․Introduction to VLSI design flow/styles/automation, technology roadmap, and CMOS Technology ․Algorithmic graph theory ․Computational Complexity and Optimization ․Physical design: partitioning, floorplanning, placement, routing, compaction, deep submicron effects ․Logic synthesis and verification ․(High Level Synthesis) ․Simulation ․Testing Unit 1 4 NTUEE / Intro. EDA Grading Policy ․Grading Policy: ⎯ Homework assignments : 25% ⎯ Midterm Exam :20% ⎯ Programming assignment: 25% ⎯ Final Exam: 30% ․Homework: 50% per day late penalty ⎯ Due dates on web ․Academic Honesty: Avoiding cheating at all cost.
    [Show full text]