Synopsys Design Flow

Digital IC Design

Victor Grimblatt R&D Group Director

Introduction

Electronic systems, an historic prospective

Synopsys Design Flow

Consumers Driving “Smart” Electronics

Product Complexity / Capabilities

1980 1990 2000 2010 2020

Tablet IC Market Value ($B) 15 12 9 6 3 0 2010 2011 2012 2013 2014 2015

Source IBS, February 2011

$38B to $109B in non-memory ICs in 5 years!

$70 $60 $50 $40 Data, Data, Data $30 Billions $20 $10

1992 1990 1994 1996 1998 2000 2002 2004 2006 2008 2010

2012F 2014F

Source: Data Center Knowledge 2011; P. Otellini, Intel, Investor Meeting 2010 Creation Transportation

Global IP Traffic

1,200 Access 965.5 1,000 759.2 800 593.0 600 451.2 336.3 400 241.8 Access 200 Data IP Traffic,Exabytes 0 2010 2011F 2012F 2013F 2014F 2015F Source: Cisco Systems, VNI Global Mobile Data Traffic Forecast Update 2011

Access Data Storage 10 7.91 Manipulation Storage 8 6 4 1.8 2 0.8 1.227 0 2009 2010 2011 2012 2013 2014 2015 Source: Wikipedia, 2011; Google, Stockholder Meeting 2010

Grid Buildings Cars Toasters Dogs…?

SW & E/E Software Lines of % Vehicle Code Cost

Sensors

1970 100K <9% “Smart” Microprocessors

Storage Example 1990 1M 33%

Communication 2010 100M >40%

30%

25%

20%

15%

10%

Semiconductor Content Semiconductor 5%

Source: ST, TI, IC Insights

2 Better Sooner Applications 3 Electronics ~$1.31T Semi $320.8B

Cheaper EDA & IP $8.4B

1 Source: IC Insights, VDC Research, Synopsys Estimates

Mobile Performance

Power

Cloud Power Infrastructure

Performance

“Smart” Power/Cost/Perf.

Integration

Source: Synopsys Global Technical Services

> 370 32/28nm Active Designs

Source: Synopsys Global Technical Services

> 70 22/20nm Active Designs

Source: Synopsys Global Technical Services

> 12 16/14nm Active Designs

Source: Synopsys Global Technical Services

56% of Respondents Currently Designing at 45nm or Below

<20nm 100% 22/20nm 32/28nm

75% 45/40nm 65/55nm 90nm 50% 130nm

25% 180nm

≥250nm 0% 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 Source: 2011 Synopsys Global User Survey

Power Performance Requirements Drive Node Migrations

Last Current Next 48% of “Next Designs” ≤ 32nm! “Next Design” is this Year! 35% 31% 30%

25% 20% 20%

15% 13% 13%

10% 5% 6% 5% 5% 4% 3%

0% ≥250nm 180 130 90 65/55 45/40 32/28 22/20 <20 Source: 2011 Synopsys Global User Survey

Frequency is Increasing Over 1GHz

100% >2GHz 1-2GHz

80% 751MHz-1GHz 42%

60% 401-500MHz 301-400MHz

40% 201-300MHz

101-200MHz 20% 51-100MHz ≤50MHz 0% 2004 2005 2006 2007 2008 2009 2010 2011 Source: 2011 Synopsys Global User Survey

Memory = 48% of Gate Count (on average)

30% 28%

20% 16%

13% 13% 12% 13% 12% 10% 10% 10% 9% 9% 9% 6% 7% 7% 6% 6% 6% 5% 4%

0% 1-100K 101-500K 501K-1M 1-2M 2-5M 5-10M 10-20M 20-50M 50-100M >100M

Logic Memory Source: 2011 Synopsys Global User Survey

Software Is Half of Time-to-Market

App-Specific SW $2.50 Low-Level SW $2.00 OS Support Design Management

$1.50 Post-silicon Validation

Masks $M $1.00 Physical Design RTL Verification $0.50 RTL Development Spec Development $- IP Qualification 1 3 5 7 9 11 13 15 17 19 21 23 25 27 Months

Source: IBS, Synopsys

2005 Sonos

1961 10-3 MIPS

April, 1961 first integrated circuit developed by Robert Noyce, from Fairchild Semiconductor

1971 10-1 MIPS

1981 10 MIPS

1991 300 DMIPS

2001 ~25 GOPS

2011  100 GOPS

~160mm2, 1.4B transistors, 2.5-4GHz, 45-80W

CSI • Application processor for

smart phones and tablets SGX544 SIA

– Dual ARM Cortex A9 Periph3 @ 1.85GHz MMDSP C2C – Imagination GPU SGX544 @ 500MHz DDR

CTRL0

– Dual 32 bits LPDDR2 PHY

@ 533MHz DSS

MCDE DDR0 • 32nm technology – 10 metal layers MMDSP

• Advanced power A9

management HVA SVA

– 10+ switchable power G1 Periph1 domains with multi- DDR CTRL1

voltage/multi-supply Periph2 scenarios DDR1 PHY

 0.5 = ~0.7

The Scaling Factor Area = 1

“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year ... Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit Area = 0.5 more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years.” Gordon E. Moore, Electronic Magazine, April 19th, 1965

16 15 14 13 12 11 10 9 8 7

6 OF THEOF NUMBER OF

2 5 4 LOG 3 2 1

COMPONENTSPER INTEGRATED FUNCTION 0

1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 http://download.intel.com/museum/Moores_Law/Articles- Press_releases/Gordon_Moore_1965_Article.pdf

Fuente: Electronics, 19 Abril, 1965

Moore no siempre tuvo razón

33 MB Disk

Plotter

Digitizing Keyboard, Tablet Mainframe-500 lbs Table/Tablet and CRT 128k; 8-16 bit

• Applicon- PCB & IC Digitizing, CAM* Mag Tape-Output • ComputerVision- Wiring, Mapping, Documentation, PCB • David Mann output for IC masks • Gerber for PCB artwork The Age of Photo-Mask Generation • Autotrol for digitizing the Gods SENSES

* Computer Aided Manufacturing

Gridded Artwork Pencil IC/PCB Primitive for Manufacturing Layouts Database

Schematic Card Deck from Simulation Keypunch 01110010 00011001 10010110 00011001 01110010 Analog

Source: GE Avionics, 1968 © Synopsys 2012 74 Technology Or… Art?

Source: Intel & MoMA, 1974 © Synopsys 2012 75 Design - Synthesis

1980s VHDL & Hardware

Verilog Emulation Logic Flex

Synthesis Cathedral Ptolemy Mead & DRC Podem X

Conway & LVS Scan Test Dracula Framework Interconnect modeling BBL & Timberwolf BDD

Commercial System, Place & Industry Layout Route Logic Synthesis High-Level Multi Verilog Design DRC/LVS Discipline Innovators

Design: specify and enter the design intent

Verify: verify the correctness of Implement: refine the design design and implementation through all phases

• Bottom – up – Start from simple modules – Goes to complex modules – Suitable to create small parts that will be reused • Top – down – Start from complex modules – Goes to simple modules – Suitable for big systems

Complex system

Module (one function) Bottom – up Top – down Register and gates

Transistors

process begin Architecture wait until not CLOCK'stable and CLOCK=1; if(ENABLE='1') then TOGGLE<= not TOGGLE; Front End end if; end process; RTL Design/Logic Functional Synthesis Verification

Design Physical Design Integrity

Back End

Fabrication

Architecture: • Key Algorithms (filtering, for example) • Amount of on-chip Memories, sizes? • How many Integer Proc Units? RTL: Register Transfer Language • Verilog (1988), VHDL, SystemVerilog: an executable spec for the chip, amounting to over a million lines of code • Lots of simulations to verify the spec (literally billions of cycles) • Timing constraints, clock definitions, etc

Logic Design: convert the RTL to logic gates (NAND-NORs, NOTs, Registers) • A manual process in the past, still mostly manual for Analog • Logic Synthesis (1989): automate the process • Many discrete optimization techniques used here: boolean minimization, static timing analysis, state equivalence, etc, etc. • End point is a “netlist”, meaning a set of logic gates and their connections. A large netlist is in the 10s of millions of gates • Can be simulated or “formally verified” versus the RTL. • Key technique: how do you prove that two logic equations are equivalent?

Floorplanning • Where do we place the large blocks? Where do we place the “random” logic and “structured blocks”? A combination of manual and automated approaches is used • Need to keep connections short to meet timing, but also cannot “congest” the design too much or we cannot complete the connections • Note that connections do have R and C (to substrate and coupling between wires) so they introduce delay! Meeting timing can be very difficult! • The Power and Ground lines usually get decided here

Placement: • Now we need to complete the exact details of where each block and gate will be • Automation has been a key for many years (1980). A block may contain hundreds of thousands of cells, so it is very hard problem: minimize area, be routable and meet timing • Note may have to add logic: repeaters to restore signals a key example

Routing • Complete all the connections! • But, need to meet timing and keep signal integrity. This also involve separating some wires, for example, to avoid bad couplings • Automation is the norm here (1980) Verification: • Spacing and sizing rules are checked for all polygons (1980) • Parasitics are extracted, netlists back annotated and time analyzed using static techniques (1990) • Manufacturing requires complicated rules, such as wire density been “uniform”

Sounds simple, but have a host of very hard problems to solve!

Mask fabrication

Wafer fabrication

Wafer testing

Assembly and packaging

IC test

…the steps you take to design a chip! Blah blah blah yadaBlah yada blah blah Blah blah blah yadaBlah yada blah blah yidieBlah yadie blah blah So on and soyada forth yada yidieBlah yadie blah blah Soon onand and on so forth Jibber jabberyidie jibber yadie Soon onand and on so forth Jibberjust jawing jabber jibber Yackety yackon and on Specification just jawing Ya'll comJibber back jabber jibber Yacketyjust yack jawing System Ya'll com back Yackety yack Ya'll com back Technology Analysis Module Compiler Process System Studio Select Logic Modeling Architecture Scripts

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Design Compiler RTL Verification Power Compiler Synthesis VCS-MX DFT Compiler Links-to- Physical Compiler Design Planning Layout VCS-MX JupiterXT Magellan Design Formality Gate-level ATPG Constraints PrimeTime netlist PrimePower TetraMAX Gate-level verification Physical Compiler Mask Writer Post-Route Astro Place & Route CATS Verification Blah blah blah yadaBlah yada blah blah Blah blah blah Proteus yadaBlah yada blah blah yidieBlah yadie blah blah So on and soyada forth yada PrimeTime yidieBlah yadie blah blah Soon onand and on so forth Jibber jabberyidie jibber yadie Soon onand and on so forth Physical Design Physical Data Jibberjust jawing jabber jibber STAR-RCXT Yackety yackon and on NanoSim Jibberjust jawing jabber jibber GDSII Ya'll com back Yacketyjust yack jawing Creation Ya'll comYackety back yack HSPICE Hercules Checks Ya'll com back © Synopsys 2012 98 Design Implementation

Blah blah blah yadaBlah yada blah blah Blah blah blah yadaBlah yada blah blah yidieBlah yadie blah blah So on and soyada forth yada yidieBlah yadie blah blah Soon onand and on so forth Jibber jabberyidie jibber yadie Soon onand and on so forth Jibberjust jawing jabber jibber Yackety yackon and on Specification just jawing Ya'll comJibber back jabber jibber Yacketyjust yack jawing System Ya'll com back Yackety yack Ya'll com back Technology Analysis Module Compiler Process System Studio Select Logic Modeling Architecture Scripts

Design Compiler RTL Verification Power Compiler Synthesis VCS-MX DFT Compiler Verification Links-to- Physical Compiler Design Planning Layout VCS-MX JupiterXT Magellan Design Formality Gate-level ATPG Constraints PrimeTime netlist PrimePower TetraMAX Gate-level Design for Manufacturing verification Physical Compiler Mask Writer Post-Route Astro Place & Route CATS Verification Blah blah blah yadaBlah yada blah blah Blah blah blah Proteus yadaBlah yada blah blah yidieBlah yadie blah blah So on and soyada forth yada PrimeTime yidieBlah yadie blah blah Soon onand and on so forth Jibber jabberyidie jibber yadie Soon onand and on so forth Physical Design Physical Data Jibberjust jawing jabber jibber STAR-RCXT Yackety yackon and on NanoSim Jibberjust jawing jabber jibber GDSII Ya'll com back Yacketyjust yack jawing Creation Ya'll comYackety back yack HSPICE Hercules Checks Ya'll com back © Synopsys 2012 99 Systems

System Design

SoC Verification IP Implementation

Manufacturing Silicon

Architectural choices, RTL compilation and simulation (VCS)

Logic synthesis (Design Compiler)

Formal verification (Formality)

Generation of test patterns (TetraMAX)

Physical design (IC Compiler)

Physical verification (Hercules)

Layout parasitics extraction (StarRC)

SPICE level simulation of completed design (HSPICE)

VCS supports multiple languages • Verilog • VHDL • C/C++ • SystemC • SystemVerilog • OpenVera • Analog Intuitive GUI help find bugs quickly • Assertions • Testbench • Coverage • Post-simulation analysis

The most used features are: • Tracing the Cause of Failed Assertion • Trace drivers and loads of a signal at any time to see the drivers and loads that caused a value change and see all the drivers/loads that possibly contributed to a signal value. RTL and Gate Signal Comparison

Highlighting the net in gate- level schematic and Verilog

Design Compiler performs logic synthesis and optimization of design • Synthesizes HDL designs into optimized technology- dependent gate-level designs. • Results in smallest and fastest logical representation of a given function • Design Compiler supports a wide range of flat and hierarchical design styles • Combinational and sequential designs can be optimized for • timing • area • power

Constraints HDL

IP DesignWare Design Compiler Library Timing & power Datapath Power Timing analysis optimization optimization optimization

Technology Library Area Test Timing optimization synthesis closure Formal verification

Symbol Library

Optimized SDF gate-level netlist PDEF Back-annotation Place & route

Develop HDL files

Specify libraries

Read design

Design rule constraints set_max_transition Define design environment Design optimization constraints set_max_fanout create_clock set_max_capacitance set_clock_latency set_propagated_clock set_clock_uncertaintly Set design constraints set_clock_transition set_input_delay set_output_delay set_max_area compile Optimize the design

check_design Analyze and resolve design report_area problems report_constraint report_timing

write Save the design database

Design source Code Reports and logs (text formats) Verilog(.v ) VHDL (.vhd) Design Design database Synthesis (.db - Synopsys internal scripts (.tcl) Compiler database format) Design Gate level Verilog description constraints (.con, .sdc)

Synopsys' design-for-test (DFT) synthesis solution (DFT Compiler) – enables scan insertion within Design Compiler

DFT Compiler's integration with Design Compiler ensures DFT with optimization of area, power, and timing constraints, and predictable timing closure of physically optimized scan designs.

One-pass test synthesis

Comprehensive RTL and gate-level DFT design rule checking

Rapid scan synthesis

Adaptive scan technology

Hierarchical scan synthesis

Observe point insertion

Automatic fixing of scan violations (autoFix)

Location-based scan ordering

Timing-based scan ordering

Formality checks whether two designs are functionally equivalent or not

Its purpose is to detect unexpected differences that may have been introduced into a design during development.

Design level 1 Design process Design level 2

Formality

Equivalent Yes/No ?

Compare Point • Primary output of a circuit • Registers within a circuit • An input to black boxes within circuit Logic Cone • A block of combinational logic which drives a compare point

Equivalence checking is a four-phase process: • Reading and elaborating language descriptions into logical representations • Setting up prompt for verification • Mapping of corresponding compare points between pairs of designs (Matching) • Comparison of logic cones that drive the compare points (Verification)

Formality supports the following input formats:

Input formats Command Verilog (synthesizable subset) - read_verilog

Verilog (simulation libraries) - read_verilog -vcs

VHDL (synthesizable subset) - read_vhdl

EDIF - read_edif

Synopsys binary files - read_db, read_ddc, read_mdb (*)

Guidance (Loading of automated setup file) • The purpose of automated file (.svf) is to help Formality process design changes caused by other tools, which it should have access to as the changes are made. Referencing (Specifying the reference design) • The reference design is the design against which the transformed (implementation) design is compared. Implementation (Specifying the implementation design) • This is the changed design. It is the design correctness that needs to be verified. Matching (Matching compare points) • Process of aligning compare points between two designs. Verification (Verify the Designs) • Process of proving or disproving that compare points are equivalent (have same functionality). Debug • During debug the user should determined where and why the comparison results were unsuccessful.

TetraMAX is a high-speed, high-capacity automatic test pattern generation (ATPG) tool.

It can generate test patterns that maximize test coverage while using a minimum number of test vectors for a wide variety of design types and design flows.

It is well suited for designs of all sizes up to millions of gates.

Basic-Scan ATPG, an efficient combinational- only mode for full-scan designs

Fast-Sequential ATPG for limited support of partial-scan designs

Full-Sequential ATPG for maximum test coverage in partial-scan designs.

HDL netlist

Design Compiler

Design for test

Writing test protocol

Compiled, STIL test protocol scanned netlist file

TetraMAX ATPG

Verilog library

Pre-process netlist

Models Read netlist

Read Library STL test protocol file Build the model

Perform test design rule checking(DRC)

Prepare to run ATPG

Run ATPG

Review test coverage

Re-run ATPG

Save test patterns

Test protocol

Reading the netlist

Reading Verilog library models

Building the ATPG model

Performing Test Design Rule Checking (Test DRC)

Generating test protocols

Test DRC checks for the following conditions:

Whether the scan chains inputs and outputs are logically connected

Whether all the clocks and asynchronous set/reset pins connected to scan chain flip-flops are controlled only by primary input ports

Whether the clocks/sets/resets are off when you switch from normal mode to scan shift mode and again when you switch back to normal mode

Whether any internal multiple-driver nets can be in contention

PrimeTime is a full-chip, gate-level static timing analysis tool that is an essential part of the design and analysis flow for today's large chip designs.

PrimeTime validates the timing performance of a design by checking all possible paths for timing violations, without using logic simulation or test vectors.

Gate-level SDF netlist Libraries

Parasitics Design PrimeTime Constraints Initial timing reports Saved Restore session in session PrimeTime for further debugging

.db RTL Technology description Timing constraints for library Cell delays, transition resynthesis and logic times, capacitance, optimization Synthesis wire load models, .lcctcl, .sdc design rules, operating conditions

Design data Command-specified PrimeTime conditions Gate-level .db, Verilog, VHDL (Static Timing Analysis) description .tcl .sdc .pt Path constraints Place & Route .sdf

Delay data; detailed parasitic data for back-annotation Chip layout .db, interface logic .sdf; RSPF, DSPF, SPEF, SBPF Timing description models models, extracted timing models Design sign-off

Netlist (.v, .ddc)

Verilog Cell Library.db (.v) (.db)

GDSII TluPlusTluPlus,, IC Compiler (.gds) .map.map

Standard TechTech file file Parasitics . tf.tf Exchange Format Milkyway Ref (.spef) library

Invoke ICC

Data preparation

Floorplanning

Power Planning

Placement

Clock Tree Synthesis

Routing

Finishing

Results (.v, .gds, .spef)

Data preparation • Milkyway design library creation, logic libraries setup and parasitic models setup, design import. Floorplanning • Setting up the core area, top-level ports, and placement sites. Power Planning • Rectangular rings creation, power straps creation, etc. Core Placement and Optimization • During the placement phase the design's standard cells will be automatically placed in horizontal placement rows. • Allows following optimizations: power, optimize_dft, effort, etc

Core Clock Tree Synthesis and Optimization • During clock tree synthesis, IC Compiler builds clock trees that meet the clock tree design rule constraints while balancing the loads and minimizing the clock skew. Allows the following options: area_recovery, power, optimize_dft, only_cts, etc. Core Routing and Optimization • This command performs simultaneous routing and postroute optimization on the current design. Allows following optimizations: power, size_only, stage, only_hold_time, only_design_rule etc. Check DRC (Design Rule Checking) and LVS (layout vs. schematic)

Export the design • Allows following formats: Verilog ,GDS format etc.

Hercules is a hierarchical physical verification tool that performs design rule checking (DRC) and layout vs. schematic (LVS) on IC design.

Hercules uses several input files to perform DRC, LVS, LPE and ERC design verification. These input files are: • Database • Runset file • Schematic netlist

The primary input file is the runset file.

In the beginning of a Hercules run, primary group files are created that consist of one file per layer listed in the ASSIGN section of the runset file.

Read different design databases using:

• GDSII • GDSOUT • OASIS • Milkyway

Runset file is a control file that instructs Hercules where to find input data, which checks to perform and where to write output files.

Separate runsets are typically created for DRC and LVS.

• A DRC Runset instructs Hercules to check layout files for errors. • A LVS Runset instructs Hercules to compare the layout netlist to the schematic netlist of a design.

The schematic Netlist file is used during LVS comparison. It provides complete net information with each cell.

If schematic netlist is in CDL, NetTran will translate it to Hercules format.

nettran –verilog Johnson_count.v –cdl-a-cdl-s-sp-S-verilog-b1 VDD –verilog-b0 VSS\ -rootCell Johnson_count –sp ./saed90nm.cdl –outName Johnson_count.sp

Hercules uses the NetTran utility to translate the netlist between different formats. (e.g. Verilog to SPICE, SPICE to Hercules netlist format)

INPUT OUTPUT

SPICE Hercules SPICE CDL Netlist Verilog Verilog NetTran NetTran EDIF EDIF EDIF3 EDIF3 Hercules (default) Hercules Silos

Physical Input DRC Runset database runset.ev

Hercules (DRC run)

Output Summary files (Error database)

Physical Input LVS Runset database runset.ev

Hercules (LVSrun)

Output Summary files (Error database)

StarRC is a layout parasitic extraction tool. StarRC can be used at any physical design cycle stage to extract accurate parasitics.

StarRC reads OpenAccess, Milkyway, LEF/DEF or Hercules connected databases directly, without external processing.

Extracted parasitics can be written into the Synopsys centralized Milkyway database for use by analysis and optimization tools.

Because StarRC gracefully handles designs with layout versus schematic (LVS) violations, including opens and shorts, timing convergence can be ensured before the physical verification cycle begins.

TCAD_GRD_FILE saed90nm_9lm.nxtgrd

MAPPING_FILE .spf tech2itf.map StarRC

star_cmd rcx_cmd

• TCAD_GRD_FILE -File containing the modeled layers of a circuit. • MAPPING_FILE-File containing physical layer mapping information between the input database and the specified TCAD_GRD_FILE • star_cmd -ASCII file containing StarRC commands that controls extraction functions

StarRC supports these industry-standard formats: Input formats • LEF(Layout Exchange Format)/DEF(Design Exchange Format) • GDSII • Milkyway Output Netlist Formats • SPICE • Synopsys Binary Parasitic Format (SBPF) • Standard Parasitic Exchange Format (SPEF) • Detailed Standard Parasitic Format (DSPF) StarRC accepts input from GDSII, LEF/DEF, and IC Compiler formats.

Schematic Milkyway OR GDSII database Netlist Physical Database

StarRC Command File

Technology data (layer physical information) StarRC *.nxtgrd

Mapping file (used to map layers used in StarRC to technology layers) Parasitic Netlist

HSPICE supports: • Analog/RF/mixed-signal IC Design • Verilog-A Behavioral Modeling • Design For Yield- Process Variability and MosRa Device Reliability Analysis • Transient Noise Analysis • Cell and Memory Characterization

Waveforms (*.tr) Netlist Measure Analyze type Options HSPICE Model file Measurement Results (*.mt)

Architectural choices, RTL compilation and simulation (VCS)

Logic synthesis (Design Compiler)

Formal verification (Formality)

Generation of test patterns (TetraMAX)

Physical design (IC Compiler)

Physical Verification (Hercules)

Layout Parasitics Extraction (StarRC)

SPICE-level simulation of completed design (HSPICE)