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Cadence Physical Verification System In-Design and Back-End Physical Verification for Faster Final Signoff

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Cadence Physical Verification System In-Design and Back-End Physical Verification for Faster Final Signoff Cadence Physical Verification System In-design and back-end physical verification for faster final signoff Proven on many successful production tapeouts in nanometer process technologies, Cadence® Physical Verification System is the premier Cadence signoff solution enabling in-design and back-end physical verification, constraint validation, and reliability checking. It offers competitive distributed processing performance for advanced nodes, and its file compatibility and ease-of-use make it a drop-in replacement for existing physical verification technologies. Designed to preserve design intent, ensure design convergence, and deliver a predictable debug cycle, Cadence Physical Verification System provides a faster path to final signoff. Cadence Physical Seamless integration with the Virtuoso Annotation Browser or with Verification System Virtuoso platform the PVS Results Manager. Intuitive PVS debug tools (Interactive Short Locator As an integrated component, Physical Cadence Physical Verification System and Graphical LVS Debug) are available Verification System works seamlessly (PVS) integrates with industry-standard in the Virtuoso platform. They can ® within the Virtuoso custom IC design Cadence Virtuoso custom/mixed- verify designs by using the technology ® platform. Through interactive mode, signal and Cadence Encounter digital constraints, design constraints, and PVS provides dynamic and real-time design flows. This provides designers signoff rule deck. with an end-to-end design and signoff signoff design-rule checking (DRC) for solution from a single vendor. every edit. Through in-memory/batch In-line integration with the full-signoff verification mode, PVS can Encounter platform PVS is a trusted solution that enables directly read in design data from the users to achieve advanced node design Within the Encounter digital imple- Virtuoso environment, which elimi- signoff in a quick total turnaround mentation platform, PVS can inter- nates redundant Pcell evaluation and time. It provides efficient, effective actively verify the design by directly stream out. PVS can rapidly check the debug tools to reduce debug time accessing Encounter data and standard design to maximize productivity with and increase productivity. This cell data from the OpenAccess what-if analysis. The results can be solution supports advanced process database. This means designers can viewed and debugged with either the node technology (such as double invoke PVS and browse its error patterning, 3D-IC, and advanced device extraction), and it extends physical verification technology into design reliability checking and Virtuoso Custom Encounter Faster Turnaround Time IC Platform Digital Platform constraint validation. PVS also offers a distributed multi-threading processing In-Design PVS In-Design PVS Higher Productivity capability that greatly accelerates throughput without requiring specialized hardware. Tight Integration Standalone PVS Pre-Tapeout Signoff Figure 1: Used either in-design or standalone, PVS enables efficient design, implementation, and foundry signoff closure Cadence Physical Verification System block and chip levels by using the fully foundry-qualified signoff deck, and it can be run from Virtuoso memory space. Using Virtuoso DRC, layout designers can perform design, implementation, and in-memory signoff checks within the Virtuoso environment. With correct- by-construction and dynamic detection/ verification of the editing geometries, this DRC technology speeds turnaround time, brings signoff confidence to layout designers, and ultimately improves design quality. Figure 2: The Virtuoso GUI displays the DRC debug environment Programmable Electrical Rule Checker markers without converting data from PVS integrates seamlessly with Cadence the Encounter design environment. Using QuickView Layout and Manufacturing The PVS Programmable Electrical Rule PVS, they can generate regular metal Data Viewer. It also runs standalone to Checker (PERC) reduces the risk of low fill and advanced timing-aware metal verify the finished chip. reliability and provides a platform to fill using the signoff rule file. Designers translate the designer’s intent into a set Virtuoso DRC can launch the PVS Results Manager and of rules. The PERC uses the designer’s intuitive debug tools within the Encounter Traditional DRC use models involve rules throughout the whole development design environment. packaging up the layout (i.e. GDSII) and process, at pre- and post-layout stages. invoking a DRC run. This requires the data It identifies the place with high reliability Benefits preparation, launching of the job, and risk in the early stage of development, then pushing any error data/markers back and it checks that the solution used • Trusted solution with production- into the layout view. Virtuoso DRC is a to reduce reliability risk satisfies the proven accuracy new capability that integrates PVS DRC designer’s netlist-based and layout-based • Single-vendor solution for implemen- technology with Virtuoso Layout Suite requirements. tation and pre-tapeout signoff in a real-time mode. This convenient use The PVS PERC can be applied to find ESD model enables layout designers to run • Quick turnaround time from design unprotected devices and pads, to check DRC using a signoff-level DRC deck as to signoff through integration with the ESD protection structure, and to find they complete each edit. Virtuoso and Encounter design flows cross-power domain interface structures Layout designers can also leverage this and check them. The PERC can be used • Innovative technology to support technology to do interactive editing to find common errors (such as floating advanced process node design checks by using the OA tech file. Full gates or prohibited power domains) in the • Reduced debug time with powerful and signoff verification can be done at the intuitive debugging tools • Simplified migration through compat- ibility with industry-standard formats • Cost-effective parallel computing systems, eliminating the need for hardware modifications Features Interactive and batch verification Physical Verification System (PVS) works for both interactive and batch modes. Interactive physical verification, integrated within the Virtuoso and Encounter platforms, helps designers preserve design intent to ensure design conver- gence. PVS also operates in DFII and OpenAccess environments. Furthermore, Figure 3: Virtuoso DRC technology www.cadence.com 2 Cadence Physical Verification System Conventional Short Isolation Error results visualization and management ERC Run Debug ERC Run Debug ERC Run Debug The PVS Results Manager provides an PVS Interactive Short Isolation easy-to-use, interactive error-navigation system to efficiently review, waive, and ERC Run Debug correct physical verification issues. The Results Manager can be launched within Run Debug Virtuoso and Encounter environments. An interface with a high-performance, high- Run Debug One-Pass Closure = 2x Productivity capacity design data viewer—Cadence QuickView—enables PVS users to efficiently debug extremely large system- 3 hrs 8 hrs on-chip (SoC) designs with design-file Figure 4: The Interactive Short Locator improves productivity by at least 2x sizes in the tens-of-gigabytes range. Competitive performance for design pre-layout stage. It can also be used to Interactive Short Locator throughput verify that third-party IP blocks satisfy the Shorts, especially power/ground shorts, designer’s reliability standards. PVS delivers multi-processor perfor- are the most difficult debug issues. mance that is highly competitive with Constraint Validator The PVS Interactive Short Locator facili- other physical verification solutions. tates one-pass short isolation to deliver The PVS Constraint Validator shortens Large designs can also take advantage an efficient and intuitive LVS debug total turnaround time and improves of the PVS distributed multi-threading solution that helps designers quickly design quality by detecting design errors processing architecture that leverages detect and solve short issues. Designers in the very early stages of the IC devel- low-cost, off-the-shelf compute platforms can start debug analysis while the run is opment process, and by validating the to greatly accelerate design throughput. in progress, as soon as first results are design at the final stage. This new PVS available. Drop-in compatibility with industry- tool is able to verify the correctness of standard formats created layout according to specified Graphical LVS debug constraints. For example, whether all All PVS rule files and output files are Identifying the causes of complex LVS nets that should be routed symmetrically compatible with industry-standard mismatches is extremely time-consuming. are indeed symmetrical, or whether halo formats. This allows PVS users to leverage The PVS Graphical LVS Debug solution distance is being taken into account. The their existing investments in rule decks accelerates identification of complex Constraint Validator can detect errors in and infrastructure with less effort for LVS mismatches in cell/block designs. the implementation stage that conven- translation or scripts. Rule decks execute By showing all errors and warnings in tional tools would only reveal during the natively on PVS, and PVS reports design a consistent and simplified graphical very last parasitic extraction stage (i.e., errors in an intuitive, predictable, and view, users can easily debug complex symmetrical layout impacted by neighbor familiar
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