Junction Leakage Current Degradation Under High Temperature Reverse-Bias Stress Induced by Band-Defect-Band Tunnelling in Power VDMOS

Microelectronics Reliability 45 (2005) 994–999 www.elsevier.com/locate/microrel

Junction leakage current degradation under high temperature reverse-bias stress induced by band-defect-band tunnelling in power VDMOS

Giacomo Barletta *, Giuseppe Curro`

ST Microelectronics, Stradale Primosole 51, 95121 Catania, Italy

Received 28 June 2004; received in revised form 29 September 2004 Available online 19 January 2005

Abstract

A deep analysis of the intrinsic junction and surface currents in power vertically diffused MOS devices with sub- micrometer channel length and thin gate oxide has been carried on after a typical reliability high temperature reverse bias (HTRB) stress. A reference set of gated diodes has also been examined in order to better understand the onset and evolution of post-stress leakage degradation. A comparison among complete MOSs, single body diodes and enriched diodes allows to highlight the role played by the point defectivity both at gate interface and in the bulk silicon close to the junction surface. We found that the typical interface defects involved in the leakage degradation are shallow traps and can be de-populated simply by a thermally activated mechanism. More specifically, the main degradation mechanism relies to band-defect-band tunneling localized at the surface drain/body junction where an intrinsic n-i-p region evolves due to a birdÕs beak lateral profile of the body diffusion. We have demonstrated that the most important contribution to the activation of the precursor defect sites is given by the transverse electrical field that develops just below the SiO2/Si interface within the n-i-p region during the stress. 2004 Elsevier Ltd. All rights reserved.

1. Introduction Among them, HTRB (high temperature reverse bias) is the test needed to characterize the PowerMOS junctions Some particular microelectronics devices, as power- robustness. In that case the test conditions are MOSFETs for civil (automotive, motor drivers, audio T = 448 K, inverse polarization at 80% of the nominal amplifiers etc.) and military applications [1], are re- drain–source breakdown voltage (gate electrode is quested to ensure very restrictive reliability conditions. shorted to source) for 1000 h cumulative stress. As a The standard reliability tests are oriented to monitor consequence of the high electrical field at the metallurgi- the lifetime robustness in particular operation environ- cal body/drain junction and of the more and more severe ments, by just quantifying the device response to well de- scaling down of the surface geometry, the HTRB test fined electrical, mechanical and environmental stresses. highlights the fragility of the device surface showed as the gate oxide degradation and even breakdown or, in a better case, as a drain current (Idss) increase. * Corresponding author. Tel.: +39 95 740 7643; fax: +39 95 This work investigates the intrinsic mechanisms 740 7099. standing behind the Idss degradation that appear even E-mail address: [email protected] (G. Barletta). at very low drain voltage after the test in a low voltage,

0026-2714/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.11.008 G. Barletta, G. Curro` / Microelectronics Reliability 45 (2005) 994–999 995 p-type scaled Power-VDMOS. The peculiar feature of 10-2 the device in concern relies to its n-base diffusion profile (a) which is somewhat recessed with respect to the gate sur- 10-4 face, as required for a low ON-resistance vertically diffused device. In that case a high transverse electrical 10-6 Initial field arises from gate to drain during the HTRB test aft.6h aft.12h

and this turns to be a crucial point in the defect evolu- (A)| aft.24h -8

D 10 aft.48h tion within the surface depletion region which expands |I aft.96h aft.168h like a birdÕs beak in the body range. The drain current nd Evolution: 2 stage degradation basically involve conventional emission 10-10 processes as those described by Shockly–Read–Hall -12 theory (SRH), and more peculiar mechanisms as band- 10 Evolution: 1st stage defect-band tunneling (BDT). We have found that the latter kind of degradation source is mainly involved in 0 -5 -10 -15 VD (V) the overall Idss failure. 10-2 (b) 10-4 2. Experimental

10-6 The device investigated is a typical p-channel power Initial VDMOS, Fig. 1, for low voltage ( 30 V) operations, aft.6h

(A)| -8 aft.12h with 350 A˚ gate oxide, n+ poly gate electrode and sub- D 10 aft.24h |I aft.48h micrometric channel length. nd aft.96h + Evolution: 2 stage aft.168h Two diodes n –p were realized for comparison fol- 10-10 lowing the same flow-chart of the VDMOSs in which + the source p diffusion is absent. Also the diodes are pat- -12 st 10 Evolution: 1 stage terned and driven by the gate. N-type region is realized with only one phosphorus implant in the first diode type 0 -5 -10 -15 VD (V) (Body Diode), while, the second diode type includes also 10-2 a surface enrichement via arsenic implant. All drain/ (c) source leakage and gated-diodes measurements were car- 10-4 ried out with a parameter analyzer HP4156B (Agilent).

10-6 Initial aft.6h

3. Electric characteristics (Idss) evolution (A)| aft.12h 10-8

DSS aft.24h |I Evolution aft.48h Fig. 2 shows the current evolution (Id vs. Vd) at some aft.96h aft.168h end-points after typical HTRB stress, for VDMOSs 10-10 (Fig. 2(a)) and for simple and enriched body diodes

(Fig. 2(b) and (c), respectively). All electrical curves were -12 10 carried out at room temperature, and the voltage range is between 0 V and 15 V because the HTRB stress 0 -5 -10 -15 doesnot shift rigidly the blocking voltage curves in our VDS (V) case, but it only degrade the current characteristics at Fig. 2. Id–Vd characteristics of the leakage typical evolution at seven end-points after HTRB. (a) Power VDMOS, (b) diode with only body (P), (c) body diode with double implants (P) and (As).

lower drain voltage. The figures clearly shows the influ- ence of the stress time, in fact drain leakage current increases with increasing the stress duration and concur- rently the curves shift towards the y-axis till flattening on it. The behavior of the junction leakage current can be examined in two separate voltage regions: low drain Fig. 1. Cross-section view of VDMOS device [2]. voltage (Vd < 5 V) where at a short drain voltage 996 G. Barletta, G. Curro` / Microelectronics Reliability 45 (2005) 994–999 variation corresponds a large current variation DId, and stage is characterized from a curve shift towards y-axis high drain voltage, (Vd > 5 V), where leakage current is while progressively increases the leakage current level; less sensible to large varying the drain voltage. the second stage is characterized by a shift towards high- VDMOSs and diodes after 48 h of stress have both high er drain voltage (2nd evolution) and the formation of a level leakage values, (10–100) lA. However, contrary knee at lower drain voltage. Instead, the enriched diode to the n+-enriched diode, the leakage trends in the characteristics trend shows only one kinetic path: the stressed VDMOSs and simple body diodes show strong progressive flattening onto y-axis at lower drain voltage. analogies at low drain voltage (Vd < 5 V). In fact, the The same kinetics above described can be seen on IDS– Idss in both devices evolves through two stages: the first VGS characteristics (gate-diode technique).

-2 10-2 10 (a) (a)

-4 -4 Pwr. MOSs 10 10

-6 10-6 10 Initial aft.168h of HTRB@175oC aft.6h o

(A)| aft.117h of HTS@150 C (A)| o -8 aft.12h -8 aft.595h of HTS@150 C

DS 10 DS 10 aft.24h |I |I aft.48h Evolution: 2nd stage aft.96h aft.168h -10 10-10 10

-12 -12 st 10 10 Evolution: 1 stage

0 5 10 15 0 -5 -10 -15 V (V) -2 VGS (V) -2 DS 10 10 (b) (b)

-4 -4 Gated-Diode: Body(P) 10 10

-6 10-6 10 aft.168h of HTRB@175oC Initial o

(A)| aft.117h of HTS@150 C (A)| aft.6h o -8 aft.12h -8 aft.595h of HTS@150 C

DS 10

DS 10 |I

|I aft.24h nd aft.48h Evolution: 2 stage aft.96h -10 10-10 aft.168h 10

-12 -12 10 Evolution: 1st stage 10

0 5 10 15 0 -5 -10 -15 V (V) -2 VGS (V) -2 DS 10 10 (c) (c)

-4 10-4 10 Gated-Diode: Body(P)+Arr(As)

10-6 10-6 (A)| (A)| -8 Initial -8

DS 10 DS 10 aft.6h o |I |I aft.168h of HTRB@175 C aft.12h o aft.24h aft.117h of HTS@150 C aft.595h of HTS@150oC -10 aft.48h -10 10 aft.96h 10 aft.168h

-12 -12 10 Evolution 10

0 5 10 15 0 -5 -10 -15

VGS (V) VDS (V)

Fig. 3. IDS–VGS characteristics with VDS@50 mV after Fig. 4. IDS–VS recovery after HTS@150 C. (a) Power HTRB@175 C. (a) Power VDMOSs, (b) simple body diode VDMOSs, (b) simple body diode (P), (c) simple diode (P) (P), (c) simple diode enriched. enriched with As. G. Barletta, G. Curro` / Microelectronics Reliability 45 (2005) 994–999 997

conventional one that relies to emission processes involving surface traps in silicon. The latter type includes emission components due either to the band- to-band tunneling (BBT) and to the band-defect-band tunneling (BDT). The defects involved in the non-conventional leakage mechanism are localized in the intrinsic region of the n+-i-p surface diode [5], that is the birdÕs beak shaped depletion protrusion entering the n-body region under blocking polarization. In fact, the space charge region just below the overlap between gate oxide and body/drain junction is characterized by a deep depletion (uninverted) behavior even at large drain ﬁelds, due to the lower surface doping. Fig. 6(b) and (c) sketch the two possible mechanisms of surface tunneling, both in the longitudinal direction

Fig. 5. IDS@8 V evolution after HTRB@175 C plus HTS@ (x-direction) Fig. 6(c) and vertical direction (y-direction) 150 C. Fig. 6(b), just close to the gate-junction overlap region and under deep-depletion regime of the surface diode.

Fig. 3 shows IDS–VGS curves when the drain elec- The two tunneling mechanisms are possible if the sur- trode is biased at 50 mV, while the gate electrode driv- face electric field is sufficiently large (1 MV) so as the ing the surface depletion region is swept between 3 and band bending is larger than the energy band gap +15 V. (1.2 eV). In this condition the top of valence band is The sharp peak observed at negative voltages, at moved above the bottom of a conduction band allowing about 500 mV, is due to fast interfacial states genera- an electron in the valence band to tunnel directly into tion [3,4]. On the positive voltage side the same leakage the conduction band (1st process). This emission process current stress-driven evolution of Fig. 2 is recognized. It leaves holes in the valence band that are swept towards must be noticed that the interface state peak doesnot the p-type region electrode, while the new conduction change after HTRB stress, but it is buried by the in- electrons drift towards the opposite electrode, providing creased drain leakage current. an overall contribution to the to leakage current (Fig. We aspect that if the leakage source is dependent on a 6(c) and (b) 1st process). deep energy level, a thermal annealing will not signifi- In this first case we have considered only a vertical cantly affect the leakage level. Instead, if the leakage cur- BBT due to an high transverse electrical field. But if rent is caused from Ônot conventionalÕ mechanisms, as we must consider the possible involvement of the surface those involving surface and interface defects, then we defects activated or produced by HTRB then we have to will notice some variations in the curve profiles and leak- include also a BDT-corrected mechanism (Fig. 6(b), 2nd age current values. process) which, for energetic reasons, concerns electrons Fig. 4 shows the drain leakage characteristics after only and contributes to increase the leakage current 120 and 600 h unbiased annealing at 150 C (HTS). level. The surface field in silicon depends on the differ- Its clear that the defects activated by the previous ence between VDS and VGS HTRB are not permanent. In fact the leakage current is reduced in the VDMOSs and in the simple body diode, V GS ¼ V DS þ V FB þ 3toxes þ us ð1Þ and it recovers its pre-HTRB original value (Fig. 2a). In Fig. 5 a comparison is made among the degrada- where es is electrical field at silicon surface, us is deep- depletion surface potential, V is flat band voltage tion and recovery kinetics of Idssaverage measured at FB 8 V. The observations made in this paragraph prove and tox is the gate oxide thickness, 3 is the ratio of silicon that the leakage current degradation is driven by permittivity to oxide permittivity. The above description ‘‘non-conventional mechanism’’, i.e. it cannot be attrib- is complicated if to the vertical electric field at the Si/ uted to a typical SHR mechanism only. SiO2 interface we also add the longitudinal field devel- oped from drain to source under reverse-bias. This field component turns to lower the potential barrier height 4. Leakage mechanisms seen by the captured electron and, in synergy with vertical field, it rises the tunneling emission rate of the carri- In VDMOSs and diodes the sources of leakage cur- ers into conduction and valence band. rent can be divided in two main types: a conventional Turning to an analytical representation of the leakage mechanism that depends on bulk emission pro- two leakage mechanisms [6], the emission rate can be cess, well described by an SRH model, and a non- modeled as 998 G. Barletta, G. Curro` / Microelectronics Reliability 45 (2005) 994–999

where GSRH is the generation rate by SRH model valid for arbitrary injection levels in a non-degenerate semiconductor [8], while Te/h is the electron and hole tunneling component that depends on vertical and longi- tudinally fields. In the right member n and p are the carrier densities under arbitrary injection conditions, ni is the intrinsic carrier density, n1 and p1 are the captured carrier densities, sn and sp are the minority carrier lifetime constants. e in the last terms of (2) it is the total electric field (vertical plus longitudinal) for carrier tunneling in deep-depletion regime, while A end B are field-indepen- dent constants. The leakage current is then obtained by integration of Eq. (2) on the whole trap energy distribu- tion in the silicon band gap, and on the depletion region volume. ZZ I ¼ cos t UðE; xÞdE dx Area ð3Þ

Eq. (2) can be simpliﬁed through the following conditions

• When VGS < VDS we can neglect the tunneling emission rate term and the leakage current is suﬃciently described by the ﬁrst term with the further approxi- mation of accounting only for the minority (electrons) carriers

GSHR ¼ ni=sn ð4Þ

• Instead, when the vertical ﬁeld at Si/SiO2 interface is much larger than the longitudinal one, VGS > VDS the leakage current is described by the second term Te/h only.

The integration (3) provides

2 B=e I ¼ðqniW =sn þ Ae ‘ ÞArea ð5Þ

Fig. 7 shows the experimental IDS–VGS curve of a body-alone gated-diode after 168 h of HTRB stress, to- gether with the theoretic curve as from the above Eq. (5) relative to the case of a gradual junction doping. The A and B constants have been estimated through curve fit: A = 0.65 mA/V2 and B = 18.4 MV/cm [7]. The overlap between the experimental and model curves is generally satisfactory, unless in the low voltage region (enclosed in the oval in Fig. 6) where the pro- Fig. 6. Electrical setup of a planar n+–p diode, with the surface posed model fails to properly fit the data. This is prob- field and depletion silicon region (a). (b) shows band-bending ably due to the simplified model employed, where the in vertical (y-direction) and (c) concerns longitudinal direc- longitudinal field to the interface of Si/SiO2 is neglected tion (x-direction) at the silicon surface under deep depletion and only two mechanisms of generation are involved. A regime. tunneling modellization more complex then (5) would allow a more accurate estimation of the involved trap levels. U ¼ GSRH þ T e=h We have showed that the main mechanism acting to ðnp n2 ‘DEg=ðKT ÞÞ ð2Þ ¼ io þ Ae2‘B=e increase the Idss leakage current after HTRB involves sn0ðn þ n1Þþsp0ðp þ p1Þ the surface-defect emission rate which can be removed G. Barletta, G. Curro` / Microelectronics Reliability 45 (2005) 994–999 999

5. Conclusion

In this work we have shown that the leakage current degradation after HTRB stress in sub-micron power VDMOS devices and gated-diodes is driven mainly by a non-conventional surface-defect-assisted tunneling mechanism. The leakage current increase involves carrier generation processes by shallow traps localized in the sub-surface depletion region extending with a birdÕs beak proﬁle within the body side of the intrinsic diode. Band-to-band tunneling and band-defect-band tunneling are the two mechanisms that dominates the drain leakage degradation after the stress. The two tunneling process are deﬁnitively caused by the presence of a

Fig. 7. IDS–VGS experimental and theoretical curve (5) at low relatively strong transverse field in the gate-to-diode drain voltages. junction overlap region, especially for low doped, sub- micrometer devices. via thermal processing. A significative contribution to the activation or even to the creation of such defects is given by the high transverse electric field in the depletion References region extending in a birdÕs beak shape during the stress. A possible way to reduce the leakage current degrada- [1] Department of defense USA. Military Standard test meth- tion is decreasing the above mentioned transverse elec- ods for semiconductors devices. 28 February 1995. trical field. The Eq. (1) may address some solutions [2] US patent 5,841,167. [3] Grove AS, Fitzgerald DJ. Surface effects on p–n junctions: and limits being it a function containing characteristics of surface space-charge regions under non- equilibrium conditions. Solid-State Electron 1966;9:783–806. • The thickness gate oxide tox. [4] Schroder KD. Semiconductor material and device charac- • The voltage flat band VFB. terization. John Wiley & Sons Inc; 1990. • The surface potential, us, that depends from surface [5] Baliga BJ. Modern power devices. New York: Wiley & silicon doping [8]. Sons Inc.; 1987. [6] Voldmaman SH, Johnson JB, Linton TD, Titcomb S. In particular, the third point suggests that a proper Unified generation model with donor and acceptor-type trap design of the body region in VDMOSs would be re- states for heavily doped silicon, 1990. IEDM Tech Dig. quired in order to eliminate the intrinsic junction region. p. 349. [7] Chan TY, Chen J, Ko PK, Hu C. The impact of gate- Of course, this approach must avoid the onset of new induced drain leakage current on MOSFET scaling, 1987. and unwanted feasibility problems in VDMOS design IEDM Tech Dig. p.718. and moreover must compell with the need to minimize [8] Sze M. Phisics of semiconductos devices. second ed. John any hot-electron reliability counter-effect. Wiley & Sons Inc.; 1981.