PHY Daughter Card User Guide
For ML32x Development Platforms
UG065 (v1.0) P/N 0402279 May 5, 2004
R R
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PHY Daughter Card User Guide www.xilinx.com UG065 (v1.0) P/N 0402279 May 5, 2004 1-800-255-7778 PHY Daughter Card User Guide UG065 (v1.0) P/N 0402279 May 5, 2004
The following table shows the revision history for this document..
Version Revision 05/05/04 1.0 Initial Xilinx release.
UG065 (v1.0) P/N 0402279 May 5, 2004 www.xilinx.com PHY Daughter Card User Guide 1-800-255-7778 PHY Daughter Card User Guide www.xilinx.com UG065 (v1.0) P/N 0402279 May 5, 2004 1-800-255-7778 R Preface
About This Guide
This guide documents the PHY daughter card for use with Xilinx ML32x Development Platforms.
Additional Resources For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.
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PHY Daughter Card User Guide www.xilinx.com 5 UG065 (v1.0) P/N 0402279 May 5, 2004 1-800-255-7778 R Preface: About This Guide
Conventions This document uses the following conventions. An example illustrates each convention.
Online Document The following conventions are used in this document:
Convention Meaning or Use Example See the section “Additional Cross-reference link to a Resources” for details. Blue text location in the current document Refer to “Title Formats” in Chapter 1 for details. Cross-reference link to a See Figure 2-5 in the Virtex-II Red text location in another document Handbook. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files.
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PHY Daughter Card
Overview The PHY daughter card provides Ethernet capability to Xilinx ML32x Development Platforms by using two Marvell Alaska Gigabit Ethernet over copper transceivers, 88E1111. These PHY devices can perform all physical layer (PHY) functions, can operate at 10/100/1000 Mb/s, and support many interfaces to the MAC. The PHY daughter card connects to ML32x boards through the J55 and J56 headers as shown in Figure 1.
UG065_01_042704
Figure 1: PHY Daughter Card Connected to an ML320 Board
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Features The PHY daughter card features the following: • Two Marvell Alaska PHY devices (88E1111) with 10/100/1000 Mb/s operation • Support for the following interfaces: ♦ GMII/MII ♦ SGMII ♦ RGMII • Two power connection options: ♦ ML32x header pins ♦ 5V external power jack • Two-port RJ-45 connector • 2.5V - 25 MHz crystal oscillator for both PHY devices • SMA connectors for the SGMII interface
Power Settings
The ML32x PHY daughter card can be powered up either through the VCC pins of the ML32x board when the daughter card is connected to it, or through an external power 5V jack if used on other boards.
To power the daughter card from the VCC pins of the ML32x board through the headers, set the jumpers according to Figure 2.
J32 J42 J40 J41 J36 J35 J31 J38 UG065_02_043004 Figure 2: Jumper Settings to Power Up from an ML32x Board
To power the daughter card from the 5V jack connector, set the jumpers according to Figure 3.
J32 J42 J40 J41 J36 J35 J31 J38 UG065_03_043004 Figure 3: Jumper Settings to Power Up from 5V Jack Connector
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Signal Connectivity Table 1 shows the signal connections between the PHY daughter card and the ML320, ML321, and ML323 Platforms.
Table 1: Connections Between the PHY Daughter Card and the ML32x J15 J56 J16 J55 PHY ML320 ML321 ML323 PHY ML320 ML321 ML323
1 - P1_TXD1 E19 E23 K31 1 - D21 A25 N33 3 - P1_TXEN F19 G23 L32 3 - P1_RXC_RXCLK E21 C25 P33 5 - P1_GTXCLK F18 H23 M32 5 - P1_RXD1 F21 D25 R33 7 - P1_COL G19 J23 N32 7 - P1_RXCTL_RXDV G21 E25 T33 9 - P1_TXD3 H19 E24 P32 9 - P1_RCLK1 H21 H25 U33 11 - P1_TXD2 J19 G24 R32 11 - P1_CRS J21 B26 V33 13 - K19 H24 T32 13 - P1_RXER K21 C26 E34 15 - P1_TXD0 L19 J24 U32 15 - P1_RXD7 L21 D26 F30 17 - P1_TXD7 E20 K24 E33 17 - P1_RXD0 D22 E26 L31 19 - P1_TXD6 F20 L24 E31 19 - E22 F26 H34 21 - P1_TXD5 G20 M24 F31 21 - P1_RXD2 F22 G26 K34 23 - P1_TXD4 H20 N24 H33 23 - P1_RXD3 G22 H26 L34 25 - P1_MDC J20 J25 J33 25 - P1_RXD4 H22 J26 M34 27 - P1_MDIO K20 L25 K33 27 - P1_RXD5 J22 K26 N34 29 - P1_TXER L20 M25 L33 29 - P1_RXD6 K22 L26 P34 31 - P1_INT M20 N25 M33 31 - P0_CRS N22 M26 R34 33 - P0_COL N20 P25 AD33 33 - P22 R26 Y34 35 - P0_TXD7 P20 R25 AE33 35 - P0_RXD0 R22 T26 AA34 37 - P0_INT R20 P24 AF33 37 - P0_RXD1 T22 U26 AB34 39 - P0_TXD6 T20 R24 AD31 39 - U22 V26 AC34 41 - P0_TXD5 U20 T24 AH30 41 - P0_RXD2 V22 W26 AD34 43 - P0_TXD4 V20 U24 AK31 43 - W22 Y26 AE34 45 - P0_TXD3 M19 V24 AL33 45 - P0_RXCTL_RXDV Y22 AA26 AG34 47 - P0_TXD2 M18 W24 V32 47 - P0_RXD4 M21 AC26 AD32 49 - P0_TXD1 N19 Y24 W32 49 - P0_RXD5 N21 AD26 AE30 51 - P0_TXD0 P19 AB24 Y32 51 - P0_RXD6 P21 AE26 AK32 53 - P0_MDC R18 AC24 AA32 53 - P0_RXD7 R21 T25 AL34 55 - P0_MDIO R19 AD23 AB32 55 - P0_RCLK1 T21 V25 W33 57 - RESET T19 U23 AC32 57 - P0_RXD3 U21 W25 Y33
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Table 1: Connections Between the PHY Daughter Card and the ML32x (Continued) J15 J56 J16 J55 PHY ML320 ML321 ML323 PHY ML320 ML321 ML323
59 - P0_GTXCLK U18 V23 AF32 59 - P0_RXER V21 AC25 AA33 61 - P0_TXEN U19 W23 AD30 61 - P0_RXC_RXCLK W21 AD25 AB33 63 - P0_TXER V19 Y23 AE31 63 - Y21 AF25 AC33
Configuration Settings The Marvell Alaska PHY can be configured with several options such as the physical address, the PHY operating mode, auto-negotiation, the physical connection type, and others. The CONFIG[6:0] pins are used to set these options. Please refer to the ML32x PHY daughter card schematic attached to this document, specifically to sheets 7 and 8 for PHY0 and PHY1, respectively, and to the Marvell Alaska PHY data sheet for details. The CONFIG[6:0] pins must be tied to one of the pins as shown in Table 2. These seven CONFIG pins should not be left floating. The pins shown in Table 2 are LEDs, VDDO, and VSS pins of the PHY where each pin encodes a 3-bit constant value. Table 2: Pin to Constant Mapping Pin Bit[2:0] P0_VDDOH / P1_VDDOH 111 P0_LED_LINK10 / P1_LED_LINK10 110 P0_LED_LINK100 / P1_LED_LINK100 101 P0_LED_LINK1000 / P0_LED_LINK1000 100 P0_LED_DUPLEX / P1_LED_DUPLEX 011 P0_LED_RX / P1_LED_RX 010 P0_LED_TX / P1_LED_TX 001 VSS (GND) 000
Table 3 shows the configuration register map to the CONFIG[6:0] pins of the Marvell Alaska PHY 88E1111.
Table 3: Pin to Configuration Register Mapping Pin Bit[2] Bit[1] Bit[0]
CONFIG0 PHYADR[2] PHYADR[1] PHYADR[0] CONFIG1 ENA_PAUSE PHYADR[4] PHYADR[3] CONFIG2 ANEG[3] ANEG[2] ANEG[1] CONFIG3 ANEG[0] ENA_XC DIS_125 CONFIG4 HWCFG_MODE[2] HWCFG_MODE[1] HWCFG_MODE[0] CONFIG5 DIS_FC DIS_SLEEP HWCFG_MODE[3] CONFIG6 SEL_BDT INT_POL 75/50 OHM
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These configuration options are described in the Hardware Configuration section of the PHY data sheet. These options, except for the PHY address configuration, can be overwritten by writing to the registers through the MDIO interface. Table 4 lists the options available by setting jumpers on the configuration header pins of the PHY daughter card.
Table 4: Configuration Options on the ML32x PHY Daughter Card Configuration Option Signal Configuration Register Signal
CONFIG0 PHYADR = 00000 VSS PHYADR[2:0] = 000 CONFIG0 PHYADR = 00001 P0_LED_TX / P1_LED_TX PHYADR[2:0] = 001 CONFIG1 VSS ENA_PAUSE = 0; PHYADR[4:3] = 00 CONFIG2 Auto-Neg, 1000 Base-T, FD, P0_LED_LINK100 / ANEG[3:1] = 101 Master P1_LED_LINK100
CONFIG3 P0_LED_TX / P1_LED_TX ANEG[0] = 0; ENA_XC = 0; DIS_125 = 1 CONFIG4 SGMII to Cu w/o clock, w/ P0_LED_LINK1000 / HWCFG_MODE[2:0] = 100 auto-neg P1_LED_LINK1000 CONFIG4 RGMII, w/ modified MII in P0_LED_DUPLEX / HWCFG_MODE[2:0] = 011 10/100 Cu P1_LED_DUPLEX
CONFIG4 GMII to Cu P0_VDDOH / P1_VDDOH HWCFG_MODE[2:0] = 111 CONFIG4 RTBI to Cu P0_LED_TX / P1_LED_TX HWCFG_MODE[2:0] = 001 CONFIG4 TBI to Cu P0_LED_LINK100 / HWCFG_MODE[2:0] = 101 P1_LED_LINK100
CONFIG5 SGMII/TBI to Cu P0_LED_LINK1000 / DIS_FC=1; DIS_SLEEP=0; P1_LED_LINK1000 HWCFG_MODE[3]=0 CONFIG5 GMII/RGMII/RTBI to Cu P0_LED_LINK100 / DIS_FC=1; DIS_SLEEP=0; P1_LED_LINK100 HWCFG_MODE[3]=1 CONFIG6 50 Ohm P0_LED_RX / P1_LED_RX SEL_BDT = 0; INT_POL = 1; 75/50 OHM = 0
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GMII To set the PHY to operate in GMII mode, jumper the configuration headers as illustrated in Figure 4.
P1_CONFIG2
P1_CONFIG1
P1_CONFIG0
P1_CONFIG4
P1_CONFIG3
P1_CONFIG6
P1_CONFIG5 PHY 1 24682468 24682468
J5 J6 J7 J10
13571357 13571357
PHY 0 24682468 24682468
J2 J3 J4 J9
13571357 13571357
P0_CONFIG6
P0_CONFIG2
P0_CONFIG1
P0_CONFIG0
P0_CONFIG4
P0_CONFIG3
P0_CONFIG5 UG065_04_043004
Figure 4: Configuration Headers in GMII Mode
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Table 5: Configuration Settings for GMII Mode Configuration Option Signal Configuration Register Signal CONFIG0 PHYADR = 00000 VSS PHYADR[2:0] = 000 CONFIG1 VSS ENA_PAUSE = 0; PHYADR[4:3] = 00 CONFIG2 Auto-Neg, 1000 Base-T, FD, P0_LED_LINK100 / ANEG[3:1] = 101 Master P1_LED_LINK100 CONFIG3 P0_LED_TX / P1_LED_TX ANEG[0] = 0; ENA_XC = 0; DIS_125 = 1 CONFIG4 GMII to Cu P0_VDDOH / P1_VDDOH HWCFG_MODE[2:0] = 111 CONFIG5 GMII/RGMII/RTBI to Cu P0_LED_LINK100 / DIS_FC=1; DIS_SLEEP=0; P1_LED_LINK100 HWCFG_MODE[3]=1 CONFIG6 50 Ohm P0_LED_RX / P1_LED_RX SEL_BDT = 0; INT_POL = 1; 75/50 OHM = 0
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RGMII To set the PHY to operate in RGMII mode, jumper the configuration headers as illustrated in Figure 5.
P1_CONFIG2
P1_CONFIG1
P1_CONFIG0
P1_CONFIG4
P1_CONFIG3
P1_CONFIG6
P1_CONFIG5 PHY 1 24682468 24682468
J5 J6 J7 J10
13571357 13571357
PHY 0 24682468 24682468
J2 J3 J4 J9
13571357 13571357
P0_CONFIG6
P0_CONFIG2
P0_CONFIG1
P0_CONFIG0
P0_CONFIG4
P0_CONFIG3
P0_CONFIG5 UG065_05_043004
Figure 5: Configuration Headers for RGMII Mode
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Table 6: Configuration Settings for RGMII Mode Configuration Option Signal Configuration Register Signal CONFIG0 PHYADR = 00000 VSS PHYADR[2:0] = 000 CONFIG1 VSS ENA_PAUSE = 0; PHYADR[4:3] = 00 CONFIG2 Auto-Neg, 1000 Base-T, FD, P0_LED_LINK100 / ANEG[3:1] = 101 Master P1_LED_LINK100 CONFIG3 P0_LED_TX / P1_LED_TX ANEG[0] = 0; ENA_XC = 0; DIS_125 = 1 CONFIG4 RGMII, w/ modified MII in P0_LED_DUPLEX / HWCFG_MODE[2:0] = 011 10/100 Cu P1_LED_DUPLEX CONFIG5 GMII/RGMII/RTBI to Cu P0_LED_LINK100 / DIS_FC=1; DIS_SLEEP=0; P1_LED_LINK100 HWCFG_MODE[3]=1 CONFIG6 50 Ohm P0_LED_RX / P1_LED_RX SEL_BDT = 0; INT_POL = 1; 75/50 OHM = 0
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SGMII To set the PHY to operate in SGMII mode, jumper the configuration headers as illustrated in Figure 6.
P1_CONFIG2
P1_CONFIG1
P1_CONFIG0
P1_CONFIG4
P1_CONFIG3
P1_CONFIG6
P1_CONFIG5 PHY 1 24682468 24682468
J5 J6 J7 J10
13571357 13571357
PHY 0 24682468 24682468
J2 J3 J4 J9
13571357 13571357
P0_CONFIG6
P0_CONFIG2
P0_CONFIG1
P0_CONFIG0
P0_CONFIG4
P0_CONFIG3
P0_CONFIG5 UG065_06_043004
Figure 6: Configuration Headers for SGMII Mode
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Table 7: Configuration Settings for SGMII Mode Configuration Option Signal Configuration Register Signal CONFIG0 PHYADR = 00000 VSS PHYADR[2:0] = 000 CONFIG1 VSS ENA_PAUSE = 0; PHYADR[4:3] = 00 CONFIG2 Auto-Neg, 1000 Base-T, FD, P0_LED_LINK100 / ANEG[3:1] = 101 Master P1_LED_LINK100 CONFIG3 P0_LED_TX / P1_LED_TX ANEG[0] = 0; ENA_XC = 0; DIS_125 = 1 CONFIG4 SGMII to Cu w/o clock, w/ P0_LED_LINK1000 / HWCFG_MODE[2:0] = 100 auto-neg P1_LED_LINK1000 CONFIG5 SGMII/TBI to Cu P0_LED_LINK1000 / DIS_FC=1; DIS_SLEEP=0; P1_LED_LINK1000 HWCFG_MODE[3]=0 CONFIG6 50 Ohm P0_LED_RX / P1_LED_RX SEL_BDT = 0; INT_POL = 1; 75/50 OHM = 0
For SGMII operation, connect the SMA connectors of the PHY daughter card to the ML32x MGTs as follows: • For PHY 1: ♦ J24 to ML32x TXP ♦ J23 to ML32x TXN ♦ J13 to ML32x RXP ♦ J14 to ML32x RXN • For PHY 0: ♦ J26 to ML32x TXP ♦ J25 to ML32x TXN ♦ J11 to ML32x RXP ♦ J12 to ML32x RXN
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MII To set either PHY device in 10/100 Mb/s MII mode, the configuration headers for both devices must be connected together. The PHY devices must be set with auto-negotiation for any speed and for duplex capability. The speed and duplex are set by the other end to which the PHY daughter card is connected. To set PHY 0 to work in MII mode, jumper the configuration headers as illustrated in Figure 7.
PHY 1 24682468 24682468
J5 J6 J7 J10
13571357 13571357
PHY 0 24682468 24682468
J2 J3 J4 J9
13571357 13571357
P0_CONFIG6
P0_CONFIG2
P0_CONFIG1
P0_CONFIG0
P0_CONFIG4
P0_CONFIG3
P0_CONFIG5 UG065_07_043004
Figure 7: Configuration Headers for PHY 0 in MII Mode
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Table 8: Configuration Settings for MII Mode on PHY 0 Configuration Options Signal Configuration Register Signal CONFIG0 PHYADR = 00000 VSS PHYADR[2:0] = 000 CONFIG1 VSS ENA_PAUSE = 0; PHYADR[4:3] = 00 CONFIG2 Auto-Neg, all capabilities, P0_VDDOH / P1_VDDOH ANEG[3:1] = 111 Master CONFIG3 P0_LED_TX / P1_LED_TX ANEG[0] = 0; ENA_XC = 0; DIS_125 = 1 CONFIG4 GMII to Cu P0_VDDOH / P1_VDDOH HWCFG_MODE[2:0] = 111 CONFIG5 GMII/RGMII/RTBI to Cu P0_LED_LINK100 / DIS_FC=1; DIS_SLEEP=0; P1_LED_LINK100 HWCFG_MODE[3]=1 CONFIG6 50 Ohm P0_LED_RX / P1_LED_RX SEL_BDT = 0; INT_POL = 1; 75/50 OHM = 0
To set PHY 1 to work in MII mode, jumper the configuration headers as illustrated in Figure 8.
P1_CONFIG2
P1_CONFIG1
P1_CONFIG0
P1_CONFIG4
P1_CONFIG3
P1_CONFIG6
P1_CONFIG5 PHY 1 24682468 24682468
J5 J6 J7 J10
13571357 13571357
PHY 0 24682468 24682468
J2 J3 J4 J9
13571357 13571357
UG065_08_043004 Figure 8: Configuration Headers for PHY 1 in MII Mode
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Table 9: Configuration Settings for MII Mode on PHY 1 Configuration Options Signal Configuration Register Signal CONFIG0 PHYADR = 00000 VSS PHYADR[2:0] = 000 CONFIG1 VSS ENA_PAUSE = 0; PHYADR[4:3] = 00 CONFIG2 Auto-Neg, all capabilities, P0_VDDOH / P1_VDDOH ANEG[3:1] = 111 Master CONFIG3 P0_LED_TX / P1_LED_TX ANEG[0] = 0; ENA_XC = 0; DIS_125 = 1 CONFIG4 GMII to Cu P0_VDDOH / P1_VDDOH HWCFG_MODE[2:0] = 111 CONFIG5 GMII/RGMII/RTBI to Cu P0_LED_LINK100 / DIS_FC=1; DIS_SLEEP=0; P1_LED_LINK100 HWCFG_MODE[3]=1 CONFIG6 50 Ohm P0_LED_RX / P1_LED_RX SEL_BDT = 0; INT_POL = 1; 75/50 OHM = 0
References 1. Marvell, Marvell Alaska 88E1111 Data Sheet (Available under NDA) http://www.marvell.com 2. Xilinx, Inc., Virtex-II Pro ML320, ML321, ML323 Platform User Guide 3. IEEE, IEEE Std 802.3, 2002 Edition
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SGMII_RXD_+/-
SGMII_TXD_+/- D D
SNA_CONNECTORS MDI0_+/-
MDI1_+/- RX GMII SIGNALS PORT_0 RX RGMII (GMII SUBSET) RJ45 MDI2_+/- MAGNETICS
PHY_0 MDI3_+/- TX GMII SIGNALS TX RGMII (GMII SUBSET) CONNECTOR
AUX GMII SIGNALS Marvell 88E1111
C C
CONFIGURATION/LEDS
BLOCK
SGMII_RXD_+/-
SGMII_TXD_+/-
SNA_CONNECTORS MDI0_+/-
MDI1_+/- RX GMII SIGNALS PORT_1 B B RX RGMII (GMII SUBSET) RJ45 MDI2_+/- MAGNETICS
PHY_1 MDI3_+/- TX GMII SIGNALS TX RGMII (GMII SUBSET) CONNECTOR
AUX GMII SIGNALS Marvell 88E1111
CONFIGURATION/LEDS
BLOCK AUX_JACK
Title: A Schematic, PHY Daughter PCB, 1280327 5 Vdc 0381166 A 07/11/03 C AUX. POWER SUPPLY Date: Ver: Sheet Size: B Rev: 1.0 GND Sheet 1 of 11 Drawn By SEG
4 3 2 1 4 3 2 1 R92 2 1 R93 P1_TXER 0 2 1 P1_TXCTL_TXEN R94 0 R141 2 1 P1_TXD4 R95 P1_TXD[4:7] P1_RXC_RXCLK 1 2 0 2 1 P1_TXD5 R142 33 R96 P1_RXCTL_RXDV 1 2 2 1 0 P1_TXD6 R97 33 R117 D 0 P1_RCLK1 D 2 1 P1_TXD7 2 1 R98 R143 0 33 2 1 P1_TD_TXD0 P1_TD_TXD[0:3] P1_CRS 1 2 R100 0 33 R144 2 1 P1_TD_TXD1 P1_RXER R99 1 2 0 VCCO_CONN 2 1 P1_TD_TXD2 P1_RD_RXD[0:3] R145 33 R101 0 P1_RD_RXD0 1 2 2 1 P1_TD_TXD3 R102 33 R146 0 2 1 P1_TXC_GTXCLK P1_RD_RXD1 1 2 R147 33 P1_INT 0 P1_RD_RXD2 1 2 HDR_2x32 R148 HDR_2x32 HDR_1x32 1 2 P1_RD_RXD3 33 1 2 1 3 4 1 2 3 4 2 5 6 P1_RXD[4:7] R149 33 5 6 3 7 8 7 8 4 P1_RXD4 9 10 1 2 9 10 5 11 12 33 R150 11 12 6 13 14 P1_RXD5 1 2 13 14 7 15 16 R151 15 16 8 17 18 33 17 18 9 19 20 P1_RXD6 1 2 19 20 10 21 22 33 R152 21 22 11 23 24 P1_RXD7 23 24 12 1 2 C 25 26 25 26 13 C 27 28 33 27 28 14 29 30 R133 29 30 P0_RD_RXD[0:3] P0_RD_RXD0 15 31 32 1 2 31 32 16 R134 33 34 33 33 34 17 35 36 P0_RD_RXD1 1 2 35 36 18 P1_MDC R135 37 38 33 37 38 19 39 40 P0_RD_RXD2 1 2 39 40 20 P1_MDIO 41 42 R136 41 42 21 P0_RD_RXD3 33 43 44 1 2 43 44 22 45 46 P0_RXD[4:7] R137 45 46 23 P0_MDC 47 48 33 47 48 24 P0_RXD4 1 2 49 50 49 50 25 51 52 33 R138 51 52 26 53 54 P0_RXD5 1 2 53 54 27 55 56 55 56 P0_MDIO R139 33 28 SW-PBUTTON 57 58 P0_RXD6 1 2 57 58 29 59 60 59 60 30 2 R140 2 1 61 62 33 61 62 31 63 64 P0_RXD7 1 2 63 64 32 RESET R131 33 0 P0_CRS 1 2 SW1 R113 J15 J16 J8 2 1 33 R130 (ML32X_J56) P0_RXCTL_RXDV 1 2 [ML32X_J50] [ML32X_J55] 0 R118 33 R115 P0_RCLK1 1 2 1 B 33 R132 B 2 P0_RXER 1 2 2 R129 33
0 P0_RXC_RXCLK 1 2 0 R114 33
1 R116 1 P0_INT R106 2 1 P0_COL R107 33 2 1 P1_COL 33 R112 P0_TXD4 2 1 P0_TXD[4:7] P0_VDDO R111 2 1 0 P0_TXD5 R110 0 2 1 P0_TXD6 R1 R109 2 1 2 1 0 P0_TXD7 4.7K 0 R2 P0_TD_TXD0 P0_TD_TXD[0:3] 2 1 P0_TD_TXD1 4.7K R3 Title: A 2 1 P0_TD_TXD2 Schematic, PHY Daughter PCB, 1280327 R4 4.7K 0381166 2 1 P0_TD_TXD3 A R103 Date: 07/11/03 Ver: C 4.7K 2 1 P0_TXC_GTXCLK R104 Sheet Size: B Rev: RESISTERS LOCATED AT 88E1111 PINS P0_TXCTL_TXEN 1.0 0 2 1 R108 Sheet 2 of 11 Drawn By 0 2 1 P0_TXER SEG 0
4 3 2 1 4 3 2 1
P0_VDDO_T
2 2 2 PKG_TYPE=SMA LEVEL=STD 68_NOB PARTS=1 68_NOB 100_NOB J26 1 1 1 DEVICE=CON_SMA_EN R6 R121 R13 D D R128 2 C25 3 P0_SGMII_RX_P 0603 .01 2 1 1 1
1 2 3 P0_SGMII_TX_P 0 2 2
100 R127 C26 P0_SGMII_RX_N 0603 DEVICE=CON_SMA_EN 1 1 .01 J11 2 1 PARTS=1 R14 LEVEL=STD 1 2 PKG_TYPE=SMA
2 0 DEVICE=2_PIN_JUMP PKG_TYPE=SMA J19 PARTS=1 P0_SGMII_TX_N LEVEL=STD LEVEL=STD PARTS=1 PKG_TYPE=2X1_100_MIL_STD 2 2 2 J25 DEVICE=CON_SMA_EN 200_NOB 200_NOB 100_NOB 1 1 1 R8
R7 R9 2 3 1 C 1 C 3 2 1 DEVICE=CON_SMA_EN J12
2 PARTS=1 DEVICE=2_PIN_JUMP LEVEL=STD J20 PARTS=1 PKG_TYPE=SMA LEVEL=STD PKG_TYPE=2X1_100_MIL_STD
P1_VDDO_T
2 2 2 PKG_TYPE=SMA 68_NOB LEVEL=STD 68_NOB 100_NOB PARTS=1 J24 1 1 1 DEVICE=CON_SMA_EN R122 R125 R12
R126
C27 2 3 0603 P1_SGMII_RX_P .01 B 2 1 1 B 1
1 2 3 P1_SGMII_TX_P 0 2 2
100
R11 C28 0603 DEVICE=CON_SMA_EN 1 P1_SGMII_RX_N 1 .01 J13 2 1 PARTS=1 R5 LEVEL=STD 1 2
2 0 PKG_TYPE=SMA DEVICE=2_PIN_JUMP PKG_TYPE=SMA J18 PARTS=1 P1_SGMII_TX_N LEVEL=STD LEVEL=STD PARTS=1 PKG_TYPE=2X1_100_MIL_STD 2 2 2 J23 200_NOB DEVICE=CON_SMA_EN 200_NOB 100_NOB
1 1 1 R123 R124 R10 2 3 1 1 3 2 Title: A 1 Schematic, PHY Daughter PCB, 1280327 DEVICE=CON_SMA_EN 0381166 J14 A
2 PARTS=1 Date: 07/11/03 Ver: C DEVICE=2_PIN_JUMP J17 LEVEL=STD PARTS=1 LEVEL=STD PKG_TYPE=SMA Sheet Size: B Rev: 1.0 PKG_TYPE=2X1_100_MIL_STD Sheet 3 of 11 Drawn By SEG
4 3 2 1 4 3 2 1
1 2 P0_AVDDO PKG_TYPE=1X4_100_MIL_STD LEVEL=STD PARTS=1 1 C5 1 C31 J38 22UF .1UF C 0603 DEVICE=HDR_1X4 DEVICE=FERRITE1 2 2 L1 D D PARTS=1 LEVEL=STD 3.3V_JACK 8 1 PKG_TYPE=SMB20 IN OUT 8 7 4 5 3 SHDN GND1 6 5 3 2 6 1 2 P0_VDDO ADJ GND2 4 3 2 100 2 4 7 10UF NC GND3 2 1 1 C7 1 C33 1 1 C3 22UF .1UF C 0603 DEVICE=FERRITE1 2 2 1 L3 C DEVICE=2X4_JUMPER 2 J31 PARTS=1 DEVICE=LT1963-ADJ PARTS=1 R19 33UF LEVEL=STD LEVEL=STD U1 PKG_TYPE=2X4_100MIL_STD PARTS=1 PKG_TYPE=SMB20 1 C4 LEVEL=STD PKG_TYPE=SO8 1 C30 C 2 2 2 0.1UF 93.1 1 2 0603 P0_VDDOX 2 300 1 C8 1 C34 1 1 22UF .1UF DEVICE=FERRITE1 C 0603 R18 R20 2 2 L4 PARTS=1 C LEVEL=STD C PKG_TYPE=SMB20
1 2 P0_VDDOH
1 C9 1 C79 VCCO_CONN 22UF .1UF C 0603 DEVICE=FERRITE1 2 2 L9 PARTS=1 LEVEL=STD PKG_TYPE=SMB20
1 2 P0_VDDO_T
1 C10 1 C80 VDDO_2_5V C 0603 DEVICE=FERRITE1 2 2 L10 .1UF_NOB PARTS=1 22UF_NOB LEVEL=STD PKG_TYPE=SMB20 B B
8IN OUT1 1 2 P0_DVDD
5SHDN GND13 2 6 ADJ GND2 1 C6 1 C32 2 DEVICE=FERRITE1 1 1 22UF .1UF 1 10UF 4 7 L2 NC GND3 C 0603 0 PARTS=1 2 2 2 2 2 1 C1 LEVEL=STD PKG_TYPE=SMB20 3 3 3 C 1 2 DEVICE=LT1963-ADJ 4 4 4 U2 R16 33UF PARTS=1 LEVEL=STD 1 C2 PKG_TYPE=SO8 1 C29 C 2 2 2 DEVICE=HDR_1X4 DEVICE=HDR_1X4 DEVICE=HDR_1X4 0.1UF 93.1 0603 J35 J36 J37 2 300 PARTS=1 PARTS=1 PARTS=1 LEVEL=STD LEVEL=STD LEVEL=STD PKG_TYPE=1X4_100_MIL_STDPKG_TYPE=1X4_100_MIL_STDPKG_TYPE=1X4_100_MIL_STD 1 1 Title: A R15 R17 Schematic, PHY Daughter PCB, 1280327 0381166 A Date: 07/11/03 Ver: C
Sheet Size: B Rev: 1.0
Sheet 4 of 11 Drawn By SEG
4 3 2 1 4 3 2 1
1 2 P1_AVDDO
1 C17 1 C40 22UF .1UF C 0603 DEVICE=FERRITE1 2 2 L7 D PKG_TYPE=1X4_100_MIL_STD PARTS=1 D LEVEL=STD LEVEL=STD PARTS=1 PKG_TYPE=SMB20 J42 DEVICE=HDR_1X4
1 2 P1_VDDO 3.3V_JACK 8IN OUT1 8 7 4 1 C12 1 C36 5 3 6 5 SHDN GND1 22UF .1UF 3 DEVICE=FERRITE1 C 0603 2 6 4 3 2 2 ADJ GND2 2 L6 100 2 PARTS=1 10UF 4 7 2 1 NC GND3 LEVEL=STD 1 1 C18 PKG_TYPE=SMB20 1 C DEVICE=2X4_JUMPER 2 J32 PARTS=1 DEVICE=LT1963-ADJ R25 33UF LEVEL=STD P1_VDDOX U4 PKG_TYPE=2X4_100MIL_STD 1 2 PARTS=1 1 C16 LEVEL=STD 1 C11 1 C35 1 C39 PKG_TYPE=SO8 C 2 2 2 22UF .1UF 0.1UF 93.1 DEVICE=FERRITE1 C 0603 0603 2 2 2 300 L5 PARTS=1 C LEVEL=STD C 1 1 PKG_TYPE=SMB20 R24 R26
1 2 P1_VDDOH
1 C74 1 C82 22UF .1UF C 0603 DEVICE=FERRITE1 2 2 L11 PARTS=1 LEVEL=STD VCCO_CONN PKG_TYPE=SMB20
1 2 P1_VDDO_T
33UF 1 C75 1 C83
1 C41 C 0603 DEVICE=FERRITE1 2 2 L12 C .1UF_NOB 2 PARTS=1 22UF_NOB LEVEL=STD PKG_TYPE=SMB20 B B
8IN OUT1 1 2 P1_DVDD
5SHDN GND13 2 6 ADJ GND2 1 C13 1 C37 2 DEVICE=FERRITE1 1 1 22UF .1UF 1 10UF 4 7 L8 NC GND3 C 0603 PARTS=1 2 2 2 2 2 1 C14 0 LEVEL=STD PKG_TYPE=SMB20 3 3 3 C 1 2
DEVICE=LT1963-ADJ R22 4 4 33UF 4 U5 PARTS=1 1 C15 LEVEL=STD 1 C38 PKG_TYPE=SO8 C 2 2 2 DEVICE=HDR_1X4 DEVICE=HDR_1X4 DEVICE=HDR_1X4 0.1UF 93.1 0603 J39 J40 J41 2 300 PARTS=1 PARTS=1 PARTS=1 LEVEL=STD LEVEL=STD LEVEL=STD Title: A PKG_TYPE=1X4_100_MIL_STDPKG_TYPE=1X4_100_MIL_STDPKG_TYPE=1X4_100_MIL_STD 1 1 Schematic, PHY Daughter PCB, 1280327
R21 R23 0381166 A Date: 07/11/03 Ver: C
Sheet Size: B Rev: 1.0
Sheet 5 of 11 Drawn By SEG
4 3 2 1 4 3 2 1
D D
VDDO_2_5V
Note: 1 C104 Double Footprint for SMD .1UF 0603 and Half Size Metal Can 2
1N/C VCC8
0 1 2 4GND OUT5 P0_25MHZ
R27 DEVICE=25MHZ_OSC U3 PARTS=1 LEVEL=STD 0 C PKG_TYPE=DIP_8 C 1 2 P1_25MHZ
R28
3.3V_JACK 1
33UF 3 2 B DEVICE=JACK_5V 1 C96 B J33 C PARTS=1 2 LEVEL=STD PKG_TYPE=DJ-005
Title: A Schematic, PHY Daughter PCB, 1280327 0381166 A Date: 07/11/03 Ver: C
Sheet Size: B Rev: 1.0
Sheet 6 of 11 Drawn By SEG
4 3 2 1 4 3 2 1
P0_VDDOH DPLX
2 2 D LINK_10 D 2 LINK_100 LINK_1000 2 249 249 8 7 249 1 1 249 6 5
1 R32 R30 1 4 3 R31 R29
2 1 1 1 1 1 DS2 DS1 DS3 DS4
DEVICE=2X4_JUMPER J3 PARTS=1 LEVEL=STD
2 2 2 2 PKG_TYPE=2X4_100MIL_STD
P0_LED_TX 8 7
P0_LED_LINK1000 6 5
P0_LED_DUPLEX 4 3
2 1
C C
DEVICE=2X4_JUMPER J4 PARTS=1 LEVEL=STD PKG_TYPE=2X4_100MIL_STD 8 7
6 5
4 3
P0_LED_LINK100 2 1
DEVICE=2X4_JUMPER J9 PARTS=1 LEVEL=STD PKG_TYPE=2X4_100MIL_STD
P0_LED_RX 8 7
P0_LED_LINK10 6 5
4 3
2 1
DEVICE=2X4_JUMPER B J2 B PARTS=1 P0_CONFIG1 P0_CONFIG0 LEVEL=STD P0_CONFIG3 P0_CONFIG2 PKG_TYPE=2X4_100MIL_STD P0_CONFIG5 P0_CONFIG4 P0_CONFIG[0:6] P0_CONFIG6
PHY_0 CONFIGURATION (RGMII_CU 1000T) CONFIG SIG DEFAULT FUNCTION SIGNAL CONFIG0 INSTALLED PHYADR=0 VSS
CONFIG0 PHYADR=1 LED_TX
CONFIG1 INSTALLED VSS
CONFIG2 INSTALLED ANEG 1000M LED_LINK100
CONFIG3 INSTALLED ANEG_1000M LED_TX
WARNING CONFIG4 SGMII_CU LED_LINK1000
CONFIG4 INSTALLED RGMII_CU LED_DUPLEX Make sure that only one jumper pair CONFIG4 GMII_CU VDD is active on each of these 7 CONFIG4 RTBI_CU LED_TX Title: A CONFIG4 TBI_CU LED_LINK100 configuration signals Schematic, PHY Daughter PCB, 1280327 CONFIG5 SG/TBI_CU LED_LINK1000 0381166 A CONFIG5 INSTALLED GMII/RGMII LED_LINK100 Date: 07/11/03 Ver: C INSTALLED 50 Ohm CONFIG6 LED_RX Sheet Size: B Rev: 1.0 SPARE LED_LINK100 Sheet 7 of 11 Drawn By SEG
4 3 2 1 4 3 2 1
P1_VDDOH DPLX
2 2 D D LINK_10
2 LINK_100 LINK_1000 2 8 7 249 249
6 5 249 1 1 249
1 R37 R35 1 4 3
R36 R34 2 1 1 1 1 1 DS10 DS11 DS9 DS8
DEVICE=2X4_JUMPER J5 PARTS=1 LEVEL=STD PKG_TYPE=2X4_100MIL_STD 2 2 2 2
P1_LED_TX 8 7
P1_LED_LINK1000 6 5
P1_LED_DUPLEX 4 3
2 1
C C
DEVICE=2X4_JUMPER J6 PARTS=1 LEVEL=STD PKG_TYPE=2X4_100MIL_STD
8 7
6 5
4 3
P1_LED_LINK100 2 1
DEVICE=2X4_JUMPER J10 PARTS=1 LEVEL=STD PKG_TYPE=2X4_100MIL_STD
P1_LED_RX 8 7
P1_LED_LINK10 6 5
4 3
2 1 B B
DEVICE=2X4_JUMPER P1_CONFIG2 P1_CONFIG1 P1_CONFIG0 J7 P1_CONFIG6 P1_CONFIG5 P1_CONFIG4 P1_CONFIG3 PARTS=1 P1_CONFIG[0:6] LEVEL=STD PKG_TYPE=2X4_100MIL_STD
CONFIG SIG DEFAULT FUNCTION SIGNAL
CONFIG0 INSTALLED PHYADR=0 VSS PHY_1 CONFIGURATION (SGMII_CU 1000T) CONFIG0 PHYADR=1 LED_TX CONFIG1 INSTALLED VSS
CONFIG2 INSTALLED ANEG 1000M LED_LINK100
CONFIG3 INSTALLED ANEG_1000M LED_TX WARNING CONFIG4 INSTALLED SGMII_CU LED_LINK1000 CONFIG4 RGMII_CU LED_DUPLEX Make sure that only one jumper pair CONFIG4 GMII_CU VDD CONFIG4 RTBI_CU LED_TX Title: A is active on each of these 7 Schematic, PHY Daughter PCB, 1280327 CONFIG4 TBI_CU LED_LINK100 configuration signals 0381166 CONFIG5 INSTALLED SG/TBI_CU LED_LINK1000 A Date: 07/11/03 Ver: C CONFIG5 GMII/RGMII LED_LINK100 Sheet Size: B Rev: 1.0 CONFIG6 INSTALLED 50 Ohm LED_RX Sheet of Drawn By SPARE LED_LINK100 8 11 SEG
4 3 2 1 4 3 2 1
P0_VDDO
2 2 2 2 2 2 2 2 P0_DVDD 1DVDD_1 VDDO_9696 P0_VDDO 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K 4.7K 2 95 P0_RD_RXD0 4.7K RXCLK RXD0 1 1 1 1 1 1 1 1 3RXER RXDV94 P0_RXCTL_RXDV
P0_RCLK1 R54 R53 R52 R50 R49 R48 R46
R47 4 93 P0_RD_RXD2 D TXCLK RXD2 D P0_RXC_RXCLK 5VDDO_5 RXD192 P0_RD_RXD1 P0_RXER P0_RD_RXD[0:3] 6DVDD_6 RXD391 P0_RD_RXD3
P0_TXER 7TXER RXD490 P0_RXD4
P0_TXC_GTXCLK 8GTXCLK RXD589 P0_RXD5
P0_TXCTL_TXEN 9TXEN VDDO_8888
10DVDD_10 RXD687 P0_RXD6 P0_TD_TXD[0:3] P0_RXD[4:7] P0_TD_TXD0 11TXD0 RXD786 P0_RXD7
P0_TD_TXD1 12TXD1 DVDD_8585 P0_DVDD
13N/C_13 CRS84 P0_CRS
P0_TD_TXD2 14TXD2 COL83 P0_COL
15DVDD_15 RXP82 P0_SGMII_TX_P
P0_TD_TXD3 16TXD3 RXN81 P0_SGMII_TX_N
P0_TXD4 17TXD4 TCN80 P0_SGMII_RX_P C P0_TXD5 18TXD5 TCP79 C P0_SGMII_RX_N P0_TXD6 19TXD6 AVDD_7878 P0_AVDDO P0_TXD[4:7] P0_TXD7 20TXD7 TXP77
P0_VDDO 21VDDO_21 LED_LINK1076 P0_LED_LINK10 R105 22CLK125 TXN75 P0_VDDOX 2 1 R154 2 1 P0_INT 23 74 P0_LED_LINK100 4.7K INT LED_LINK100 4.7K P0_MDIO 24MDIO LED_LINK100073 P0_LED_LINK1000
P0_MDC 25MDC VDDOH_7272 P0_VDDOH RESET 26 71 R119 VDDOX_26 DVDD_71 2 1 27COMMA LED_DPLX70 P0_LED_DUPLEX 4.7K 28RESET LED_RX69 P0_LED_RX 1 C19 P0_AVDDO 1 C57 1 C55 1 C54 1 C53 P0_MDIP0 29 68 P0_LED_TX 1 C56 MDIP_0 LED_TX C 2 0603 0603 0603 0603 2 2 2 2 30 67 0603 RSET DVDD_67 10UF 2 1 C97 .01 .01 .1 .1 1000PF 1 C107 1 C106 1 C108 1 C109 P0_MDIN0 31 66 10UF MDIN_0 VDDOH_66 P0_CONFIG[0:6] C B 0603 0603 0603 0603 2 B P0_AVDDO 32AVDD_32 CONFIG065 P0_CONFIG0 2 2 2 2 .1 .01 .1 1000PF P0_MDIP1 33MDIP_1 CONFIG164 P0_CONFIG1 P0_MDIN1 34 63 P0_CONFIG2 5K 1% MDIN_1 CONFIG2 1 2 P0_RSET 35AVDD_35 DVDD_6262 36 61 P0_CONFIG3 P0_VDDOH AVDD_36 CONFIG3 P0_DVDD R45 P0_HDACP 37 60 P0_CONFIG4 1 2 HSDACP CONFIG4
DEVICE=2_PIN_JUMP J21 PARTS=1 LEVEL=STD PKG_TYPE=2X1_100_MIL_STD P0_HDACM 38 59 P0_CONFIG5 HSDACN CONFIG5 1 C20 1 C49 1 C50 1 C51 1 C45 1 C46 1 C47 1 C44 1 C43 1 C42 10UF P0_MDIP2 39 58 P0_CONFIG6 MDIP_2 CONFIG6 C 0603 0603 0603 2 0603 0603 0603 0603 0603 0603 2 2 2 2 2 2 2 2 2 40AVDD_40 DVDD_5757 1000PF .01 .1 .01 .1 .01 .1 1000PF 1000PF P0_MDIN2 41MDIN_2 SEL_OSC56 P0_SEL_OSC
P0_MDIP3 42MDIP_3 XTAL155 P0_25MHZ P0_MDIN3 43 54 4.7K MDIN_3 XTAL2 2 1 2 P0_TDI 44 53 P0_VDDOX TDI VSSC
45AVDD_45 VDDOH_5252 Title: A R44 4.7K Schematic, PHY Daughter PCB, 1280327 1 2 P0_TMS 46 51 1 C21 TMS N/C 4.7K 1 1 C52 1 C48 4.7K 0381166 P0_TRST 47 50 P0_TDO 1 2 R55 A C 4.7K TRST TDO 2 0603 0603 R43 Date: 07/11/03 Ver: C 2 2 1 2 48VDDOX_48 TCK49 P0_TCK R40 .01 .1 Sheet Size: B Rev: 10UF P0_VDDOX 1.0 4.7K R42 P0_VDDOX 1 2 Sheet 9 of 11 Drawn By SEG R41 DEVICE=M88E1111 U6 4 3 2 1 PARTS=1 LEVEL=STD PKG_TYPE=BCC_96 4 3 2 1
P1_VDDO 2 2 2 2 2 2 2 2 2 2 2 2 P1_DVDD 1DVDD_1 VDDO_9696 P1_VDDO 2 95 P1_RD_RXD0 4.7K RXCLK RXD0 R65 R66 R62 R63 R61 R60 R59 R68 R56 1 1 1 R57 R58 1 1 1 1 1 1 1 1 1 3RXER RXDV94 P1_RXCTL_RXDV R64 4TXCLK RXD293 P1_RD_RXD2 4.7K 4.7K
D 4.7K 4.7K 4.7K D 4.7K 4.7K 4.7K 4.7K P1_RXC_RXCLK 4.7K 4.7K 5VDDO_5 RXD192 P1_RD_RXD1 P1_RD_RXD[0:3] P1_RXER 6DVDD_6 RXD391 P1_RD_RXD3
P1_TXER 7TXER RXD490 P1_RXD4
P1_TXC_GTXCLK 8GTXCLK RXD589 P1_RXD5
P1_TXCTL_TXEN 9TXEN VDDO_8888 P1_RCLK1 10DVDD_10 RXD687 P1_RXD6 P1_TD_TXD[0:3] P1_RXD[4:7] P1_TD_TXD0 11TXD0 RXD786 P1_RXD7
P1_TD_TXD1 12TXD1 DVDD_8585 P1_DVDD
13N/C_13 CRS84 P1_CRS
P1_TD_TXD2 14TXD2 COL83 P1_COL
15DVDD_15 RXP82 P1_SGMII_TX_P
P1_TD_TXD3 16TXD3 RXN81 P1_SGMII_TX_N
P1_TXD4 17TXD4 TCN80
P1_TXD5 18TXD5 TCP79 P1_SGMII_RX_P C C P1_TXD6 19TXD6 AVDD_7878 P1_AVDDO P1_SGMII_RX_N P1_TXD[4:7] P1_TXD7 20TXD7 TXP77
P1_VDDO 21VDDO_21 LED_LINK1076 P1_LED_LINK10 22 75 4.7K CLK125 TXN 1 2 4.7K P1_INT 2 1 P1_VDDOX 23INT LED_LINK10074 P1_LED_LINK100 R67 R153 24 73 P1_LED_LINK1000 P1_MDIO MDIO LED_LINK1000 25 72 P1_VDDOH P1_MDC MDC VDDOH_72
RESET 26VDDOX_26 DVDD_7171 4.7K 1 2 27COMMA LED_DPLX70 P1_LED_DUPLEX R120 28 69 P1_LED_RX 1 C23 RESET LED_RX P1_AVDDO 1 C65 1 C67 1 C64 1 C63 1 C66 P1_MDIP0 29 68 P1_LED_TX C MDIP_0 LED_TX 2 0603 0603 0603 0603 2 2 2 2 0603 30 67 10UF 2 RSET DVDD_67 1 C98 .01 .01 .1 .1 1000PF 1 C111 1 C110 1 C112 1 C113 10UF P1_MDIN0 31 66 MDIN_0 VDDOH_66 C P1_CONFIG[0:6] 0603 0603 0603 0603 2 2 2 2 2 P1_AVDDO 32AVDD_32 CONFIG065 P1_CONFIG0 B .1 .01 .1 1000PF B P1_MDIP1 33MDIP_1 CONFIG164 P1_CONFIG1 P1_MDIN1 34 63 P1_CONFIG2 5K 1% MDIN_1 CONFIG2 1 2 P1_RSET 35AVDD_35 DVDD_6262 36 61 P1_CONFIG3 P1_VDDOH AVDD_36 CONFIG3 P1_DVDD R75 P1_HDACP 37 60 P1_CONFIG4 1 2 HSDACP CONFIG4
DEVICE=2_PIN_JUMP J22 PARTS=1 LEVEL=STD PKG_TYPE=2X1_100_MIL_STD P1_HDACM 38 59 P1_CONFIG5 HSDACN CONFIG5 1 C24 1 C70 1 C69 1 C68 1 C60 1 C58 1 C73 1 C72 1 C71 1 C59 P1_MDIP2 39 58 P1_CONFIG6 MDIP_2 CONFIG6 C 0603 0603 0603 2 0603 0603 0603 0603 0603 0603 2 2 2 2 2 2 2 2 2 40AVDD_40 DVDD_5757 .01 .1 .01 .1 1000PF 1000PF 1000PF .01 .1 10UF P1_MDIN2 41MDIN_2 SEL_OSC56 P1_SEL_OSC
P1_MDIP3 42MDIP_3 XTAL155 P1_25MHZ
P1_MDIN3 43MDIN_3 XTAL254 4.7K 2 1 2 P1_TDI 44 53 P1_VDDOX TDI VSSC
45AVDD_45 VDDOH_5252 R74 4.7K Title: A 1 2 P1_TMS 46 51 4.7K 1 1 C22 TMS N/C Schematic, PHY Daughter PCB, 1280327 1 C61 1 C62 4.7K R70 P1_TRST 47 50 P1_TDO 1 2 0381166 C TRST TDO 2 0603 0603 4.7K R73 A 2 2 1 2 48VDDOX_48 TCK49 P1_TCK R69 Date: 07/11/03 Ver: C .01 .1 10UF 4.7K Sheet Size: B Rev: 1.0 R72 P1_VDDOX 1 2 Sheet of Drawn By 10 11 R71 P1_VDDOX DEVICE=M88E1111 SEG U7 PARTS=1 4 3 2 1 LEVEL=STD PKG_TYPE=BCC_96 A B C D P1_MDIP0 P1_MDIN0 P1_MDIP1 P1_MDIN1 P1_MDIP2 P1_MDIN2 P1_MDIP3 P1_MDIN3 P0_MDIP0 P0_MDIN0 P0_MDIP1 P0_MDIN1 P0_MDIP2 P0_MDIP3 P0_MDIN3 P0_MDIN2 4 4
.01 1 C84 .01 1 C86 .01 1 C81 .01 1 C77 .01 1 C76 .01 1 C87 .01 1 C85 .01 1 C78 0603 0603 0603 0603 2 2 2 0603 2 0603 0603 2 2 2 0603 2 1 1 1 1 1 1 1 49.9 1 1 49.9 49.9 49.9 1 49.9 49.9 1 49.9 1 49.9 49.9 1 1 1 49.9 R84 R76 R78 49.9 R88 49.9 1 49.9 R82 R77 49.9 R79 49.9 R33 R83 49.9 R38 R86 R51 R39 R85 R80 R81 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 P1_AVDDO P0_AVDDO P1_LED_TX P1_LED_RX P0_LED_RX P0_LED_TX 10A 10B 2A 1A 4A 3A 6A 5A 8A 7A 9A 2B 1B 4B 3B 6B 5B 8B 7B 9B PKG_TYPE=RJ45_CUSTOM LEVEL=STD PARTS=1 J1 DEVICE=JG065Y729C CHB_GND MX_0B_P MX_0B_N MX_1B_P MX_1B_N MX_2B_P MX_2B_N MX_3B_P MX_3B_N VCT_B CHA_GND MX_0A_P MX_0A_N MX_1A_P MX_1A_N MX_2A_P MX_2A_N MX_3A_P MX_3A_N VCT_A 2 2
13ARA_LEDC RB_LEDC13B
14ARA_LEDA RB_LEDA14B
11ALA_LEDC LB_LEDC11B
12ALA_LEDA LB_LEDA12B Sheet Sheet Size:B Date: SHEILD Title: Schematic, PHYDaughterPCB, 1280327 SH 07/11/03 11 FGND1 PARTS=1 DEVICE=FRAME_GND of 1 2 2 2 0381166 2
249 249 249
11 249 1 R90 1 1 R91 R89 1 R87 1 1 P1_VDDOH Drawn By Rev: Ver: SEG P0_VDDOH 1.0 C A B C D