New Technology Development Tools

SPECCTRAQuest MGT Design Kit Pre-configured circuits in the design kits are ready to simulate for both typical MGT Get up to chip-to-chip and backplane PCB interfaces. There’s no time wasted hunting for models, testing and correlating them, or figuring out how to connect them together. It has all been done for you. And because the simulation Multi-Gigabit environment is graphical, adapting the cir- cuits for your unique application is as simple as dragging and dropping. Better yet, the models of the active Rocket I/O MGT circuitry are transistor-level sili- Speed with the con models that have been correlated by Xilinx to match both the actual silicon design and empirical data. This ensures that your system implementation is designed with the most advanced and accurate mod- SPECCTRAQuest els available. Add to that fully coupled fre- quency-dependent lossy package, PCB trace, and connector models, and you’re ready to carefully characterize the signal integrity and degradation issues that are Design Kit inherent in this type of design. Figure 1 shows a pre-configured simulation drawing for chip-to-chip applications. Learn how to implement Rocket I/O multi-gigabit Although this is actually a 500+ node simu- lation, it has been simplified through the use serial transceivers in the new Virtex-II Pro Platform FPGA. of subcircuits and black box models so it can be more easily modified. Just point and click to change trace parameters, physical connec- tions, or other aspects of the circuit. by Donald Telian high-speed FPGA into your system of Technologist When your simulations are done and it’s printed circuit boards (PCBs)? Cadence Design Systems time to layout your PCB, the MGT kit has [email protected] In an effort to avoid multi-gigabit sample footprints and constraint files to headaches, Xilinx and Cadence Design ensure a successful layout. It is essential to Mark Alexander Systems have assembled bind all high-speed constraints into your Product Application Engineer SPECCTRAQuest™ Xilinx, Inc. MGT Design Kits to [email protected] help you implement the With the introduction of the new Virtex-II new Rocket I/O MGTs Pro™ FPGAs, high-speed Rocket I/O™ effectively in your sys- serial transceivers are ready to find their tem. Whether you need to way into hundreds of new applications. Are craft a custom MGT interface you ready? What used to be confined to a and develop your own few exotic chips, laden with pages and PCB/backplane/cabling guide- pages of design and implementation guide- lines, or you simply need to lines, is now available to everyone. Xilinx apply your MGTs in a stan- has made it possible to integrate multi- dard configuration, the kit gigabit transceivers (MGTs) into your gets you moving towards a Figure 1 - Example of FPGA, but how will you integrate that solution within minutes. chip-to-chip simulation topology

00 Xcell Journal Spring 2002 New Technology Development Tools

MGT Design & Implementation Flow Obtain SPECCTRAQuest With both the SPECCTRAQuest software & Xilinx and MGT design kit in place, you’re ready to Design Kit exercise the advanced, high-speed design flow shown in Figure 2 to ensure your MGTs are Layout Constraint- implemented correctly. Pre-Route Post-Route Constraint Driven Simulation Simulation Derivation High-Speed The flow begins by configuring a simulation Analysis Verification & Capture PCB Layout of your unique application. Use the pre- configured topologies in the design kit as a starting point. Simulate your application Manufacture pre-route by sweeping through all the imple- Assemble mentation options and manufacturing Figure 2 - High-speed PCB design flow Test PCB tolerances to ensure that the multi-gigabit signals are transmitted and received within PCB database to automate and properly con- These measurements can be sorted so you tolerances. Use the test patterns and post-pro- strain the layout process. If you don’t bind can quickly select the best configuration. cessing tools in the kit to help with this phase. your constraints, your layout, post-layout After you have determined the best Once an acceptable solution is found, cap- simulation, and actual system behavior will implementation configuration, you can ture the layout constraints in electronic not be as clean as you would want. use Cadence’s powerful constraint man- topologies that can be bound into the layout To help you along the learning curve associ- agement (CM) tool to electronically cap- process. Once again, you can use the kit ated with designing multi-gigabit links, the ture and manage your layout constraints. examples to learn how. Perform constraint- kits also contain tutorial “movies” you can The CM tool interacts with the other driven layout, and then do post-layout sim- run on your PC to clearly illustrate how to Connected Team Design Tools (including ulation on the routed nets to verify that use the various aspects of the kit throughout Concept HDL, Allegro, SPECCTRA™, signal transmission is still within tolerance. your design process. and SPECCTRAQuest) to enable your If the layout constraints were applied and whole design team to work concurrently followed, this will be a simple verification SPECCTRAQuest’s Features and share data. step. If a problem is found, the differential SPECCTRAQuest is an integrated net can be extracted to an electrical view to design tool that allows you to include more easily identify the cause of failure, as both your MGT silicon models and shown in Figure 3. PCB databases in one simulation. You Conclusion can easily set up extensive “sweep” sim- ulations to sweep circuit variables Although using MGTs in your through a range of values to test out dif- high-speed design can bring high- ferent implementation options. er performance to your FPGA Simulation of trace parameter varia- application, you must be careful tions (such as loss tangents, skin effect, in performing the implementa- dielectric constant, and other varia- tion. By correctly using the tions), crosstalk, power noise, deter- SPECCTRAQuest MGT Design ministic/random jitter, and other effects Kit assembled for this task, you are all included. can avoid common problems and shorten your design cycle. The kit Stimulate your circuit with pre-coded includes layout guidelines, con- 8b/10b pseudo-random bit sequence Figure 3 - Simulation from layout and extracting a differential net straints, topologies, scripts, and (PRBS) patterns to create inter-symbol utilities that will help you inte- interference (ISI) and study its effect on sig- SPECCTRAQuest has a unique way of grate Rocket I/O MGTs into your high-speed nal integrity. With the push of a button, you superimposing advanced simulation on top Virtex-II Pro designs. can plot the resulting waveform as an eye of high-speed PCB layout. For more infor- diagram so you can quickly quantify the sig- mation on the features available in The MGT design kit is available for free nal degradation from transmitter to receiver. SPECCTRAQuest and other Cadence PCB download from the Spice Suite at www.xil- SPECCTRAQuest also provides automated tools, please refer to www.specctraquest.com inx.com. Registration is required if you are measurements of each circuit’s performance. and pcb.cadence.com. not already a Xilinx customer

Spring 2002 Xcell Journal 00