USOO5832279A United States Patent (19) 11 Patent Number: 5,832,279 ROStoker et al. (45) Date of Patent: Nov. 3, 1998 54 ADVANCED PROGRAMMABLE INTERRUPT 5,669,003 9/1997 Carmean et al. .................. 395/750.04 SNESIC) WITH HIGH SPEED OTHER PUBLICATIONS * LSI Logic, Serial linkTM SL300 High-Speed Serializer/ (75) Inventors: Michael D. Rostoker, Boulder Creek, Deserializer Technical Manual, May 1995. Calif.; Sushant Verman, Mississauga, Canada; Richard Egan, San Carlos; Primary Examiner—Ayaz R. Sheikh Jerry Chow, Sunnyvale, both of Calif. ASSistant Examiner Jigar Pancholi Attorney, Agent, or Firm-Oppenheimer Wolfe & Donnelly 73 Assignee: LSI Logic Corporation, Milpitas, LLP Calif. 57 ABSTRACT 21 Appl. No.: 863,373 A high speed Advanced Programmable Interrupt Controller (APIC) system includes a plurality of local units for priori 22 Filed: May 27, 1997 tizing and passing interrupts, an Input/Output (I/O) unit for feeding interrupts to the local units, and a Serial link data Related U.S. Application Data transmission System for interconnecting the I/O unit and the local units. The I/O unit and each local unit have a parallel 63 Continuation of Ser. No. 485,528, Jun. 7, 1995, abandoned. I/O interface. The Serial link transmission System includes a (51) Int. Cl." ........................................................ G06F 9/46 parallel signal bus connected to the parallel I/O interface of 52 U.S. Cl. ............................................. 395/739, 395/741 the I/O unit; a plurality of first serial link transceivers having 58 Field of Search ...................................... 395/733-742 parallel I/O interfaces connected to the parallel Signal bus, and Serial I/O interfaces respectively; a plurality of Second 56) References Cited Serial link transceivers having parallel I/O interfaces con nected to the parallel I/O interfaces of the local units, and U.S. PATENT DOCUMENTS Serial I/O interfaces respectively; and a plurality of Serial 4,992,981 2/1991 Ganssloser et al. .................... 365/154 transmission lines interconnecting the Serial I/O interfaces of 5,260.60s 11/1993 Marbot ................. ... 307/262 first serial link transceivers and the serial I/O interfaces of 5,268,937 12/1993 Marbot ......... ... 375/121 Second Serial link transceivers respectively. 5,511,200 4/1996 Jayakumar ........... ... 395/739 5,651,137 7/1997 MacWilliams et al. ................ 395/468 10 Claims, 3 Drawing Sheets f 4-1 PROCESSOR 4-1 PROCESSOR 14 PROCESSOR N 26 N 26 N 26 22 S 24 22 24 22 12 APIC 12 APIC 12 APIC LOCAL UNIT LOCAL UNIT LOCAL UNIT 34 38 54 38 J4 38 SERIAL LINK SERIAL LINK SERIA LINK 36 36 32 32 36 SERIAL LINK SERIAL LINK SERIAL LINK 301 32 t——i- A apic 16 I/O UNII 18 U.S. Patent Nov. 3, 1998 Sheet 1 of 3 5,832,279 4-1 PROCESSOR 4-1 PROCESSOR 14-1 PROCESSOR N 26 N 26 N 26 22 24 22 N 24 22 N 24 f 2 APIC 12 APIC 12 APIC LOCAL UNIT LOCAL UNIT LOCAL UNIT 34 38 4 38 34 38 SERIAL LINK SERIAL LINK SERIAL LINK 36 36 32 32 36 30 1. 4 4 20 As Apic 16 I/O UNII 18 FIG. 1 U.S. Patent Nov. 3, 1998 Sheet 2 of 3 5,832,279 6 40 R 42 46 18 20 EDGE REDIRECTION ICC BUS C. SENSE IABLE INIERFACE COWIROL LOGIC AND F.| G. 2 REGISIERS 44 24 PRIORITIZER 22 VECTOR ARRAY COWIROL WECTOR LOGIC DECODE AND 58 REGISTERS ACCEPIANCE LOGIC ICC BUS 50 INIERFACE 38 U.S. Patent Nov. 3, 1998 Sheet 3 of 3 5,832,279 FIG. 4 - 70 72 SERIAL LINK SERIAL LINK SERIAL LINK is APIC HU- I/O UNIT 14 PROCESSOR 26 22 N 24 APIC CAL SERIAL LINK 38 SERIAL 34 LINK FIG. 5 5,832,279 1 2 ADVANCED PROGRAMMABLE INTERRUPT lands or wires Such as a computer back plane or the like. The CONTROLLER (APIC) WITH HIGH SPEED close proximity of many parallel Signals having to drive a SERALDATABUS capacitive bus that may not be impedance matched creates Signal crosstalk. RELATED APPLICATIONS Signal crosstalk further restricts the effective data rate and This application is a continuation of U.S. patent applica number of digital devices that may be effectively intercon tion Ser. No. 08/485,528 filed Jun. 7, 1995 now abandoned. nected in an electronic System. Yet another problem is connecting these parallel high bit BACKGROUND OF THE INVENTION capacity buses to the IC packages and then routing the physically wide parallel buses between the various IC pack 1. Field of the Invention ages on the electronic System Substrate or printed circuit The present invention generally relates to the art of very board. Sockets for the IC packages and connectors for large integrated circuits, and more Specifically to An peripheral printed circuit boards are expensive because of Advanced Programmable Interrupt Controller (APIC) with a the large number of connections required. high Speed Serial data bus. 15 Similarly, leaded IC packages Such as, for example, Tape 2. Description of the Related Art Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Semiconductor devices Such as integrated circuits have Ball Grid Array (BGA) packages require expensive equip revolutionized the field of electronics by making possible a ment and complex procedures to accurately align the leads/ level of technological Sophistication unknown in the days of balls on the Substrate or board conductive land pattern. Vacuum tubes and even discrete transistors. An Integrated AS used herein, the term "semiconductor device' refers to circuit die may comprise, on a Small Silicon chip, many a Silicon chip or die containing electronic circuitry and is thousand or even a million or more transistors intercon more commonly referred to as a "semiconductor integrated nected together to form complex electronic functions. The circuit' or “integrated circuit.” The term “semiconductor complex electronic functions of the integrated circuit chip device assembly' or “integrated circuit assembly” refers to may require hundreds of external connections to a related 25 the Silicon die and associated packaging containing the die, electronic System. including conductive leads, Such as ball bump, pins, Surface Increases in electronic System performance, and the mount gull wing and J leads, conductive tabs or balls at the requirement to run complex computer Software programs periphery of a package and/or on the interior of a Surface or with a corresponding increase in memory requirements, the like, for connecting to a System circuit board, and have dramatically increased the data throughput or “band internal connections of the die to the conductive leads Such width' requirements of, for example, a computer System's as bond wires, flip-chip or Tape Automated Bonding (TAB). memory and especially logic functions. At the same time, The term “semiconductor device assembly' or “integrated improvements in Silicon integrated circuit technology have circuit assembly' may also refer to the silicon die and made it possible to integrate more and more logic functions asSociated leadframe Such as a tape carrier or package-leSS onto a single integrated circuit chip. The advancements in 35 Silicon die on a leadframe which may be encapsulated or not. technology and the corresponding utilization thereof have The leadframe is connected to the package-leSS Silicon die as created the need for integrated circuit packages having is well known to those skilled in the art of semiconductor Input/Output (I/O) capacity requirements of over 500 exter devices. nal connections. What is needed is a method and system for reducing the Simple function integrated circuits have been packaged in 40 required number of input-output pins necessary for commu ceramic packages for high reliability industrial and military nicating between complex integrated circuits that require applications and in lower cost molded plastic packages for high data throughput and are contained in Simple and commercial and consumer products. Recently, Very Large inexpensive integrated circuit assemblies. Scale Integration (VLSI), Ultra Large Scale Integration 45 An interrupt is a signal which causes a processor to (ULSI), and the like Integrated Circuits (IC) have outgrown Suspend its current operation in an orderly manner, and the connection capacity of traditional ceramic or molded initiate another operation designated by an associated inter plastic packaging Systems because of the large number of rupt vector which constitutes a Starting address for Stored external connections required. program code which controls the processor to perform the The IC packaging industry has therefore developed more 50 operation designated by the interrupt vector. Sophisticated IC packages to accommodate the increased If Several processors are capable of Servicing an interrupt, number of external connections required to be made to the and no specific processor is designated, Some method of asSociated electronic System. These IC packages, however, assigning a processor to Service the interrupt is required. are expensive, difficult to fabricate, may require expensive Typically, an auxiliary processor is provided for the Sole Sockets and take up a lot of valuable electronic System 55 purpose of processing, prioritizing and distributing circuit board area. In addition, IC packaging technology has interrupts, thereby introducing delays into the overall opera not been able to keep up with the rapidly increasing com tion of the System. If the interrupts cannot be processed fast plexity and Sophistication of integrated circuit technologies. enough, data overrun, data loss, and/or System malfunction This lag in IC packaging technology has limited the Cal OCC. ability of the electronic circuit designer to utilize the full 60 An Advanced Programmable Interrupt Controller (APIC) capabilities of present and future IC technologies in an easy System or equivalent would overcome this problem. An to implement and cost effective way. APIC system comprises a plurality of local units for priori Another problem with IC packaging is the close proximity tizing and passing interrupts to processors or other devices, in Spacing of Signal connections that carry parallel data and an Input/Output (I/O) unit for feeding interrupts to Signals.