iSBC 220™ SMD DISK CONTROLLER HARDWARE REFERENCE MANUAL
Manual Order Number: 121597-001, REV A
Copyright © 1980 Intel Corporation I Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051 I Additional copies of this manual or other Intel literature may be obtained from: Literature Department Intel Corporation 3065 Bowers Avenue Santa Clara, CA 95051 The information in this document is subject to change without notice. Intel Corporation makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Intel Corporation assumes no responsibility for any errors that may appear in this document. Intel Corporation makes no commitment to update nor to keep current the information contained in this document. Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subject to restrictions stated in Intel's software license, or as defined in ASPR 7-104.9(a)(9). No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Intel Corporation. The following are trademarks of Intel Corporation and its affiliates and may be used only to identify Intel products:
BXP Intel Megachassis CREDIT Intelevision Micromap i Intellec Multibus ICE iRMX Multimodule iCS iSBC PROMPT im iSBX Promware Insite Library Manager RMXlBO Intel MCS System 2000 UPI pScope
and the combination of ICE, iCS, iRMX, iSBC, iSBX, MCS, or RMX and a numerical suffix. ii CONTENTS
CHAPTER 1 Page Page GENERAL INFORMATION Interrupts ...... 3·20 Introduction 1·1 Example Controller I/O Program ...... 3·20 Description ...... 1·1 Specifications ...... 1·2 CHAPTER 4 PRINCIPLES OF OPERATION Introduction ...... 4·1 CHAPTER 2 Schematic Interpretation ...... 4·1 PREPARATION FOR USE Functional Overview ...... 4·1 Introduction ...... 2·1 Detailed Functional Description ...... 4·5 Unpacking and Inspection ...... 2·1 Controller to Host Communications ...... 4·5 Board Installation Considerations ...... 2·1 Multibus Interface ...... 4·6 Power Requirement ...... 2·1 8089 I/O Processor (lOP) ...... 4·6 Cooling Requirement ...... 2·2 Clock Circuit ...... 4·6 Multibus Connector ...... 2·2 Bus Arbiter ...... 4·6 Switch/Jumper Configurations ...... 2·6 Bus Controller Logic ...... 4·6 Wake· U p Address Selection ...... 2·6 Multibus Interface Wake·Up I/O Port Address Selection ...... 2·6 Data Transfer Logic ...... 4·8 System Data Bus Selection ...... 2·7 Controller Initialization ...... 4·8 Interrupt Priority Level ...... 2·7 Wake-Up Address Comparator ...... 4·8 Any Request Selection ...... 2·7 Controller Reset and Clear ...... 4·9 Voltage Selection ...... 2· 7 Establishing A Linlv With Drive Interface ...... 2·7 I/O Communications Blocks ...... 4·9 Cabling Requirements ...... 2·7 Interrupt Priority Logic ...... 4·11 Drive Pin Assignments ...... 2·7 Local Memory Map ...... 4·11 Single Drive Installations ...... 2·7 ROM ...... 4·11 Multiple Drive Installations ...... 2·7 RAM ...... 4·11 Power Up/Down Considerations ...... 2·9 Local Memory Mapped I/O Ports ...... 4·11 Diagnostic Check ...... 2·9 Controller to Disk Drive Communications ..... 4·12 Controller to Disk Drive Interface ...... 4·12 CHAPTER 3 Control Cable Signals ...... 4·12 PROGRAMMING INFORMATION Selection Lines ...... 4·12 Introduction ...... 3·1 Function Tags and Bus·Out Lines ...... 4·13 Disk Organization ...... 3·1 Status lines ...... 4·15 Track Sectoring Format ...... 3·2 Read/Write Cable Signals ...... 4·16 Controller I/O Communications Blocks ...... 3·2 Controller to Disk Drive Interface Timing ..... 4·16 Host CPU·Controller·Disk Drive Interaction .... 3·3 DMA Mode ...... 4·17 Wake·Up I/O Port ...... 3·3 Disk Formatting ...... 4·18 Wake·Up Block ...... 3·4 Write Data Transfer ...... 4·19 Channel Control Block ...... 3·4 Read Data Transfers ...... 4·20 Controller Invocation Block ...... 3·4 SER/DES Logic ...... 4·20 I/O Parameter Block ...... 3·4 Sync Byte Comparator Logic ...... 4·21 Typical Controller Operations ...... 3·5 32·Bit ID Comparator Logic ...... 4·21 Initializing the Controller ...... 3·5 ECC Generator Logic ...... 4·22 Track Formatting ...... 3·10 Status Register Logic ...... 4·22 Alternate and Defective Track Handling ..... 3·10 Line Drivers and Receivers ...... 4·22 Data Transfer and Verification ...... 3·10 CHAPTER 5 Read Sector ID ...... 3·12 SERVICE INFORMATION Read Data ...... 3·12 Introduction ...... 5·1 Read Data Into Controller Buffer and Verify 3·14 Service Diagrams ...... 5·1 Write Data ...... 3·15 Service and Repair Assistance ...... 5·1 Write Data from Controller Buffer to Disk '" 3·15 Self Diagnostic ...... 5·1 Initiate Track Seek ...... 3·16 Replaceable Components ...... 5-1 Buffer I/O ...... '...... 3·16 Diagnostic ...... 3·17 APPENDIX A Posting Status ...... 3·18 EXAMPLE HOST PROCESSOR Transfer Error Status ...... 3·19 DISK CONTROL PROGRAM
iii TABLESi
Table Title Page Table Title Page 1-1. Board Specifications ...... 1-2 3-2. Error Status Buffer ...... 3-20 1-2. Drive Characteristics (Typical) ...... 1-3 3-3. Bit Functions in Hard 2-1. Multibus Connector PI Pin Assignment 2-2 and Soft Error Bytes ...... 3-21 2-2. iSBC 220 Controller/Multibus 4-1. 8089 Status Line Decodes ...... 4-8 Interface Signal Descriptions ...... 2-3 4-2. Host Wake-Up Commands ...... 4-9 2-3. iSBC 220 Controller/Multibus 4-3. Local 110 Ports ...... 4-12 Interface Signal Characteristics ...... 2-3 4-4. Function Tag/Bus-Out Definitions .... 4-13 2-4. Configuration Linkages and Switches .. 2-6 4-5. Control Tag' and Bus Out Functions .. 4-14 2-5. Interrupt Priority Level Selection .,.... 2-9 4-6. Status Line Definitions ...... 4-15 2-6. Control Cable Signal/Pin List ...... 2-9 4-7. Status Register Bits ...... 4-22 2-7. Read/Write Cable Signal/Pin List ..... 2-9 5-1. Code for Manufacturers ...... 5-2 3-1. Data Block Length vs. 5-2. Controller Board Electrical Parts List .. 5-2 Sectors Per Track ...... 3-1
ILLUSTRATIONS
Figure Title Page Figure Title Page 1-1. Typical Multiple Drive System ...... 1-1 3-14. Write Data ...... 3-15 2-1. Serial Priority Resolution ...... 2-1 3-15. Write Data from Controller Buffer 2-2. iSBC 220 Controller/Multibus to Disk ...... 3-16 Interface Signal Timing ...... 2-4 3-16. Initiate Track Seek ...... 3-17 2-3. Location of Jumpers and Switches 3-17. Buffer 110 ...... 3-18 on Controller Board ...... 2-6 3-18. Diagnostic ...... 3-19 2-4. Interconnecting Cable Requirements ... 2-8 3-19. Transfer Error Status ...... 3-20 2-5. Pertec Drive Interconnecting 4-1. Logic Conventions ...... 4-1 Cable Requirements ...... 2-17 4-2. Simplified Block Diagram 2-6. Priam Drive Interconnecting of iSBC 220 Controller ...... 4-2 Cable Requirements ...... 2-19 4-3. iSBC 220™ Controller Functional 2-7. ,Controller to Drive Interfacing ...... 2-22 Block Diagram ...... 4-3 2-8. Installing the iSBX 218 Board 4-4. Bus Arbitor and Bus Controller Logic 4-7 on the iSBC 215 Controller Board ... 2-25 4-5. Data Transmission Between Multibus 3-1. Disk Drive Organization and Interface and Controller Multibus Terminology ...... 3-1 Data Transceivers ...... 4-9 3-2. Sector Data Format ...... 3-2 4-6. Wake-Up Address Logic ...... 4-10 3-3. Host CPU-Disk Controller- 4-7. Address Fetches in Interaction Through the Initialization Sequence ...... 4-10 110 Communications Blocks ...... 3-3 4-8. Local Memory Map ...... 4-11 3-4. Wake-Up Block ...... 3-4 4-9. Set Cylinder Timing ...... 4-13 3-5. Channel Control Block ...... 3-5 4-10. Timing Diagram for RDY Signal ..... 4-17 3-6. Controller Invocation Block ...... 3-6 4-11. Timing Diagram for Disk Formatting . 4-18 3-7. 110 Parameter Block Description ...... 3-7 4-12. Timing Diagram for Write Data ...... 4-20 3-8. 110 Communications Blocks Linking .. 3-9 4-13. Timing Diagram for 3-9. Track Formatting ...... 3-11 Read Data Transfer ...... 4-21 3-10. Alternate Track Formatting ...... 3-12 5-1. iSBC 220 SMD Disk Controller 3-11. Read Sector ID ...... 3-13 Parts Location Diagram ...... 5-5 3-12. Read Data ...... 3-13 5-2. iSBC 220 SMD Disk Controller 3-13. Read Data into Controller Buffer Schematic Diagram ...... 5-7 and Verify ...... 3-14
iv PREFACE
This manual provides information regarding the installation, programming, operation, and servicing of the iSBC 220 SMD Disk Controller.
Related documents include: • The 8086 Family User's Manual, Order No. 9800722 • Intel MULTIBUS Specifications, Order No. 9800683 • Intel 808018085 Assembly Language Reference Manual, Order No. 9800301 • Intel 8086 Assembly Language Reference Manual, Order No. 900640 • MCS-80 User's Manual, Order No. 9800153 • MCS-85 User's Manual, Order No. 9800722 • Intel 8089 Assembly Language Reference Manual, Order No. 9800938
v
CHAPTER 1 GENERAL INFORMATION
1-1. INTRODUCTION tion and data management. The single board assembly features automatic error recovery and The Intel iSBC 220™ SMD Disk Controller is retry, transparent data error correction and multiple designed to interface up to four Storage Module sector transfers. Seek operations on multiple drives Device (SMD) Interfacel compatible disk drives to can be overlapped with a read/write operation on any Intel Multibus™ interface compatible computer another drive. It is fully compatible with Intel 8086 system. It can operate in a multiprocessor environ CPU 20-bit addressing. ment and is fully compatible with all Intel 8-bit and 16-bit computers. The Intel Multibus™ interface is I The Storage Module Device (SMD) Interface is a pending the common interface between the iSBC 220 con American National Standards Institute (ANSI) standard. troller and the host computer, system memory, and other I/O boards. A typical drive subsystem is shown in figure 1-1. 1-2. DESCRIPTION •Compatible disk drive storage range is from 12 to The iSBC 220 SMD Disk Controller is a single board i 600 megabytes. The number of tracks per surface, assembly. It may reside in any Intel backplane or in · sectors per track, bytes per sector and alternate a custom-designed configuration that is physically •tracks per surface are software selectable for each and electrically compatible with the Intel Multibus drive unit. interface. The iSBC 220 controller's design is based on the The host Central Processing Unit (CPU) communi Intel 8089 I/O Processor, which allows Direct cates with the Disk controller via four blocks of Memory Access (DMA), error detecting and correc- information in host memory. Once the controller is
DRIVE/I DRIVE 1 DRIVE 2
CONTROL CABLE
READ/WRITE CONTROL CABLE READ/WRITE READ/WRITE CABLE CABLE CABLE READ/WRITE CABLE --I ....- ...... ~.... I J1 - I I I I P1 P2 I (NOT USED) I L __
MULTIBUsm INTERFACE
Figure 1-1. Typical Multiple Drive System
1-1 General Information iSBC220
initialized, a CPU 110 write to the controller Wake access to the Multibus interface. Intel 2732 EPROMs Up Address initiates disk activities. The controller and 2114 Static RAMs provide on-board local accesses the four blocks in the host memory to memory for storage of the controller 110 control determine the specific operation to be performed, program and a resident diagnostic exerciser, for fetches the required parameters and completes the data buffering and for temporary storage of read/ specified operation without further CPU intervention. write parameters.
The controller board generates all drive, control and To access system memory for a read or a write , data signals and receives the drive status and data operation, the controller takes command of the signals required to perform the entire disk drive Multibus interface and maintains control until the interfacing task. During a disk read operation, the data transfer is complete. The buffer memory on the controller accepts serial data from the disk, inter controller board limits this bus control time to a prets sychronizing bit patterns, verifies validity of minimum. the data, performs a serial-to-parallel data conver sion, and passes parallel data or error condition indications to host memory. During a disk write operation, the controller performs parallel-to-serial data conversion and transmits serial write data and 1-3. SPECIFICATIONS the write clock to the drive. Table 1-1 lists the physical and performance specifi The Intel 8089 110 Processor provides optimum cations of the iSBC 220 SMD Disk Controller; table performance with minimum CPU overhead. An Intel 1-2 lists typical characteristics of disk drives that are 8288 Bus Controller and 8289 Bus Arbiter control compatible with the iSBC 220 controller.
Table 1-1. Board Specifications COMPATIBILITY CPU: Any Intel mainframe or any Multibus™ interface compatible CPU. The con- trolier can operate with either 16- or 20-bit addresses and with either 8- or 16- bit data bus widths. Disk Drive: SMD Interface compatible disk drive.
DATA ORGANIZATION AND CAPACITY Bytes per Sector: 128 256 512 1024 Software Selectable Sectors per Track (Maximum Allowable for Corresponding Selection 108 64 35 18 Software Selectable of Bytes per Sector): Disk Drives per Controlier: Up to four, daisy-chained. Error Detecting and Correction: Controller appends an Error Checking Code (ECG) at the end of each ID and data field. Using this ECC, the controller hardware can detect errors of up to 32 bits in length; controller firmware can correct errors of up to 11 bits in length.
CONTROLLER CHARACTERISTICS Mounting: Occupies a card slot in iSBC 604/614 Modular CardcagelBackplane or equivalent Multibus™ backplane connector. Physical Characteristics: Width: 17.2 cm (6.8 inches) Length: 30.5 cm(12.0 inches) Height: 1.3 cm (0.5 inches) Weight: 0.54 kg (19 ounces) Power Requirements: +5 Volts ±5% @ 3.25 amperes maximum; -5 Volts ±5% @ 0.75 amperes maximum,
NOTE Jumper and on-board voltage regulator allow -5 Volts or -12 Volts from Multibus™ connector to be used as voltage source for -5 Volt.
Environmental: Temperature: O°C to +55°C, operating (+32°F to +131°F). -55°C to +85°C, non-operating (-67°F to +185°F). Humidity: Up to 90%, non-condensing.
1-2 iSBC 220 General Information
Table 1-2. Drive Characteristics (Typical)
Disk (spindle) Speed 3600 rpm Tracks per Surface 823 typical Servo Type Closed loop, track following Access Time Track to track 6 ms Average 30 ms Maximum 55 ms Data Transfer Rate 1.2 megabytes/second Storage Capacity 12 to 600 megabytes
1-3/1-4
CHAPTER 2 PREPARATION FOR USE
2-1. INTRODUCTION 2-3. BOARD INSTALLATION CONSIDERATIONS This chapter provides information for use in pre paring and installing the iSBC 220 SMD Disk The iSBC 220 controller can be installed in any Intel Controller. Included are instructions for unpacking cardcage/backplane or any user-designed backplane and inspection, installation, setting switches, that is compatible with the Multibus interface and installing jumpers, and interfacing the controller meets the controller's power and Multibus connector board with the Multibus connector and disk drives. dimensional requirements. The controller occupies one backplane slot.
When installing the controller in a serial priority environment (e.g., within any of the Intel system 2-2. UNPACKING AND INSPECTION chassis), wiring modifications are required to On receipt of the iSBC 220 controller from the support serial priority; a daisy-chain technique, see figure 2-1, establishes priority. The priority input carrier, immediately inspect the shipping carton for (BPRN/) of the highest priority master is tied to evidence of damage. If the shipping carton is ground. The priority output (BPRO/) of the highest damaged or water-stained, request that the carrier's priority master is then connected to the priority agent be present when the carton is opened; if the input (BPRN/) of the next lowest priority master, carrier's agent is not present at the time of opening, and so on. ("I" following the signal name indicates keep the carton and packing materials for sub an active low). Slaves are jumpered as shown. This sequent agent inspection. technique can accomodate a limited number of For repairs or replacement of an Intel product masters due to gate delays through the daisy-chain. damaged during shipment, contact Intel Technical Support Center (refer to Chapter 5) to obtain a 2-4. POWER REQUIREMENT Return Authorization Number and further instruc tions. A copy of the Purchase Order should be The board requires a +5 Volt ±5% power source at a submitted to the carrier with the claim. maximum current of 3.25 amperes and a -5 Volt ±5% source at 0.75 amperes maximum, both supplied Carefully unpack the shipping carton and verify through the Multibus connector. An on-board that the following items are included: voltage regulator allows the -5 Volt or -12 Volt voltage sources from the Multibus connector to be • iSBC 220 SMD Disk Controller Printed Wired jumper selected for use as a voltage source for -5 Assembly Volts (refer to paragraph 2-13). Before installing the controller into a system chassis, make certain that • iSBC 220 SMD Disk Controller Schematic the associated power supplies can supply the Diagram additional current that the controller board requires.
HIGHEST LOWEST PRIORITY PRIORITY
r-o BPRN/ -C BPRN/ -() BPRN/ (NOT INTERNALLY CONNECTED) BPRO/ P- BPRO/ P- BPRO/ 0--(
--1 --1
~)
(> -'- 1.. 1...
Figure 2-1. Serial Priority Resolution
2-1 Preparation for Use iSBC220
2-5.. COOLING REQUIREMENT 2-2 describes the controller/Multibus interfac.e signals. Figure 2-2 provides a diagram of the When the controller is installed in a high temper controller/Multibus interface timing signals and a ature environment, make certain the ambient table of the timing requirements. Table 2-3 gives operating temperature does not exceed +55°C. current requirements and other characteristics_ related to the controller/Multibus interface. 2-6. MULTIBUS™ CONNECTOR The controller is connected to the Multibus interface The controller communicates with the CPU and through connector PI, an 86-pin, double-sided, other boards via the Multibus interface. Table 2-1 printed circuit edge connector with 3.96 mm (0.156 lists the Multibus connector pin assignments; table in) contact centers. Connector P2 is not used.
Table 2-1. Multibus™ Connector PI Pin Assignment*
) P1 (Component Side) P1 (Circuit Side)
Pin Mnemonic Description Pin Mnemonic Description
1 GND Signal GND 2 GND Signal GND 3 +5V +5Vdc 4 +5V +5Vdc Power 5 +5V +5Vdc 6 +5V +5Vdc Supplies 7 +12V +12Vdc 8 +12V +12Vdc 9 -5V -5Vdc 10 -5V -5Vdc 11 GND Signal GND 12 GND Signal GND
13 BCLK/ Bus Clock 14 INIT/ Initialize 15 BPRN/ Bus Pri. In 16 BPROI Bus Pri. Out Bus 17 BUSY/ Bus Busy 18 BREOI Bus Request Controls 19 MRDCI Mem Read Cmd 20 MWTC/ Mem Write Cmd 21 10RCI 1/0 Read Cmd 22 10WCI 1/0 Write Cmd 23 XACK/ XFER Acknowledge 24 INH11 Inhibit 1 disable RAM
25 Reserved 26 INH21 Inhibit 2 disable PROM or ROM Bus 27 BHEN/ Byte High Enable Controls 28 ADR101 29 CBROI Common Bus Request and 30 ADR111 Address 31 CCLK/ Constant Clk Address 32 ADR121 Bus 33 INTA/ Intr Achknowledge 34 ADR131
35 INT61 Parallel 36 INT71 Parallel 37 INT41 Interrupts Interrput 38 INT51 Interrput 39 INT21 Requests 40 INT3/ Requests 41 INTO/ 42 INT11
43 ADRE/ 44 ADRFI 45 ADRCI 46 ADRD/ 47 ADRAI 48 ADRBI ADR81 Address Address 49 50 ADR9/ Address 51 ADR6/ Bus 52 ADR7/ Bus 53 ADR41 54 ADR5/ 55 ADR2/ 56 ADR31 57 ADROI 58 ADR11
59 DATE/ 60 DATF/ 61 DATC/ 62 DATD/ 63 DATA/ 64 DATBI 65 DAT81 Data Data 66 DAT9/ Data 67 DAT61 Bus 68 DAT7I Bus 69 DAT41 70 DAT51 71 DAT2/ 72 DAT31 73 DATO/ 74 DAT11
75 GND Signal GND 76 GND Signal GND 77 Reserved 78 Reserved Power 79 -12V -12Vdc 80 -12V -12Vdc Supplies 81 +5V +5Vdc 82 +5V +5Vdc 83 +5V +5Vdc 84 +5V +5Vdc 85 GND Signal GND 86 GND Signal GND • "/" following the signal name indicates an active low.
2-2 iSBC 220 Preparation for Use
Table 2-2. iSBC 220™ ControllerIMultibus Interface Signal Descriptions
Signal Functional Description
ADRO/, ADRFI Address. These 20 lines transmit the address of the memory location or 1/0 port to be accessed. For ADR10/-ADR131 memory access, ADROI (when active) enables the even byte bank (DATO/-DAT7/) on the Multibus'· connector; i.e., ADROI is active for all even addresses. ADR131 is the most significant address bit. BCLKI Bus Clock. Used to synchronize the bus contention logic on all bus masters. BHENI Byte High Enable. When active low, enables the odd byte bank (DAT8/-DATF/) onto the Multibus'· connector. BPRNI Bus Priority In. When low indicates to a particular bus master that no higher priority bus master is requesting use of the bus. BPRNI is synchronized with BCLK/. BPROI Bus Priority Out. In serial (daisy chain) priority resolution schemes, BPROI must be connected to the BPRNI input of the bus master with the next lower bus priority. BREQI Bus Request. In parallel priority resolution schemes, BREQI indicates that a particular bus master requires control of the bus for one or more data transfers. BREQI is synchronized with BCLK/. BUSYI Bus Busy. Indicates that the bus is in use and prevents all other bus masters from gaining control of the bus. BUSYI is synchronized with BCLK/. CBRQ/ Common Bus Request. Indicates that a bus master wishes control of the bus but does not presently have control. As soon as control of the bus is obtained, the requesting bus controller raises the CBRQ/ signal. DATO/-DATF/ Data. These 16 bidirectional data lines transmit and receive data to and from the addressed memory location or 1/0 port. DATFI is the most-significant bit. For data byte operations, DATO/-DAT7 is the even byte and DAT8-DATF/ is the odd byte. INIT/ Initialize. Reset the entire system to a known internal state. INTO/-INT7/ Interrupt Request. These eight lines transmit interrupt requests to the appropriate interrupt handler. INTO/ has the highest priority. 10WC/ I/O Write Command. Indicates that the address of an I/O port is on the Multibus'· connector address lines and that the contents on the Multibus'· connector data lines are to be accepted by the addressed port. MRDC/ Memory Read Command. Indicates that the address of a memory location is on the Multibus'· connector address lines and that the contents of that location are to be read (placed) on the Multibus'· connector data lines. MWTCI Memory Write Command. Indicates that the address of a memory location is on the Multibus'· connector address lines and that the contents on the Multibus'· connector data lines are to be written into that location. XACK/ Transfer Acknowledge. Indicates that the address memory location has completed the specified read or write operation. That is, data has been placed onto or accepted from the Multibus'· connector data lines.
Table 2-3. iSBC 220™ ControllerIMultibus Interface Signal Characteristics
Driver 1, 3 Receiver 2, 3
Bus Location Type 10L IOH Co Location I'L I'H C, Signals Minma Min/ia Min pf Max ma MaxiJ8 Maxpl
DATO/- Masters TRI 32 -5000 300 Masters -0.5 125 18 DATFI and (16 lines) Slaves ADRO/- Masters TRI 32 -5000 300 Slaves -0.8 90 18 ADR13/, BHENI (21 lines) MRDC/, Masters TRI 32 -5000 300 Slaves -0.7 50 18 MWTC/ Slaves -0.4 20 5 10WC/
2-3 Preparation for Use iSBC220
Table 2-3. iSBC 220™ ControllerIMultibus Interface Signal Characteristics (Continued)
Driver 1, 3 Receiver 2, 3
Bus Location Type 'OL 'OH CO Location 'll 'IH CI Signals Minma Min/ia Minpf Maxma Max/i8 Maxpf
XACK/ Slaves TAl 48 -2000 300 Masters -1.2 60 18 BCLK/ Master -0.5 60 18 BREQ/ Each TTL 10 -400 60 Master BPRO/ Each TTL 10 -400 60 Master BPRN/ Master -0.5 60 18 BUSY/, All O.C. 20 - 250 All -0.5 60 18 CBRQ Masters Masters INIT/ All -0.5 60 18 INTO/- Slaves O.C. 40 - 300 INT7/ (8 lines)
Notes: 1. Driver Requirements: 3. Low and High Voltage Requirements: IOH = High Output Current Drive Receiver: IOl = Low Output Current Drive Co = Capacitance Drive Capability 0~Vll~0.8V TRI = 3-State Drive O.C.= Open Collector Driver 2.0V ~ VIH ~ 5.5V TTL = Totem-pole Driver Driver:
2. Receiver Requirements: 0~Vol~0.5V IIH = High Input Current Load 2.4V ~ VOH ~ 5.5V ill = Low Input Current Load CI = Cap Active Load
BUSYI ~ BUS ACCESS BUS RELEASE Y ~IDaj ADDREsS ______-J>Er.~------~--~-AD-D-R-E-SS--ST-A-B-lE------~~~~ ______
WRITE DATA ------~*>------DATA STABlE----f---1A-H-.....i,.------I r-IDHW~ READ DATA ______--:- ______-:- ______---J~lfo ... --DATA STABLE ~r.....;------
COMMAND r-"o~ """~ __ (MRDC/OR MWTC/j ~------ID-SX--~I-,---'~I·---I-XK--CD~ XACKI , __--J/ Master Command Access Timing
Figure 2-2. iSBC 220™ ControllerIMultibus Interface Signal Timing
2-4 iSBC220 Preparation for Use
I/O ADDRESS ~k~------ADDRESSSTABLE------~~~
j;:tSAS-1 i-1SAH=::::j I/O WRITE DATA (FROM SYSTEM CPU) ----~~\L~~------DATASTABLE------~)yf~r------
COMMAND 'kr~" t:'''"w~ (lOWC/) \- 1 ____ ~~I~~_____ - __IACC~~~~~~~~ ______I_~~.y-IXKO--- XACKI
Slave Command Timing
BCLKI
l_tDRQ-1 BREQI
~~Arr~ _IDBPN BPRNI ------~«'~ ~~------~------~------IDBYF--+-!~t----_·I t:=t- 1DBY
______BUSYI T~~)------~------J~HIGHZ~~------ \--IDBP0=j }) BPROI ( ( ...... _----- Bus Exchange Timing" Time in Nanoseconds Parameter Description Minimum Maximum
tSAS 50 Address Setup Time to 110 Command tSDS a Data Setup Time to 110 Command tSAH 15 Address Hold Time from I/O Command tSOHW 30 Data Hold Time from I/O Command tACC 8000 I/O Access Time tXKO 100 XACK/Hold Time from I/O Command
tSCY 125 Bus Clock Cycle Time tSl 65 Bus Clock Low tSH 35 Bus Clock High tORQ 35 Bus Request Delay toSY 60 Bus Busy Turn On Delay tOSYF 35 Bus Busy Turn Off Delay tDSPN 15 Priority Input Setup Time tosPO 25 BPRO/Serial Delay from BPRN/ tWAIT 00 Requesting Master Bus Access Time
tos 50 Busy to Address/Data Delay tsc 50 Address/Data Setup to Command tXKCO 750 XACK/ to Command Turn Off tAH 50 Address Hold Time tOHW 50 Data Hold Time tDHR a Read Data Hold Time tosx a Data Setup Time Before XACK/
Figure 2-2. iSBC 220™ ControllerIMultibus Interface Signal Timing (Continued)
2-5 Preparation for Use iSBC220
2-7. SWITCH/JUMPER CONFIGURATIONS switches (81-1) through 81-8 and 82~3 through 82-10, see figure 2-3) are provided on the controller board A number of switches and jumper links (see table 2- that allow the user to set the controller for the selected 4) are provided on the controller board that allow the wake-up address. The switch labels in figure 2-3 cor user to conveniently set the controller for the system respond to hexadecimal addresl;! bits 0 through F. environment in which it is to operate (8-bit or I6-bit Any switch set to ON represents a logical 1. system data bus, 8-bit or I6-bit I/O addressing, etc.). Figure 2-3 shows the location of these switches and The controlle~ multiplies the settings of the WUA jumpers on the board. They should be set, as switches by 2 (shifts the number four places to the described in the following paragraphs, prior to left) to create a 20-bit WUA. Note that due to this installing the board in a cardcage or backplane. shift, the four least-significant bits of the selected WUA must be zeros. When accessing host memory, Table 2-4. Configuration the controller transmits the entire 20-bit WUA Linkages and Switches through the Multibus interface. If the host memory Function Pin or Switch No. uses I6-bit addressing, the four most significant bits Wake-Up Address S1-1 through S1-8 ofthe 20-bit WUA must be zero. This is accomplished S2-3 through S2-10 by setting the four most significant bits of the WUA 8-Bit or 16-Bit System S2-1 switches (81-1 through 81-4) to zero. Data Bus Compatibility 8-Bit or 16-Bit Host 1/0 S2-2 Processor Port Addressing 2-9. WAKE-UP I/O PORT Interrupt Priority Level W4-C to W4-0 through W4-7 ADDRESS SELECTION Any Request W2 Voltage Selection W1 and W5 The host processor communicates with the'controller through an 8-bit I/O port. The WUA switches also set the address of this I/O port. For a host processor 2-8. WAKE-UP ADDRESS SELECTION with 8-bit I/O port addressing, bits 0 through 7 of the unshifted WUA determine the wake-up 110 port The controller communicates with the host CPU address; for a host processor with I6-bit I/O port through four I/O communications blocks located in addressing, bits 0 through F determine the address. the host memory. When the controller is to receive instructions, it goes to the beginning address of the I/O Address 8election switch 82-20n the controller first 110 communication block. This address is board (see figure 2-3) determines the type of I/O port called the wake-up address (WUA). The WUA may addressing the host processor uses: ON for I6-bit be any address in host memory. 8ixteen WUA addressing; OFF for 8-bit addressing.
W1 -12 VOLTS SELECT
S1 AND S2 WAKE-UP ADDRESS AND HOST PROCESSOR SELECTION SWITCHES
F E D C $1 B 82 A 9 8
W4-C W4-0 THROUGH W4-7 W5 INTERRUPT PRIORITY -5 VOLTS LEVEL SELECT Figure 2-3. Location of Jumpers and Switches on Controller Board
2-6 iSBC220 Preparation for Use
2-10. SYSTEM DATA BUS SELECTION 2-15. CABLING REQUIREMENTS
Host processor selection switch S2-1 on the controller Unless the drive manufacturer supplies them, the board (see figure 2-3) sets the controller for the type Interface cables between the controller and disk of system data bus with which the controller is to drives will have to be fabricated (see figure 2-4). interface: ON for 16-bit bus, OFF for an 8-bit bus. Right-angle pin header connectors with ejector tabs This switch allows the controller to use its 16-bit are recommended for mating with each of the data transfer mode to access the system bus (if the controller board's edge connectors. A 60-pin mass system memory supports 16-bit accesses), even terminated socket connector (3M 3334-6060 or though the host processor only supports 8-bit equivalent) is recommended for mating with Jl; a 40- accesses. pin connector (3M 3417-6040 or equivalent) is recom mended for mating with J2 and J3. The mass termin ated sockets are easily attached to flat ribbon cable using the jig that the connector manufacturer sup 2-11. INTERRUPT PRIORITY LEVEL plies. The Control Cable, which connects to Jl, requires a 60-conductor ribbon cable; the Read/Write The controller's internal interrupt request signal can Cables, which connect to J2 and J3, each require one be assigned to any of eight interrupt priority levels or two 20-conductor ribbon cables, depending on the (INTO/ to INT7/) on the Multibus connector. To number of drives in the installation (refer to para select the interrupt request priority level, place a graph 2-17 and 2-18 below). Cable length for the jumper link as shown in table 2-5 and figure 2-3. Control Cable cannot exceed a total length of 100 feet; total length for any Read/Write cable must not exceed 50 feet. 2-12. ANY REQUEST SELECTION 2-16. DRIVE PIN ASSIGNMENTS The any request function allows the controller to be set to relinquish control of the Multibus interface Tables 2-6 and 2-7 list the pin assignments for the Jl, following a request from: J2, and J3 connectors of the controller and the Jl through J4 connectors of the drives. 1. A higher priority device only (jumper be tween pins W2-C and W2-1 on the controller board). 2-17. SINGLE DRIVE INSTALLATIONS 2. Any device, lower or higher priority, (jumper between pins W2-C and W2-2). For single drive installations, two controller-to-drive interface cables are required. The 60-conductor Figure 2:3 shows the location of the selection pins. Control Cable connects between Jl of the controller and the corresponding control cable connector on the drive. The Control Cable lines must be termin ated as described in the drive manufacturer's 2-13. VOLTAGE SELECTION hardware reference manual at the drive terminator. The 20-conductor ReadIWrite cable connects between Figure 2-3 shows the location on the controller board either J2 or J3 of the controller and the correspond of the Voltage Source Selection pins for the -5 Volt ing read/write cable connector on the drive. In power supply. Install a jumper at either W5 (-5 addition, jumpers or switches within the drive must Volts) or WI (-12 Volts) to select a voltage source for be set to assign the drive a logical address. Since the the on-board -5 Volt Supply. controller can communicate with up to four drives, the logical address can be set to 0, 1, 2 or 3.
2-14. DRIVE INTERFACE 2-18. MULTIPLE DRIVE INSTALLATIONS
The iSBC 220 SMD Disk Controller is designed for For multiple drive installations, a common Control compatibility with SMD Interface compatible disk Cable bus transmits control data between the drives. Two interface cables per drive are required, controller and the drives (see figure 1-1). The Control one that daisy-chains command information (Con Cable is connected between Jl of the controller and trol Cable) and another that provides the serial data the corresponding control cable connector on the (Read/Write Cable). The controller can support up to drive at physical address O. Drive-to-drive control four drives. Refer to paragraphs 4-22 through 4-28 cables are then installed to daisy-chain the control for a detailed description of the controller to drive data to the other drives. The control lines must be interface signals. terminated at the last drive on the bus.
2-7 Preparation for Use iSBC220
DISK iSBC'"220 CONTROLLER DRIVE ~ ~
_60-CONDUCTOR RIBBON CABLE
P1 CONTROL CABLE MATING CONNECTOR
~~~~~~==~~~20~_~C~O~N~D~U~CT~O~R~R~IB~B~O~N;C~A~B~L~E~~~._~_~_~:~~~:~~_~~(i) I'--- MULTIPLE DRIVE INSTALLATIONS liF=..-~ .. -=-----~- - .. - -... ..--======CD 1===:-= - .. ___ ~-CONDUCTOR===""'""- RIBBON CABLE I- __ .. =-- '1;2.~==~~~~~==~~~~~~~=:====~~~~~-~~~ or ""'"" P3 READ/WRITE CABLE MATING CONNECTORS
------20-CONDUCTOR RIBBON CABLE SINGLE DRIVE INSTALLATION READ/WRITE CABLE MATING CONNECTOR
P2 or P3
~ 30 ~ 20 01 O1 01 31 .. 60 2 .. 40 60-PIN CARD-EDGE 40-PIN CARD- 26-PIN CARD-EDGE CONNECTOR EDGE CONNECTOR CONNECTOR
View of cable connectors from mating side.
Figure 2-4. Interconnecting Cable Requirements
2-8 iSBC220 Preparation for Use
Table 2-5. Interrupt Priority Level Selection Table 2-7. ReadlWrite Cable Signal/Pin List
Wire Wrap Priority Signal Name Controller Drive Level Selected I/O Connector I/O Conn. From Pin To Pin Servo Clock J2/3-02,21 JXX-02,14, 0 W4-C W4-0 Gnd 01 01 Read Data 03,23 03,16 1 W4-C W4-1 Gnd 22 15 2 W4-C W4-2 Read Clock 05,24 05,171 3 W4-C W4-3 Gnd 04 04 Physical Write Clock 06,26 06,19 } Drive 4 W4-C W4-4 Gnd 25 18 ( o and 2 5 W4-C W4-5 Write Data 08,27 08,20 6 W4-C W4-6 Gnd 07 07 Unit Selected 29,09 22,09 1 7 W4-C W4-7 Gnd 28 21 Seek End 10,30 10,23' Table 2-6. Control Cable Signal/Pin List Servo Clock 12,31 JXX-02,14, Gnd 11 01 J1 Read Data 13,33 03,16 Asserted Drive Input Gnd 32 15 Signal Name Source State Connector Read Clock 15,34 05,17 Pin Polarity Gnd 14 04 Physical Write Clock 16,36 06,19 ) Drive - + - + Gnd 35 18 t 1 and 3 Device Select 0 23 53 CU 23 53 Write Data 18,37 08,20 Gnd 17 07 ) Device Select 1 24 54 CU 24 54 Unit Selected 39,19 22,09 Device Select 2 26 56 CU 26 56 Gnd 38 21 Seek End 20,40 10,23 Device Select 3 27 57 CU 27 57 Device Select Note: Each signal is a differential pair with pin Enable 22 52 CU 22 52 numbers given by: JXX-1st pin, 2nd pin. Set Cylinder Two 20-conductor Read/Write Cables (see figure 2-4) (Tag 1) 01 31 CU 01 31 connect between J2 and the corresponding read/ Set Head write cable connectors on the drives at physical Address (Tag 2) 02 32 CU 02 32 address 1 and 2. Read/write data can be transmitted Control Select between the controller and additional drives in the (Tag 3) 03 33 CU 03 33 same manner through connector J3, with the two 20- Bus 0 04 34 CU 04 34 conductor Read/Write Cables going to the drives at Bus 1 05 35 CU 05 35 physical addresses 2 and 3. As has been described Bus 2 06 36 CU 06 36 for single drive installations, the logical address of Bus 3 07 37 CU 07 37 each drive is set at each drive. Bus 4 08 38 CU 08 38 Bus 5 09 39 CU 09 39 If only two drives are to be connected to the Bus 6 10 40 CU 10 40 controller, connect a single 20-conductor Read/Write Cable between J2 of the controller and the first drive Bus 7 11 41 CU 11 41 and another cable between J3 and the second drive. Bus 8 12 42 CU 12 42 This interconnection method eliminates the need to Bus 9 13 43 CU 13 43 construct a split (double) Read/Write Cable. Interface Enable 14 44 CU 14 44 2-19. POWER UP/DOWN Index Mark 18 48 Drive 18 48 CONSIDERATIONS Sector Mark' 25 55 Drive 25 55 Fault 15 45 Drive 15 45 If power is applied to, or removed from, the system Seek Error 16 46 Drive 16 46 while a drive is READY, a spurious disk write On Cylinder 17 47 Drive 17 47 operation could occur. To prevent this from happen Unit Ready 19 49 Drive 19 49 ing always ensure that the drives are not spinning Write Protected 28 58 Drive 28 58 when system power to the controller is switched on or off. Address Mark 20 50 Drive 20 50 Reserved 21 51 - 21 51 2-20. DIAGNOSTIC CHECK Pick 29 - CU 29 - Sequence A PROM-resident self-diagnostic may be used to Disable 59 - CU 59 - verify the controller operation. Instructions for Reserved 30 60 - 30 60 execution of the diagnostic are given in chapter 3. 'Not Used
2-9/2-10
CHAPTER 3 PROGRAMMING INFORMATION
3-1. INTRODUCTION "cylinder" (see figure 3-1). A drive that has 1024 tracks per surface thus has 1024 cylinders. This chapter describes the programming conven tions that must be followed to initiate and monitor Each track is divided into equal-sized sectors. Each the transfer of data between the host memory and a of these sectors includes a sector identification block disk drive. Included in this section are a discussion with error checking information and a data block, of: disk organization, track sectoring format, disk also with error checking information. The iSBC 220 controller communications protocol, interrupt hand controller allows the user to select the size of the data ling and the use of disk control functions. block; the size of the data block then determines the maximum number of sectors permitted per track (as shown in Table 3-1).
Table 3-1. Data Block 3-2. DISK ORGANIZATION Length vs. Sectors Per Track
The iSBC 220 SMD Disk Controller can communicate Bytes Per Maximum Number with from one to four disk drive units. Each drive Data Block of Sectors Per Track has a number of disk surfaces, which are fixed, 128 108 removable or both. In the following discussion, a head is assumed to be associated with a single disk 256 64 surface. Each surface can have up to 1024 tracks (circular data paths numbered 0 through 1023). The 512 35 set of tracks on multiple recording surfaces at a 1024 18 given head position or location is referred to as a
•
TRACK
Figure 3-1. Disk Drive Organization and Terminology
3-1 Programming Information iSBC 220
3-3. TRACK SECTORING FORMAT The controller uses these blocks to perform three basic functions: initialize the controller, check and The controller generates the format of the sector transmit status, and obtain user selected disk access identification block, the data block and the error functions and parameters. In addition to these I/O checking fields of each sector of the disk, one track at communications blocks, certain controller functions a time. Figure 3-2 shows how the controller organizes (such as track formatting) also require datal this information. Refer to the paragraph 3-12 and parameter buffers in host memory. Dedicated 3-13 for further information on track formatting. locations in host memory, however, are not required for these buffers. One I/O port in the host processor's addressable 1/0 space is also required. The host uses 3-4. CONTROLLER 1/0 this port, called the Wake-Up I/O Port, to initiate COMMUNICATIONS BLOCKS controller activity.
The host processor and the disk controller use four blocks of host memQry and one host I/O port to The sequence in which the controller accesses these exchange instructions and status. The I/O commun blocks varies with the type of operation being ications blocks are titled: Wake-Up Block, Channel performed, but for general data transfers (reads or Control Block, Controller Invocation Block and I/O writes), the blocks are accessed as follows: Parameter Block. Sixty-eight bytes of host memory must be dedicated to the I/O communications CD The host loads the I/O Parameter block in blocks. system memory with a command and para meters for the function the controller is to NOTE perform (for example read data). See Figure 3-3. Following the initialization of the controller, ® The host then transmits a wake-up command the Wake-Up Block, Channel Control Block (aIR) to wake-up 1/0 port, signaling the control and Controller Invocation Block must be ler to go to I/O communications blocks for maintained at their assigned locations. The instructions. location of the I/O Parameter Block can be ® The controller goes to the Channel Control changed providing that the I/O Parameter Block and links its way through the Controller Block Pointer in the Controller Invocation Invocation Block to the I/O Parameter Block. Block is changed to correspond to the new (The Wake-Up Block is used only during con location. troller initialization and by 8089 firmware.) •
.n INDEX INDEX fl.
SYNC DATA BYTES (128, 256, 512 or 1024) BYTE
4 4 BYTES
DATA GAP 5 FIELD
132 39 260 31 516 177 1028 651
Figure 3-2. Sector Data Format.
3-2 iSBC220 Programming Information
r------, I ® INTEL DISK HOST I I 8089 DRIVE PROCESSOR lOP I UNIT I I r------, I RAM WAKE-UP II :I I BLOCK I I I I l~S~'~5-=-O~R~L~ J I I I I I I
I 1/0 { PARAMETER I BLOCK I I '------I I I DATA I MEMORY I I I l_~S~~~~M~~J
Figure 3-3. Host CPU-Disk Controller Interface Through the I/O Communications Blocks
@ At the I/O Parameter Block, the controller reads 3-5. HOST CPU-CONTROLLER-DISK the command and parameter data into its RAM DRIVE INTERACTION and begins the data transfer function. Figure 4-2 shows a simplified block diagram of the ® The controller reads data from the selected drive major hardware sections of the host CPU, host into its RAM, then performs a DMA transfer of memory, controller and disk drives. The host system the data from RAM into system memory. memory contains all the controller I/O communica tions blocks, as well as the data buffers. The host (§) When the data transfer is complete, the control initiates controller activity through the wake-up I/O ler posts the status in the Controller Invocation port, which it addresses through the Multibus inter Block, sends an interrupt to the host and awaits face. The Intel 8089 I/O processor (lOP) handles all further instructions. communicates between the host CPU, host memory and disk drives, once the host has initiated con troller activity. Controller oeprations software is contained in on-board PROM. RAM on the controller These I/O communications blocks are accessed in a board facilitates intermediate data storage between similar manner when performing a write function. the host and the disk drive. A detailed description of these blocks and the data required in each is provided in paragraphs 3-6 3-6. WAKE-UP 1/0 PORT through 3-10. Refer to paragraphs 2-7 through 2-10 for a discussion of selecting the wake-up address, To invoke controller activity, the host CPU transmits wake-up I/O port address and 8-bit or 16-bit host. a wake-up command byte to the controller through
3-3 Programming· Information iSBC220
the wake-up I/O port. Three wake-up commands are 3-8. CHANNEL CONTROL BLOCK allowed: The controller uses the Channel Control Block to OOH CLEAR INTERRUPT - Con indicate the status of the internal processor (the troller to host interrupt is reset; Intel 8089 I/O Processor) and to invoke processor controller reset is cleared. program operations. The Channel Control Block OlH START OPERATION - Instructs requires 16 bytes (see Figure 3-5). Except for the controller to start the operation BUSY 1 FLAG (byte 1) and the Controller Invocation that the elements of the I/O Block address (bytes 2 through 5), the information parameter block define. contained in this block is used to invoke controller operations that are transparent to the host. 02H RESET CONTROLLER - Per forms hardware reset of con troller. A clear interrupt (OOH) 3-9. CONTROLLER INVOCATION BLOCK must be initiated following this command. (Each time the con The controller uses the Controller Invocation Block troller is reset, the communica (CIB) to post status to the host CPU and to locate the tions link between the control starting address for the controller's on-board disk ler and the host must be re interface program. The status sempahore byte (byte established through the Initial 3) has a special purpose. The host uses this byte to izing function.) indicate to the controller whether it has read the 03H through FFH Reserved. current contents of the status byte and is ready for a The sixteen wake-up address switches on the con status update. The Controller Invocation Block troller board determine the address of the wake-up requires 16 bytes (see Figure 3-6). I/O port. 3-10. I/O PARAMETER BLOCK
The I/O Parameter Block (IOPB) contains the 3-7. WAKE-UP BLOCK controller operating commands, which define the function the controller is to perform (read, write, The Wake-Up Block is the first of the I/O communi etc.), and the parameters of the function (memory cations blocks (see Figure 3-4). It is used to establish address, disk head and cylinder, etc.). The I/O a link between the controller and the I/O communi Parameter Block requires 30 bytes of host memory cations blocks in host system memory. space. Figure 3-7 describe;; the function of each byte.
7 0 7 0 1 (Reserved)" I 01H 0 .... Wake-Up Address 3 CCB Offset 2
5 CCB Segment 4
" Set to all zeros.
Byte Function
0 SYSTEM OPERATION COMMAND - Must be set to 01H. 1 Reserved. 2 through 5 CHANNEL CONTROL BLOCK (CCB) ADDRESS - Address of first byte of Channel Control Block. (Address = Offset + Segment x24).
Figure 3-4. Wake-Up Block
3-4 iSBC220 Programming Information
7 0 7 0 1 BUSY 1 I CCW 1 0 3 CIB Offset 2
5 CIB Segment 4
7 (Reserved)' 6 9 BUSY 2 I CCW 2 8 11 CP Offset 10
13 CP Segment 12
15 CONTROL POINTER 14
* Set to all zeros.
Byte Function
0 CHANNEL CONTROL WORD 1 - Indicates location of Intel 8089 1/0 Processor control store program. Must contain 01 H. 1 BUSY 1 FLAG - Indicates whether controller Ls busy or idle. OOH - Idle FFH - Busy 2 through 5 CONTROLLER INVOCATION BLOCK (CIB) ADDRESS - Address of fifth byte of Controller Invocation Block. 6 and 7 Reserved. 8 CHANNEL CONTROL WORD 2 - Must contain 01H. 9 BUSY 2 WORD - Not meaningful to host CPU. 10 through 13 CONTROL POINTER ADDRESS - Address must point to the Control Pointer in the next sequential word. 14 and 15 CONTROL POINTER - Must be set to 0004H.
Figure 3-5. Channel Control Block
3-11. TYPICAL CONTROLLER 2. Reading the parameters that describe the disk OPERATIONS drives with which the controller is to interface into the controller's RAM buffer, using the The following section describes how to set up the I/O Initialize function (FUNCTION = OOH). communications blocks in the host memory, how to -initialize the controller and how to perform the This initialization must be performed following a: various data transfer operations. It is assumed that 1. Power-on event. the controller board has been properly installed as described in Chapter 2. 2. Controller reset (02H written to the wake-up I/O port).
3-12. INITIALIZING THE CONTROLLER After the controller has been initialized, any of the The controller must be initialized before any data data transfer functions described in paragraphs 3-13 transfer activities between the host system memory through 3-25 can be performed in any sequence. and the disk drives can be initiated. Initialization of (Refer to paragraphs 4-12 through 4-15 for a detailed the controller involves: explanation of controller initialization.) 1. Establishing a link between the 8089 and the The following procedure gives the sequence in which I/O communications blocks in host system the controller initializing activities must be per memory. formed. Prior to initializating the controller, check
3-5 Programming Information iSBC220
7 0 7 0
1 Op. Status (Reserved) , 0
3 St. Serna. CMND Serna. 2
5 CSA Offset 4
~ 7 CSA Segment 6
9 10PB Offset 8
11 10PB Segment 10
13 12 (Reserved)' 15 14
, Set to all zeros.
Byte Function
0 Reserved. 1 CONTROLLER OPERATION STATUS - Bits 0 through 2 indicate event completed. Bits 4 and 5 indi- cate drive associated with event. Bit 6 indicates error: soft (recoverable), 0, or hard, 1. Bit 7 indicates a summary error that can be checked through the transfer error status function (refer to paragraph 3-25).
I 71615 4131211101 - ,-. l Operation Complete Seek Complete Media Change Detected (Reserved) Unit 10 Hard Error Summary Error
2 COMMAND SEMPAHORE - Controller does not use this byte. It is provided for use as a multi- processor interlock. 3 STATUS SEMPAHORE - Controller posts status only when this byte is OOH; when new status has been posted, controller sets byte to FFH. When host CPU has read status, it sets this byte to OOH. 4 through 7 CONTROL STORE PROGRAM ADDRESS - Starting address of controllers on-board disk interface program. Set to OOOOOH. 8 through 11 I/O PARAMETER BLOCK ADDRESS - Address of first byte of I/O parameter block.
! Figure 3-6. Controller Invocation Block
that the system data bus switch (82-1), the host Controller Invocation Block 16 Bytes system I/O address switch (82-2), the wake-up I/O Parameter Block 30 Bytes address switches (81-1 through 81-8 and 82-3 through 82-10), and the interrupt level jumper has been set as described in the procedure titled 8witch/ Remember that the address of the first byte of Jumper Configurations in Chapter 2. the Wake- U p Block must be equal to the wake-up address set in the controller's wake-up address To initialize the controller, the host CPU must switches times 24. For example, if the switches perform the following steps: are set to 0673H, the address of byte 0 of the Wake-Up Block is: 1. Establish-addresses for the four 1/0 com munications blocks in host memory: Wake-Up Block 6 Bytes 06730H 20-Bit Addressing Channel Control Block 16 Bytes 6730H 16-Bit Addressing
3-6 iSBC220 Programming Information
7 0 7 0 1 (Reserved) , 0 3 (Reserved)' 2 5 4 Actual Transfer Count 7 6 9 (Reserved) • 8 11 Function I Unit 10 13 Modifier 12 15 Cylinder 14 17 Sector I Head 16 19 DB Offset 18
21 DB Segment 20 23 22 Requested Transfer Count 25 24 27 26 (Reserved) , 29 28
, Set to all zeros.
Byte Name and Function
o through 3 Reserved. 4 through 7 ACTUAL TRANSFER COUNT - Count of bytes actually transferred between the system and the disk or controller. Four-byte binary number, least significant bits in first byte. Controller writes count to IOPB following termination or completion of an operation. If count does not match requested transfer count, operation was prematurely terminated; check status. When performing the track formatting function, a count of 6 is set in the Actual Transfer Count word. When performing the status transfer function, the count is set to 12. When initializing drive 0, this word has a special function. It is used to dis- play the controller firmware's version number as shown below:
17161514131211101 T't= Revision Level : Version minus 1 8 and 9 Reserved. 10 UNIT - Code for drive unit being accessed and its volume identification: bits 0 an 1 indicate unit 10 codes; bit 4 indicates fixed or removable volume. If the drive unit being addressed uses either an all fixed or all removable volume, bit 4 must always be set to zero. I 716151413121~1 Unit: I ~ o through 3 : Volume: 0- Fixed 1 - Removable
Figure 3-7. 1/0 Parameter Block Description
3-7 Programming Information iSBC220
Byte Name and Function
11 FUNCTION - Code for operation to be performed. Refer to following discussion of typical controller operations for a detailed discussion of these operations: OOH INITIALIZE 01H TRANSFER STATUS 02H FORMAT 03H READ SECTOR 10 04H READ DATA 05H READ TO BUFFER AND VERIFY 06H WRITE DATA 07H WRITE BUFFER DATA OSH INITIATE TRACK SEEK 09H - ODH Reserved OEH BUFFER I/O OFH DIAGNOSTIC 12 and 13 MODIFIER - Code to modify function codes. Bit 0 Suppresses interrupt on command completion when set to 1. Bit 1 Automatic retries for error recovery are inhibited when set to 1. Bits 2 through 15 Reserved. 14 and 15 CYLINDER - Binary number specifying logical cylinder code; bit 0 is least significant bit of number. 16 HEAD - Binary number specifying logical head code; bit 0 is least significant bit of number. 17 SECTOR - Binary number specifying logical sector code; bit 0 is least significant bit of number. 1 S through 21 DATA BUFFER ADDRESS - Address of first byte in host system memory data (parameter) buffer. 22 through 25 REQUESTED TRANSFER COUNT - Count of bytes requested to be transferred between the system and the disk or controller. Four-byte binary number. least significant bits in first byte. See description of ACTUAL TRANSFER COUNT. bytes 4 through 7 in 10PB. 26 through 29 Reserved.
Figure 3-7. I/O Parameter Block Description (Continued)
2. Set up the Wake-Up Block (see Figure 3-8). byte 11, is set for the Initialize function (FUNC- TION = OOH). Initialize unit 0 first. 3. Set BUSY 1 Flag (Optional). Set the BUSY 1 flag (byte 1 of the Channel Control Block) to 10. Establish parameter buffer. Set up a disk non-zero (FFH). This allows the host to monitor drive parameter data buffer with the parameters the BUSY 1 flag to find out when the initializa- for the drive to be initialized as shown in Figure tion procedure is complete. 3-8. Be sure the data buffer address in the 110 Parameter Block points to the first address of 4. Reset the controller. Host writes a 02H to the this data buffer. wake-up 110 port. 11. Start initialize function. Poll the BUSY 1 5. Clear the reset. Host writes a OOH to the FLAG (Byte 1 of the CCB) and write a 01H to the wake-up 110 port. wake-up 110 port when the flag is zero. The 6. Establish the host-controller communica- controller goes to the Channel Control Block, tions link. Write a 01H to the wake-up 110 then links its way through the Controller port. The controller goes to the Wake-Up Block Invocation Block and 110 Parameter Block and in host memory and records the address of the reads the disk drive parameters for the unit Channel Control Block, then goes to the Channel specified. Control Block and clears the BUSY 1 FLAG. On 12. Respond to and process the resulting inter- all subsequent OlH commands to the wake-up rupt or status or both. 110 port, the controller will go to the Channel Control Block. 13. Reset I/O Parameter Block. Set the UNIT, byte 10, for the next unit to be initialized and set 7. Set up the Channel Control Block as shown the data buffer address, byte 18 through 21, for in Figure 3-8. the beginning address of the unit's disk para- meters. 8. Set up the Controller Invocation block as shown in Figure 3-8. Be sure the STATUS 14. Repeat steps 10 through 12 for each drive SEMAPHORE, byte 3, is set to OOH. unit. Note that the initialization procedure MUST BE PERFORMED FOR ALL FOUR 9. Set up the I/O Parameter Block as shown DRIVE UNITS, starting with unit 0, even if one in Figure 3-8. Be sure the UNIT, byte 10, is set or more of the drives do not exist. Initialize all for the correct unit number and the FUNCTION, unattached drives with all zeros.
;3:.8 iSBC 220 Programming Information
Wake-Up Block 1/0 Parameter Block
7 0 7 0 Wake-Up Address 7 0 7 0 X 24 Switches must 0 point to this byte. (Reserved) 0
3 2 3 (Reserved) 2
5 4 5 4 Actual Transfer Count 7 6 Channel Control Block 9 (Reserved) 8
0 11 10
3 2 13 Modifier 12
5 4 15 Cylinder 14
7 6 17 16
9 8 19 18
11 10 21 20
13 12 23 22 Requested Transfer Count 15 14 25 24
27 26 Controller Invocation Block (Reserved) 29 28
(Reserved) 0 Data Buffer 3 2 Starting address 7 0 7 0 5 4 for controller's on-board 0 7 6 program. 3 2 9 8 5 4 11 10 7 6 13 12 (Reserved) * Bytes 5 and 6 are a word, 5 being the low byte, 15 14 6 the high byte.
NOTE: Set up the shaded bytes in each of the liD Communications Blocks and in the Data Buffer.
Figure 3-8. 110 Communications Blocks Linking
3-9 Programming Information iSBC220
The controller is now initialized. This procedure When a track within the data track area is deemed need not be repeated except after a power-on or a defective, the host reformats the track, giving it a controller reset. For all subsequent disk activities, defective track code and entering the address of the the host communicates with the controller through next available alternate track in the data fields. The the Channel Control Block, the Controller Invoca alternate track that is selected must be formatted as tion Block and the I/O Parameter Block. an assigned alternate track. When the controller accesses a track that has been 3-13. TRACK FORMATI'ING previously marked defective, it will automatically invoke a seek to the assigned alternate track and use The Format Track function (FUNCTION = 02H) the alternate as if it were the data track area. This writes the gaps, sector headers and data fields (see operation is automatic and is invisible to the user, Figure 3-2) on a track - one track per command. A except for the added time required to complete the track can be designated as a normal, assigned operation. alternate or defective track. A defective track generally points to an assigned alternate track. Refer to the discussion of alternate and defective 3-15. DATA TRANSFER track handling in paragraph 3-14. AND VERIFICATION
Use the following procedure to format a track. Seven data transfer and verification command functions are allowed, selected through the FUNC 1. Set up the 110 Parameter Block as shown TION byte in the I/O Parameter Block: Read Sector in Figure 3-9. ID, Read Data, Read Data to Buffer and Verify, 2. Set up a 6-byte data buffer for the type of Write Data, Write Data from Buffer, Initiate Track track to be formated as shown in Figure 3- Seek and Buffer I/O. 9. A track can be designated as a data track, assigned alternate track or defective track. The user pattern is repeated throughout the data NOTE field of every sector. In the case of a defective All data transfers between the host system track, the user pattern is a pointer to the memory and a disk drive unit are buffered alternate track. If the alternate track is defective, through the controller's on-board RAM it can not be used to point to another alternate. buffer. During a write, the controller per An interleave factor of 1 corresponds to consecu forms a DMA transfer of a one-sector block tive sectors. of data from the host system memory to the 3. Initiate the format operation. Write a 01H to RAM buffer. It then transfers the sector the wake-up I/O port. serially from the RAM buffer to the disk in two byte increments. When reading from the 4. Respond to and process the reSUlting inter disk, the controller performs a serial trans rupt or status or both. fer of a sector of data from the disk to the RAM buffer in two byte increments. When the entire sector has been read into the RAM NOTE and all error checking has been completed, Always format the last track on head 0 as a the controller then performs a DMA transfer data track. This track should then be re of the one-sector block from the RAM to host served for use by the on-board diagnostic. system memory.
The controller contains a burst error checking code 3-14. ALTERNATE AND DEFECTIVE (ECC) computing circuit that creates an error TRACK HANDLING checking code for each sector ID and each data block written into disk memory. When reading data from It is suggested that each disk surface be divided into the disk, the controller verifies the sector ID and the two areas (see Figure 3-10), the data track area and information in the data blocks using these error the alternate track area. The user assigns the checking codes. If errors are detected that can be number of tracks in the alternate track area, corrected (occur within an eleven-bit burst or less), typically 1 - 2% of the total number of available they are corrected and the remainder of the operation tracks on the surface. If a disk surface has 512 is completed. If the error cannot be corrected, the tracks, tracks 0 through 500 would constitute the sector is re-read. If after 27 retries the errors remain data track area and tracks 501 through 510 would un correctable, the operation is terminated and a constitute the alternate track area. The last track Hard Error is indicated in the operation status byte at Head 0 must be reserved for the diagnostic (byte 1) of the Controller Invocation Block. To obtain program. detailed information on the nature of the error,
3-10 iSBC220 Programming Information
Data Buffer
7 o 7 o o Format Data Track 3 2 -+---1
5 4
o Format Assigned Alternate Track 3 2
5 4
o Format Defective Track 3 2
5 4
"Byte 1 - high byte; byte 2 - low byte.
Figure 3-9. Track Formatting
3-11 Programming Information iSBC220
ALTERNATE TRACK AREA
TRACK ZERO
Figure 3-10. Alternate Track Formatting
perform the Transfer Error Status function (refer to To perform this function, set up the shaded bytes in paragraph 3-25). the I/O parameter block as shown in Figure 3-11, and reserve a 5-byte data buffer in host system memory. Each of the data transfer and verification functions is described in detail in the following paragraphs. To use anyone of these functions, the host CPU must 3-17. READ DATA perform the following steps: The Read Data function (FUNCTION = 04R) reads 1. Set up the 1/0 parameter block as shown data from the disk into host system memory. It in the paragraph describing the function. begins reading with the first byte of the selected sector and ends reading when the requested byte 2. Initiate the operation. Write a 01R to the count is reached, end of media is reached or a hard wake-up I/O port. failure is detected. If multi-sector data transfers are 3. Respond to and process the resulting inter requested the controller automatically seeks to the rupt or status or both. next sector, the next head and the next cylinder, in that order. Automatic head increments are supported only within the volume, fixed or removable, but not between volumes, for example, fixed across to 3-16. READ SECTOR ID removable. The last sector, head and track address in the data track area defines the end of media. An The Read Sector ID function (FUNCTION = 03R) implied seek is invoked ifthe current head position is searches for the first error free sector on the selected different from the specified track identification. The track and writes the contents of the sector ID field DATA BUFFER address set in the I/O parameter into a 5-byte data buffer in host memory (see Figure block is the address in host system memory where 3-11). An implied seek, head select or volume change, the first data byte read from the disk is to be is not performed. The Read Sector ID is performed on transferred. Since the data being transmitted from the cylinder, volume and head that the previous the disk drive is buffered in the controller's RAM, function selected. One use of this function is to data overruns cannot occur. To perform this func search the alternate track area for tracks that have tion, set up the shaded bytes in the I/O parameter not been assigned as alternates. block as shown in Figure 3-12.
3-12 iSBC220 Programming Information
1/0 Parameter Block
(Reserved) o
3 (Reserved) 2 Data Buffer 5 4 Actual Transfer Count 7 6 High Cylinder Low Cylinder o
9 (Reserved) 8 3 Sector Head 2
11 10 Flags 4
13 12
15 14 Byte 4 Flags 17 16 -Czeros 19 18 .. Sector Size 00 - 128 Bytes 21 20 01 - 256 Bytes 10 - 512 Bytes 22 23 11 - 1024 Bytes Requested Transfer Count L-______~~ Track Type 25 24 00 - Normal 27 26 01 - Assigned Alternate (Reserved) 10 - Defective 29 28 11 - Invalid
Figure 3-11. Read Sector ID
1/0 Parameter Block
(Reserved) o
3 (Reserved) 2
5 4 Actual Transfer Count 7 6
9 (Reserved) 8
11 10
13 12
15 14
17 16
19 18
21 20 23 22
25 24 27 (Reserved) 26 29 (Reserved) 28
Figure 3-12. Read Data
3-13 Programming Information iSBC220
3-18. READ DATA INTO CONTROLLER The Read Data into Controller Buffer and Verify BUFFER AND VERIFY function has two applications: The Read Data into Controller Buffer and Verify function (FUNCTION = 05H) reads data from the 1. Allows data to be verified after it has been disk into the controller on-board RAM and checks written from host system memory to the disk. the ECCs to verify the sector ID and data fields for all sectors affected. It begins reading with the first 2. Allows data to be transferred from one disk byte of the selected sector and ends reading when the location to another by coupling this function requested byte count is reached, end of media is with the Write Data from Controller Buffer reached or a hard failure is detected. The multi function. sector data verification is supported through the auto-sector, auto-head, auto-cylinder protocol de scribed for Read Data function. End of media and To perform the Read Data into Controller Buffer and implied seek are also supported as described for the Verify function, set up the shaded bytes in the I/O Read Data functions. parameter block as shown in Figure 3-13.
1/0 Parameter Block
(Reserved) 0 3 (Reserved) 2 5 4 Actual Transfer Count 7 6 9 (Reserved) 8 11 10 13 12 15 14
17 16 19 18 21 20 23 22 25 24
27 (Reserved) 26 29 (Reserved) 28
Figure 3-13. Read Data into Controller Buffer and Verify
3-14 iSBC220 Programming Information
3-19. WRITE DATA 3-20. WRITE DATA FROM CONTROLLER BUFFER TO DISK The Write Data function (FUNCTION = 06H) writes data from host system memory onto the disk. It The Write Data from Controller Buffer to Disk begins reading from the specified host data buffer (FUNCTION = 07H) writes data from the controller address and writes to the first byte of the selected on-board RAM onto the disk. It begins reading from sector. It ends writing when the requested byte count the first address of the controller's data buffer is reached, end of media occurs (system memory or (4010H) and writes to the first byte of the selected disk space) or a hard failure is detected. When disk sector. It ends writing when the requested byte writing to more than one sector, the sector selection count is reached, end of media occurs (controller is automatic as described for the Read Data function. memory or disk space) or a hard failure is detected. Auto-head increments and implied seek are also When writing to more than one sector, the sector supported as described for the Read Data function. If selection is automatic as described for the Read Data writing ends in the midst of a sector, the remaining function and the data in the buffer is repeated for area of the sector is filled with zeros. each sector written. Auto-head increments, implied seek and end of media are also supported as is described for the Read Data function. If writing ends To perform this function, set up the shaded bytes in in the midst of a sector, the remaining area of the the I/O parameter block as shown in Figure 3-14. sector is filled with zeros.
I/O Parameter Block
(Reserved) 0
3 (Reserved) 2 5 4 Actual Transfer Count 7 6
9 (Reserved) 8 11 10 13 12 15 14 17 16 19 18 21 20 23 22 25 24
27 (Reserved) 26
29 (Reserved) 28
Figure 3-14. Write Data
3-15 Programming Information iSBC220
To perfotiri this function, set up the shaded bytes in To perform this function,set up the shaded bytes in the I/O parameter block as shown in Figure 3-15. the 110 parameter block as shown in Figure 3-16.
3-22. BUFFER I/O 3-21. INITIATE TRACK SEEK The Buffer 110 function (FUNCTION = OEH) The Initiate Track Seek function (FUNCTION = transfers data between the host system memory and 08H) positions the read/write head on a specified controller on-board RAM. Beginning addresses in track, if the head is not already on that track. When the host system memory and controller buffer issued sequentially to several drives, this command memory are specified. Data transfer begins at these allows multiple disk drives to perform concurrent addresses and ends when the requested byte count is (overlapping) seeks. If a seek to a cylinder beyond reached. Since the controller has only 64K bytes of the end of media (which includes alternates) is local memory address space, the most significant initiated, the heads are automatically returned to bytes of the REQUESTED TRANSFER COUNT track zero, and an invalid address error is posted. If (bytes 24 and 25) are ignored. an operation complete interrupt is enabled, it is invoked when the seek command has been initiated and a seek complete interrupt (which is always ~ enabled) is invoked when the seek is completed. The Data transfers from the host system memory operation complete interrupt allows a function to be to the controller-buffer must be written to initiated on a second drive while the seek is being addresses within the range of 4000H to performed on the first drive. 4600H.
I/O Parjlmeter Block
(Reserved) 0
3 (Reserved) 2 5 4 Actual Transfer Count 7 6
9 (Reserved) 8 11 10 13 12 15 14
17 16 19 18 21 20 23 22 25 24
27 (Reserved) 26 29 (Reserved) 28
Figure 3-15. Write Data from Controller Buffer to Disk
3-16 iSBC220 Programming Information
I/O Parameter Block
(Reserved) 0
3 (Reserved) 2 5 4 Actual Transfer Count 7 6
9 (Reserved) 8 11 10 13 12 15 14 17 16
19 Data Buffer Offset 18
21 Data Buffer Segment 20 23 22 Requested Transfer Count 25 24
27 (Reserved) 26
29 (Reserved) 28
Figure 3-16. Initiate Track Seek
The beginning address in controller memory and the 3-23. DIAGNOSTIC direction of data transfer are specified in the CYLINDER and HEAD fields, respectively: The Diagnostic function (FUNCTION = OFH) causes the controller to perform a go/no-go self diagnostic test that verifies internal data and status Bytes 14 and 15 Starting controller memory ad electronics and checks position and read/write dress: electronics in the disk units. The diagnostic test Byte 15 - High Byte program is contained in the controller's on-board Byte 14 - Low Byte PROM. Byte 16 Direction of data transfer: OOH - From controller to host The diagnostic track is always located on a drive FFH - From host to controller unit's last (highest number) track of head O. When allocating memory space for the disk unit, this track The Buffer 110 function has two applications. Its must be dedicated to the diagnostic program. When primary purpose is for use with the diagnostic initiating the diagnostic program, the head and program. It also allows memory-to-memory transfers cylinder are selected automatically, the user selects with a minimum of host overhead. the drive unit. The diagnostic test is divided into three parts. The upper byte of the MODIFIER field To perform this function, set up the shaded bytes in (byte 13) determines the part of the diagnostic test the I/O parameter block as shown in Figure 3-17. that is executed:
3-17 Programming Information iSBC220
I/O Parameter Block
(Reserved) 0
3 (Reserved) 2
5 4 Actual Transfer Count 7 6 Unit address must be entered even though 9 the specified unit is not accessed.
11
13 Starting Controller 15 Memory Address: Byte 15 - High Byte 17 Byte 14 - Low Byte
19 Direction of Data Transfer: 21 Byte 16 - OOH (from Controller to Host) FFH (from Host to Controller) 23 Requested Transfer Count 22
25 (Reserved) 24
27 (Reserved) 26
29 (Reserved) 28
Figure 3-17. Buffer I/O
Byte 13 Function Executed 3-24. POSTING STATUS OOH Controller seeks the designated diag nostic track, performs a read ID and When the controller has completed an operation (read data, seek track, etc.), it posts the operation verifies the track position. It then status in byte 1, the OPERATION STATUS byte, of writes and reads sector 0 with a the controller invocation block, using the following 55AAH data pattern and verifies that the data read matches the data procedure: written. 1. The controller checks the STATUS SEMA OIH Controller performs a ROM check PHORE byte (byte 3 of the controller invocation sum test to verify the contents of block) for OOH. ROM. 2. If the STATUS SEMAPHORE byte is non-zero, 02H or Controller recalibrates the drive. it indicates that the host CPU has not checked greater the OPERATION STATUS byte for the last status posted. When the host CPU does check the operation status, it sets the STATUS SEMA PHORE byte to OOH and clears the interrupt. Any errors in the reading or writing are posted in the 3. When the controller reads OOH in the STATUS error status registers. SEMAPHORE byte, it posts the current status in the OPERATING STATUS byte, sets the To perform this function, set up th~ shaded bytes in STATUS SEMAPHORE byte back to non-zero the I/O parameter block as/shown in Figure 3-18. and sets the interrupt.
3-18 iSBC220 Programming Information
I/O Parameter Block
(Reserved) 0
3 (Reserved) 2 5 4 Actual Transfer Count 7 6 9 (Reserved) 8 11 10 13 12 15 Cylinder 14
17 Sector Head 16
19 Data Buffer Offset 18
21 Data Buffer Segment 20 23 22 Requested Transfer Count 25 24
27 (Reserved) 26
29 (Reserved) 28
Figure 3-18. Diagnostic
4. The host CPU in tum, either polls the STATUS at the beginning of each new command operation, SEMAPHORE byte periodically for a non-zero except the Transfer Error Status Command. or is interrupted, indicating that new status is present. The status posted includes: operation complete, seek 3-25. TRANSFER ERROR STATUS complete, media change detected and errors detected. If an error was detected, the unit on which the error The Transfer Error Status function (FUNCTION = occurred and an indication of whether the error was 01H) transfers error status from the 12-byte error a hard error or a summary error is posted (see Figure status buffer in the controller memory to a data 3-6). A more detailed description of the error is buffer in the host system memory. The user can then recorded in the error status buffer in the controller examine the status bits to determine the cause ofthe memory. To examine this error status the user error. Table 3-2 shows the information stored in each transfers the information in the error status buffer byte of the error status buffer. Table 3-3 describes from the controller to host system memory using the which kind of errors are indicated by the setting of transfer error status function (FUNCTION = OlH) the hard (unretrievable) error and soft (retrievable) described in the following paragraph. error bits in bytes 0 through 2. To perform the Transfer Error Status function, set up the shaded It should be noted that error status information is bytes in the I/O parameter block as shown in Figure not cumulative. The error status buffers are cleared 3-19. Pr~gramming Information iSBC220
Table 3-2. Error Status· Buffer The interrupt on command complete can be disabled by entering a one in bit 0 of the Modifier word in the Error Status Buffer I/O parameter block (bytes 12 and 13). The seek Byte Function complete and media change interrupts can not be disabled. To clear an interrupt, the host writes a OOH o and 1 HARD ERROR STATUS - See Table 3-3 to the Wake-Up I/O port. 2 SOFT ERROR STATUS - See Table 3-3 3 and 4 DESIRED CYLINDER 5 DESIRED HEAD Pins on the controller board allow the interrupt 6 DESIRED SECTOR priority level of the controller to be set to from 0 to 7. 7 and 8 ACTUAL CYLINDER & FLAGS Refer to the discussion of interrupt priority level 9 ACTUAL HEAD & VOLUME selection in Chapter 2. 10 ACTUAL SECTOR 11 NUMBER OF RETRIES ATTEMPTED
3-26. INTERRUPTS 3-27. EXAMPLE CONTROLLER The controller normally posts interrupts to the host 1/0 PROGRAM on three conditions: 1. Command complete Appendix A provides an example of a host processor program to initiate data transfers between the host 2. Seek complete system memory and disk drives through the iSBC 3. Media change (change disk pack) 220 controller.
I/O Parameter Block
(Reserved) 0
3 (Reserved) 2
5 4 Actual Transfer Count 7 6
9 (Reserved) 8
11 10 ... Unit address must be entered even though the specified unit is not accessed. 13 12
15 14
17 16
19 18
21 20
23 22 Requested Transfer Count 25 24
27 (Reserved) 26
29 (Reserved) 28
Figure 3-19. Transfer Error Status
3-20 iSBC220 Programming Information
Table 3-3. Bit Functions in Hard and Soft Error Bytes
Byte Bit Function
0 o through 2 Reserved for future use. 3 RAM ERROR - Controller RAM error was detected. 4 ROM ERROR - Controller ROM error was detected. 5 SEEK IN PROGRESS - Indicates a seek was already in progress for a unit when another seek was requested. 6 ILLEGAL FORMAT TYPE - Both alternate track and defective alternate track flag set indi- cating an attempt to create an alternate track for a defective alternate track, which is not allowed, or an attempt to access an unassigned alternate track. 7 END OF MEDIA - End of media was encountered before requested transfer count expired.
1 8 ILLEGAL SECTOR SIZE - Sector size read from the sector 10 field conflicts with sector size information that controller specified in initialization command. 9 DIAGNOSTIC FAULT - Micro-diagnostic fault detected. A NO INDEX - Controller did not detect index pulse. B INVALID COMMAND - Invalid function code detected. C SECTOR NOT FOUND - Desired sector could not be located on selected track. 0 INVALID ADDRESS - Invalid address was requested. E SELECTED UNIT NOT READY - Selected unit is not ready, not connected, or not respond- ing to unit connect request. F WRITE PROTECTION FAULT - An attempt has been made to write to a write protected unit.
2 o through 2 Reserved for future use. 3 DATA FIELD ECC ERROR - Error has been detected in the data field of a sector. If bit 6 in Controller-Invocation status byte (byte 1) is set, error is hard and uncorrectable. If bit 6 is not set, error is soft and correctable. 4 10 FIELD ECC ERROR - Error has been detected in the ID field of a sector. If bit 6 in Controller- Invocation status byte (byte 1) is set, error is hard and uncorrectable. If bit 6 is not set, error is soft and correctable. 5 DRIVE FAULT - Hardware fault detected in selected drive unit. Fault characterized by: read/write fault, positioner fault, power fault or speed fault. 6 CYLINDER ADDRESS MISCOMPARE - 10 field contains a cylinder address different from the expected cylinder address. 7 SEEK ERROR - Hardware seek error was detected.
3-21/3-22
CHAPTER 4 PRINCIPLES OF OPERATION
4-1. INTRODUCTION Logic gating symbols are 'drawn according to their circuit function rather -than the manufacturer's This chapter provides a functional description of the definition. For example, the gates shown in figure 4-1 iSBC 220 SMD Disk Controller circuit operation. The can be drawn in one of the two configurations shown, discussion assumes that the reader has a working depending on their circuit application. knowledge of digital electronics and has access to the individual component description of each integrated circuit used on the board. As a pre In addition to the inversion symbol convention, requisite, the reader should be familiar with the signal nomenclature also follows an active state con programming conventions discussed in Chapter 3 of vention. When a signal (or level) is active in its low this manual, and the functional operation of the state, the signal name is followed by a virgule or Intel 8089 I/O processor and the Multibus interface. "slash" (e.g., XACK/); when a signal is active in its Familiarity with the disk drive's operation and high state, the slash is omitted from the signal interface specifications will also prove beneficial in name, (e.g., XACK). This convention corresponds to understanding the controller operation. putting a bar over a signal name to indicate it is active in its low state (e.g., XACK).
4-2. SCHEMATIC INTERPRETATION
A set of schematic diagrams for the controller board 4-3. FUNCTIONAL OVERVIEW (figure 5-2) and a component location diagram (figure 5-1) are included in Chapter 5 ofthis manual. General. The function of the iSBC 220 SMD Disk Controller board is to allow the host system to access The schematics are drawn to standard drafting any location on a specific disk of a selected disk conventions with input signals entering from the left drive and either: and output signals exiting to the right. Input and output signals between individual sheets of a 1. Transfer data to that disk location from system schematic include a location coordinate code imme (host) memory (write operation), or diately preceeding (input signals) or following (output signals) the signal name. This code defines 2. Transfer data from that disk location to system the location of the origin or destination of the signal memory (read operation). within the schematic diagrams. The first digit of the code is the schematic sheet number, and the last two To accomplish this task, the controller circuitry is characters specify the zone defined by the horizontal divided into two sections (see figure 4-2): and vertical grid coordinates, which are printed around the perimeter of each schematic sheet. For example, the code "7B8" indicates that the origin or destination ofthe associated signal appears on sheet ACTIVE INPUT ACTIVE ACTIVE INPUT ACTIVE 7 of the schematic set within the zone defined by grid RELATIVE OUTPUT RELATIVE OUTPUT HIGH RELATIVE LOW RELATIVE coordinates "B" and "8". HIGH BaLOW An "X" for one of the grid coordinates indicates an E> entire vertical column or horizontal row on the ACTIVE INPUT ACTIVE ACTIVE INPUT ACTIVE schematic sheet. For example, the code "7BX" RELATIVE OUTPUT RELATIVE OUTPUT indicates the entire "B" zone on sheet 7. LOW RELATIVE HIGH RELATIVE SHIGH LOW The logic symbols used in this manual are drawn as E> specified in ANSI Standards 14.15 and Y32.14. Standard definitions are used for symbols and active line levels on inputs and outputs (see figure 4-1). A small circle on the input of a logic element indicates ==lD------EXCLUSIVE that a relative low level is needed to activate the OR element. The absence of a circle indicates that a relative high level is needed to activate the element. Output levels are indicated in the same manner. Figure 4-1. Logic conventions.
4-1 Principles of Operation :i~BC220 ~
r------~------l I I I I I INTEL I I 8089 I I lOP I ISBCN MICROCOMPUTER I I J1 DISK INTERFACE INTERFACE TO (L-_----' LOCAL BUS J2 ~'?~1l~~g; r-----~--, INTERFACE
J3 "«"----I1.Jl ~------~ ~------~ I I I I PROM RAM I SYSTEM MEMORY I 1/0 COMMUNICA TIONS BLOCKS I I TERMINATION L ______~~~~~~~~~N~~~~ ______J
Figure 4-2. Simplified block diagram of iSBC 220 controller.
1. Logic that controls communications and data between system memory and the on-board RAM. It transfer between the host processor and the also controls the transfer of data from RAM to the controller through the Multibus interface, and disk communication circuitry. 2. Logic that controls data transfer between the controller and the disk drive(s) through the SMD The Multibus interface Address Latches transmit 20- interface. bit addresses to system memory via the Multibus interface. The Multibus interface Data Transceiver The Intel 8089 I/O processor (IOP) controls the data transmits data either to or from system memory via transfer process, using a program stored in on-board the Multibus IntE;lrface. The controller data bus is 16- ROM. It receives instructions from the host processor bits. The Data Transceiver uses a byte-swap tech- through four I/O communications blocks in system . nique to allow data transfer with either an 8-bit or 16 memory. Once the host instructs the controller to bit system memory. begin a data transfer, the 8089's internal processor makes a DMA transfer to or from system memory, The Wake-Up Address Comparator is used to assign independent of the host processor. the controller a host system I/O port address and to set up a communications link between the 8089 lOP 2K bytes of RAM are included on the board for and the I/O communications blocks in system intermediate storage of data and to allow on-board memory. (A detailed discussion of the controller error checking. This data buffer allows DMA initialization procedure is given in Chapter 3 and in transfer to be made between the controller and host paragraphs 4-12 through 4-15 in this section.) system memory, which minimizes Multibus overhead and eliminates disk drive overruns. Communicating with the disk. The 8089 lOP treats the ROM, RAM and disk communications side Communicating with the host. Figure 4-3 pro of the controller circuitry as local memory. The Local vides a detailed block diagram ofthe controller. The Address Latches transmit 16-bit addresses to local Bus Arbiter and the Bus Controller manage the memory. The Local Data Transceiver transmits data transfer of data between system memory and con either to or from local memory. Some of the addresses troller through the Multibus interface. The Bus in local memory provide access to local I/O ports Arbiter negotiates with the current bus master for (see paragraph 4-20 for a detailed-discussion of local control of the Multibus interface. The Bus Controller I/O ports). The Address Decoder decodes these generates control signals that gate data transfers addresses· and generates chip select or enable
4-2 iSBC220 Principles of Operation
L. + SERIAL INPUT DATA RE~ - CHNL 14 CHIP SELECT SERIAL ECC FR OM WAKE-UP ADDRESS 32 BIT ATTN INTEL ECC DATA SERIAL ECC ERROR DI SK ADDRESS 8089 -+ DECODER ECC ...... - SELECTOr;- GENERATOR [7 DETECTOR[7 DR IVE COMPARATOR lOP [5 r 12 i or( SERIAL INPUT DATA "SHEET 10 [4 CSROMI II: r-- fI) () r 8089 16 MULTIBUS'· 16 SERIAL + ADDRS/DATA LOCAL ~ .. INTERFACE IADR SERIAL INPUT DATA 16 BIT OUTPUT DATA ADDRESS ADDRESS SELECTOR LATCH ~ SER/DES 17 WR~VDAT MULTIBUS'· LATCHES + ~ - INTERFACE IT ADDRESS 14 Is V TO ROM RAM DIS K 8K 2K f DRI VE MULTIBUS'· LOCAL [6 rs MULTIBUS'· DATA INTERFACE ..... INTERFACE DATA DATA TRANSCEIVER TRANSCEIVE~ IDAT L16 i t [4 NC.'" MULTIBUS" INTERFACE ID NCMPRI ~"-,,,, I COMP BUS ~ONTROL CONTROLLER 1 - MULTIB 13 ~ I INTER FACE DISK CONTROL STATUS U'f~ 16 BIT 16 BIT 32 BIT DISK ~ CONTROL BUS WRITE READ ID STATUS INTERFACE CONTROL RECEIVED ARBITER BUFFER BUFFER ... COMPARATOR REGISTER DISK +-- LOGIC ~ .... ~ [1i STATUS [7 [7 rg '12 11 [12 [3 AND FRO M CLOCK DISK t t 1 t DR IV E l I ~ o = SCHEMATIC SHEET NUMBER OUT 0 GAP SMD BUS -±- OUT 1 DISK CONTROL CONTROL GAP CONTROL .. CONTROL COUNTER DRIVERS OUT 2 LOGIC TIMING LOGIC CONTROL -=--. 8 JI fi2 lTI TO DISK t DISK STATUS AND CLOCK DRIV E
Figure 4-3. iSBC 220™Controller Functional Block Diagram
4-3/4-4 iSBC220 Principles of Operation signals that control the transfer of data to and from 4-4. DETAILED FUNCTIONAL the disk. For example, the address 8028H enables the DESCRIPTION I6-Bit Write Buffer to receive a data word from the local memory. The ROM and RAM are also assigned The detailed functional description of the iSBC 220 specific ranges of addresses in local memory. SMD Disk Controller circuitry is divided into two major sections: Controller to Host Communications The I6-Bit SER/DES (Serializer/Deserializer) per and Controller to Disk Communications. Within forms the serial-to-parallel and parallel-to-serial each of these sections, the following subjects are conversion required to transfer data between the discussed: disk and system memory. The I6-Bit Write Buffer and the I6-Bit Read Buffer provide intermediate storage for a single 16-bit parallel word between the Controller to Host Communications: RAM and the SER/DES. On a write operation, a 16- • Multibus Interface bit word is transferred from RAM to the write buffer. The SER/DES then converts the word from parallel • 8089 lOP to serial and transmits it to the disk through the • Bus Arbiter write data driver. On a read operation, a I6-bit serial word is transmitted from the disk through the Read • Bus Controller Data Receivers to the SER/DES. The SER/DES • Multibus Interface Data Transfer Logic then performs a ser~al-to-parallel conversion and • Controller Initialization stores the resulting parallel word in the read buffer. The Write Data Driver and the Read Data Receivers • Wake-Up Address Comparator are designed to generate and read SMD standard • Controller Reset and Clear drive signals. • Establishing a Link with I/O Communications Blocks The 32-Bit ID Comparator determines when the • Interrupt Priority selected sector on the disk is found during the search for sector ID operation that precedes a write or read • Memory Map function. When a write or read is initiated, the 32-bit • ROM sector identification (cylinder, head and sector number) is loaded in the 32-Bit ID Comparator. • RAM Sector IDs from the disk are then read and compared • I/O Port Decode Logic with the selected sector ID. When the selected sector is found, data transfer is initiated. Controller to Disk Communications
The 32-Bit ECC Generator creates an error checking • Controller to Disk Drive Interface code (ECC) that is appended to the end of each sector • DMA Mode ID field and to each data field (see figure 3-1). This Disk Formatting ECC is used for error checking and correction of data • errors. It allows all the errors in a burst of up to 11 • Write Data Transfer bits to be corrected. • Read Data Transfer • SER/DES Logic The Gap Control Logic controls the spacing of data Sync Byte Comparator Logic within a sector. Three programmable Counters, • which count disk clock pulses, provide timing for the • 32-Bit ID Comparator Logic Gap Control Logic. The ability to program the • ECC Generator Logic Counters allows the disk(s) to be formatted for a Status Register Logic number of different record sizes. • • Line Drivers and Receivers The SMD Bus Control Logic transmits disk control information to the disk drive units through the Control Line Drivers. The Input Control Logic receives status information from the disk drive units 4-5. CONTROLLER TO HOST and controls the sequencing of the controller read COMMUNICATIONS and write operations. The following discussion provides a detailed func tional description ofthe section ofthe iSBC 220 SMD A more detailed overview of the read and write Disk Controller that communicates with the host operations is given in paragraph 4-29 through 4-33. through the Multibus interface.
4-5 Principles of Operation iSBC220
4-6. MULTIBUS INTERFACE 4-8. CLOCK CIRCUIT
The 8089 lOP communicates with the host processor The clock circuit consists of U59, an 8284A Clockl and the system memory through the Multibus Driver (4C5), and a 15 MHz crystal. The 8284A interface. The Multibus interface signal description divides the crystal output by three to produce the 5 and pin configurations are explained in Chapter 2. A MHz CLK necessary to drive the 8089 lOP. The detailed description of the Multibus interface 8284A produces a reset signal (RST), which is used operation can be found in the Intel Multibus on power-up to reset the 8089, Interrupt Latch U60 Specification Intel Order Number 9800683. (3B6) and the Read/Write Control logic. In addition to the reset signal, .the 8284A also produces a synchronized ready input to the 8089. A high on the READY line received from the addressed device (XACKI from external memory, RDY I TIME OUT 4-7. 8089 1/0 PROCESSOR (lOP) from the on-board read/write port), indicates that the memory or read/write port has accepted data The 8089 IOP, U79 (4X4), is a microprocessor device during a write operation or data is ready to be read that has been designed specifically to perform high during a read operation. speed I/O transfers of data between system memory and mass storage devices such as disk drives. Its ability to perform DMA data transfers independent 4-9. BUS ARBITER of the host processor allows it to carry out most system memory-to-disk transfers of data simultane The 8289 Bus Arbiter, U85 (3D6), controls the 8089 ously with other host processor operations. Refer to lOP's access to the Multibus interface (see Figure The 8086 Family User's Manual, Intel Order Number 4-4). The 8289 monitors the 8089's status lines (SOli, 9800727 for a detailed explanation of the 8089 and SlI and S2/). When the lines indicate that the 8089 supporting IC devices. needs a Multibus interface cycle, and the 8089 does not presently control the bus, the 8289 activates a bus request (BREQ/). The low on BREQI is trans A number of 8089 control lines have important func mitted to the bus priority resolving circuitry in the tions in the controller design. The RESET line (4D4), host processor, which returns a low on Bus Priority when pulled high, resets the 8089 to the beginning of In line BPRN/, giving the 8089 access to the its internal firmware control program. Channel Multibus interface. Having received access to the Attention line CA (4C4) allows the host to gain the Multibus interface, the 8289 activates its busy signal attention of the 8089. On the first channel attention (BUSY I), indicating to the other masters on the following a reset, the 8089 fetches the contents of system that the Multibus interface is in use. The address FFFF6H and begins an internal initializa 8289 then activates the address enable signal tion procedure. On subsequent channel attentions, (AEN I), which is transmitted to the 8288 Bus the 8089 looks to the I/O communications blocks in Controller, U86 (3C4), to enable its command system memory for further instructions. Refer to outputs, to the 8284A Clock Generator, U59 (4C6), to paragraphs 4-12 through 4-15 for a detailed discus enable its bus ready logic, and to the System sion of the controller initialization procedure and the use of the CA line. Address Latches, U76-U78 (4X2), to allow an address to be gated on to the Multibus interface.
The Bus Interface Unit (BIU) in the' 8089 controls the controller local data bus cycles, transferring 4-10. BUS CONTROLLER LOGIC instructions and data between the 8089 lOP and external memory or the disk. Every bus access is The 8288 Bus Controller, U86 (3C4), decodes the associated with a register tag bit that indicates to status line outputs (SOl, SlI and S2/) from the 808.9 the BIU whether the host system memory or local lOP and generates the appropriate bus cycle signal. memory is to be addressed. The BIU outputs the type Table 4-1 shows the different signals generated for of bus cycle on status lines SOl, SlI and S2/. The each configuration of the lOP's status lines. 8288 Bus Controller decodes these lines and provides signals that selectively enable one bus or the other. These bus cycle signals can be divided into two groups: those which allow the 8089 to access system The 8089 is a 16-bit processor, but it is capable of memory (MWTCI and MRDC/) and those which making both single-byte fetches (8-bit system allow the 8089 to access local memory (I-AIOWCI memory) or two-byte fetches (16-bit system memory). and I-IORC!). The 8089 uses the I/O Read (I-IORC/) The address zero line, IADR-O (5Cl), controls the and I/O Write (I-AIOWC/) signals to read informa byte swapping facility of the controller when tion from the local ROM, U82 and U83, (6X7), or to communicating with an 8-bit system memory. read from or write to the local RAM, U94 through.
4-6 iSBC 220 Principles of Operation
ROY + TIME OUT ROY 1 US9 RESET RESET FROM READY ROY 2 T RANSFER ACKNOWLEDGE WAKE-UP (XACKI) lOGIC (U39) ---<: AEN 1 AEN2 ClK14
U8S BUS ClK ARBITER MULTIBUS CONTROL ~l OGIC
r- SO/-S2/ CHNl ATTN CA ClK AEN f3 8089 CHANNEL U79 SELECT SEl (RDC18) <"""( END EXT 1 TIME AEN 50/-52/ 50/-52/ MRDC. 0-_ MEMORY READ COMMAND
ClK MWTC 0-- MEMORY WRITE COMMAND ADO-AD19 f4 INTA 110 READ 10RC ct U86 110 WRITE 10WC ALE BUS ~ CONTROllER STB / STB OE PDEN DT/R DENf3 / 20 lOCAL 16 MUlTIBUS U80/U81 ADO-AD19 U76/U78 /20 ADDRESS ADDRESS ~ IADR-O - IADR-F ~ LINES (ADR-O/ - ADR-13/, BHEN/) Is f4
1 ~ OE T V T OE / 16 U56/U57 U91/U93 lOCAL ADO-AD1S /16 _ DATA ..;.. .. MUlTlBUS DATA LINES IDAT-O-IDAT-F / (DAT-O - OAT-F) [4 f4
Figure 4-4. Bus Arbiter and Bus Controller Logic
4-7 Principles of Operation iSBC 220
Table 4-1. 8089 Status Line Decodes the controller is interfacing with an 8-bit system memory. In this case, every odd address read from Status Input CPU Cycle 8288 Command system memory is transmitted to the high-byte data 521 511 501 lines of the controller. The procedure is reversed 0 0 0 Instruction Fetch, INTAI when writing to the 8-bit system memory. Three Local signals control the transceiver: ENBL HI BYTEI 0 0 1 Read Memory, IORCI Local (5Cl), which controls the high-byte transceiver; ENBL LO BYTEI (5Cl), which controls the low-byte 0 1 0 Write Memory, IOWC/, AIOWCI Local transceiver (derived from ADRO/); and ENBL 8WAP BYTE I (5C1), which controls the swap byte 0 1 1 Halt None transceiver. Figure 4-5 shows when each of the 1 0 0 Instruction Fetch, MRDCI System control signals is active. 1 0 1 Read Memory, MRDCI System 1 1 0 Write Memory, MWTC/, AMWCI System 1 1 1 Passive None 4-12. CONTROLLER INITIALIZATION
U97, (6X4). The 8089 also uses l-IORCI and 1-IOWCI Before data can be transferred between system to gate on the Read and Write Function Decoders, memory and the controller, the controller must be U33 and U32 (5B2 and 5A2). The function decoders initialized. The initialization procedure, which is are explained further in paragraph 4-20. described in paragraph 3-12, involves:
The 8288 Bus Controller also generates a group of 1. Resetting the 8089 IOP. signals that control address and data flow through 2. Clearing the reset. out the i8BC 220 controller. The Address Latch Enable line (ALE) is used to strobe addresses from 3. Establishing a communication link between the the 8089 into both the system Address Latches, U76- 8089 and the I/O communications blocks in U78 (4X2), and the Local Address Latches, U80-U81 system memory. (5X7). 4. Reading the disk drive parameters from system memory to the controller on-board RAM .. Data TransmitlReceive (DT IR), Data Enable (DEN), and Peripheral Data Enable (PDEN/) control the The following paragraphs describe the hardware data flow through the controller. DT/R controls the operations that take place during this initialization direction of data transmission through the Multibus procedure. interface and local transceivers. If DT IR is high, data is transmitted either on to the Multibus interface through transceivers U91, U92 and U93 (4X7) or on to the local bus through transceivers U56 and U57 (4X6). IfDTIR is low, the data transfer is in the opposite direction, into the 8089 through one of 4-13. WAKE-UP ADDRESS COMPARATOR the two sets of transceivers. DEN and PDEN controls the selection of the transceivers. If DEN is For the purpose of resetting the controller, clearing high the Multibus interface transceivers U91, U92 the reset or getting the attention of the 8089 lOP and U93 are enabled, and if PDENI is low (indicat (raising CA), the host addresses the controller as an ing a peripheral cycle) local transceivers U56 and 1/0 port in its system I/O space. To perform one of U57 are enabled. these functions it writes a one byte command to the specified I/O port called the wake-up I/O port (see Figure 4-6). Table 4-2 shows the three possible com 4-11. MULTIBUS INTERFACE DATA mands. The user determines the address of the I/O TRANSFER LOGIC port at which the controller is to reside (called the "Wake-Up Address") and sets the address on the The controller has three sets of Multibus interface Wake-Up Address switches 81-1 through 81-8 and data transceivers: low-byte transceiver U92, which 82-3 through 82-10 (2x6) , on the controller board. buffers DAT-OI through DAT-7I, high-byte trans When the host issues a write command (IOWC/) to ceiver U91, which buffers DAT-81 through DAT-F/, the Wake-Up Address in system I/O space, U70 and and swap-byte transceiver U93, which takes the un (2A5) on the controller compare the address data from DAT-OI through DAT-71 on the Multibus with the switch settings. If they agree, WAKEUP/is interface and switches it to high-byte data bus lines pulled low, enabling the controller to decode the com AD8 through AD15 on the controller board (see mand on the Multibus interface data lines and deter figure 4-5). This byte-swap is performed only when mine the action to be taken.
4-8 iSBC220 Principles of Operation
HIGH HIGH /8 BYTE /8 /8 HIGH BYTE BUFFER BYTE
8 + 8089 SWAP ADDRESSI MULTIBUS DATA BUS BYTE ADD- BUFFER AD15
LOW LOW /8 /8 LOW BYTE BYTE , " BUFFER BYTE
iSBC 220 CONTROLLER
8-BIT 16-BIT SYSTEM MEMORY SYSTEM MEMORY
I-ADRO/ = L I-ADRO/ = H I-ADRO/ = L I-ADRO/ c H , ENBL LO BYTE/ L H L , ENBL SWAP BYTE/ H L H , ENBL HI BYTE/ H H L 'NOT APPLICABLE
Figure 4-5. Data Transmission Between Multibus™ Interface and Controller Data Transceivers
The host may use 8-bit or I6-bit I/O port addressing. 4-14. CONTROLLER RESET AND CLEAR The user sets switch 82-2 (2A 7) to indicate to the con troller the type of addressing that is being used. The first operation that must be performed during When 82-2 is open (8-bit addressing), pin 9 of U70 is the initialization of the controller is a reset of the held high, creating a "don't care" situation for the 8089 lOP. To reset the 8089, the host processor writes outputs of High-Byte Wake-Up Address Comparators an 02H to the wake-up address. The WAKE-UP/ U72 and U73. lines goes low and gates the 02H (DAT-O/ high and DAT-l/ low) into the Wake-Up Decoder, U39 (3B7), producing a low on the controller reset (CNTLR RST /) line. A low on CNTLR R8T / resets the 8089 Table 4-2. Host Wake-Up Commands (4X4), resets Read/Write Control Logic U36 (sheet 8) Command Description and clears Control Register U2I (UB7). Once the controller has been reset, the host processor writes a OOH Clear Interrupt and Clear Reset OOH (Clear Interrupt) to the wake-up address, which 01H Channel Attention (Start 8089 lOP) clears the reset. The Wake-Up Decoder U39 decodes 02H Reset 8089 lOP the highs on DAT-O/ and DAT-l/ to raise CNTLR R8T/.
As it is discussed in Chapter 3, the controller also 4-15. ESTABLISHING A LINK WITH uses the setting of the Wake-Up Address switches to I/O COMMUNICATIONS BLOCKS calculate the address of the first byte ofthe Wake-U p Block, which is the first I/O communications block Following a power-up event or a software reset (02H in system memory. written to the wake-up I/O port), the link between
4-9 Principles of Operation iSBC220
WAKE-UP ADDRESS MULTIBUS'· DAT-O-D~ INTERFAC~ /16 DATA AD-O - AD-15 , TRANSCEIVER V16 / / / 16 S'· 16 WAKE-UP MULTIBU /16 INTERFA CE WAKE-UP BUFFERS 8089 / ~ -+ U79 SWITCHES U88 - U90 WAKE-UP ADDRESS TO SYSTEM MEMO RY 16-BIT SYSTEM BUS TO BEGIN COMMUNICATI ON 8/16 I BIT S2-2 rCA WA KE-UP RESET ADD RESS FROM HOST /16 WAKE-UP CHNL ATTN ADR -0/ - ADR-F/ , ADDRESS COMPARATOR - WAKE-UP DECODER U39 RESET RESET CNTLR RST/ WAKE-UP I/O PORT CLEAR LATCH MULTIBUS'· DAT-O/ and DAT-1/ /16 RESET U40 INTERFACE , ADDRESS OOH - CLEAR RESET 01H - INITIALIZE 02H - RESET 8089
Figure 4-6. Wake-Up Address Logic
the controller and the I/O communications blocks in Fetching addresses FFFF8/9H gates zeros into the system memory must be established. To establish 8089. Fetching addresses FFFFA/BH causes the this link, a clear reset (OOH) is written to the wake-up GATE SWS/ line (5C1) to go low. GATE SWS/ gates I/O port followed by a channel attention (OlH). The the settings of the wake-up address switches, Sl-l 01H is gated into U39, producing a high on CHNL through Sl-8 and S2-3 through S2-10 through buffers ATTN, which in turn raises the CA input to the 8089 U88, U89 and U90 (2X2) and into the 8089. The 8089 IOP (4C4). multiplies the settings of the wake-up switch by 24, to determine the 20-bit address of the wake-up block, the first I/O communications block in system Being the first Channel Attention following reset, memory. The 8089 then uses this address to fetch the the 8089 begins an internal initialization process. wake-up block and establish a link with the I/O The first step of this prpcess is to do a fetch of communications blocks. On subsequent channel address FFFF6H. The address is transmitted on the attentions (host writes 01H to the wake-up I/O port), 8089 AddresslData lines (ADO-AD15) to latches U80 the 8089 skips the wake-up block and goes directly to and U81 (5C7). Gates U61, U69, un and U47 (5D4) the channel control block, the second I/O communi decode the output of these latches. The output of un cations block. The 8089 uses the channel control enables U67, gating the status ofthe 16-bit SYS BUS switch (S2-1) through Data Bit 0 line (DAT-O/) to the 8089. Switch S2-1 on (16 Bit SYS BUS/ low) indicates that the host memory system supports 16-bit data transfers and 82-1 off indicates 8-bit data transfers. FFFF6 Inverter U67 also generates Transfer Acknowledge FFFF8~ (XACK/), which is sent to the 8089 (through the 8-BIT FFFF9 16-BIT 8284A) indicating that the operation has been SYSTEM BUS ~ FFFFA SYSTEM BUS completed. FFFFB
After determining the width of the system bus (8-bit Figure 4-7. Address Fetches In Initialization or 16-bit) the 8089 fetches the addresses shown in Sequence. figure 4-7 as part of the initialization sequence.
4-10 iSBC220 Principles of Operation
block to obtain the starting address of the con 4-18. ROM troller's ROM resident I/O transfer program (also called the channel control program). From this point The controller ROM, which contains the 8089 lOP's on, this firmware program directs the controller disk control program, consists of two (4K x 8-bit) activities. One of the first operations of the firmware ROM devices, U82 and U83 (6C7). On any read from is to again fetch the starting address of the wake-up local memory in the range of OOOOH to IFFFH, chip block. It then links its way through the channel select decoder U39 (5C2) decodes address lines control block and the controller invocation block to lADR-E and lADR-F and pulls ROM chip-select line the I/O parameter block where it obtains instruc CSROMI low, enabling the ROM devices. tions and parameters for a specific I/O operation.
4-16. INTERRUPT PRIORITY LOGIC 4-19. RAM
Wire wrap pins W4-C and W4-0 through W4-7 (3B2) The controller RAM consists of four (IK x 4-bit) allow the user to select the interrupt priority of the RAM devices, U94 through U97 (6X4). On any read controller with respect to other peripherals in the or write to local memory in the range of 4000H to system. To issue an interrupt to the host, the 8089 47FFH, chip select decoder U39 (5C3) pulls RAM lOP writes an OIOOH to local 110 port 8010H. A high chip-select line CSRAMI low, enabling the RAM on data line BDAT-8 and a low on write decoder line devices. WDClOl is then generated, causing interrupt latch U60 (3B6) to pull its output high and pull the selected interrupt line to the Multibus interface low. A OOH 4-20. LOCAL MEMORY MAPPED written to the system I/O port wake-up address, 1/0 PORTS clears the interrupt (refer to paragraph 4-14).
Jumper pins W2-C, 1 and 2 allow the user to select The 8089 IOP views the controlling devices in the the Any Request option. A jumper installed between disk control circuitry (such as lD comparators, pins W2-C and 1 causes the controller to relinquish counters, write buffer, read buffer, etc.) as local 110 control of the Multibus interface following a request ports, each with an address in local memory space. from a higher priority device only. A jumper installed To enable one of these devices, the 8089 executes a read or a write to the devices respective address. On between pins W2-C and 2 causes the controller to any read or write to local memory in the range relinquish control of the Multibus interface following 8000H through 8038H, chip select decoder U39 (5C3) a request from any device, higher or lower priority. pulls its pin 10 low. When this low on pin 10 ofU39 is accompanied by a low on I/O read line I-IORC/, 4-17. LOCAL MEMORY MAP read I/O port address decoder U33 (5B2) is enabled; when the low on pin 10 of U39 is accompanied by a As was discussed in the Functional Overview, the low on I/O write line l-AlOWC/, write I/O port 8089 lOP addresses the ROM, RAM and the disk address decoder U32 (5A2) is enabled. When enabled, communications side of the controller circuitry as U32 or U33 decode local memory address lines local memory. Figure 4-8 shows a map of this local lADR-3 through lADR-5 to select the desired disk memory. The following paragraphs discuss the control device. Table 4-3 shows the address of each ROM, RAM and I/O ports. local 110 port and its function.
FFFFH
8038H 8000H SHADED AREA INDICATES UNUSED ADDRESS SPACE
47FFH 4000H
1FFFH
OOOOH '------' Figure 4-8. Local Memory Map
4-11 Principles of Operation iSBC220
Table 4-3. Local 1/0 Ports
Read (U33 Enabled) Write (U32 Enabied) Address Enable Line Function Enable Line Function" 8000H RDCOOI "Read Disk Status WDCOOI Write to bils O. 1.4.5,6 and 9 of SMD bus. 8008H WDC081 Clear index and 10 not compare latches 8010H WDC101 Write to control register. 8018H RDC181 Raise 8089 Ch 2 CA input. WDC181 Write" to SMD bus Unit Select register 8020H RDC201 Read contents of counter 2 WDC201 Load counter 0 8022H RDC201 Read contents of counter 1 WDC201 Load counter 1 8024H RDC201 Read contents of counter 2 WDC201 Load counter 2 8026H WDC261 Write mode word 8028H RDC281 Read contents of read buffer WDC281 Write data to write buffer 8030H WDC301 Write sector 10 to high comparator. start track format operation. 8038H WDC381 Write sector 10 to low comparator
4-21. CONTROLLER TO DISK DRIVE 4-23. CONTROL CABLE SIGNALS COMMUNICATIONS Control and status information is exchanged be The following discussion provides a detailed func tween the controller and the drive through the tional description of the section of the iSBC 220 SMD Control Cable. Output signals are defined as those Disk Controller that communicates with the disk signals that the controller transmits and input drive through the SMD interface. The discussion is signals as those the controller receives. The Control broken into four areas: (1) description of the SMD Cable is connected to Jl on the iSBC 220 board and interface signals; (2) explanation of how the con goes to the first drive in a string of up to four. troller formats a disk prior to the performing read Subsequent Control Cables are connected from drive and write functions; (3) explanation of how writes to drive in a daisy chain fashion. The eighteen and reads are performed; and (4) descriptions ofthe output lines, which the controller transmits to the various circuits that perform the data transfer. disk drives through the Control Cable, are: a. Device Select Enable Line b. Device Select Lines (4) c. Function Tag Lines (3) 4-22. CONTROLLER TO DISK DRIVE INTERFACE d. Bus Out Lines (10) The eight input lines, which the controller receives All the signals that are transmitted between the from the disk drives through the Control Cable, are controller and the disk drives are transmitted status lines. through either the Control Cable or the Read/Write Cable. The physical configuration of these cables is described and illustrated in Chapter 2. The SMD 4-24. SELECTION LINES specification requires signals that are transmitted between the drives and the controller to be differen The controller transmits five disk drive selection tial signals, and receivers to translate the differential signals to the drives: input signals to levels compatible with internal logic. a. Device Select Enable. (Unit Select Strobe). Enables the decode logic that the drive uses to decode the device select lines. b. Device Select 0 through Device Select 3. The following functional description of the interface Four binary coded lines select the desired disk signals is based on a typical drive installation. drive. A module select identifier plug in each Different drive manufacturers may use these signals drive (which the operator can change) deter for other functions. While reading this discussion, mines the address of each drive. See the disk consult the drive manufacturer's user manual for the drive manufactuer's OEM manual for instruc specific drive being employed. tions.
4-12 iSBC220 Principles of Operation
Table 4-4. Function Tag/Bus-Out Definitions
BUS OUT FUNCTION DECODE BITS SET CYLINDER·TAG 1 SET HEAD ADDRESS-TAG 2 CONTROL SELECT-TAG 3 0 Cylinder Address 1 Head Select 1 Write Select 1 Cylinder Address 2 Head Select 2 Read Select 2 Cylinder Address 4 Head Select 4 Offset Forward 3 Cylinder Address 8 Head Select 8 Offset Reverse 4 Cylinder Address 16 Head Select 16 Unsafe Reset 5 Cylinder Address 32 Address Mark 6 Cylinder Address 64 Rezero 7 Cylinder Address 128 Data Strobe Early 8 Cylinder Address 256 Data Strobe Late 9 Cylinder Address 512 Not Used
4-25. FUNCTION TAGS AND b. SET HEAD ADDRESS (TAG 2). Gates the BUS-OUT LINES Bus-Out lines to the selected disk drive. These lines are decoded in the drive to select the fixed or The controller generates three different function tag removable volume and the head within the volume. signals. These lines are used in conjunction with the Selection of a surface is normally referred to as Bus-Out lines to control the disk drive operations. selecting a head (the head that corresponds to a Only one of the tag lines may be active at a time. surface). The head address corresponds to one track Table 4-4 shows how the Bus-Out lines and tag lines in a given cylinder of a fixed or removable volume. are decoded to perform tasks or transmit data to the The head number within a volume is always as disk drive. sumed to start with zero. Bus Out bit 4 selects the type of volume: fixed or removable. a. SET CYLINDER (TAG 1). Transfers the cylinder address bits to the drive via the Bus-Out lines and initiates internal drive functions. Typically the Set Cylinder Tag line loads the next cylinder address into the drive logic at the leading edge of the set cylinder pulse (see Figure 4-9), allowing sufficient c. CONTROL SELECT (TAG 3). Gates coded time for the drive logic to perform necessary internal commands, as listed in Table 4-4, to a selected disk operations (difference calculations and set up of the drive. A description of the functions of these servo circuitry), and initiates the seek signal within commands is given in Table 4-5. A detailed func the drive coincident with the trailing edge of the set tional description of each of the listed operations can cylinder pulse. The typical times required for this be found in the disk drive manufacturer's OEM operation are provided in Figure 4-9. manual.
~B=U_S-_-O=T_H-R=U=_9-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_--~--~~~~~I~------~i~' ~ ______I I I I I I I I SET CYLINDER TAG I . !-I------!I I I ON CYLINDER I i T1 = 0.2 /lsec (min.) I T2 = 1 JlSec (min.) I T3 = 0.2 JlSec (min.)
Figure 4-9. Set Cylinder Timing
4·13 Principles of Operation iSBC220
Table 4-5 Control Tag and Bus Out Line Functions
CONTROL FUNCTIONS DESCRIPTION WRITE SELECT Enable the write circuitry in the drive, permitting write data, sent to the drive over the Read/Write cable, to be written on the selected disk surface. If one of the following conditions occurs when the Write Select signal is sent to the drive, the drive fault logic activates and sends an Unsafe status to the controller: 1. no write data is sent, 2. the Write Protect Line in the drive is active, 3. offset is active, or 4. the drive Ready signal is not active, READ SELECT Causes the drive circuitry to read from a selected area of the disk, convert that raw data to Non Return To Zero format (NRZ) data, and transmits it over the Read/Write cable to the controller. OFFSET FORWARD Causes the head positioner in the selected disk drive to move the selected R/W head a fixed distance towards the center of the disk, from the nominal track position. If this signal is activated while Write Select is active, the drive will activate the Fault status line to the controller. This signal is activated in an attempt to recover hard to read data (suspected soft error). OFFSET REVERSE Causes the head positioner in the selected disk drive to move the selected R/W head a fixed distance towards the outer edge of the disk, from the nominal track position. If the signal is activated while Write Select is active, the drive will activate the Fault Status line to the controller. This signal is activated in an attempt to recover hard to read data (suspected soft errors). - FAULT CLEAR Clears the Fault or Unsafe status line in a selected drive. This signal has no effect unless the fault condition has been corrected. ADDRESS MARK ENABLE Used in conjunction with either Write Select or Read Select. When it is used with Write Select, it allows the controller to write an AM. When used with the Read Select, it indicates the controller is looking for an address mark. Activating the address mark enable line in the drive enables the address mark detection logic to look for a 16 bit gap in read data pulses. See AM Found Status Line, Table 4-6. REZERO Causes the head positioner in the selected disk drive to position the Read/Write heads over cylinder o. Activation of the Rezero signal in the drive causes the Seek Error and the Head Address Register (HAR) to be reset and set to zero respectively. DATA STROBE EARLY Used with the Read Select Signal to a selected disk drive to attempt to recover hard to read data (suspected soft error). Activation of this signal causes the clocked data separator in the disk drive to strobe the data at a fixed time earlier than nominal. DATA STROBE LATE Used with the Read Select Signal to a selected disk drive to attempt to recover hard to read data (suspected soft error). Activation of this signal causes the clocked data separator in the disk drive to strobe the data at a fixed time later than nominal.
4-14 iSBC220 Principles of Operation
4-26. STATUS LINES b. data relating to the position of the R/W heads on the disk surface, which the controller uses to The eight status lines sent to the controller form a condition circuitry for timing, reading, or selected disk drive over the Control Cable provide: writing. A description of these status lines is a. an indication of the drive status provided in Table 4-6.
Table 4-6 Status Line Definitions
STATUS LINE DESCRIPTION INTERFACE ENABLE Indicates to the drive that continuity exists between the controller and the drive via the Control Cable. Without this continuity, line receivers in the disk drive will not be enabled for communications with the controller. This signal may be called Open Cable Detect in some drive manuals. INDEX MARK A pulse received from a selected disk drive once every disk revolution (16.67 ms); nominally 2.4J.1s in duration. The index pulse indicates to the controller that a particular reference on the disk is passing under the R/W heads. FAULT Indicates to the controller that, within the selected disk drive, an unsafe condition has been detected, which would make the reliability of read/write operations questionable. Normally, logic in the drive will disable the read, write, and positioning circuitry until a Rezero operation, Fault Reset or operator intervention occurs. Depending on the particular disk drive, some conditions that would cause the Fault circuitry to activate are: a. Write Unsafe b. Write Transition Failure c. Write Current Failure d. Power Failure e. Multiple Head Select SEEK ERROR Indicates to the controller that the selected disk drive has failed to complete an initial head load, Seek operation, or Rezero operation within drive specified time limits. Seek Error is also set when an invalid cylinder address is sent to the drive. This signal may be reset by the controller issuing a Rezero command or by operator intervention. ON CYLINDER Indicates to the controller that the selected disk drive has successfully completed the initial head load, a Seek operation, or Rezero operation within drive specified time limits. On Cylinder goes inactive coincident with the issuance of Seek, Offset Forward, Offset Reverse or Rezero and is reactivated at the completion of the operation. UNIT READY Indicates to the controller the selected disk drive is: a. Selected b. The disk pack is up to its nominal speed c. The head load operation was completed successfully d. Fault. (unsafe) conditions do not exist in the drive e. The drive is not in the CE mode or off-line (see drive manufacturer's OEM manual).
4-15 iSBC220 Principles of Operation
Table 4-6. Status Line Definitions (Continued) ... STATUS LINE DESCRIPTION
WRITE PROTECTED Indicates to the controller that the selected disk drive's Write Protect switch is in the Protect position. The operator sets this switch to prevent the controller from writing over sensitive data. 7'0 deactivate this line, the switch must be moved to the other position. Receipt of this signal by the controller prevents writing on the selected disk drive. ADDRESS MARK FOUND Indicates to the controller that the selected disk drive has detected an area of a selected track that has an absence of data bits for at least 16 bit cell times. This signal is used to establish timing in the controller for the assertion of Read Enable, prior to reading an ID field and header.
4-27. READ/WRITE CABLE SIGNALS c. READ DATA. The Read Data signal is trans mitted from the disk to the controller via differential Read Data, Write Data, Clocks, and some status line pairs. This data read from the disk pack has lines constitute the information exchanged over the been separated from the clocks and put into the NRZ Read/Write cables. Output signals are defined as format. The data is transmitted to the controller in a those signals that the controller transmits to the serial fashion, bit-by-bit. The read data received at disk drives, and input signals those that the the controller and gated through the line receiver is controller receives. The Read/Write cables are strobed into the controller logic by the Read clock. connected from the controller to the disk drive in radial fashion, that is one cable from the controller to each of the drives. The Read/Write cable that d. READ CLOCK. The Read Clock signal is connects to J2 on the controller splits into two transmitted to the controller via differential line cables; one going to the drive at physical address 0; pairs. It is derived in the disk drive from the data the other going to physical address 1. The Read/ read from the disk. The controller uses Read Clock to Write cable that connects to J3 on the controller strobe the read data onto the board at the proper splits into two cables; one going to the drive at time relationship, see U63 (10B2). physical address 2; the other going to physical address 3. The physical configuration ofthese cables is explained and illustrated in Chapter 2. Each of the e. SERVO CLOCK. The 9.677 MHZ Servo Clock discussed signals are received or output by all the signal is transmitted to the controller via differential drives. The controller multiplexes all received line pairs. This signal is transmitted back to the signals (except SELECTED-DEV 0-3)(9B8) to com drive as Write Clock. Since the Servo Clock is mon lines (see Figure 5-2, sheet 10). All output derived from the servo signal that is recorded on the signals from the controller are fanned out to all four rotating disk, it reflects any speed variations. cables simultaneously. Therefore, the descriptions provided apply only to signals of a selected Read/ Write cable. . 4-28. SELECTED The only status line sent to the controller via the Read/Write cable is the Selected signal. This signal a. WRITE DATA. The Write Data differential is a result of the disk drive comparing the four device line pairs from the controller transmit the NRZ data select lines to the module select plug and achieving a to the drive for recording on the disk surface. The favorable comparison. When the Selected line for a write data transmitted over this differential line pair particular drive activates, it, in turn, enables the line is synchronized with the Write Clock signal. receivers for the selected drive's Read/Write cable on the controller. h. WRITE CLOCK. The Write Clock signal sent to the drive via differential line pairs synchronizes 4-29. CONTROLLER TO DISK DRIVE the write data. The write clock is derived from the INTERFACE TIMING Servo clock signal sent to the controller from the selected disk drive and thus ensures the proper bit The following paragraphs provide a detailed discus rate transmission when writing as well as when sion of the inter-circuit timing that occurs when reading the data back. formatting a disk, writing to a disk or reading from a
4-16 iSBC220 Principles of Operation
disk. The discussion is provided to describe the inter To perform a write or a read, the 8089 executes action of the timing logic shown on Sheet 8 of the firmware to set up data (write only) and condition Schematic Diagram, with the disk drive interface the hardware for the selected operation. It then receivers and drivers shown on sheets 9 through 12 enters the DMA mode and attempts to transfer data. and the other data transfer circuitry described in At this time; the R/W GATE (8D1) is high (see paragraphs 4-34 through 4-39. Figure 4-10); U45-8 (8D3) is high, held so by the low on the ENBL XFER line (8D1); and the R/WDC 28 line, the output of U42-6 (8D7), is low. The low on 4-30. DMA MODE R/WDC 28 is thus keeping RDY activated. On this first attempt to transfer data in the DMA mode, the 8089 activates either RDC 28/ or WDC 28/ (8D8), In general, when the controller is performing a read depending on whether a read or a write is being or a write function it locates the area of the disk performed, respectively (refer to paragraph 4-34). where the read or write is to be performed, then When RDC 28/ or WDC 28/ is activated, the enters its DMA mode to perform the actual transfer. R/WDC 28 lines is activated, lowering RDY and (The process oflocating the area to be read or written putting the 8089 into its quiescent (wait) state. When to is discussed in the following paragraphs.) In the the controller's data transfer circuitry has found the DMA mode, the 8089 lOP (see figure 4-2) controls the area on the disk where the read or write is to begin, it transfer of data between the local RAM block and activates ENBL XFER (8D1). On the next occurance the write and read buffers (called the read/write of a Bit Ring-O pulse, BR-O (8D1), following the port). The data transfer circuitry on the controller activation ofENBL XFER, U45-8 (8D3) is activated, board controls the transfer of data between the read/ activating RDY. The 8089 then immediately per write port and the disk. forms the data transfer (writes a word into the write buffer or reads a word from the read buffer) and The RDY (Ready) line (8D1) is used for hand shaking lowers R/WDC 28. On the next clock into U45-11, between the 8089 and the data transfer circuitry. U45-8 is raised. On the 8089's next attempt to When RDY is low, the 8089 is quiescent; when RDY perform a data transfer, R/WDC 28 is also raised, is high, the 8089 performs a DMA transfer of data lowering RDY. The data transfer does not occur and either from local RAM to the write buffer (block-to the 8089 goes into its wait state. During this time, port) or from the read buffer to local RAM (port-to the SER/DES either transfers the word from the block). Gate U46 (8D3) controls the RDY line. write buffer to the disk or reads another word from
BR-O (801)
U45-8 ----~ ~---I--..,.t (803)
RIWOCU42-6 28 ~ (807)
ROY (801)
R/W GATE (801) L
ENBL XFER (801) S J\ CTR11 ------11
Figure 4-10. Timing Diagram for RDY Signal
4-17 Principles of Operation iSBC220
the disk into the read buffer. Then on the next BR-O even physical data fields (0, 2, 4, ... ). Three disk pulse, RDY is again activated and the next DMA revolutions are thus required to format a single data transfer occurs; The 8089 continues in this track. The hardware execution portion of the format DMA mode until the R/W GATE line is lowered. operation is discussed in the following paragraphs.
When the Format command is issued to the con 4-31. DISK FORMATrING troller, the 8089 lOP begins the format operation by performing a Seek to the desired track (cylinder). Before the surfaces of a disk volume can be used for When the heads are positioned over the desired the writing and reading of data, the disk volume track, the 8089 writes a OOOOH to I/O port 80l0H must be formatted. Formatting is the operation of (decoded as WDC WI), which enables U21 (lIB7) writing all the address fields, gaps, ID headers, etc. and activates the Write Gate-F (U21-12), Control for the complete disk·volume. The controller performs Select-Tag 3 (U21-2) and FORMAT lines (lIA1). See this operation under software control. The software Figure 4-11.) Write Gate-F, which is transmitted routine that controls this disk formatting operation through U49 (lIB4) and BUS 0 (lIB1), and Control allows only. a single track to be formatted for each Select-Tag 3 are transmitted to the selected drive Format command. The host thus issues a new where they enable the write circuitry. The controller Format command to the controller board for each then writes all zeros to the drive while the 8089 waits track to be formatted until the formatting of the for the receipt of the first Index pulse (12D8). entire disk volume is complete. The receipt of Index sets latch U41 (12D5), which in The implementation of the Format command is turn sets bit F ofthe Status Register, U26 (12D3). To divided into two operations. During the first opera monitor the Status Register, the 8089 reads 1/0 port tion, address marks (AM), gaps and ID fields are 8000H (decoded as RDC 00). Upon detecting Index, written during a single disk revolution. During the the 8089 writes a XXXXH to lIO port 8030H second operation, data fields are written (using the (decoded as WDC 30), which enables the format logic write data sequence described in paragraph 4-32) U41 (8B6). Then the 8089 writes a OOOlH to I/O port with user supplied data. The second operation 8000H(decoded as WDC 00), which activates WRT requires two disk revolutions, one to write the odd GATE and allows the writing of address marks (AM) physical data fields (1, 3, 5, .... ) and one to write the and Sector ID fields.
~ I~I 10 IEccl ~ I~IID IEccl
( WRT GATE-F ---...r'' ~ FORMAT~ INDEXI ~
WRT GATE ,1 WDC 301 ,1
WRT AMI ,1
CTR 01 ,I
CTR 11 ,1
CTR 21 ,1
WRT XFERI ECC TlMEI L{ END TIME ~ :~, Figure 4-11. Timing Diagram for Disk Formatting
4-18 iSBC220 Principles of Operation
The time that the 8089 allows between the detecting The 8089 has previously written to I/O port 8020H ofIndex and the activating ofU41 (I2D5) is approxi (decoded as WDC20/) to load counters 0, 1 and 2 of mately 38 byte times, which is the predetermined U64 (8A 7). It also writes to I/O ports 8030H and time for the first gap of the track format, GI (see 8038H (decoded as WDC301 and WDC38/), loading figure 3-1 for a pictorial representation of the track the ID of the sector to be written to, into the 32-bit ID format). Also during GI, the 8089 writes the sync comparator logic. byte (00I9H) to the write buffer, U50 and U53 (7C7 and 7D7), by writing to I/O port 8028H (decoded as WDC 28/). It performs this operation in preparation When an address mark is found, the drive activates for writing the ID field on the track. the AM FNDI line, which resets U41 (8C7) and activates the ID FIELDI line. The enabling ofthe ID FIELDI line lowers the AM ENABLE gate to the When U 41 (8B7) is activated, it activates WRT AMI drive and initiates the search for the sync byte. (8B1), which is transmitted through BUS 5 (llC1) to the drive, causing the AM to be written on the disk. WRT AMI also starts counter 1, CTR 1 of U64 (8A 7). In searching for the sync byte, serial data from the (The 8089 preset the counters in U64 at the beginning disk is read into the SER/DES. Sync byte compar of the format operation.) When CTR 1 times out at ator U68 and U58 (7B5) monitors the outputs of the the end of 11 byte times, it activates the WRT XFERI SER/DES and pulls the SYNC BYTEI line (9C6) low line through U41-9 (8C4) and CTR 2. The activation when 19H - the sync byte - is detected. The of WRT XFERI initiates the 8089's DMA mode (as enabling of SYNC BYTE/, enables the SYNC FNDI discussed in paragraph 4-30), durihg which time the line, which in turn activates the ID comparator UI9, sync byte and the sector ID are written onto the disk. U20, U37 and U38 (9DX) and word clock U35 (8D6). CTR 2 times out at the end of the ID field, starting (See the discussion of the Sync Byte Comparator CTR 0 and activating the ECC TIME line (8BI). Logic in paragraph 4-35.) During the ECC TIME, the ECC code from the ECC generator is written following the ID field (refer to SYNC FNDI also raises the ENBL XFER line, paragraph 4-37 for a description of the operation of which enables the ECC Generator logic (7AX) and the ECC generator). At the end of ECC TIME, the Ready Latch U45 (8D3), and gates on counter 0 of END TIME line is enabled, which lowers the WRT U64 (8A7). XFERI line and takes the 8089 out of the DMA mode. The 32-bit comparator (see paragraph 4-36) com CTR 0 is set for a time equal to the ECC+G3+DATA pares the ID read from the disk with the ID of the +G4, which the 8089 sets according to the sector size selected sector. At the end ·of the ID time, counter 0 selected for the drive. When CTR 0 times out, it times out, pulling the ECC TIMEI line low and activates WRT AMI and CTR 2, which begins the initiating the ECC compare (see paragraph 4-37). If formatting of the second sector. This procedure is the ID and the ECC are valid, bit 6 of the controller repeated until the 8089 determines that the last ID status register U27 (I2C3) is reset. At the end of ECC field has been formatted. The 8089 then begins time, U36-7 (8A2) pulls the END TIME line high, searching for the Index pulse. Upon receipt of Index which resets RD GATE. The 8089 then checks bit 6 the 8089 resets WRITE GATE-F and FORMAT, of control status register U27 (I2C3). If the bit is inhibiting the writing of the next AM. The 8089 then inactive, the 8089 continues with the write operation. continues through the Format routine to the second If the ID or ECC are not valid (bit 6 active), the AM operation, which is the writing of the data fields ENABLE and RD GATE lines are then reasserted with user supplied data. The write data function, and the controller searches for the next address discussed in the following paragraphs, describes the mark. write data operation. To begin the second step of the write operation, the 8089 writes to I/O port 8000H (decoded WDCOO/) and enables the write gate (WRT GATE), which in 4-32. WRITE DATA TRANSFER turn activates BUS 0 (llBI), enabling the drive's write circuitry. When counter 0 times out, counter 1 The write operation is divided into two steps: (1) read is started. Counter 1 is set for a time interval equiva sector ID and (2) write data. When a write is lent to the ECC time plus GAP 2. When counter 1 initiated, the 8089 IOP writes 01H to I/O port 8000H times out, counter 2 is started and the U41-9 (8C4) is (decoded as WDCOO/). Latch U2 (llC6) then sets set, activating WRT XFER/. WRT XFERI enables BUS 5 (lICI) high, enabling the drives address write buffers U50 and U53 (7C7) and the ECC mark (AM) search; and sets BUS 1 (lIBI) high, comparator logic (7AX), and raises the RDY line enabling the drive's read circuitry and raising the high indicating to the 8089 that the write buffer is read gate, RD GATE (llAI). (See figure 4-12.) ready to receive data.
4-19 Principles of Operation iSBC220
I~I DATA IECCI I~I DATA
AM ENABLE J~I...-______~ RD GATE rl (BCS) ---1
AM FND/ ----, (SCS)
SYNC FND/ ------, (5C1) tr---~ ECC TIME/ n------r'----, (SB1)
END TIME (SA1)
CTRO/-----~ (SBS)
CTR 1/ ------.ir. (SAS)
CTR2/---______+--,
(SAS) 1...-____.....
WRT GATE (SCS)
WRTXFER/ ______~~
(SC1)
Figure 4-12. Timing Diagram for Write Data
The 8089 then enters its DMA mode to write data When counter 2 times out, ECC TIME is activated. from local RAM to the disk (see the discussion of the Following ECC TIME, END TIME is raised, termin DMA mode in paragraph 4-30). The controller ating the read operation. continues transferring data to the disk in this manner until Counter 2 times out, indicating the end of the data field, and raises the ECC TIME line. With 4-34. SER/DES LOGIC the ECC TIME line activated, the ECC generated during the data transfer is written to the disk. END The serial!deserialize logic performs two functions: TIME then terminates the write operation. (1) converts parallel data words into a serial string of bits to be sent to the disk drive during a write operation, and (2) converts a serial string of bits into 4-33. READ DATA TRANSFERS I6-bit words during a read operation. The SER/DES logic is made up of Write Buffer U50 and U53 (7C7), The read operation is divided into two steps: (1) read SERializer/DESerializer U5I and U54 (7C5), Read sector ID and (2) read data. The reading ofthe sector Buffer U52 and U55 (7C4), and Selector U65 (7A7). ID is performed in the same manner as for the write operation (see figure 4-13). During a write operation (WRT XFERI low), the 8089 lOP writes to 110 port address 8028H. Write When the desired sector is located, the RD GATE is 110 port address decoder U32 (5A2) decodes this again raised to search for the sync byte of the data address and pulls WDC281 low, clocking the data to field. When SYNC FNDI is activated, counter 2 is be written to the disk (BDAT-O through BDAT-F) started through U42-11 (8D5) and U3I-6 (8A5), the into write buffer U50 and U53 (7C7). A high on load ECC generator is enabled and the RDY line is serial register line LDSR (7C6), derived from word activated, initiating the DMA read data transfer clock U35 (8C6) loads the contents ofthe write buffer mode. Data is then transferred from the disk to local (SR-O through SR-F) into the SER/DES (7C5). RAM for the duration of counter 2. Read/write clock R/W CLK-B (7B8) then clocks the
4-20 iSBC220 Principles of Operation
I~I DATA I~I DATA
AM ENABLE.J /10 DOES COMPARE
RD GATE (SCS) AM FND/ ___....., (SCS)
SYNC FND/ _____---. (9C1)
ECC TIME/ _____-I- _ __. (SB1)
END TIME _____+_~- .... (SA1) CTR 0/ _____...... (SB6)
CTR2/ ______~
(SA6) L.-.___ ~
Figure 4-13. Timing Diagram for Read Data
data bit by bit through the QH output of U51 (7D5), BYTE I goes low indicating the presence of the sync and through selector U65 (7A7) to the WRT DATA byte. SYNC BYTEI and the next output of R/W line. R/W CLK-A clocks the serial data string on CLK-B set the SYNC FND flip-flop, U29 (9C6). WRT DATA through U12 (10C3) to the selected SYNC FND activates word clock U35 (SD6), and drive. activates the read/write logic (sheet 8). A further explanation of the sync byte logic can be found in During a read operation, the R/W CLK-B (lOB2) paragraphs 4-31 through 4-33. gates the serial data string (RD DATA) from the disk drive through U63 (lOB2) and selector U65 (7 A 7) and into the SI input of U54 (7C5), creating a 16-bit parallel word. Bit ring-O line BR-O (7B7) then clocks 4-36. 32-BIT 10 COMPARATOR LOGIC this word into read buffer U52 and U55 (7C4). BR-O is derived from word clock U35 (SC6). With the read The 32-bit ID comparator logic compares the sector buffer loaded, the SOS9 initiates a read to I/O port ID of the record being searched for with the sector ID address 8028H. Read I/O port address decoder U33 being read from the disk drive. The sector ID is made (5B2) decodes this address and pulls RDC281 low, up of the flags, cylinder number, sector number and which clocks the data word from the read buffer onto head address. internal data bus IDAT-O through IDAT-F. To load the sector ID of the record being searched for into 32-bit ID comparator U19, U37, U20 and U38 (9DX), the S089 lOP writes to I/O ports 8030H, 4-35. SYNC BYTE COMPARATOR LOGIC enabling the WDC301 and WDC3S1 lines, respec tively. WDC301 and WDC381 initiate the loading of The sync byte comparator detects the presence of a the sector ID into the ID comparator. This loading sync byte during a read operation and synchronizes occurs prior to performing either a read or write data word clock U35 (8C6) with the data. A sync byte operation. The ID compare operation begins after (always a 19H) is written preceding each sector ID the sync byte of an ID field has been detected (SYNC and each data field to indicate to the controller that FND). R/W CLK-B clocks the ID information, which data to be read is forthcoming (see Figure 3-1). is stored in the ID comparator, out of U38 (pins 7 and 9) bit by bit. U28 (9D2) compares the serial string of During a read operation, sync byte decoder U58 and bits with the sector ID from the disk drive (RD U68 (7B5) monitors the output of the SER/DES, U51 DATA). If the two sector IDs differ, ID no-compare and U54 (7C5). When a 19H is detected, SYNC line ID NCMPRI is activated; if they are the same,
4-21 Principles of Operation iSBC220
ID NCMPRI is raised. Selector U65 (7A7) ORs the comparison is non-zero, the difference is called the ID NCMPRI and the ECC NCMPRI lines (see error syndrome. The controller's firmware uses this paragraph 4-37). The resulting ID-ECC NCMPRI syndrome to correct errors in a sector ID or data field lines is latched into U29 (9B6). The QI output of U29, (if correctable). ID NCMPR-L, is transmitted to bit 6 of status. register U27 (12C3). The 8089 lOP then reads the contents of the status register and checks the condition of bit 6. Bit 6 being set high indicates that the record read from the disk was either not the 4-38. STATUS REGISTER LOGIC record being searched for or had an ECC error; conversely, bit 6 being set low indicates that the ID Status register U26 and U27 (12X3) stores status field compared and that there was not an ECC error. information (see Table 4-7) transmitted to the con The 8089 lOP can then read or write the data portion troller from the selected disk drive and the status of of the record. the ID-ECC NCMPRI line. When the 8089 lOP issues a Read Status command, Read Decode Output (RDCOO/) goes low transferring the output of the status register U26 and U27 (12X3) onto the internal bus (IDAT-O through IDAT-F). The status informa ECC GENERATOR LOGIC tion is transmitted on IDAT-O through IDAT-F to the 4-37. 8089 through transceivers U56 and U57 (4A5). The 8089 analyzes the status information and communi· The error checking code (ECC) logic performs two cates this status to the host processor, on request, functions: (1) during a write operation, it generates a four byte ECC polynomial that is appended to the ID through system memory. Refer to Chapter 3 for more detail on the status information. field (format operation only) and the data field (normal write) of a record (see figure 3-1), (2) during a read operation, it regenerates the ECC polynomial and compares it to the ECC field read from the disk record to ensure that the correct data was read from 4-39. LINE DRIVERS AND RECEIVERS the drive. All the control, data and high speed clock signals During a write operation, serial data (either an ID transmitted between the controller and the disk field or a data field) is transmitted from the drive use differential pair line drivers and receivers. SER/DES (7C5) through selector U65 (7 A 7) and into The polarity on these lines is positive true logic i.e., the ECC generator through pins 1 and 2 of U98 when the + side of the line is more positive than the (7 A6), where the ECC polynomial is generated. At side ofline, a positive logic "I" is being transmitted. the same time a high on the WRT XFER DLYD line enables the serial data to be transmitted through gate U46 (7A7), U66 (7A3) and selector U65 (7A7) to Table 4-7. Status Register Bits the WRT DATA line, where it is transmitted to the disk. At ECC time (end of data field), WRT XFER BITS FUNCTION DLYD goes low, inhibiting write data from being F INDEX transferred through gate U 46 (7 A 7). The ECC E - NOT DEFINED TIMEI line goes low, causing the ECC polynomial to D NOT DEFINED be written onto the disk through U66 (7A3), U65 C WRITE PROTECT (7A7) and the WRT DATA line. B UNIT 3 SELECTEDI A UNIT 2 SELECTEDI During a read operation, serial data (again either a 9 UNIT 1 SELECTEDI sector ID or a data field) is read into the ECC 8 UNIT 0 SELECTED! generator through selector U65 (7 A 7) and into the 7 0 SER/DES through U66 (7A3) and U65. At ECC 6 ID NOT COMPARE time, U66compares the ECC polynomial from the 5 0 ECC generator bit by bit with the ECC polynomial 4 DRIVE FAULT from the disk and transmits the difference through 3 SEEK ERROR U65 to the SER/DES for storage in RAM. If the 2 ON CYLINDERI difference is zero, the ID-ECC NCMPRI line is 1 DRIVE READY I pulled high indicating the sector ID was error free. 0 0 (Refer to paragraph 4-36). If the result of the
4-22 CHAPTER 5 SERVICE INFORMATION
5-1. INTRODUCTION Use the following numbers for contacting the Intel Product Service Hotline: This chapter provides service and repair assistance instructions, service diagrams, a complete electronic Telephone parts list for the printed circuit board assembly and All U.S. locations, a reference to the controller's self diagnostic. Except Alaska, Arizona, & Hawaii: (800) 528-0595 All other locations: (602) 869-4600 5-2. SERVICE DIAGRAMS TWX Number The controller board component locations and schematic diagrams (figures 5-1 and 5-2, respec 910 - 951 - 1330 tively) are included at the end of this chapter. Note that these diagrams are intended only for reference; Always contact the Product Service Hotline before they reflect the iSBC 220 controller design at the returning a product to Intel for repair. You will be time this manual was printed. The schematics and given a repair authorization number, shipping component location diagrams packaged with the instructions, and other important information controller reflect the design version shipped and which will help Intel provide you with fast, efficient thus supercede the diagrams in this manual. service. If you are returning the product because of damage sustained during shipment or if the product is out of warranty, a purchase order is required before Intel can initiate the repair. 5-3. SERVICE AND REPAIR ASSISTANCE
United States customers can obtain service and repair assistance by contacting the Intel Product 5-4. SELF DIAGNOSTIC Service Hotline in Phoenix, Arizona. Customers outside the United States should contact their sales A self diagnostic is provided with the iSBC 220 source (Intel Sales Office or Authorized Distributor) controller, stored in the on-board PROM. It performs for service information and repair assistance. a go/no-go test of the controller hardware and firmware. If the controller passes the test, it indicates with a high degree of certainty that the Before calling the Product Service Hotline, you controller is operating properly. See the discussion of should have the following information available: the diagnostic in Chapter 3 for a description of the program and instructions for initiating the opera a. Date you received the product. tion. b. Complete part number of the product (including dash number). On boards, this number is usually silk-screeRed onto the board. On other 5-5. REPLACEABLE COMPONENTS MCSD products, it is usually stamped on a label. c. Serial number of product. On boards, this number is usually stamped on the board. On This section contains the information necessary to procure replacement components directly from other MCSD products, the serial number is commercial sources. Component manufacturers usually stamped on a label. have been abbreviated in the parts list with a two to d. Shipping and billing addresses. five character code. Table 5-1 cross-references the manufacturer's code with the name and location of e. If your Intel product warranty has expired, you the prime commercial source. Table 5-2 lists all the must provide a purchase order number for replaceable components on the controller board. billing purposes. Note that the components that are available com mercially are listed in the "MFR CODE" column as f. If you have an extended warranty agreement, be "COML" and that they are ordered by description sure to advise the Hotline personnel of this (OBD). Procure commercially-available components agreement. from a local distributor whenever possible.
5-1 Service Information iSBC220
Table 5.;1. Code for Manufacturers
Mfr. Code Manufacturer Location
BECK Beckman Instruments Inc. Fullerton, CA BOUR Bourns, Inc .. Riverside, CA CRYST Crystek Ft. Meyers, FL CTSK CTS Keene, Inc. Paso Robles, CA DALE Dale Electronics Columbus, NE FAI Fairchild Semiconductor Mt. View, CA INTEL Intel Santa Clara, CA MOT Motorola Phoenix, AZ SNGMO Sangamo-Weston, Inc. Pickens, SC SPEC Spectrol Electronics Corp. City of Industry, CA SPRG Sprague Electronic Co. Adams, MA 3M 3M Co. St. Paul, MN TI Texas Instruments Dallas, TX COML Any Commercial Source; Order By Description (OBO)
Table 5-2. Controller Board Electrical Parts List
Reference Designation Description Mfr. Part No. Mfr. Code Qty.
C1, C2, C3, CS Capacitor, 220pF, Tant, ±10%, 1SV 1S00226X901SE2 SPRG 4 C4 Capacitor, 0.33pF, Cer. ZSU Axial OBO COML 1 C6 Capacitor, 10pF, Tant, ±10%, 20V 1S00106X9020B SPRG 1 C7 Capacitor, 10pF, ±S% 01S-SC100J03 SNGMO 1 C8 through C3S Capacitor, O.~OpF, Cer. ZSU Axial OBO COML 28 CR1 Diode, Zener 7.SV 'I2W 1NS236B COML 1 CR2 Diode, GP Switching 7SV, SW 1N4148 COML 1 J1 Connector, )-leader 60 Pin 3372-1302 3M 1 J2, J3 Connector, Header 40 Pin 3432-1302 3M 2 01 Transistor, NPN, GP 40 2N3904 TI 1 02 Transistor, PNP, GP 40V 2N3906 MOT 1 R1, R2, R7, R11, Resistor, Carb, 1 kn, V.W, ±S% OBO COML 7 R13, R21, R29 R3 Resistor, Carb., 2.2 kn, V.W, ±S% OBO COML 1 R4, R10, R24, R2S Resistor, Carb., 680 n, V.W, ±S% OBO COML 4 RS, R8 Resistor, Carb 2.7 kn, V.W, ±S% OBO. COML 2 R6, R9, Resistor, Carb., 270 n, 'I.W, ±S% OBO COML 8 R12, R17, R19, R20, R27, R28 R14, R1S, R22, Resistor, Carb., 10 kn, V.W, ±S% OBO COML S R23, R26 R18 Resistor, Carb, 100 kn, '/.W, ±S% OBO COML 1 R30 Resistor, Wirewound, 3 n, SW, ±S% CWS DALE 1 RP1 through RP7 Resistor, Pack, S6 n, 8 Pin 4308R-101-S6D BOUR 7 RP8, RP10, RP11 Resistor, Pack, 68 n, 8 Pin 4308R-101-68D BOUR 6 RP12, RP14, RP1S RP9, RP13, Resistor, Pack, 470 n, 8 Pin 764-3-R470 BECK 13 RP16 through RP23 RP2S through RP27 RP 24 Resistor, Pack 47 kn 764-1-R4.7K BECK 1 RP28, RP29 Resistor, Carb., 10 kn, 8 Pin 764-1-R10K BECK 2 S1 Switch, 8 Position, DIP 206-08LPST CTSK 1 82 Switch, 10 Position, 'DIP 206-108T CT8K 1
5-2 iSBC 220 Service Information
Table 5-2. Controller Board Electrical Parts List (Continued)
Reference Designation Description Mfr. Part No. Mfr. Code Qty. U1, U2, U36 IC, Hex D Type Flip-Flop SN74LS174N TI 3 U3 through U6, U11, IC, Quad Differential Driver MC3453 MOT 6 U16 U7 IC, Dual J-K Flip-Flop SN74S112N TI 1 U8 through U10, U14, IC, Quad Differential Rec. MC3450 MOT 7 U15, U24, U25 U12 IC, Dual Pas. Edge. Trig. Flip-Flop SN74S74N TI 1 U13, U43, U49, IC Quad 2 Input OR SN74LS32N TI 5 U71, U87 U17, U29, U45, IC, Dual Pas. Edge Trig. Flip-Flop SN74LS74N TI 5 U60, U63 U18 IC, Quad 2 Input NOR SN74S02N TI 1 U19, U20, U37, U38 IC, 8 Bit Shift Reg 74LS165N TI 4 U21 IC, Octal D Type Flip-Flop SN74LS273N TI 1 U22, U23, U88, IC, Octal Three State Buffer SN74LS244N TI 5 U89, U90 U56, U27, U50, IC, Octal D Type Flip-Flop SN74LS374N TI 6 U52, U53, U55 U28 IC, 2 Wide, 3 in, 2 in And-Or-Invert SN74LS51N TI 1 U30 IC, Hex Inverter SN74LS04N TI 1 U31, U47 IC, Quad 2 Input AND SN74LS08N TI 2 U32, U33 IC, 3 to 8 Decoder SN74LS138 TI 2 U34 IC, Hex Inverter SN74S04 TI 1 U35 IC, 4 Bit Binary Counter SN74LS161N TI 1 U39 IC, Dual 2 to 4 Line Decoder SN74LS139N TI 1 U40, U42, U44 IC, Quad 2 Input NAND SN74LSOO T1 3 U41 IC, Quad R-S Type Latch SN74LS279 TI 1 U46, U70 IC, TR1 3 Input NAND SN74LS10N TI 2 U48 IC, Hex Inverting Buf/Drvr SN7406N TI 1 U51, U54 IC, 8 Bit Shift/Storage Register SN74LS299N TI 2 U56, U57 IC, Octal Bus Transceiver 8286 INTEL 2 U58 IC, Dual 4 Input NAND SN74LS20 TI 1 U59 IC, Clock Generator 8284A INTEL 1 U61 IC, 13 input NAND SN74S133N TI 1 U62, U68 IC, Quad 2 Input NOR SN74LS02N TI 2 U64 IC, Programmable Counter/Timer 8253-5 INTEL 1 U65 IC, 257 Quad 2:1 MUX SN74LS257N TI 1 U66 IC, 9 Bit Parity Generator SN74S280N TI 1 U67 IC, Quad 3 State Buffer SN74LS125N TI 1 U69 IC, Hex Schmidt Trigger 74LS14 TI 1 U72, U73, U74, U75 IC, Quad 2 Input XNOR OC SN74LS266 TI 4 U76, U77, U78 IC, Octal Latch, Inverting 8283 INTEL 3 U79 IC, Input/Output Processor 8089 INTEL 1 U80, U81 IC, Octal D Type Latch SN74LS373N TI 2 U85 IC, Bus Arbiter 8289 INTEL 1 U86 IC, Bus Controller 8288 INTEL 1 U91, U92, U93 IC, Octal Bus Transceiver, Invert. 8287 INTEL 3 U94, U95, U96, U97 IC, Static RAM 2114A-5 INTEL 4 U98, U99, U100, U101 IC, 8 Bit Shift Register SN74LS164 TI 4 VR1 Voltage Regulator, -5V MC7905CT MOT 1 Y1 Crystal, 15.000 MHz Type 44 Miniature HC45 CRYST 1
5-3/5-4 iSBC220 Service Information
7 6 5 4 3 - ...... - --~ EC.O 14-0060 PR<' PILOi KL':>E
D D
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VIEW DETAIL FOR tv\OUN,IN6 VR1..
6. MA..X,MUM CCMI'ON:.N' HE.IG \-1, TO' BE: .410'. 'SEE SEPARA'l"e: PA~ U':>'l" [2J TNSiALL i/>PE,TTEM I
Figure 5-1. iSBC 220 SMD Disk Controller Parts Location Oiagram
5-5/5-6 iSBC220 Service Information
_110. 8 I 7 I 6 I 5 4 I 3 I 162:)33 1"'1 1 I II£VISIGNS • aw: DESCRIPI10N OFT CH" DATE ...... ,..., EC:) ,"I -OObO?Ft. 1'1\.0\ ?.LSI:: I~;- J< ,-s-tet -A ~j ,.~.& L~ '=' E..CO \4-0\\:' I,it.I'" I%~, ~-Il'~ } J..1>l1O,-, 1- C E-CO 14-01':>1 I"~<:-BC t~f-,~ 10 °'.11 f4>~
D D +5V ~~ 4(-- 5(-- Clr2 1 1 C 5,10,12-33,35 G~ 22 + jlIl (j/~ 62-E-- 83(-- R9 J 1 +SV 64 /44 +:INT;=-C ENBL \~~g2. 270 -5V ~+5V 2N39{P'G -sV I-- - Joh .WI P6 -ICfV 'NS -I(/V ;;h at -'5V 2.7K .2 R30 YRI / -12V .C '\IV"-. 3n 5W 31 790'5, f-i2 -/2V :~ 1 C3 .\ I C4 J! (51 C9,1I,34 l.-; CPJ... PI I --:- 1 GND +122 22. ¢.! R'1 ~ ~ IN5236B I ¢.~?J 1+ I 680 ~E -::- -::- C C ;~,~ RIO <,A7 75 680 Ii< 76
FWR&GRD LOC'lTJR CHART 10 \J2':> 9" II JI I~ Z REF POWER PINS - LE/ +5¥"- I ./ u 3-6. 11,16 8 10 :1 8 ~'100 8 UI2.13,17, Ie. «;'31, 3>4, 1'\ r---- 10,42-49. '55, W, ,,2 . .,3 11..1:'::;;. 10 6<>-75,57 98-101 r---- I J l/?"!OG u I,Z,7, 19 20, 32,33,35-39 8 10 '11,101,65 J l 9...I:::::. 8 U59,9"\-97 Ie 9 t?r"!OIO U21-23, 2b, 27 ':l0-S7 10 20 70-lB,BO 81,55,86,5'0 I I .89, \IO-Y3 J, I-- - U&t,B2,63 12 24 U79 1,20 40
NOTES: UNLE5~ OiHERY-JISE. S\>EC.IFIED, I. RES\STANCE VALUES ARE IN OHMS, '/A,Wz5'7o YI I. I I I I I I I PART NUMBER D£SCRIPI1ON 2. CAPACIIANCE VALUES ARE IN IV\I(ROF,ARAJ)S. W5 W3 111111 ~1 f-'VRI QUANTITY PEA DASH NO. PARTS UST 7'1S(2I2 U Ie, 1 13 UIOI 74 LS 32 UI:, 3,11 UNLESS OTHERWISE SPECIFIED: SIGNATURE DAtE _lOWERS AYE A. S2 ID SANT. ClARA A. 74LS32 U49 :3 RI>Z9 1. DIMENSIONS ARE IN INCHES. """ BY A C/GN£77. ~ inteI CALlF.95D5l 74 LSI(2) F(lb CHK BY J.CIE ... ",,,, -5-00 U70 12 R30 2. BREAK ALL SHMP EDGES. TITLE SCHEMATIC DIAGRAM 74 LS IZI4 \.J"30 6 Q2 3. DO NOT SCALE DRAWING. 1=:1 L1>.I(:'" ,-u-8' LS(lI2. DI5K 74 u
Figure 5-2. iSBC 220 SMD Disk Controller Schematic Diagram (Sheet 1 of 12)
5-7/5-8 iSBC220 Service Information
7 6 5 4 3 IMaNO. '62033
OFT CHK DATE APPROVED SeE SHEET I
+5V D "Ie I (ADR-f)l)-(ADR-Ol> -----, D Si NX{-F! Ir ;:::--;::' I~ 9N-F/ 1 2j~Illi-52b ,.K?2 10K N:)R-E/ 2 ~ 15 ~W-£J J68 J Rf'l.Sc:: ! I T~j~ SW-F/ 17 74LS2'f'l 3 PA.T fbI< Affi-PI SWEI 2 Ie;' -F/ DAi- SWDt e 2Gb SW-D/ 15 ~ E/ ~.?> 9~~ DAT- SW-C{ 1./ ""It' D/ J~3 r T DAT- ADP.-C/ IZ> '=>W-'Oj II ~ c/ /DI< r---- DAT- ....-----_: 13 '5WC1 SW-A/ 6 13/ r-f!-, OAT- 1~J.j '2.~h" 5W 9/ 8 AI " I I ~ DAT- 101< ADP--'O/ SW-8/ 13 9/ r-Z-- DAT- 12 ~ 5 SW-"e>1 O£ 8/ I RPf.I!>5 I I ~~~ 'i19 YI /01( : AfX=>.-A' (Q ~ /I ~W-f>...1 2)~I) LS2 c ,~(' T I c /b"l{ : ADR-9! 13]~ 7 ~ 10 SW-9/ r 12 )jLS2 1/ RP2.e 7 1 10K f>.DR-S/ ~..,~( R24 8 ...-; 9 sw-el B ) ~2bb <:) +-5 V U8? G8Jtf ,RP2e>e, L"- --' I 1 'it:::/ SW-F/ 17 74Le:.2JI'I 3 DAI 10K §i!_.-,. N:>R-7/ SW-E/ 2 -7/ 4! U7'\ :!> R25 rw DAi- to/ /81. 3 SW7/ -1 ))[526 -n.. 5V SW-D/ 15 r--'5' ~ IC7 G8¢ DAi-'5/ RP29 Z> T T Sw-c/ 4 ~ DA"\- II I.i/ Ibl( /'-DR-v/ 5~~ SW-B/ ~ DAT-3/ SW-A/ 6 17 ...... -;, 1./ SW61 T 6 )1152.0 fJi:I DAT- ,RP292. SW-9/ 8 f--7t' 2/ T DAT- 1/ loT<- ADR-si SW 8/ 13 ~ ~ DAi- S /6 'OWSI o£ ¢I ....---:.. I 12eQ~ J. 526 10 U71 J RP2.9<4 [ ~ 19, 1 Ib"K ADR-J..Ij ~B ~ (DAT-F/> -(DAT-¢/) ~BB 6 ...... -;, 1'5 SW41 , RP2.9 s I I~'~ LJ90 B • IbX r\DR-~/ SW-71 17 74LS24L1 3 I--' DAT- SW-6/ 2. 7/ 7 ~ I~ ~W-3/ ~ DAT- 6/ I ~96 T T ~~~I SW-5/ /5 5 OAT-~I NJP,-2.! 5W-L{! 'i 10K "10 DAT- a 13 . SW-3/ II '-II ~ 'OW2/ r--'9 DA"\-3/ I RP297 I I~~ sw-al 6 f-JZI lo'K 5WII 8 ~"\- 2/ ADR-IL ~ DAi- ~; 12. '?:JW-II 13~~ SWC)/ /3 f-'7 ~L , I2.J)L526 I--' DAT JiPj.J e : , OE '/; Ib"'K A\)P.-¢/ '1.19 '( I 10 ~; II 5W~¢/ 9~~5J 6 R26 T 1 10K 2' 1 19 16BIT :zpi J 5 B,23 I l 4P3~ 6 ~~~~),/I l ~ 6 10K , I WAKE upl 388, SDe / 2C> 161317 SIS BUS! IE. BIT 5Y513U5/ 5DB .~J5 1 A P ~ A -=- IlJ7<' 9 It, e, IOWC/ 22 4LSI4 SCI IADR-{i/ 13 SBI IADR-rJ 71 II 12;;15 5CI GATE sws/ SIZE I CODE I ' _NO. I 162033 ... ISSU£D 2. - • 7 6 5 4 3 2. 1
Figure 5-2. iSBC 220 SMD Disk Controller Schematic Diagram (Sheet 2 of 12)
5-9/5-10 iSBC220 Service Information
_NO. 7 6 5 4 3 162033
ZONE lIlY IlfSCRIPI10N CHK DATE APPROVID SEE SKEET I
D D "IAI LOCK/ /)85 U56 /8 <'52139 5¢/19 8288 /2 "tf\1 s¢ 50 5r;f AIOWC I-A IO WC/ 5~o, bAD I 19;. 51/ 3;: '1AI .901 51 51 AMWC / ( 13 52/4: "tAl :,2/ 52 A£N 52 .rowe P:1 /6 ~9 P..L LOCK MWTC 20/v1WT C/ 5 7 8CLK/ 13( 8CLK 8REQ 7 MRDC 19 /I1RrC/ 9 13 8PRN/ I BPRN BPRO <'5 IORe 2 ().q7 G 14- 3 X-IORC! 5E'o, bAS INIT/ 14- IN(T +5Y INTA J Ji..MB ,n. /2 C8RQ/2 CBR.Q ~ II 2 4- 8USV/ 17 ..... BUSY CLK DT/A. or/R tJAB 4- 6- ·5 RESB RI'3 A£N ALE ALE Ij8B,5B8 W2_2 '5 17 J- IOB II<. CEN PDEN POEN/ 'lAB I (6 =c. 4 CRQLCK IOB DEN DEN 5DB 14 ANVRQST 17 'lDI 5MHrCLK CLK 'l ~ SY5B I pup RI~ IBe, C A£N/ '-ICB,5D8 c 1-
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I L'=>IO 12 CHNLATTN 5BJ ROC 18/ ~~ 2.
A. A.
REV II1II 162033 ISSUED SHEEr :3 - 8 7 6 5 4 3 1 1 Figure 5-2. iSBC 220 SMD Disk Controller Schematic Diagram (Sheet 3 of 12)
5-11/5-12 iSQC220 Service Information
_NO. 7 6 5 4 3 162033
+SV I ZONE REV DESCRIPnON 1 0FT cttK DATE APPROVED ( - a ( RI4 R29 I'-..J ISEE SHEET I I \c;l'>K IK
!lBI CN,LR R 51/ 10 Jpn~8 \~ 2-
I , 3CI ALE , , r , , (ADI 508 (DAT-F/)-(DAT-¢/) , U510 , , 2.e/ U93 , , DAT-7/ 19 8207 AI ADI5 I 8280 J9 :IPAT-F , I U77 B A B . -E , I 8283 DAT-6/ 18 I~ 2- 18 ~ B A 2- A B ~' PI DAT-S/ 17 13 :3 17 -D 8089 9 AD7 1 19 B A 3 A B DI DO 52 "OP.-7/ • DAT-4/ 16 A 4 12- J.f 16 -c If' 6 2. /8 • B A B .,51 A DR-reI DAT-3/ 15 II 5 15 -B II S :3 17 B A 5 A B 5'/1'-DR-51 DAT-2/ 1"1 IrJ 6 1'1 -A.. 12 4 'I 16 8 A 6 A B '53",DR-4/ OAT-II I~ ., 7 13 /5 .3 5 J5 B A 7 A B -9 5bAD"R.?>/ OAT-(l/ 12. 8 AD 8 8 12 .IDt\T-B 14- 2 6 1'1 B A 5S ADR-2/ A B 15 7 13 T OE T OE I 5'8 A DR-II II y'3 lID AD(I 8 12- 5(.1 £NBL SWAP BYTE/ III '9 57ADp.-¢I L STRB 17 - ~ DE SINTR 1 y9 PI U92 U57 SINTR 2. 19 8287 1 NJ7 1 8286 19 .IDf'.-T-7 ~ DAT-7/~/ B A A B Ie 2- & 2- 18 -& DAr-61 (07--..- B A A 8 17 :3 5 3 /7 -5 DAr:-.51 70 B A A 8 52/ 28 10 .q 'I 'I 16 -~ 52 / 3D8 OAT 41 G9 B A A B 51/ 27 IS 5 :!> 5 15 -3 51/ 3Df> DAT..3/72 8 A A B s¢/ 26 I"J G e 6 1'1 -2- sriI 3D8 DAT-2/71 B A A B 29 13 7 I 7 13 -I LOC kl 3De 3BB OAT-1/ -,. B A A B t-.OCIV 12 8 AD(J) B 12 .:rI)AT-f6 lit. 3BB.5t>1 OAT--#/Z9 B A A 8 (IDAi-F)-(J:D T oc- T OE (IMr-7)f-rD6i: VI '19 SCI £NBL LO BYr.£1 :3<:..1 DT/R 1 r 3C.I PDEN/ r RFV -"" . G: 162033 ISSUED SHEET 4 - • 7 6 5 4 3 2 1
Figure 5-2. iSBC 220 SMD Disk Controller Schematic Diagram (Sheet 4 of 12)
5-13/5-14 iSBC220 Service Information
7 6 5 4 3 162033
IIESCRtPI10N DFT CHK DATI APPIlCWED SEE. SHE.E.T I 7L1LSI2.5" 5 U~7 6 ~.-ft I DAT¢/ '-lAS D D 74 125 12 Ub7 /I XN:.K./ • 'feB .lffll (A.OI5)-(ADO) 12 -=- 1':3 ¢ei ,1/ ueo 15 '1L5125 ADI5 3 74LS373 2 IADR-F 7 ~~474L<;;14 D Q 9U ADI4 '1 5 IADR-E 6 Q 10 AD 13 17 0 16IADR-O 2. -=- Q AD 12 18 D 19IADR-C :3 Q AD B 7 D b IADR eo, .. " . .-2 ~ ~~ 1'1 Q ~ AD 7 0 15 IAOR- 7 I 4 Q 8 D '1 IAOR-3 IADR-:3 6 AD '" Q ~~_-=_6 _. 3It£f¢ GP--TE.. S'-NS/ 2M AD5 13 D 12IADR-5 I'i IADR-i st D Q 5 IISTB 10 OE Lj ~~2. & /1 I~ ~ II ENBL !-II BYTE/ "".CB / -4 10 ~ U4 e ~27 --4IE.. 9 L5 i :3 271/> 2. Jt'S'3zj- ENBL 5WAP f?:.YTE/ I-JBf) ~ -~ ENBL LO E3YTE/ '-lAB C c i!.rt;,- 10 9 U I ~ADR-¢ I 2AB '1/'74L~14 ~8 ADR FFF FX/ ·~CB UBI ADII :3 D 7'1-L5.373 2 I ADR-B 13 [':;,.)2 Q U39 ADIO 'i 5IADR-I\ 74'-5139 12- D Q 1774LSI4 G 0 CSROM/ f:>N3 AD9 18 I?IADR 9 ~ 1/ 0 Q / e:sRAM/ 6N3 AD'I- 8 9 IAOR--'I- IADR-£ D Q i'lA 2 AD3 13 2IADR 3 IADR F 13 8 ~ 0 Q 3 pf-i AD2 7 bIADR-2 I.ADR-¢ ·0 6'"1 AD/ Q 15IADR-/ 1"1 0 AD¢ 17 Q oIADR-¢ 2. 7J/~?'4G ~ 0 Q SD II .5T8 ~-4 ':)L O£ C R QI V74L':>C>4 1'--.IADi<.-2. '-(I / I'--IP--t>R- I '--I~B-¢ 3C1 ALE U33 6 7'1-L5138 /5 ADR-FXXXxj 12.'B8 • '1DI G ¢ 14 T<:DCOo! • 3CI I-IORC/ '" G I ~ G 2 ~ 3DI I-AIOWC/ 3 3'28, ~/Be> .IAo.R-3 f?--/I 1001 PUP RP24 I A
U32 7#L'5138 15 G WDC-0(lJ1 IIC8 ~-F ¢ /4 G 1 WDC (/leI XB,I2. DB 13 .5 G 2 WDC I¢/ 3B8,IIAe /2 3 wDe 1'0/ lice .IAOR-3 /I 'A .If- WVC 2¢/ 3Ae IADR-4 I¢ 2 B 5 HOC 281 7C6,BD8 IAOR-5 3 9 C 6 VVDC 3¢1 CBe>/ 9C8 7 A 7 woc~ 9CB A
- .ClGNE: IG2033 ISSUED 5 - • 7 6 5 4 3 2. 1 Figure 5-2. iSBC 220 SMD Disk Controller Schematic Diagram (Sheet 5 of 12)
5-15/5-16 iSBC220 Service Information
_NO. I 7 I 6 I 5 + 4 I 3 I 162033 \~ I-I • REVISIONS U94 DESCRIPTlON OfT CH" DATE ...... ,ED .IADR-A 5 2114A-5 I""'· ... A I~ 5E.£ 5f1E.ET I I ::t:ADR-9 17 A ::t:APR-8 Z A IADR-7 S A IADR-6 1 1"1 IDAT -F - A I/O :LADR-5 tI 13 IDAT -£ D A .I/O D 7 12- IDAT -0 ~-pR-4 A I/O ~ADR-3 -~ II IOAT -G A Ilo "fAI (I.T::Ar-F)-{IDAT-S) IADR-2 " A :IAPR-- I ff&> 'fAI (:rDAT-i}-troA"""F aI) AWE CS ys 5B!tIADRC )(IAD?-I; I'P
r-- (e>I».T-'f"}(eP~~) roe., 9DS - UB?> ----,. IAOR-C 21 2732 Ail u95 IAOR-B 19 .::r:ADR-A 5 AM A 2/1L/-A-5 ____ (BDAr-9)-(8DAT-O) IAOR-A 22. IAPR -9 "---;T IIDB A9 A IADR-9 23 17 IDAT -F IAPP.- 8 2- fit IOAT -8 A8 0 A IAOR-8 I 16 rOAT -E-~ :IADR-7 3 13 IOAT -A A7 0 A ..122 IADR-7 2 15 I DAT D lAPP. 6 1 IZ IDAT -9 -"F A6 0 A I OAT if 7'1/..5244 9 8DAT-F IAOR-6 .3 14 I OAT -c .IADR-S "I /I reAT 8 AS 0 A IDAT £ 6 IAOR-5 4- 13 IOAT -8 IADR-4 7 IDAT -D ., ~~1'1 BCAT-D A4 0 A BDA.T-D IIDB C IADR-L/- 5 1/ IOAT -A :IAtl? .3 15 13 C A3 0 A IDAT -c 7 'i3D!\T-C 'BDAI-C IAOR-3 6 liD IDAT -9 :::rAPR-2 6 IOAT -8 15 5 B\),',.i-B \IDe. A2 0 A IADR-2 7 I DAT -8 :IADfi-/ 16 I OAT -A 'i 16 "e>PI'\T-1> AI 0 ~ IADR-I 8 AWE rDAT -9 2 181O>])/'.T-9 A¢ C5 yB IOAT -8 17 3 "E"P1"f-8 -eDI'\f-B "3CB CE oe: I'" oE 2{t! '1 / '? 19 1'8 U96 .:I:ADR-A 5 2//L/-A-5 A -+ .IAPR.-9 17 A ~ .IAPR-8 2- A ..IADR-7 3 ~ rDAT -7 A UB2. TAPR-6 1 t:3 IOAT -6 A IADR-C 21 2732 .::r:ADR-5 12- IOAT -5 All 'f A IAOR-8 /9 .:rAPR-4 7 /I IDAT -4- AI¢ ~ A IADR A 22 IOAT -7 .IA~-3 /5 A9 0 17 A IADR-9 23 I DAr 6 IAtIR-2 A8 o /6 6 A U23 IAOR-8 I IDAT -5 I"ADR-/ /e, A7 o /5 IDAT- 7 8 74L52/.//./ f2 BDAT-7 rAOR-7 2 r OAT -/I AWe: C5 A6 o 14- IDAT-6 JIf 8DAT-b • IAOR-6 3 IOAT -3 y8 :r.DAT-5 I( 168DAT-5 13 • AS o " IADR-5 L/- IOAT -2 I'~ :IDAT-/./ 18BDAT-'1 A4 o 1/ 2 IAOR 4 5 IOAT I IOAT -3 17 3 1:>D"T-3 A3 o 1(/ IAOR 3 6 I DAT -f<' U97 IDAr -2 5~\-2 A2 o 9 15 IAOR-2 JAPR. -A 2114A-5 I OAT -/ 7 1O>D"'T-1 7 AI !SA I:' IADR-/ 8 iADR- 9 I OAT -~ /I 9 "BDI'.T-() A{i1' 17 A SADR--B 2.A OE C£ oE IAPR-7 3 A ff IDAT -3 'tJ -'119 IN IADR-6 IOAT -2 - 1'8 / A /I I-- IADR-.5 J.{ /2- rDAT -I 5CI CSROM/ A .:rAt>R-4 7 13 IDAr -(17 "'12 A -::... 27¢ :J:APR--3 /!S 3CI I-IORC/ A r",p~-2 6 'SCI CSRAM/ A 5 LS32 6 .:rAPR-1 /6 AWE $I U4 GS 3DI I-AIOWC/ 10 LSl2ie ~b ,NT '1'8 5BI IADR-¢ 1~ "-I::t::V"" A 1 A
J.lC.1 8/-1£/ '~9 Ji.s32
SIZE 1000E !'::...... s 1""" NO. IRfY DRAWN D i4 0\ 162033 ISSUED SCALE IMCNE SHEET~ - • I 7 I 6 I 5 t 4 I 3 2- I 1 Figure 5-2. iSBC 220 SMD Disk Controller Schematic Diagram (Sheet 6 of 12)
5-17/5-18 iSBC220 Service Information
7 6 5 4 3 .... NO. 162033
ZONE REV DESCRlPIlON "- SEE SI-IEET I
~~e. :;;IUSI U52. D 74LS2?1t, 17 SR-F .5 74LS374 2J:DA""-F Q 16 SR-F SA E /8 o 19:f6A'T-=-It------~ 0/-1 o Q U50 'I- SR-£ SR-D 17 ~_oAT-P----~ QG D Q --- BDA1-F ~ 2sR -F SR 0 "b'l-LS37f; /5 SR-C '-I '5j:DAi-C. QF D Q Bt>Ai--':' 16 /9 5R-E 12 5 SR C SR-8 7 6 :I:DAT-'2> D Q CLK Q£ o Q I!>DAT-P 17 16 SR-O 14 SR B SR A JDA.-e 7 6SR-B 13 SR-9 SR-8 I'> 9 IP"'T-8 o Q 50 QB o Q BDAT-A PI Ii!' SR-A ~2 7 SR-B Q GI QA ,---!J- CLK B>PAi- 9 o 125R 9 OE IS o Q ~ G2 QA' ?iDA'-8 eo 9 SR-8 SI ~ y' D Q III ~ ,--!!. CLKo£ yl JIB U"i5 -SI U54 5R-7 3 7'1-L537/f eel LD SR 2IDA'-7 18 0 Q \lAI RDGf>...IE./ 74LS299, 17 :5R-6 19:tPAT-b Q/-I ~5R-5 17° Q II AI C.TRL TAG 16 SR-7 J;;:IPAT-S 0/-1 ~5R-4 ,/0 Q QG 4 SR-6 5:l:.D",,-4 c VB3 15 SR-5 SR-3 7° Q 6IDAT-'3 c B0A1-7 SR-7 OF 4 0 Q :3 074LS37~ 2 12 CLK 5 SR-4 5R-Z 15:rt>AT-2. Q£ 13 0 Q eo OA'-E> 16 D Q 19 SR-6 14 5R-3 ~SR-I 2. -IDAT-I ~-{cCL.R QD Q '2>DAT-S 16 SR-5 6 sR-2 SR-¢ aO 9.:ro"'T-¢ 17 0 Q I S/ Qc o Q 6DA'-"I !5 SR-4 I 13 SR-I "0 Q S(1 ~ elK eDAT-3 6 SR--3 '---z- Q8 .sR? ~ OE 70 Q GI QA 7 -eVA-r-2 15 SR-Z 'il //.{D Q Llc G2 QA' -ePAT-1 12 SR-I SJ: ~ ~D Q =- RI7 13P",T-¢ 8 0 Q 9 SR-¢ -::-270 III 5AI WOC28V II CLK DE SR-3 10
.. _--_._. BCI WRTXF£R/ I' SR-/ SYNC BYTE-/ 9CB s~(1 2.3~~ ~~21 LSI¢ 6
r ~ IOAI R/WCLK-8 ~ • lOBi RODATA I OCI WRT XFER. Dl:yp • ... ---.----~- _ 6DI BR-{:! -- .. _ .. ------~- 5BI R[)C28 / -- ID/ ECC NCMPR/ 9B8 WRT D".,..A IODa . S 74L5Z57UG5 U'-I 9PI ID NCMP.'R/ 2. 8 Y ~A ,___ + __ ~ 8 Y 7 I Ub6 5 A U98 U99 UIOO UlOI 12 7451:o/b J2..... 74-LS 16!f/-l 7'1-LS/64- 13 74L516Q1j; 74LS/G~1I T 10 B yr2- ~ 0/-1 ~ ~ ~ /3 Lr-4.A QG QG QG QG I ~ ~B y~ QF OF QF QF ~ ~- 000 Q£ QE QE JL QE ~A_ "s G - - QD QO Qo Qo 1 P,-::- II R20 Qc Qc ~ Qc Qc A. A. 6131 £CCTIM.'E/ I5270 8 CLK Q8 'f- CLK Q8 ~CLK Q8 f- CLK Qf3 ~ 9A~ ----2.. £3 lOBI R/w CU~-A r~C~R ~ CjR r~CJrR ~ I~C~ %1 I' i 11 1-' l' 1'<: 11 12 BDI E:I\JBL Xn=.R 1 1 1 I 162033 DRAWN A ClGNETTI '"01'1""\ - • 7 6 5 4 3 1 1 Figure 5-2. iSBC 220 SMD Disk Controller Schematic Diagram (Sheet 7 of 12)
5-19/5-20 iSBC 220 Service Information
7 6 5 4 3 _NO. 162033 ZONE _ DESCRIP11aN DFT CHK DATE APPROY£D "--.. I SE.E SHEET I 9~ B I 1./14~4 A,n 5 71fLS7Jf ~ DI..Yi5Q D pel RDC28/ D 5 L'.l(I¢/ ....--!!- C Q/ JJ U~6 SA-I woc 2tJ/ ~ IILSI¢> 8 RDY 12~ --- R re, ~ 1061 A~S Q~ ~~ ~~2. I?J '?Be 2 U6~ r--'" /J U'!J5 .3 7"ILS74 R/'N bAlE l'2Ae A 74LS/6I QA r C R Q/ 12 L.SQkJJ EN8L XF€R 71>8 ~I~ ~ B Qe ~" ~ '1" gC Qc f{t- lOCI NP RI \ 1 D QD 1-'-'- 10AI R/WCLK-:B -=- ~ eLK 2 1 / CLR 11"'-1 RD GAT£" 9 IS t...O 12~ 9C1 sYNC FNO/ 'l~ /5 P co IU 2 13)t:':l32 ,/I U . ti T "I~ 74SQl"! ).,10 ~ 9 1& So ["1i!iC /2 7'-IL.571f 9 B "154> D IJC() Q C lOBI R/W elK-A. II 7JlLS279 9 l- Qf:- ~; II C Gil R ~ ~R WRTGAT£ I '?13 /lAI 7"ILS1Z5 '--- '} UI3 - 8 UI/I Su 5_~ 10 LS32 Z " ~"'~24 LO SR 7C8 270R2e r4St,l\., ~'") II/. R W- 12.~ AM FND/ ~~il - -=' IO FIELD/ /lee
~ ; ~ II U36 I S USb 7ifLSI74 2 ~A L ~ lJ'I4 .3 2 64~7~ 5... blfLSI7t FORMAT . I 5 D Q LSOO LfU l2. WDC3t3/ R ~~~~5..e. WRT AMI /156 '<------..2.. c ---2 Q/ - R c R .f!- ~ c R • yl 9/ '---< '11 •
4A1 trDAT-7).¢:-DAT-o) u6JI ECC liME/' 8253-5 I ::IL\I'.T-7 J 9 U36 07 CLKt/ :IDAT-Io 2 ~ I U II 74LS I 7'1 1/5 D,;;, GATE ~52 I LSGlrzl /!L D Q Rjw GAlE P.slj' 1188 IMT-S 3 Ds OUTg Iii ~2 :; ~ IDAT-'1 "+ 04 5 "t ~ J:I)I(T-?> !5 G R 03 eLK 1 ~~ :rDAT-z ~14 'fl GATE 1 IDAT-I '"7 02 ·13 01 OUTI J:tlAT-D e 0(11 CLK2 U36 U'!>6 U36 aD ~1(# 674LS/7f 7 IA't>?c-2 AI GATE o Q 1/ b4LS1~Lt o Q END TIME: 19 17 14, I.StlI ~DI PWR RSTj I ..a CODE ClASS _NO. DRAWN ,ClG 162033 ISSUED - 8 • 7 6 5 4 3 1 Figure 5-2. iSBC 220 SMD Disk Controller Schematic Diagram (Sheet 8 of 12) 5-21/5-22 iSBC220 Service Information 7 6 5 4 3 ..... NO. 1G203 3 lONE ... IIESCR'PIlON SEE SHEET I D IJI9 LJ37 U2.0 /foB BDAT-7 74LS/65 8DAT-F 6 74LS/65 8DAT-7 BDAT-F 6 J4L5/65 ~ 1/ Q/I ~ H QII ,.L lt4LS/6~1l ~ Q/I B DAT-6 .5 BDAT-~ .5 BDA7-6 S BDAT-£ 5 G '" G Q/V 8DAT-5 Qui ~ BDAT-P 4 G Q/.// P--s BDAT-5 "I G ClIJ/ P--s 4 F F F BDAT-D .If F 8DAT iI 8DAT-C .3 8DAT-~ 3 .3 £ £ £ BDAT-C .3 £ B DAT-,3 //1 8DAT-1!> 14 BDAT-3 !4 8DAT-8 14 D 0 D D BDAT-2., /3 BDAT-A /3 BDAT-2 !3 BDAT-A 1.3 C C e e B DAT-I 8DAT-9 12 BDA7-/ 12 8DAT-9 12 B /2 £3 B ~ NCMPR/ B B :w BDAT-¢ II BDAT-(/J II B DAT-e, 1/ 2 ~I A BDAT-8 " A A A 2. 2. 2. 2. CLK eLK CLK eLK ~ CLKINH ,---l2- CLKINH -4- CLK IN II ,----f2. eLK IN II ,9 ,!c LD --Lc LD ,lc LD ,.t LD ~ SI SI SI SI -!If-' I/~ 1/,13 I/~ ICiAI R/WCLK-8 SYNC FND/ ace C 51'\1 WDC-38/ c 51'\1 WDC-30/ '-! loel RD DATA/ loa I RD DATA 5~I WDe ¢tJ/ IIAI ALW SYNC SRCII 0/0 5 12- 7el SYNC BYTE/ Jtk~7~ ~ IV NCfv1PR-L I2.CB 1/ c B 1RP2"1 '2. 7 RPe I R ~ +5V ~ J. q 4.7K.fl. 1 68.n... Y/'3 I RPZ'2.~ '::' 2~~o 2. 74LS74 5 4i'<2fL 781 rDfi::cc NCMPN D U2!1 Q F- UIO ~ DRv' ¢ SCTDI 10C8,12De I RP23 2 ?Ie '~ DRVJ 5/...TDj Io:;e"I2.06 R Q/ ~r- 18~\ _~JL I 3'2. ~ .b DRY 2. SLT1>/ Icee/I2.D8 I -SELECI'ED-DEV ¢ 29...;...------1 +5ELECTED-DEV 0 ¢9...;------' [;RV.3 5LTD/10A.8/12.D8 :T2 -SELECTED-OEV I 394------' +SaECIED-DEVI /94------~~~~~-~ 3'.3 -SELECIED-OEV 2 29 ...;; ::J3 -5ELEC~DEV3.394__------. +SELECTED-DEY3194------, A A """IICI. REV DRAWN .C/ 162033 ISSUED - • 7 6 5 4 3 2. 1 Figure 5-2. iSBC 220 SMD Disk Controller Schematic Diagram (Sheet 9 of 12) 5-23/5-24 Service Information 7 6 5 4 3 _NO. 162033 ZONE REV DESCRIPTION OfT CHK DATE APPROVED 5EE 5f1EET , 2 RP!' I ~ J I 1 G~-"- -=-1 RPZO~ 2 MC3450 4'70.1L 7BI WRT DATA 7 <; PUP RP24 sse Z. RP9 1 II~?> J 2 v 1'"1 -::- 4- D +SE.RVO CLK- DEV ¢ 2 / I T 2 RP8 470-'1- ~ MC~53 :rz D ~ \ GSn- c:!:- -SERVO CLK- DEV al ~~- IS .I"l 27+\NPSiT OJ>..\f>..-DEV ¢ 68~ -t.jRP20~ /4 +R.Ei'\D eLK. -DEV ¢ 24 470-1l... IP'!.>'?> ¢-B-WRI'iE D{S;\A.-OC\! C/J 7 s c. 3 RP9.~ jl~'3 - 4- ~0 - REi'\D CLK -DEV ¢ f5~v 'I -:J2 Lh...RIT>_1 470-!1. 37.WRI-n-=- Df>..\f>..-DEv I ~ ~5V 101;- 1.1 RP6 .J Z 68A.~ -e. 1 -c 1 UQ>12 [ 68.lL~5RP2.0b 10 /8-WRI"TE I)/>..-r", DE-V \ +R.EAD DAiA- DEV ¢ 23 I RP24 ... s ~0 470-'1- t.1I :l.3 7 RPZ0 5 9 ~ 7 - 4 4.7K -READ DATA-DEV¢ ~ 6 ;1.' ILl 27... WR\"TE DA-rf>..-DEIJ 2 T~ ppe \ 4'70-'1.. "~ I 15 UI§>I roe:n--~ ~ ) ¢8-WRI-Tt. D."--r "'-DEV 2 9B( DRV ¢ SLTD/ 10 30'13 5 J 2. 2J\PJ.~\ J3 + 5 +5ERVO CU'--DE:V I 3 f( ~~"~5 2- 7 _ ---11. D74S7t 9 t II 37... WRnE DA."TA-DEV 3 _ 4 1~1~12. 5 RP?470~~ ,- U/2. 18-WRnE- DA-rA.-DEV 3 -SERVO ClK-DEV I 12 ( ,lie ~~ ~ ~ C4/&.s ~6 ~RPIO 1 "8-"- - R J Z PUP Ril SB6, OCB J 68-'1- ~ -~ RP.z.1 3 11/ RII 'ii?) +RE"'-D CLK-DEV I 34L t5'1i J '3Z 4-70.1L C .)3 IK 2 ¢&-wRnE CLK-DEV 1 R1'21...2.. r ¢ C ClK-OCV , 15%; 1 U!J>3 -REi'\D /5 26+WRIIE CL\<--DEV ¢ ~~)J. 470-'1- ~ 68-'1- ~ II RPiO I ~~ J 2- '32- - I -~.il-~5RP2IG 10 +R'i:'-AD DA.-rA-DE.Y 1 .33 5 liO-WRIlE CLK- DEV I 470Jl- 7RP2~ JU9 lL 36>WR\"TE- CLK-DE-V I -READ DA,"'-DEV I 13 ( J!...;:G 7~?>4 ~ 470-'1- ~ :J3 9BJ DRV / SL TD/ rL-=- 06-WRITE- CLK-DEV2 ~!:,~I +~ 11'~ J.~ 26+WRfTE ClK-DE\! 2 +,::£RVO CLK - DEV 2 2 1 1 68JL ~2RPl31 Z R2. ~~3 ::r.3 2. -SERVO CLK-DE\J 2 ¢2 1 ~ 1~3 IK 7 5 16-WRIl"E ClK-DEV 3 ~~-.l 4-70JL IrUl§>'I b RP\2...L 68.!L c:!:- 36MJRfTE ClK-DEV3 J~ ~6 '5 RPl:'_~ 1'( R2.1 1 WL~ ~5V +R.EA-D elK -DEV2 24 ~ pup R2.1 3C8, BDB 470.n.. If) IK Alo '4 RP253 15,1~J3 - 'I 5 5 -REA-D CLK -DEV2 (is 745112 9 I l7m~I 470...1L 12 74L574 9 ~ J U7 Q D Q RD DAiA 7B61 9DB B <08Jl.. ~ ~RP\2 1 -f:.13 I----" J 3 CLJ( Ub3 6a".rL?rRP25 8 10 /2. +READ DAiA-DEV 2 23 1 K Q/ ,---!L c RD DATAl 9C8 47011- cl-- Q/~ RPl3 ~~/I R R -RE"'D DA-rA -DEV 2 (113 4 3 ~K..~I 470JL ~ y/l.f 13 68-'1-~ --;r, 9BI DRV 2 SLTO/ 3~6 1..3~12 J :3 .3~PI"l1 R/W CLK-A 7Af>,ec~ I 6tl- 5-25/5-26 iSBC220 Service Information 7 6 5 4 3 """ NO. 162033 ZONE REV DESCRIPnON DFT CHK DATE APPROVED SEE SHEE1' I JI 15 /J V-I C-.5GJL-= 54 + DE\! 5LCT I ~13 ) 24 -DE\} 5LCTI D MC3'-153 £) PP5 I 6" ~ D 10 u(; I I 56Jl..::;:- .12.. -= , 0G1 (BDAT-9)-(BDAT-O) ~ 1 53 +OEV 5LCT(} IT /12. 23 -DEV .5LCT(l) UI ~IO l5~~ I .f,~'r~..l. 3 074-L5174Q 5G1L -= lSi U 1'-\ 1 5G-fL ~ bel BDAT-D ~ 42 +BUS 8 'f 5 1//\:' -... lOCI BDAT-C 1'/0 Q 12 -BUS 8 8 DAT-8 ~ .5. RPO> J. "16 liORY?-.l 0 B DAT-7 /3 Q 12 101, 1\ 1 56.n. '7 .561L -=:- /I 0 Q 41 +BU5 7 BDAT- 3 10 1~5 /12- 1/ -BUS 7 f3 DAT-2 6 D Q 7- D Q ~ ~0 ls.RP"j..L .e,1~n-l. 5G1L -= 10 U II 1 56.12.. ~ 37 +L3US 3 wocle/ 9 eLK IT /12. f17 -L3U.5 3 7 RP2-l. ~6 'I&l'PZ..L PI 56..Cl.'7 ... 5V CLR 7 U4 '5 1 .561L '7 -... 36 +8US2 I~ 1/'-\ fif6 -BU52 L 10 T 7,K~1 JPP.1.l~ > .5tOJL7= 5IO-fL '7 I '2 1 4-3 +BU59 lru~3 -- /3 _ BU.5 9 V'l6 > c L3 DAT-9 17Lf ~56.1L -= , c 'I o7'1t"'s Q J I us 2. Fl~ q.o +BUSG 8DAT-6 13 0 Q~ ,':-' 10 -BUS6 BDAT- 5 II 0 Q 10 U';3 .3RP3~ B DAT-4- 5. U58 6 ~\"-v----h. , JII 0 Q 15 "I L: ¢ 9 LJI ,B 5G..1L -= 5 1 .56..!l.'=:: 39 +BUS .5 B DAT-I 7 U,:,<>'-I ..--, 3 D Q~ ~ ~9 - L3US .5 BDAT-O 6 0 Q~ 1 2,HPLi ..L ~16 l3..RPLi..L 15 U4 V-l 1 561L 7 56-<1. -= 12.4:iJl II 38 +f3US 4 13,J_5I;'B 9 CLK IT, -<'1::2 (#'8 -f3US 4 'SAl WDC¢¢/ ~G ~r? .1 61:;'t'.f..L I .56..Cl. -= 5W1.7 , 8BI R/W GATE Rsl;I CLR I ru~2 1 35 +BU51 -" ~5 -BU51 .s. RP2 .1 ~(~ 1hh~1 ~ ._-1--- 13 U.1.I9 / 5IO.n.. '7 15 U 1'-1 1 .56.n... '7 -"- 34 +BUS Ii /2 )LS32 l~':>./I3 ~ /' (J4 -BUS Ii ..!:iRPI J. 5BI ID F/£LD/ ~6 ls..~P~ ..5(,..1L -= 1 561L -= 5BI WRTAM/ 10 ~'3-11 /' 33 +CfRL SoLCT-TAG 3 1';/12 fl3 -eTRL SLCT-iA-G 3 3 RP2 I "'16 ~Y,fJ U21 5 1 .56..1L-= 56-'2.. '7 • ) 32 +SE, HD ADR-iAG.2 • L3 DAT-7 /3 074L527,% 12 WR.T GATE-F Ri2 -SET I-ID ADR-1A62 1'-1 J~->'-I B DAT-6 o Q 15 b.RPI I 2 f;:\pl I B DA T- 5 17 16 o Q ..56..lL -= ~ ) 31 +SET CYL-iAG I BDAT-4 18 I u~.o D Q 79 fll -SET CYL-,AG I f3 DAT-3 3 MC.34'53 RP5 3 I o Q '2 L 1 ~6 L2~-:,2 f3DAT-2 ,5",-'2.. ::- MC3453 .561L -= "/ o q 5 1 52 +DEV 5LCT ENbL f3 DAT-I 7 {;, 7 u",)" D Q IT J.j :;:. 22 -DEV SLCT ENBL BDAT-YJ 8 D Q >' I L..3<0 l.z.W-r-h. C1'I' DllAWN . CIGNETT. 162J33 ISSUED SH££T II - 8 7 6 5 4 3 2. 1 Figure 5-2. iSBC 220 SMD Disk Controller Schematic Diagram (Sheet 11 of 12) 5-27/5-28 iSBC220 Service Information 7 6 5 4 3 .... NO. 162033 SE:E SHEE.T 1 U2.6 1'3 74LS374 ~ .IDA'- - F" D Q 8 o Q n:DAi-t. J "7 6IDAi-P-~~ D o Q D iii o Q ~:rDA\-C 17 ,f;~~A'- - 'O_~' '36 I ORV 3SLTO/ o Q 5I\)AT- A 961 DRV 25LTO/ ------_._---_. ------J: Q :3 o 2--:LDAT-9 961 DRV 1 SLTD/ D Q Je f9IDAT-8 981 DRV SLTD/ ------_.- D Q rI 1/ 5AI WOC¢8/ eLK JI '-\ RP6 I \VIC3450 a£ I RPI7? 1 1 56.a.--=- IJ.f~ U'-II -INDE.)<' Ml\R\\ /8 13 6 74LS2797 3 ~;JLR 17 5 - +::LNDE)<. MM<.\\ 48 '--I - "I "' l'-\ I-!-I:'? I -iit/JL 5;r L2c R .56.iL ~ 8 RP:, \ 5G.JL --::!:- 5 RPlb h +1=!\I..lLI 45 L 1 47¢JL 7_ RPI6..a f U2'-1 :, -rA.\JLI 15 L. 2~- "I '--I70n. -I4f137I./Q 9 IDA'--7 D 5IDAT-E> C 9AI ID NCMPR-L ~n ~ c f7 D Q\I6ID"-'--'=i ;, RPl6 ~ I , I~ D Q ZIDA-'--~ + sEEK ERROR % D Q V5'IDAT-'3 5 18 6~7 U24 'I o Q 5IDAT-2. -SEEK ERROR 16 - '-/ I~ 7 D Q 6:rDA"T-1 : 47i - _... _--"-_. ;: I i 56JL --=- 1:3 o Q \l2IDA"T-(2S ;""=fI D Q 3.RP6...L eLK 5 RPl7 ~ -ON CYLINDER 17 1 5GJL~ f.¥.JL OE I I 7 RPI7 p, 9 U2'-1 1/ 1 +ON CYLINDEI=<. 47 _L ~~- '-I 12.~ -f'7(3'JL 56JL --=- 13~12 5131 ROC ?i¢/ ~~_I I -t-?74LS04 S6JL "7 5 RPIB 0 I -UNIT R'rAIJY 19 1 4-7jf.-fL 2~3 l 7 RPla& -tUN" READY 49 -- AM FND/ ~t'P_1 4-7 LiPo.I (.IbAT-7)-(.:LDAT-\2S) ----- A OCI R/W GATE. A ~DI .... NO. REV DRAWN _ CiS T 162033 ISSUED SHEET 12. - • 7 6 5 4 3 1 Figure 5-2. iSBC 220 SMD Disk Controller Schematic Diagram (Sheet 12 of 12) 5-29/5-30 APPENDIX A EXAMPLE HOST PROCESSOR DISK CONTROL PROGRAM INTRODUCTION The following listing provides an example program that a host processor would run to direct data transfer between the host and the iSBC 220 controller. The program is written in MCS-86 Macro Assembler language. It illustrates the data structures that the iSBC 220 controller requires and shows a few simple disk operation drivers. ISIS-II MCS-86 MACRO ASSEMBLER V2.1 ASSEMBLY OF MOllULE· PRGIlXII NO OBJECT MODULE REQUESTED ASSEMBLER INVOKED BY: ASM86 :FO:PRGEXM.SRC DATE(80100611) NOOBJECT LOC OBJ LINE SOURCE $PAGELENGTlI(85) PAGEWIOTH(!15) TITI.F.(iSBC 220 SlID OISI( CONTROLLF.R I'ROGRAtllll'lG EX AlIPLE) XREF 2 3 #########H###########8######D##########################Q##U 4 HH H 5 ## 1SBC 220 SlID nISI: CONTROI.LER PROGRA:I!IING EXAttPLE #U 6 ## nn 7 ########8#####008#######0#########90###0##############unnuo R 9 THIS PROGRAM II.LUSTRATES TqE nATA STRUCTURES REQUIRED BY THE lSBG 220 SliD 10 DISK CONTROLLER. A FEW SIHPLR nISK O~ERATION DRIVERS ARE ALSO SHOWN. 11 12 THE HARDWARE CONFIGURATION SUPPORTED IS: 13 14 I. 1SRC R6/12A HOST C'U IS 2. 20 HIT SYSTEI! IIEtlORY "'IlDRESS IIlDTH 16 3. 16 HIT SYSTEII DATA RUS IlIlJTlI 17 4. 16 HIT SYSTEM I/O ADDRESS WIDTH IA 5. 1S1\C 220 19 a. WAKE UP ADDRf.S~ ( \lUA ) AT I/O 'nRT 06351! 20 b. INTERRUPT 5 21 c. -12 VOLTS InpUT 22 d. RELINQUISH RUS CONTROL ON ANY REQUEST 23 24 FOR (2), PROGRAMMING OF DATA TRANSFERS ttnST TAKR T~IR INTO ACCOUNT,e.R. THERE 25 IS NO I,RAPAROUND IN S1lG~fF.NTS IF IIORE THAN 64K BYTES "'HE TRANSFERRETl. 2(, 27 lSHC 220 SIIlTC'! AND JUIIPr.R SETTINGS: 28 2q FOR (3), SWITCH 52-1 IS CLoSBn. 30 FOR (4), SWITCH 52-2 IS CLOSED. 31 FOR (Sa), SWITCHf.S SI-6,SI-7,S2-5,S2-6,s2-8, AND 52-10 ARE CLOSED, THE 32 RF.MAINING ADDRESS SELECT SWITCHES ARE OPEN. 33 FOR (5b), W4-C CONNECTS TO W4-5; INn:RRUPT VECTORS lfUST BE SET Ul' PROPERLY. 34 FOR (5c), WI-C CONNECTS TO WI-2, W5-C CONNECTS TO US-I. 35 FOR (5d), W2-C CONNECTS TO 1'12-2. 36 37 +1 $INCLUDE(COHBLY..SRC) -I 38 +1 $EJECT TITLE(1SRC 220 COlUfUNICATION BI.OCKS) A-I Appendix A iSBC.,~20 LOC OU LINE SOURCE -I 39 -I 40 -I 41 COMMUNICATION BLOCKS -I 42 -I 43 -I 44 -I 45 -I 46 1_ SCB ~I 47 -I 48 -I 49 THE SCB TELLS THE ROR9 ON THE iSBC 220 TOE WIDTH OF THE ROR9's LOCAL ~I 50 BUS A~D POINTS TO THE CCB. -I 51 -I 52 **************.******************************************************** ~·I 53 * THE IIElmRY ADDRESS OF· THF. SCB I S EQUAL TO TlIE I/O WAKE-UP ADDRESS * -I 54 * ( WUA ) OF THE iSBC 220 MULTIPLIED BY 16. * -I 55 *********************************************************************** -I 56 0635 -I 57 WtJA f.QU 0635R WAKE-UP ADDRESS I/O PORT NUHnE~ =1 58 -I 59 SCBSEG SEGHf.NT AT WDA PUTS SCB AT ADDRESS 061509 -I 60 0000 -I 61 SCB LABEL FAR 0000 01 ~I 62 SOC DR OIH TELL ROR9 IT IS ON A 16 BIT LOCAL BUS 0001 00 =1 63 DR 0011 RESRRVED 0002 0000---- R -I 64 CCBPTR DO CClI POINTER (SEGMENT + OFFSET) TO cca -I 65 =1 66 SC8SEG ENDS =1 67 -I 68 =1 69 II. CCB -I 70 -I 71 -I 72 THIS BLOCK CONTAINS TlIE CONTROL BYTES, BUSY FLAGS, AND POINTERS TO TRE -I 73 STARTING ADDRESSES OF TRE CHANNEL PROGRAMS FOR THE 80R9. =1 74 , -I 75 CCBSRG SEGMENT CCl! flUST BE CONTIGUOUS -I 76 0000 -I 77 CCl! LABEL FAR 0000 01 -I 78 CCWI DB OIR START CH. I PROGRAM IN LOCAL MEMORY 0001 00 -I 79 I!SYFLGI DB 0011 Cll. I BUSY FLAG 0002 0400---- R -I 80 CHIPTR DO CRIPC POINTER TO FIFTll BYTE OF CIR, WHICR -I 81 CONTAINS STARTING ADDRESS OF CH. I -I 82 FIRHWARll PROGRAl! 0006 0000 =1 83 0\1 OOOOR 1l.ESRRVED 0008 01 -I 84 CCW2 DB OIR START CR. 2 PROGRAll IN I.OCAL HEMORY 0009 00 -I 85 BSYFLG2 DB DOH ClI. 2 BUSY FLAG OOOA OEOO.---- R -I 86 CH2PTR DO CH2PC POINTER TO LAST WORD OF CCl!, WRICH -I 87 CONTAINS STARTING ADDRESS OF CR. 2 -I 88 FIRMWARE PRO GRAIl OOOE -I 89 CH2PC LABEL FAR OOOE 0400 -I 90 OW 0004H STARTING ADDRESS OF CII. 2 PROGRAM -I 91 , -I 92 CCBSEG ENDS -I 93 , -I 94 +1 $EJECT A-2 iSBC220 Appendix A LOC OBJ LINE SOURCY. -I 95 -I 96 Ill. ClB =1 97 -I 98 -I 99 THIS BLOCK CONTAINS GRNRRAI. PURPOSE DomlANO AND STATUS HYTES. SEMA -I 100 PHORES. AND POINTERS TO ALI.OI~ THr. USE OF THF. iSBC 220 IN A HULTt -I 101 PROCESSOR/MULTI-PROCESSING SYSTE~. =1 102 -I 103 CaSEG SEGtlF.NT CIS MUST lIF. CONTIGUOUS =1 104 0000 -I 105 CIlI LAlIEI. FAR 0000 00 -1 106 CIBGIIO DB 0011 CIll CO?IIIAND BYTE NOT USED BY iSBC 220 0001 00 -I 107 OPSTS DB DOl! CIlI STATUS BYTE IS USED BY iSBC 220 0002 00 =1 108 CHOSEM DB OOH COMMAND BYTR SEMAPHORE 0003 00 =1 109 STSSEI1 DB OOH STATUS BYTE SF.MAPIIORF. 0004 -I 110 CHIPC LAlIEL FAR 0004 00000000 =1 III Oil nOOOH STARTING ADDRESS OF CR. 1 PROGRAH 0008 0000 =1 112 IOPBOFF OW OFFS£T IOPB POINTER TO 10PB OOOA R -I 111 tOPl\SG OW IOPBSEG OOOC 00000000 -1 114 OD OOOOH RESERVED -I 115 -I 116 ·CnSEG F.1l!lS =1 117 =1 118 =1 119 IV. IOPlI =1 120 =1 121 =1 122 THB BLOCK CON'l'AlN~ THE DEVICE DEPF.NOr.'fT CONTROl. INFOR!1ATION FOR THE -I 123 iSBC 220 CONTROLLER. =1 124 =1 125 ·10P~~EG SEGI1ENT IOP8 }IlJST BE CONTIGUOUS =1 126 0000 -I 127 IOP8 LABF.!. FAR 0000 00000000 -I 128 DD OOOOH RESERVED 0004 00000000 =1 129 ACTCNT 00 OOOOH ACTUAl. TRANSFER COUNT (32 lilT INTEGER) 0008 0200 -I 130 DEvcon 0\, 0002H DEVICE CODF. (- 000211 FOR iSBC 220) OOOA 00 =1 131 UNIT DB OOH UNIT NU!!BER (0 <= UNIT <- 3) OOOB 00 -I 132 FUNC 011 OOH FUNCTION CODE (0 <- FUNCTIon <- OFH) OOOC 0000 =1 133 1I00IFY DW OOOOH 110nIFIER 1l0RD OOOE 0000 =1 134 CYI.NDR Oil OOOOH CYLINDER NUIIBER 0010 00 -I 135 HEAD DB DOli HEAn NUtiBER 0011 00 -I 136 SECTOR DB 001! SECTOR NUUlIF.R 0012 0000 =1 137 BUFOFF DW OOOOH POINTER TO DATA lIUFFER 0014 0000 -I 138 nUFSEG DI, oooon 0016 00000000 -I 139 REQCNT DO OOOOH REQUESTED TRANSFER COU~T (INTEGER) 001A 00000000 =1 140 DO OOOOH RESERVED -I 141 -I 142 IOPBSEG ENDS 143 144 +l ·SINCI.UDE(INITlIL.SRC) 145 +1 $EJECT TITLE(DISK DRIVE INITIALIZATION TABLF.S) A-3 Appendix A iSBC220 LOC ORJ LINE SOIlRCr. ~1 146 =1 147 -I 148 DBK DRIVE INITIALI%ATION PARAar.Tr.;! TARLF.S =1 149 =1 150 =1 151 =1 152 THIS SF.OnENT CONTAINS TnE DRIVE CONFIGURATION DATA TARLES TRAT ARE USED -I 153 BY TilE INITIALIZATION ROUTINY.. THP.Y flllST I:E tlOOIFIRD TO REFLr.CT TilE -I !S4 PARTICIlI.AR DRIVES REING [Jsr.1) IIlTIl Til,: i~RC 220 RllD DISK CONTROLLER. =1 155 -I 156 - IF A DRIVE IS NOT PRESENT, ITS INITIALI%ATION TADLE MUST HF. ALL ZEROES. -I 157 =1 158 -I 159 1 :lYTES P~"1 Sr.CTOR 1 '!AXI'''''l SECTORS PER TrACK 1 =1 [(.0 I------~------I =1 161 1 12R 1 lOR 1 -I 162 1 256 1 64 1 =1 161 1 .512 1 15 1 -I 164 1 102/, 1 lR 1 =1 165 -I 166 -I 167 =1 IfiR INITRLSEr. =1 16q -I 170 lJRIVE PO CARTRI!lGr. T!OOULI: !lIlIVT-: (C'IO) (32TT!I: 16/lTl FIXF.O. 16HH Rf.110VAJlLF.) =1 171 0000 3703 -I 172 OIl R23 NU!mER OF CY!.INI)P.RS 0002 01 =1 173 on I NunKeR OF FIXEn Rr.AD/wRIT~ SURFACES 0003 01 =1 174 DB 1 '!lPlBER OF RE;IOVAHLP. R/!l SUR~·ACF.S 0004 23 =1 175 DR 35 Nu!!lIP.R OF SP.CTOI\S PER TRACK 0005 0002 =1 176 DH 512 ~U~BIR OF IYTES PER SECTOR 0007 OS =1 177 nn 5 ~;UqI\ER OF Ar.n:R~ATf: CYLINDERS -I 17~ =1 179 Dill V,: ill :!IIH-:!OIlULP. 1l~IVF. el!!!l) (tl01m \HllCHEsn:R: \1.1. FIXI:I» -I 180 ODOR 3703 -I 18 I llH n23 NU!!BER OF CY!.l'lDERS OOOA O~ -I 182 08 5 'IUlmF.p. OF FIXP.D READ/I~RITr. SURFACr.S OOOR 00 =1 11\3 DR o NU'lnIlR OF RF.I!OVA~J.F. R'" SIJRFACES OOOC 12 -I 184 DR IR HU'!lIP.R OF SF.CTOR~ PER TRACK OOOD 0004 =1 IRS my 1024 '1mmER OF ilyn:s PI:R seCTOR OOOF 06 =1 11\6 OR (, '1TJnllll~ OF ALTERNATE CYLI'lDF.RS =1 IR7 =1 IRR DRIVE #2 NONRXIST~NT =1 IRq 0010 0000 =1 190 Oil 000011 >!HHBF.R OF CYLHIOF.RS 0012 00 =1 191 DB DOl! :I!l'tnER OF PEP.!) Rr.AT>/lmiTE SIJRFACES 0013 00 -1 192 DR Dill! 'l!l!tnF.~ OF ~EHOVAI\Lr-: R/!! SUPFAC~S 0014 00 -I 193 08 (Hllt NU~HER OF SECTORS PHR TRAC~ 0015 0000 -I 194 DII 000011 NU:1RF.R OF BYTES PF.R SRCTOR 0017 00 -I 195 DR DOli NUMB F.. OF ALTF.~NATF. CYLINnr.RS -I 196 =1 197 DRln: fl1 NOIIEXISTENT -I 198 0018 0000 -I 199 nw 000011 !JlH!nER OF CYLINnr.RS 001A 00 -1 200 DB 0011 NUlIRER OF FIXF.I) READ/WRITF. SURFACES 001R 00 -I 201 !lB 0011 !11Jl!BRR OF HE/lOVABLE RI'I SURFACF.S ODIC 00 -I 202 Oil DOH NUI!HllR OF SECTORS PF.R TRACK 001D 0000 =1 203 !'>W 000011 NUMBER OF gYTeS PER seCTOR 001F 00 -I 204 DB 0011 :W;!BER OF ALTER/IATr. CYLINDERS =1 205 . -I 206 INITRI.SBG ENnS 207 208 +1 $INCLUDE(~ATSEG.SRC) =1 209 +1 $F.JRCT TlTLr.(DATA SEG/IENT) A-4 iSBC220 Appendix A LOC OBJ LINE SOURCE -I 210 al 211 -I 212 DATA SEGIIENT -I 213 -I 214 -I 215 -I 216 DATASEG SEGlIENT -I 217 -I 218 THIS SEGIIENT CONTAINS VARIOUS DATA THAT ARE USED BY THE lSBC 220 DRIVER -I 219 SOFTWARE. -1 220 -I 221 - THE FLAGS ARE SET BY THE INTERRUPT SERVICE ROUTINE, AND ARE COPIES OF THE -I 222 CIR STATUS POSTED BY THE lSBC 220. THE ROUTINES THAT USE THE FLAGS ARE -1 223 RESPONSIBLE FOR CLEARING THEM AFTER USE. -I 224 j------al 225 -I 226 PUBLIC OPCIIP,~KCIIP,PKCHG,ERRSTS =1 227 -I 228 OPERATIon COllPLRTF. FLAGS =1 229 , 0000 =1 230 fll'CHl' T..ARF.T. RYTF. 0000 00 =1 231 OI'C~IPO DlI 0011 OPRRATION COnPLETE ON UNIT 0 000 I 00 al 232 OPClIP 1 DR non OPERATION COMPLETE ON UNIT 1 00()2 00 -I 233 OPClIP2 DR 0011 OPERATION COMPLETE ON UNIT 2 0003 00 -I 234 OPCIIP3 DB 0011 OPERATION COIIPLETE ON UNIT 3 =1 215 =1 236 SEEK COHPLETR FLAGS -I 237 0004 -I 238 SKC'fP LAlIEL BYTE 0004 00 =1 239 SKC!1PO I)R DOH SEEK COMPLETE ON UNIT 0 0005 00 =1 240 SKC'IPI 011 DOH SEEK COIIPLRTE ON UNIT 1 0006 00 =1 241 SKCl!P2 DB DOli SEEK COUPLETE ON UNIT 2 0007 00 -I 242 SKC:IP3 DR OOll SEEK COUPLETE ON UNIT 3 -I 243 -I 244 PACK CHANGE FLAGS -I 245 0008 -1 246 PKCHG LASH BYTE 0008 00 -I 247 PKCHGO D1I Don PACK CHANGE ON UNIT a 0009 00 =1 248 PKCHGI DII 001! PACK CHANGE ON UNIT I OOOA 00 =1 249 PKCIIG2 DB OOH PACK CHANGE ON UNIT 2 ooon 00 =1 250 PKCflG3 DB OOll PACK CHANGE ON UNIT 3 =1 251 -I 252 BRROR STAT1JS BLOCK -I 251 (LOADED FROII CONTROLLF.R n ERROR HANDLER) =1 254 OOOC 0000 -I 255 ERRSTS D\, 000011 ERROR STATUS WORD OOOF. 00 -I 256 SFERST DB OOll SOFT ERROR STATUS BYTE OOOF 0000 -I 257 DESCYL Oil OOOOH DESIRED CYLINDER 00 II 00 -I 258 DESlID 011 OOR DESIRED HEAIl 0012 00 -I 259 DY.fiSF.C 01\ DOli DESIRED SECTOR 0013 0000 -I 260 ACTCYL nil 00001! ACTUAL CYLINDER + FLAG BITS 0015 00 -I 261 ACTIID DB DOH ACTUAL HEAD 0016 00 -I 262 ACT SEC OS 0011 ACTUAL SECTOR 0017 00 =1 263 NlIRTRY DB OOH NUIIBER OF RETRIES MADE -1 264 -I 265 LAST OPERATION COIIPLET! BYTE -I 266 (COPIED FROM CIB BY WAIT220) -I 267 0018 00 -I 268 LSTSTS DB DOH -I 269 0019 90 -1 270 EVEN =1 271 OOIA -1 272 RNDDAT LABEL FAR END OF DATA SEGMENT -1 273 , -1 274 DATASEG ENDS 275 , 276 +1 $INCLUDE(USER.SRC) -I 277 +1 $EJECT TITLE(SYSTEM DEPENDENT INITIALIZATION) A-5 Appendix A iSBC220 LOC ORJ LINE ~OURCE -1 278 -I 279 =1 280 SYSTE" DEPENnC~T IMITIALIZATIon -1 281 =1 282 -1 283 -1 284 TnIS ROUTINE SETS UP THE INTERRUPT VECTOR FOR AIT ISRC 86/12A CPU =1 285 RUNNl'lC urmER T~lF. 1SRC 957,\ I~TI;RFACE/EXECIJTION PACKAGE. =1 286 =1 287 - TilE 8259 IriTERRUPT CONTROLLER AND OTHER I~IITIAL7.ATIONS ARE PERFOR~!Ef) -I 2RS BY THE 1snc 957A FI~"UAR~. =1 289 =1 290 -1 291 =1 292 INTERRUPT veCTOR DeFINITION -I 293 =1 294 0005 =1 295 I'ITRPT EQII -1 296 , =1 297 RRcnooo SECYE'T AT 0nonn HITERRIlI'T VECTORS A~I': I'ROll ARSOT.HTf: -I 298 \DDRERSEs oonoon TO nOFFoH =1 299 0094 =1 100 ORC Ron + 4*Iwr~fDT T.n~ATIn~r OF I~T~~RUPT V~CT()R :ll'rlt =1 101 isnc q57A FIq~f1JARR 0094 onoo =1 102 HlTRIP nu 000011 - I~~TRIJCTI()n pnI~T~R 0096 0000 =1 101 INTRCS D'.! ononH - 0)1)1: sr·:\'~n:~IT =1 104 =1 105 SEGOOOO r.~ns = 1 106 =1 107 =1 308 STACY ALLOCA'1'IflN =1 109 -I 110 =1 111 =1 312 0000 (fi/, =1 313 fi4 flTlP(OOIf) 00 ) =1 .314 =1 315 brOSTK LABEl. FAR =1 31fi =1 317 STACK r.rJl)g =1 3IS =1 319 =1 320 ~TAC~ AN!) tNTRRRtJPT C!)NFl~U!tATIO~ l~nIJTI'J~ = I 121 =1 322 , =1 121 U~r.RgF.G 5r.r:!lr,~·!T =1 124 =1 325 PHill.IC COtlFIC =1 326 ASSWI" llS: SEr.OOOO =1 327 , 0000 =1 128 conFIr. PROG FAP =1 329 0000 FA =1 330 eLI ; nI::;A~T.r. It::,p.nRUPT~ 11!111.F. S~TTIi'Ir. Ill' 0001 R8---- R =1 331 :IOV AX,~TACy': 0004 8EOO =1 112 HOV SS,AX 0006 RC4000 =1 111 :fOV S'PJ(lFF~r.'l' ~N'n~TK. 0009 n ROOOO =1 114 ~10V AX,nooo'l OOOC BED8 =1 315 H(1V DS,AX OOOF. C70fi94001202 =1 336 1I0V InTRIP,oFFSKT INT2zn 0014 C706%OO---- R =1 337 :10V INTRCS,SCG INT220 001A MC2 =1 138 III AL,ne2lf ItiPUT INTKRRIJPT ~A~!: FflO~1 "259 ODIC 24DF =1 339 AND AI. ,110111118 CNARL~ INT~RRUPT 5 ODIE f.fiC2 =1 340 OUT OC2 l l,AI. WRITE NEW HASK nUT TO 8259 0020 FH =1 341 STI ENARL~ INTERRUPTS 0021 CC =1 342 INT GO TO lfonTOR =1 343 , =1 344 CONFIG R'IOP =1 345 , =1 346 URERSI:G ENDS 347 348 SRC220flRIVER 349 350 ARsunE Cs:RRC220DRIVER 351 , 352 +1 $INCLUDE(RF.SET.SRC) 353 +1 $EJECT TITLE(CONTRnLLR~ RESET ROUTINE) A-6 iSBC220 Appendix A LOC ORJ LINF. ~OIlRCF. =1 354 =1 155 =1 356 CONTRnLLC~ RE~CT RonTI~C =1 357 =1 158 =1 359 =1 360 ~F.~220 ~ETS llf' Till; CO'l~lIJr!ICATlntl 1l1.nCI:~ FOR T:11: lS~C 220, LINK, THE!! =1 361 TOCETHf~R AND GIVr.S :\ Rr.:S:J:T. CLP.A~ RF:SET. c;rrA}PJEI. ATTr~~lTrrHJ SI:qlH::JCf: Tf) ·1 %2 THE CONTRnLl.r.R. TlIIS CAIISES THE HIlg9 OJI TilE COtlTROL1.r.~ Til ~ET I1P In =1 163 INTE'P1AL POINTF.l( TO TilE cee BY TlIRF.Af)I~H-: DOU:l 'fll!: LINKS STA~THJr. I-IIT!I =1 %4 TilE ~lIITCIlt::S 011 Tm: CONT~OLLr,H. S!)l\~EQIJENT CA's IHLL r.AlJSJ: TilE ~089 TO =1 365 FITCH ITS POINTSRS ~T'RTI.G AT TIIR CClI. =1 366 =1 367 - If T~lF. Gil. 1 RUSY FLAG IS !IOT CLEARED \JIT!lI~ /I. IIREASO'iABLr." AilOU:1T OF Tl:U:. =1 168 THEN Tim isr.r; 220 IS PRORARLY NOT nESPONUPlr. TO T:IE CIIAt~:!EL ATTi~NTU)~. =1 36q ON T!lE COt!TROLLI:R: CIlECt: ~\llTCH SI:TTI;JGS; VOLTAC:es; ~ESET. CLI~AR RF:SCT. =1 370 Cl!A~JrJEI. ATTHNTI0:'i S[(aJAl.Sj '{EAf)Y HIPUT TO COM!); ,~089 STATUS LItIES; t{/h! =1 371 C;TflORCCi. =1 372 -I 373 - Til~~ ~YST~~11 rr(TI~p.r..UPT LOGIC. ANn VECTOP,S rO!l TIJI: CO~:TROT.LF.K ARE ASStr:tr-:n TO ra: =1 174 C()r!FIr:ur.:l~n roy AN I:XT~:R~'IAL' PR0r.RA'I. =1 375 =1 176 I:JPI1T ~AT.~: =1 177 "'lorn=: =1 17R =1 1]q OtlTPtlT 1),\1.'\: =1 180 CA~RY FLAr.: = 0 I~ I!SSF:~ ()KAY =1 lRI "" 1 Il~ C,ll. 1 p.nsy FLAr. ~r()T P.~<;ET (t~OT Rr.spn~!!H'!r.) =1 ln2 =1 183 =1 184 P1T1H,Ir. f~r:~220 =1 185 0000 =1 lA (, :'.:'~ 2 2 0 PRor; FAR =1 1R7 0000 50 =1 1Rn PUSIl AX ~ 1\ V': Itr.r. I <:;T!:P,;, 0001 53 =1 389 PUSH T~ :-: 0002 51 =1 390 PUSil cx 0003 52 =1 391 P iJS 1\ DX 0004 IE =1 192 PiJ~il O~ =1 393 =1 394 '11·:7 UP 1.1~n:s IH~T\JEt:~J C{)!Ll1JfnCATIO?1 ~\LOCI~S =1 195 =1 396 sen =1 397 =1 398 ASSU'1r: ilS: ')CRSI:G 0005 883506 =1 399 ~10V AX,SC!\~~G G~T POI~T~!t TO SCB 0008 8EDR =1 400 nov nfl,AX OOOA C70600000100 =1 401 'IOV Honn PTR SOC,OOOl'! SET SOC "VT~ A~l) CLEAR ~ES~RVEll nYT~ 0010 C70602000000 =1 402 nov \.JOf{J) PTR CCRPTR,nfFSET cen ~~T POI~TBR TO CCR 0016 C7060400---- Tl =1 403 nov '.1{)~J) PTR r:CRPTIt+2,:'F.G CCR =1 404 =1 405 cen =1 406 T.ns I\.X,CCRPTR ~~T POT~Tl:R 70 eCR =1 407 A::;:=;IJ:n: IHi: CCHS!~r. OOIC C70600000lFF =1 408 nov IJOI~n PTr.. CCiH,OFFOlll '1F.T r.r.U! ANn CII. 1 RUSY FT..Ar. 0022 C,70(,02000400 =1 409 nov Honn PTR CHIPTR,OFFSET ClllPC; :>T:T POINTr.:R TO FIFT'j !1YTE OF CI~ 0028 C7060400---- R -I 410 nov \\l0P-n PTR CII1?TR+2,SEC C:IIPC; (lI1\S ~TARTI\(G !\['JDRE,)S ~'()n CH. 1) 002E C70608000100 =1 411 ~fOV ~Jorn PTI{ CCW2,nOOPT SET CClf2 A:'·W CLf.A.R CI{. 2 l~IJ.C;Y FT~Ar. 0034 C7060AOOnr.00 =1 412 HOV \v-or.n P'I'R CH2PT~,OFF~r.T r.H2PC; SET POI:~T~:R TO ell_ 2 STI\.RTT\lr. A[)nnr::ss 003A C7060COO---- R =1 413 I\OV \;IlRn PTP, CIl2PTP+2,SEC CI121'C 0040 C7060F.000400 =1 4 I1~ 7ff)V HOnTl PT:~ CI!2 P C,tJO()411 81~T ell. 2: STARTI.'JC-; A.il11P.ES A-7 Appendix A iSBC220 LOC ORJ LINJ:; ~OURCF. =1 42~ CLEAR OIlT nATA sr.Grlf:NT -I 42q -I 1,30 .~R5ll!1F. DR:1JAT~Rr.C; 006Q RR---- 1\ -I 431 'IOV AX,1J~TA~F.C; CET POl~TP.R Tn nATA 5}:mlr.NT 006C REnR -I 432 !fOV nS,AX 006F. R90DOO -I 433 'IOV ex, (OFFQF.T F.~110AT)/2 r:E'r COIliJT ( # \JORnn p.: DATA RF. G~I r.NT) 0071 BlIOOOn =1 434 !lOV BX,0000H CLP.AR BileX Rr.GIS;~R 0074 C7070000 =1 41~ r.T.~I.P : ~10V WORn PTf~ ["'Xl,oOOOIl CLEAR NRXT HOI\I) l~ nAT~ ~~G'IEtJT 007R 43 =1 41~ INC 1\l{ POl'!T TO !IEXT HORO 0079 41 -I 417 INC 1IY. 007A F.OFR -I 43R LOOPNl: CLP.I.? f)ONE? -I 41q ~O--CLF.AR AN()T~IF. R UOitll =1 440 vr. ~ --1'11 TI.~T. I 7. r. Cml!lUNICATlOtl LI 'H~S =1 441 -I 41,2 OUTPITT :a:~I:T/cLE.~P. Rr.~ P.T ICIIAN'lF.L ATTEN'i'IO:'; ';'0 CONTROLI. ER =1 443 007C lIA3506 -I 441, !lOV nX,H!JA ra:T I.1Al:E-UP 1/0 PORT AOIlJ:r.S5 007F B002 =1 445 nov AL,0211 GI;T ~F.Sr.T COitHANO llyn: 0081 In: =1 446 OUT OX ,AL OUTPUT TO \IAKE-Ul' 1/0 PORT 00R2 11000 =1 447 'IOV AL,OOH GET CI.EAR RESET C(l'!:IANIl llyn: 0084 r.r. =1 448 OUT DY.,AI. OUTPU-:: TO 'IAKE-UP I/O PORT 0085 nool =1 449 'to V 1I\.,o1H r:wr CHANNEL II Ttl: ~lT 10 N con:IAND lIYTE 0087 EF. =1 450 OTJT DX ,III. OUTPUT Tn \IAKF.-Ul' I/O PORT =1 451 ASS~JifJ~ 1)5: cell!":1:C 0088 lIR---- R -I 452 ~101.' AX,CCnREG Gf:T PIl{;lTF.R TO CClI 00811 REllR ~I 453 'IOV nS,Ax =1 tlSi, (OT'1F.R I~IPI.r.'lI:NTATlm:s OF Rr. S 2 ~ 0 COULD -I 455 Ir!l T l.\\. I 7. F. OT'lEn or.v Ir.r.S I!HIJ.F. TlfE -I 456 i::;gC 220 l){)r.~ ITS RF.SF.T SF.0IJENCE HERr. ) OORD 1I90010 =1 457 '10V GX,lOnOJl ~r.T TIIIF.-OllT COI1~~T~R OOQO FR -I I,SR CLC CLeAR CA~RY FLAn nOql F6060100FF =1 4~9 nESLP: 'rEg'!' RSY!-·T.~l ,f)OFFl1 ClIt:Cf: r.H. 1 lI!1SV FLAt: : =1 460 ~F.!:n FLAr. = l\~YFLC 1 1'1' " 0096 7403 =1 461 .J7. Rf.S1H! nnsY FLAr. CI.r.A~I'Il? =1 4(.2 YI: S --lU:1' I) R ~1 r.ARnY r:l.r.A'l on9R .. on -I 463 LnOP~IC P,r.SLP '10--OF.CRF'IE;1T r.OU~ITF. R =1 464 IF C~ ~ 0, Ta,Er! q~;VFLGI :'-1f.Vf-:R r.OT 009A 1'9 -I 465 STr. C1.F.AR~1), ~O Sr.T CARRY FLAG oon IF =1 466 RESIH!: POP DS RESTOP.F. JIEGIsn:RS 009C 5A =1 467 POI' DX 009D 59 =1 468 POP CX 009E 58 =1 469 POP BX 009F 5R =1 470 POP AX OOAO CB =1 471 RET RF.T:JRf: =1 472 =1 473 RES220. ENDP 474 475 +1 iINCLIlDE(INIT.SRC) -I 476 +1 $EJECT TlTLE(INITIALI7.ATION ROUTINE) A·8 iSBC220 Appendix A LOC OHJ I. PIP. SOIlP-Cr. -I 477 =1 473 -I 479 INITIALIIATIO~ .onTINK =1 480 =1 481 -I 482 =1 483 INIT220 I~ITIALIIRR T"E 19ijC 220 CONTROLLP.R RY LOAOI4n P~~TINBNT INFOR =1 484 "ATIO~I AnOliT nil: 11ISI: IlRIVf.(G) ATTACHr.O. =1 485 -I 486 - I' A D~IVR THAT IS SPECIFIEO AS PRRSENT ~ILL 10T R~RPoun, INIT220 'ETIlRNR =1 487 IW!F.J)IAT<:LY 'IITI! T'!E CI\R~Y FLAG SET. -I 4RR =1 4S9 I'"PUT flATA: =1 49n nI~~ nRIV~ I~ITIALI~ATIOrJ TARL~~, IN REG~fENT "I!1ITRT.RE~". -I 491 -I 4n nUTI' UT :1A TA: -I 49) CAI'.~Y FLAt; = 0 IF r.OU"'ROLLE!! I~ITtAJ.t7.f;n ~UCCF.RSFIJLI.Y -I 494 = 1 T" I~ITIALIIATIDN HannR =1 495 -I 4% =1 4q7 pnil1.Ie: T!JTT?20 =1 49r:l AR5U:tr. !)~: InP1S'I"'.G =1 499 OOAI -I 500 INIT220 P~OC FAR =1 501 OOAI ';0 =1 502 PU51l AX ~AVr. HEGIs-rr:ns 00A2 IE -I 501 P!1f,q !)~ O,OAJ RS--- R =1 504 HOV AX,IOPRSr.r. GET POI'~TE~ TC) rOPR OOA(' RoOR =1 505 ~10V 1)S .A:{ pur IN nfi REG UjTI:I~ 00A3 C6060BOOOO =1 50(, l10V fl:~:C, nOli R~T Iopa FUNCTIon IYTK - INITIALIZE OOAD C70('OCOOOOOO =1 507 NOV :!OIlIFY, noOnl! CLI:AR 'WlllFIER (f.:lAilLE r.f:'rRP:R ANI) =1 SOP. rlT~RRUPT on CO:IPLf.T rON) oonJ C7061400---- R -I 509 lIOV BU'~Rn,INITnLR~G PUT t:lITIA!.tZATIOtl TA~LER' SEGIIENT It: -I Sin IOP~ DATA RUFFER POI~TKR 00B9 C7061200F3FF =1 511 'IOV llu~'()rr',-8 START IXITIAJ.IIR UITU UNIT 0 OOBF HOOD -I 512 HOV AI.,OOl! CLEAR unIT COUNTER OOCI 8)06120008 -I 513 IlnTLP: Ann n.UFOf'to' ,R PoI~T TO N~XT QRIVE's I~ITIALI7.E TARLE 00C6 A20AOO -I 5 )I, HOV lIr:IT,AL PIIT !JNIT I;!T0 IOPB 00C9 E8CHOO -I 515 CAT.!. G0221l no I'll TIAL II E -I 51~ (Rr.TURNS CARRY FJ.AG ~ET DR CLEAR) OOCC 7205 =1 517 JC It'ITlll·: UNIT INITIALIIED? -I SIR )1(1--TF.I:lI'1AT>: IHT'I C~RRY ~ IT SilT OOCE 40 =1 519 Inr. AX YER--INCRf:lr.r:T urn T COI!'IT':I~ nOCF JC04 -I 520 Cll. AI., I~ CHECK U'lIT COlTNT';~ (CLEARS CARRY) OODI 75EE =1 521 .In? INtTL? LART DRIVE 11ITIALIIED? =1 522 ~O--!~ITIAL!~R ~!XT ~nIVS OODJ IF =1 52J I'IlTI>:I: por nR YES~-nES'l:n~C ~RGISTER9 00D4 58 -I 524 POP AX ODDS cn -I 525 RF.'l: RF.TURII -I ';26 -I 527 IIIIT220 ENDP 52R , 529 +1 $INCLlIDE(FOR"I\T.~~C) 510 +1 $!JECT TITLR(FORHAT TRACK ROUTINE) A-9 Appendix A iSBC220 LOC OSJ LINP. SOURCE ~'1 531 ~I 532 -I 513 FOR~AT TRACK ROUTINE =1 534 -1 535 =1 536 =1 537 FIITTRI: SETS UP THE IOPH FOR A FORltAT TRACK FUNCTION, AND =1 538 INVOKES THE lSBC 220 CONTROLLER TO PERFORII THE nPERATION. -I 539 -I 540 IUPUT DATA: -I 541 RP + 9 => INTERLRAVE FACTOR -I 542 '81' + 8 -> USBR DATA BYTE 3 -I 543 SP + 7 => USER nATA BYTE 2 -I 544 BP + 6 -> USER DATA BYTE 1 =1 545 SP + 5 =) USBR OATA BYTE 0 -I 546 RP + 4 -) TYPE OF FOR~AT =,1 547 BP + 3 =) IlEAD ~I 548 SP + 1 -) CYLINllER -1 549 BP =) UNIT =1 550 =1 551 OUTPUT DATA: =1 552 CARRY FLAG o IF TRACK FORMATTED SUCCESSFULLY -I 553 1 IF NON-RECOVERABLE'IRRDR OCCURRED -I 554 -I 555 - INTERLEAVE FACTOR OF 1 ItlPLIF.S S~:QUENTIAL SECTOR NUHBIRING. ~1 5~6 - USER OATA RYTES a - 3 ARE RF.PLICATllD TIIROUGHOUT THE OATA FIELD. -I 557 - INTERLEAVE TYPES: -I 558 00 - NORItAI. TRACI( -I 559 40 = AI.T!R~AT! TRACK (POINTED TO BY EXACTLY ONE nEFICTIVE TRACI(, =1 560 CANlUlT StJBSEQUF.NTJ,Y RF. FORlIATTr.D DEFRCTIVP.) -I 561 80 = DEFECTIVE T~ACI( (DATA FIELD POINTS TO ALTERnATE T~ACI() -I 562 - TO SET UP A POINTER TO AN ALT~RNATE TRACK, SET: =1 563 USER ~ATA BYTE 0 = ALTERRATF. CYLI~OER LOU BYTE -I 564 USER DATA nYT! 1 ALTF.RNATE CYLINDER HIGH BYTE =1 565 USER DATA nYTE 2 ALTERNATE REAn -I 566 USER nATA BYTE 3 • non -I 567 =1 568 -I 569 PUBLIC Flt'f22 a =1 570 ASSUME D5:IOPBSKC -I 571 , 00D6 =1 572 Fl1T220 PROC FAR -I 573 00D6 50 =1 574 PUSH AX SAVE REGISTERS OOD7 IE =1 575 PUSH DS 00D8 S8---- R =1 576 IIOV AX,IOPBSEC GET POINTER TO IOPB OODS BEDB -I 577 HOV DS,AX DODD 8A4600 -I 578 nov AI., [BP] GET UNIT NUHRER INTO IOPB OOEO A20AOO -I 579 HOV UNIT,AL 00E3 8B4601 -I 580 ItOV AX, [1IP+l] GET CYLI!'IDER NUIIBER INTO IOPB 00E6 A30EOO ~I 581 IIOV 'CYLNDR,AX 00E9 8A4603 -I 582 IIOV AL, [BP+3] GET HEAD INTO IOPB OOEC A21000 -I 583 }fOV HEAD,AL OOEF B92EI200 -I 584 MOV BUFDFF,BP GET POINTER TO FaRHAT ARGUMENT LIST 00F3 8306120004 -I 585 ADD BUFOFF,4 INTO DATA BUFFER POINTER 00F8 8CI61400 =1 586 IIOV BUFSEG,55 OOFC C6060S0002 -I 587 HOV FUNC,02l! SET FUNCTION • FORMAT 0101 C7060COOOOOO =1 588 !10V MODIFY,OOOOn CLEAR MODIFIER (ALLOW ERROR RECOVERY -I ,589 AND INTERRUPT ON COMPLETION) 0107 E88DOO =1 590 CALT. G0220 START 1SBC 220 AND WAIT FOR DONE -I 591 (1lETURNS CARRY FLAG SET OR CLEAR) OIOA IF -I 592 FIITDN: POP DS RESTORE REGISTERS 010B 58 -I 593 POP AX 010C CAOAOO -I 594 RET 10 RETURN (AND POP INPUT DATA OFF STACK) -I 595 , -I 596 FlIT220 ENDP 597 , 598 +1 $INCLUDE(RDWRT.SRC) 599 +1 $EJECT TITLE(READ DATA ROUTINE) A·10 iSBC220 Appendix A LOC ORJ LItlE SOURCr. =1 600 ------=1 60 I =1 602 READ TlAT.~ =1 603 =1 604 ------=1 605 =1 606 Rll220 SETS UP 'fliP, I()r~ FOR A REA1l OP!':RATIO~J , AND =1 607 INVOKr.S T'IE iSIlr. no TO pr~~H'OR~! THE OPCR.HION. =1 60R =1 609 IUPUT DATA: =1 610 RP + II =) BYTF. r.OU~!T 'Ur.1I IIORll =1 1>11 llP + 9 =) nYTF. COln:T LOll ,JORn =1 612 81' + 7 =) DATA RlTl~FF:R ~EG·1r.~!T =1 613 UP + 5 =) DATA l1nFFI<:R OFFSET =1 614 81' + 4 =) Sr.CTOR =1 (,15 81' + 3 =) ImAll =1 filii 3P + =) CYLP~nr.R =1 617 HI' =) unT =1 61H =1 (>19 OUTPUT DATA: =1 620 CARRY FLAr. = n IF TRt\~Sl~r.1{ OCCUI~Rr.n '.II T H ~w OR "r.COVI';(AnT.F. RKRon =1 621 = I IF U;~Rr.COVJ:RAnLF. ERRor. OCCURRf: I) =1 622 nATA BUFFeR PrJ,LEO filTH \lATA FHO!I or 51: IF IHl UNRIlCOVEilAllLI, E.RROH =1 621 ------=1 624 =1 625 PUIIL re R0220 =1 6H ASSII:!r. DR:TopaST-:G =1 627 , OIOF =1 628 R0220 PROC FAR =1 629 OIOF 50 =1 630 PUSII AX <;AVE RE(:rST"P'S OllO IF. =1 631 PUSH Il~ o III BS---- R =1 632 :-fO\1 AX t tOPI\Sf.G GET P'lI'H>;R Tn lOPR 0114 8EOS =1 633 110V D5,Av.. Oll6 BAHOO =1 (,34 ~IOV AT.,! r.l'] GET rpnT PHO lOPR Oll9 A20AOO -I 635 1I0V U~nT,AT. OllC 8114601 =1 636 'IOV A)(,[BP+I] GET CY1.INPP.'{ I:ITO IOP!1 OIIF "'30EOO =1 637 :10 V CYLrTnr.,AX 0122 8B4603 -I 638 ~1nv AX,!~P+3] GET IlEAl) Ann 'lBCTnp.. 1'ITO I()P~ 0125 A31000 =1 639 :IOV \IDRTl PTR IIEAO,AX 0128 8114605 =1 640 HOV AX, [llP+51 r,wr OATA nIJFFp.R POI"T':R VITO [OrB 012l! A31200 -I 641 'lOV BUFon' ,AX o 12E 8B4607 -I 642 ~[Ov AX, [111'+7 J 0131 A3!401) =1 643 'IOV BlIFSI:G ,AX 0134 884609 -I 544 HOV AX,[1IP+9J CF.T BYTE COUllT rr;ro IOP~ 0137 A31600 =1 645 l\OV ~"ORf) I'TR Rl~0cNT,AX 013A 8B460B =1 646 rtOV AX, [HP+II J 013D A31800 =1 647 llOV llORD pTR RF.QCNT+2,AX 0140 C7060COOOOOO -I 648 nov ~\OOIFY, 000011 CLr.A;t 'WOIFIER (ENABLE I~TI;RRUPT ON =1 649 COtlPLF.TION AN]) RF.TRl':S) 0146 C60601l0004 =1 650 :IOV FUNC,0411 SET FUNCTION = READ DATA Ol4B E84900 =1 651 CALL G0220 ~'fART FUNCTION AND IIAIT FOR COIlPL F.T ION =1 652 (RETURNS CARRY FLAG SET OR CLEAR) 014E IF -I 653 POP os RESTOR!:: REGISTERS 014F 58 =1 654 POP AX 0150 CAODOO =1 655 RET 13 POP PARAIIF.TERS OFF STACK ANO RF.TIJR:I -I 656 =1 657 RD220 END I' -I 658 -I 659 +1 $EJRCT TITLF.(IIRITF. OATA ROUTINF.) A-ll Appendix A iSBC220 I.OC 08.1 LINE SOUlIGR ~I 660 sl ~H ------sl H2 IIRIT" nATA sl ()61 sl 664 -I 665 ------I 6(,6 1-1RT22 0 r,r.T~ UP Trlf- tn P 'l FOR A \~RITF. OPERATION, ANt> -I 667 INVOKES THE ifil\C 220 TO Pr.RFOR:1 THE OPE~ATI(H!o -I (,6R -I 669 INPUT IlATA: -I 670 BP + 11 -> llYTR COU)!T IIICH IIORD -I 671 liP + 9 -> BYTE COUNT \.Ol! \IORD -I 672 lH' + 7 -) nATA llUl'F1:R ~EC·.p::NT sl 673 liP + 5 =) DATA IlIlFl-'I':" OFFSET -I 674 Bl' + 4 =) Sf;CTOR =1 675 fiP + 3 =) , HEM -I 676 liP + 1 =) CY1.lnDER -I 677 qp =) UNIT -I 67R =1 r,7~ OAT" t\1JFFI: Jt CONTA1"J" TnFOR;fATIOM' TO HE lJR. 11'TEN Tn nISI: sl 6RO -I "RI OUTPIIT nATA: -I 6R2 CA.RRY nAC c n If TP,AN~FF.n OCClJRRr: I) '11TH 110 O~ Rr.COV"~AP.I.r. r.nROR -I 6Rl = 1 If ntmr.COVF;RI\~L~ f':n~np. OCCIIRRF,I) sl f)n.4 ------I ~R; -I 6R6 PUlIl.Ie lIRT220 -I 6R7 ASSIJIIF. 1)5: tnfi~~~l:r. -I 6HR , 0153 -I 6A9 lHtT?20 PlInc FhR -I 690 0153 50 -I 691 1'U:111 AV 5A\,I~ ."r.IQn:RS 0154 I~ -I ~92 ?USlf ns 0155 1\8---- R sl ~93 HOV A~'tIOpa~lo:c r.ET I.)n I '!Tl~ 1~ TO Ior~ 015ij 8ED8 -I 694 aov !)S •.'l.X Ol5A 8A4bOO -I ~q5 nov AL, [np] G"T UNIT I~TO IOPB 0150 A20AOO -I r,q~ 'IOV UiHT,AL 0160 8n46IJI -I 697 !!OV AX, [r,P+I] GoT CYLI~Ilr.H WTO IOPB 0163 A3MOO -I 698 'IOV CYI..Nn1t.A~ 0166 884603 -I 699 !IOV AX,[BI'+3] G,:T ;I P. All AlIIl f1eCTOr. INTO IOPR 0169 1\31000 -I 700 lIOV WOllfl l'TR IIP.AIl ,AX 016C RB4b05 -I 701 HOV AX, [RP+5] GET DATA RIlHER POUIT~:R INTO In PR Ol6F A31200 -I 702 lIOV RIIFOFF,AX 0172 8B4607 sl 703 nov AX, [RP+7] 0175 A31400 -I 704 ~OV RUFSr.r.,I\X 0178 8B4609 -I 70S HOV AX,[BP+9] GET 'lYTE COUtlT INTO IOPR 017B A31bOO -I 706 MOV HORO PTR ~P.QCNT,AX 017E 8114608 -I 707 ~OV AX, [81'+!1] OIRI AllROO -I 70R !lOV \lORfl PTR REQCIlT+2,AX 0184 C7060COOOOOO -I 709 "fOV !'-lO!lIF'Y • 0000'1 Cl.f:AR '100IF UR (ENARLF. I!ITERRUPT ON -I 710 COrtPLETION ANIl RP.TRI .. S) 018A C60601l0006 -I 711 'IOV FUNC,06H SET ,'IlIICTION lIRITP. nATA 018F E80S00 -I 712 CAJ.I. G0220 START iS8C 220- ANI) \IAIT FOR flO:IF. -I 713 (RETIJI\11S InTI! CARl\Y SET OR CLF.AR) 0192 IF -I 714 POP VS RRSTOll.P. RP.GISTERS 0193 58 -I 71, POP AX 0194 CAOflOO -1 716 RET 11 POP PARAllr.TF.RS On' STACY. AIIll RRTIlRN -I 717 , -I 71R WRT220 Em)p 719 720 +1 iINCLllnE(COREoSnC) -1 721 +1 $F.JECT TITLE(START FUIICTION ANfl (IAIT FOR COIfPLF.TION) A-12 iSBC220 Appendix A Loe OBJ LItlE ~()URCP' -I 722 -1 723 -I 724 START Ft:NCT[OIl ,"In !lAIT ~'()R CnrlPT.~TI A-13 Appendix A iSBC220 LOC OBJ LINe zI 759 -I 760 -I 761 WAIT FOR FUNCTION COHPLETE zl 762 -I 763 =1 764 -I 765 NOP~IAI.LY, TillS IIAIT ROUTINf: HOULTl TRAP TO TlIr. S¥STE:I OISI'i\Tcnr.R/ =1 706 SCHI:nllLEll. TO ALLO'I A~lOTIlER TASJ: TO r.Xr.CUE IiIlII.E T1\I: iSIlC 220 CO:IPLP.TEIl =1 767 ITS }<~UNC'rION'. IIOlJf.VF:R. FOr. T'llS E:·~A~IPJ~r.t T 11r: ROHTINF. SrlPLY I~Ar!.'s FOR =1 768 THE INTr.:R~UPT SEnVICE RflllTI'lE TO LOi\D :r'IF. OPERATION COHP1.r.TE STATUS -I 769 F~Ort Tl1E eln OPCllAT10I: STATIlS I'lTO T'IE DATA SEG!IF.NT. H' A~ ERROR =1 770 OCCtJRRF.l). T\.-IF: STATTJS 1<; AVAIT.ARLr. TlIF.H.F: FOR ~IJH5F.(pn:NT PR('P'::Ef;~I\'G T1Y =1 771 1\11 r.R.Or. "ANn1.ER. =1 772 =1 771 INPUT J)ATA: =1 774 OPER.ATION C{HIPLr.TF: C;T!\TU~ rRO~[ 7111: r.IP., C()[>Ir.:n tNTf) T!lS flAT.'\ sr.r.n;':NT =1 775 MY T~lE tNT~~~UPT ROUTIM~ =1 776 =1 777 OUTPUT OATA: -I 77R ()'PT:I!A,.t.,~! cmtPLr.T~ "YTF. CLI:AREO =1 779 c,\rpy PLAn = 0 IF riO f.~R()P. =1 7P:O = 1 IF ERRn~~ OCCURRl:i1 =1 7RI COPY OF (:rn np~RATln~r STAT!JS IN t'T.STqTS" IF ER~nR nCCURR~n =1 7 R2 =1 7RJ ( f)PEr.ATIfW CO![PT.F'.Tr: I\VT~: Arm "LSTSTs,n f\TIP. 1:1 ~:n:r.;f~:JT "DA"ASEG" =1 784 =1 7R5 =1 786 Al-lfiU:tI: DS: I)ATASEr. =1 787 , OIAA =1 7RR YAIT220 P90C NEAR -I 789 OIAA 50 =1 790 PUSI{ AX t;AVS lU=:GISTERS OIAR 53 =1 791 PUSH BY. OIAC IE =1 792 PU~H os OIAD 8B---- 11 =1 793 :!OV IiX,nt\TO\~EG nF.T POl'JTElt TO DATA SF.Gnr:NT OIBO SEOB -I 794 nov DS, BX 0lR2 BBFFFF =1 795 nov RX.-l INIT1ALI~H 1Nn~1 REnISTHR OlliS FB =1 79r. STI ~AKE SURE I~TE1~RIJPT CA~ G8T T'IRor)r,fl OI~6 F4 =1 797 liLT ***** WAIT FOR I~T~RRU!)T ***** 0lB7 43 =1 798 IIAITLP: INC HX GET I~J)HX FOR ~r:XT UrlIT OIBR 81E30300 =1 799 A'm RX,00031l 'tASK qPPP.R '!H'I'r; o lllC F607FF =1 800 T!,ST IlYT'! I'TR [llXl,OrFH npF.r.;\TtO~J CO'IPl..ETr: STATIJS "" nOli? =1 801 (SInN FLAG = .11 7 OF OP. STATUS, =1 R02 TEST INS!I. CLEARS CARRY FLAG) 018F 74F6 =1 803 J7. 11AITLV ST:\TIlS <> nOli (()!'E~AT10N CO:1PLETE)1 =1 804 NO--Cllr:CK NEXT lI"IT OICI 7906 =1 R05 1!AI't"PI YES--tRnoR "CCURR~I) nURI~G FlJ~CTIO~? =1 806 I,O--rJ':T'JRN InTH CARRY FLAG CT."AR OIC3 RA07 -I R07 uov AT., [~Xl YES--SAVR erR OP. qTATU~ IN "LSTSTS" OIC5 A2I800 -I 808 !IOV LSTc;1'S ,AT. OICR F9 =1 809 STC BET CARRY PLAn TO INJ)ICATE ERROR OIC9 C60700 ~I 810 WAITDN: uov BYTE ~TR [RX],OOH r.LCAR OPERATlON CO'lPLETr: BYTE OICC IF =1 81 I POP DS RESTORE RECISTERS OICD 5B -I 812 POP BX OICE 58 =1 813 POP AX OleF C3 =1 814 RET ReTURN -I 815 =1 816 IIAIT220 ENDP 817 , 818 +1 $INCLUOE(ERROR.SRC) =1 819 +1 $RJECT TITLE(ERROR DANDLER) A-14 iSBC220 Appendix A LOC OBJ LINE ~OlJRCr. =1 820 -I 821 -I 822 ERROR IIANDLER =1 823 =1 824 -I 825 =1 826 TillS ROUTINE IS SYSTEII DEPENDENT. IN TKIS EXAIlPLf., Tm: f.RROR INFO~ -I 827 'IATION PKO'I TlIE COIITROLI.f.R IS REAO PITO SOFTWAR~: RECISTIlRS IN DATASEG, =1 828 WllERt IT CAN BE EXAHINI:Il. 'lORE SOPIIISTICAn:1l SYSTf.llS HIGIlT LOG Till, = 1 829 ERRORS TO DETER"IN~ WilEN A TRACK IS COlac BAD, FOR EXMIPLE. -1 830 =1 811 - TIlB TRANSFeR STATUS FUNCTIon .nLL IIOT RETIlRN AI! I:RROR. =1 832 - TilE urnT NmtRER I:"J TIlE IOP]\ Il) NOT CHAt!GED, !10 THAT TUR OPERATION CortPLP.TF. =1 833 STAT'fS FOR TilE T'lAr!Sl'fH STATUS FUNCTtON llILt RE POSTI:Il AGAINST TilE SAll1: =1 834 UllIT AS CAUSED 'r'IE ERROR. -I 1315 =1 816 InpUT DATA: -I 837 CIR OPERATION STATUS It! "L::;T~TStl It! nATA gr.r.nENT =1 SlB =1 819 OllTPUT DATA: =1 R40 r:RROR STATl1fJ rHO'! (;(P1TROJ.Lf:n HI nATA C)EGHr:!!T =1 R41 erR OPRnATIO!1 STAT1JS t~ "LSTST~" I~ nATA ~E~\tEMT -I 842 CARRY I'J,,\G = 0 IP SOFT (RRCOVE~ABLf.) ERROR =1 ,Q43 = I IF liAR!) (U1IRRCOVF.RAP.LF.) 8RROR = I 841, =1 845 -I 84fi = I 847 0100 =1 848 ERHor. PROC ~! EAR =1 849 0100 50 =1 850 PI!S!f AX SAVE REGISTEP.S 0101 IF. =1 851 PU~1l IJ~ 0lD2 ns---- R =1 852 :IOV AX, IOPf.!H:C. Gf:T POINTER TO lorB 0105 REDS = I 853 IIOV n~; ,AX 0lD7 AI1200 =1 854 :IOV ,\X, BIJI'OF I' ~AVR lOPS DATA BUFFER POI~TER OIDA 50 = I 855 PUS I! AX OIDB AI1400 =1 856 HOV l\X, RUFSt:C: OIOE 50 =1 857 PHS'\ A" OIOF C70r,12000COO =1 q 5R :fOV SUFOPP,()FFSET EqRRTS GET POI.T~R TO nATA SEGnERT ERROR 01E5 C7061400--- R =1 8,Q ?WV HIJFSEC,OATASEG STATUS REGISTERS OIRB C6060BOOOI =1 860 HOV l'~UNC, nIH ~ET FUNCTI(}N = TRANS PER STATIJS 01FO C7060COOOOOO -1 861 'IOV :lODHY,OOOOn CLEAR 'I01JIFIER (ENARLE I'lTERRUPT ON = I 8fi2 conPLPTION AND RETRIES) OlF6 E89F.FF =1 Rfi1 r.AU, r.02:?O START PUNCTIO~ ANIl VAIT FOR CO~PLET~ 0lF9 58 =1 U,4 P~P AX "F.STORE IOPR nATA RUFFER POI1TCR OIFA A31400 = I· 865 flOV !HJFS~:G,"X 01 FD 58 =1 R66 par AX OIH A31200 =1 867 !toV UUFOH, AX 0201 B8---- R =1 868 ~lOV AX,DATAREr. CF.T POl'lTER TO DATA SF.GlIcllT 0204 BEDS =1 869 uov nS,AX 0206 F8 = I 870 CtC CLCAR CARRY FLAG 0207 A01800 =1 871 'JOV AI.,DS:LSTSTS GET OLD (ERROR) CIa OPERATION STATUS 020A 2440 =1 872 AND AL f 40H CHECK HARD ERROR BIT OZOC 7401 =1 873 JZ S FTF. RR liARD ERROR BIT SET? =1 874 NO--J,P.AVE CARRY FLAG CLF.A~ 020E F9 = I 875 STC YES--SET CARRY FLAG o 20F 1 F =1 876 SFTERR: POP DS RESTORE REGISTERS 0210 58 =1 877 POP AX 0211 C3 =1 878 RET -I 879 , =1 880 F.RROR ENIlP 881 882 +1 $INCLUDE(INTRPT.SRC) =1 883 +1 $EJRCT TITLF.(INTERRUPT SERVICE ROUTINE) A-15 Appendix A iSBC220 LaC OBJ LINE SOURCE ~I 884 =1 885 -I 886 INTF.RRUPT ~ERVICE RnUTINE -I 887 -I 888 -I 889 -I 890 THIS ROUTINE SERVICES TRE INT!.RUPT GENERATED BY TUE iSHC 220 UPON -I 891 OPERATION COflPLBTE, SEEK CO~IPLF-TE, OR DISK PACK CHANGE. IT COPIES THE =1 892 CIS OPERATION STATU~ InTO ONE OF FOUR BYTHS ASSOCIATED WITH EACU OF =1 893 THESE EVENTS. IT IS ASSUIIF-Il TIIAT SYSTEI·\ PROGRAIIS flAKF. USg OF THF. =1 894 INFORKATtON TO RlsunE TASKS, nANDLE ERROR LOGGING/RECOVERY, AND KEEP -I 895 TRACK OF IlIRECTORY INFOR1IATIOtl. FOR TnB PROGRAnllING EXA:lPLF., ONLY -1 896 TIIP. OPERATtON COHPLETF. RYTr:S ARE lISEn. =1 897 -I 898 - TIlE SYSTE,I INTI;RRUPTS ARE COIIFlGUREIl BY l~XTl:RIIAL PROr:RAIIS. =1 899 =1 900 ~I 901 PURI.Ie INT220 =1 902 , 0212 =1 903 INT22n PRnc FAR -I 904 0212 F]\ =1 905 5TI BrlAnl.r. nIr.nE~ PRIORITY UlT>;RRlIPTS 0213 50 =1 90~ PUSH AX SAVE Rr.r.tSTP.HS 0214 53 -I 907 PUSI1 BY. 0215 52 =1 908 PIlSH nx 0216 IE =1 909 'Pn~H DR =1 91n AS ~"!~1 r. as: r.IR~r:G 0217 B8---- R =1 911 'IOV A::JClnt;~:G GI:T POlrrTRll TO elR 021A SROS =1 912 nov lJ5,AX 021C AOOIOO =1 911 lIllV AL,OPSTt; GET CIB OPERATION STATUS 021F 8AOO -I 914 tlOV DL,AI. ~AV1: IT 0221 C60603000n =1 915 '10V STSSr.:I,OOH G1.EAR CI!\ ')T<\TIJS S~::IAPIlOnF. 0226 SADS -I 916 nov nL,AT. '1()V~ IT TO Irrnex RE(:IRT~R 0228 81EllOOO =1 917 Ann ~X,O()30H IIASK ALI. BITS I:XCF.PT UNIT SU1IREIl 022C OIE]\ -1 918 SHH !\X',l SIlIFT UNIT IlU:IIIER TO BITS 0 AND 1 0221': DlF.R =1 919 SllR RX,l 0230 0lE8 =1 920 ~llR RX,l 0232 OIER =1 921 SIlR fiX,1 0234 250600 =1 922 Aun A.X,nnn6H iiASl: AU. ~tTS EXCCPT SF.EK Cnrn'LE'fI, -I 923 Aim PACl: C IIANGB 0217 OlEO =1 924 sm. AX,I SHIFT I.CfT TO Gl:T OFFS(;T INTO PRO":11 -1 925 BYTE IN DATA SBGHEKT 0239 03DS =1 92(, ADO fiX,AX CD:I!IH!r. 'lIT II UNIT IN IH\)>;X REGIsn:R =1 927 A..~~1THF, nR: nATAS1~G 0238 88---- R =1 928 HOV AX,OATl\~EG 0231:: BEDS -I 92q 'IOV f}f).AX 0240 8A17 =1 Q30 ~~ov [gXj,% nov>; 01'E'<.ATION STATUS TO llATA SF.GIIf.NT 0242 8A5063 =1 931 !-10V OX ,'·/IIA*16 GET P()I'lT~R TO I/O IIAKF.-UP ADDRESS 0245 8002 =1 932 'IOV AJ.,0211 r.F.'f r.T~F.AR P~1'I~HP.IJPT COWfA~H) RYTC 0247 EY. =1 913 011T DX,AL 01JTPIJT TO i~RC 220 -1 934 0248 IF =1 935 POP 1)~ Rf,9TORF. Rr.GISTRRS 0249 SA =1 936 POP llX 024A 58 =1 937 POP nx 0248 FA -1 938 CLI DISABLE IUTF-RRUrTS FOR RESTORE =1 939 (RISTnRATIO~ OF IN:ERRUPT 1.0GIC STATE -I 940 IS SYST!II DEP':NDF.NT. THIS IlXAIiPLE IlS1,S =1 941 THE iRHC ~6/12A CPU.) 024C 8020 =1 942 !·10V AL,20H GCT EnD-O'-INTERRUPT crniliAND 024E E6CO =1 943 OUT DCOn, AI. OUTPUT EOI COlI!lAliD TO 8259 0250 58 =1 944 POP AX 0251 CF -1 945 IR1;T ~NTERRUPT RETURN ENABLES INT~RRUPTS -I 946 =1 947 iNT220 EN])P 948 , 949 S8C220DRIVER ENDS END OF iSHC 220 DRIVER CODE 950 , 951 +1 $TITLE(SYM80L TABLE AND CROSS REFERENCE) 952 953 END END OF PROGRAIIlIING EXAIIPJ.F. A-16 iSBC220 Appendix A XR~F SYnnOL TARLE LISTlnc NAIIE TYPF. VA!.!!r. ATTRI BUTES. XRF.FS ??SEC SF-GMENT SIZE-OOOOI! PARA PUHLIC ACTCNT. v TJIJORn 000411 IOPBSF.G 129# ACTCYL. v IIORD 001311 IlATASEG 2601/ ACTHD • V BYTE 001511 OATASEG 261# ACTSEC. V BYTE 001611 IlATASF.G 262# BSYFLGI V BYTE 000111 GCBSEG 79/1 459 BSYFLG2 V nyn: 000911 CCBSF.G R5# BUFOFF. v 1I0Rn 0012H IOP.S~G 1371 511 513 5R4 585 641 702 854 85H Hr.7 BUFSr.G. v IlOilO 001411 I(lpnSF.~ 13A#· 509 5H6 64] 704 R5fi 859 865 CCII •• i, FAR OOOOH CCHSRG 64 77' 402 403 CCBPTR. V OIlORD 000211 9C'SRG 64' 402 403 CCBSEG. SV,r.'IENT SIZR-OOIO" PARA 759 92 407 451 452 CCIH. v RYTr: 000011 CCR!)gC 7gf. 40r. CCII2 •• 11 l\YT~ noonll CCRf;"P.G ~4ll 411 CIII PC • L FAR 000411 Clq~~~ Rn lIne 409 41() 411 CHi PTR. I' T}IHlRn Ol)02H ~~qq~n R(lfl 40 Q 410 CI12PC • I. FI\n 000>:11 Cr.RSBr. n~ ~o# 412 4t1 414 CH2P1'P.. OliO?!) 000A1I ccn~~G R~# 412 411 CIR •• I." f'A~ ~OOOIl CJR~r.r: 105# crPoc,!o. v BYTE oooon CIH~F.r. 106!1 421 CIIISF.G. ~':r.'lP,f1T ~I~~=nnJnll PARA 101* It~ 41R 61q °10 ryl1 CLK!,P • tlEAr.. 007411 snC2~OD~IV~R 41~' 41q ClfDSr.~! • II" l~YT!~ nt')o 11{ Cln~F.r; 10R# 42'- CO~JFlr: • L F.\H (lOOO'1 11q~R~~r. PT'RLIC 12~ 12~# 344 CYl.Nn~. v IJORn 0001:11 Inr~~~G 114* SRI ~17 6qR DATA!H:r. .,~r.·1~NT SJZE=nOlA" PAPA 21~' 274 ~3() 411 7N~ 7"1 ~,q R~~ 027 92R nF.SCYL. v IJon]) OOOF'; llATASP.r. 257tl nF.SIIO • l\VTr.: (lOIIH nATASEG 2,)g·-1 nr.SSEC. "v nYTf. onl?~ f)AT;\r.;l:r. 2:;(1<1 nr.vr,oo. v uonn (lOOR'l Inp~Sf:G 11011 DOME •• L nF.AR 0lA7n ~~~220DRIVE~ 74A 752# ENIlOAT. F'A!l OOIAH l]ATA~RG 272' 413 ENDST~. "L FAR Ot14(Pl STACK 3151' 333 EP..ROR • L Nr.~R 01 no', SRC220nRlvRR 750 R4R# ~80 E1\RS1'5. v t~op..n OOOCII nATAS~G P{JBLI~ 226 255' !l~~ F'lT220. L FAR 00n(,H SBC220DRIVER PIJRLIC 56Q 572# ')y~ F~lT!lN L NrAR OIOAl! ~RC22nDRIVER 5q2~ FIlNC. v IlYTI: 0001l1[ [OPlsr.e 112# 506 SR7 650 711 R60 GOZ20 T. ~JEAH 0197\1 SB~22nnRIVRR 515 5~O fiSt 712 74(1~ 7Sh R~J '1EAl). V nYT": 001011 InrD~~~ 135# 51~3 63~ 7 f )O INI1'220 T. PAn OOAIII SBC220DRIVRR P"RI.[~ 497 SOOI 527 INITllLSEG SF.G~tr.~fT SI%£-002011 PARA I~RI 200 509 InTI)[i. T. NEAR 00n3l! S"C220n~IVER 517 521# HIlTL? I. t~r. AP. OOr.lll SSC~20nnrV~R 511# 521 INT220. L FAR 021?f! 6J1~2?nnRIVRP """LIe 116 337 rynl 90]# 947 INT~CS. V ~10'Rn (lO'l6H SEcoono 3031 317 INTIlIP. v '10~n OOQI,1I 'R~nnnn 1021 13fi INTRPT. f.rmtn":;;H 0005H 295* 300 rOPE •• T. FAR 000011 IOPRSCC lIZ 117' 424 425 IOPEOFF v IIORO OOOSH CI~r:F.(: 11~!' 424 IOPBSr.G ~cG:IF.NT SI~~=nnlRJl PAQA 111 12~# 142 4qfl 5114 570 576 62~ ~12 ~R7 693 R46 R~2 IOl'nSG. v IfORIl OOOAl! Clasr.~ 11.1# 425 LSTSTS. v BYTe OOIRH nATAS8G 2fiR# ~OH 871 nODIF\'. v 110Rn OOOC]l IOpnS~G 131' 507 snR ~4R 7r)9 R~l NllRTRY. v JlYTE (l017H nATI\f,l~G 261 Jt OPCllP • V BYTE OOOO'! nATASF.~ PUBLIC 2~6 210' OPC'lPO. V RYTf: 0000i! n ..\T"~J~~ 211 '1 OPCfIP I. V BYTE OOOIH llATASEr. 232!1" OPCtlP2. V llYTY. 0002l! nATA~F.r, 233# OPCllP 3. 11 BYTE 000311 OATASEG 23411 OPSTS • V BYT,: OOOIH CIlISEr. 10711 913 PKCHG • v BYTE OOORl! DATASRG PUBLIC 226 246' PKCIIGO. V BYTE 00081\ nATI',S,:G 247# PKCIIGI. V llYTE 0009l! OATASEG 24M PKCHG2. V IIYTE OOOAH OATASF.G 2498 PKCHG3. V BYTE OOOIlH DATASP.G 250# RD220 • I. FAR OIOFII SBC220DRIVER PUBLIC 625 fi2R# 657 REQCNT. V OliORD 001611 IOP1\SF.G 139# 645 647 706 70B RES220. I. FAR OOOOH SBC220DRIVRR PUBLIC 384 386# 473 REsnN • L NEAR 009BII SBC220DRIVF.R 461 466# RESLP • • • • L NEAR 0091H SBC220DRIVER 459# 463 SBC220nRlvER. SEGMENT SrZF.~0252H PARA 348# 350 949 SCB •• L FAR OOOOH SCBSEG 6!# SCBSEG. SEGMENT SIZE-000611 PARA ABS 59# 66 ]98 399 SECTOR. V IIYTE 001111 IOPRSEG 136# SEGOOOO SEGMENT SIZE-0098H PARA ADS 2970 305 326 A-17 Appendix A iSBC220 NAME TYPE VALUE ATTRIBUTES, XRF.FS SFERST. V BYTE OOOEII OATASf:G 2~6H SFTERR. L NEAR 020Fll 5nC2200RIVER 873 876# 5KCMP v BYTE 00041l OATASEG PURLle 220 23R~ SKC~IPO • ·V llyn: O(If}4H IlATA5EG 239# SKCMP 1. V RYTE 000511 DATASEG 240# SKCMP2. V BYTE 000611 DATASEG 24H SKCMP3. V RYTE 0007" DATASEG 242# SOC V RYTE 000011 SC1l5EG 62H 401 STACK SEGMENT SIZf.~0040!I PARA 5TSSEII. V BYTE 000311 ClBSEG 109# 915 UNIT. . V IlYT·E OOOA" IOPBSEG 131# 514 579 635 696 USERSEG SEGMENT 517.E=002211 PARA 3230 346 WAIT220 L NEAR OIAAH SBC220DRIVER 747 788# 816 WAlTDN. L NEAR 0lC9H SBC220DRlVER 805 810# WAlTLP. L NEAR 01B7" SBC220DRIVER 798# 803 WRT220. L FAR 0153H SUC220DRIVER PUBLIC 686 689# 718 WUA . . NUMIlER 063511 ~7# 59 444 744 931 ASSEMBLY COMPLETE, NO ERRORS FOUND A-18 I .~ ...... J ...... -. , 8 I 7 I 6 I S 4 I 3 'I ,_ 16:J33 1"71 (')1 .... K " ...... -- -...... J' r ~ -.:... E'~~·OO~E. r-....Cil or;.· ....~E -.""'." , ...... ,.J ... lU;" 0 LC.O \4-011::- .j\,.,:. ,-,(,...- I-u·ia - j."~ ~ C. I.-Ol~" u:.o h~~ :!::~-...... ~ ID teo 1,,"-O25~ 'l,::" '. . I.·.· .. ••·K_ .. D D -fSV ';1~.;:=: I c~ t t C&.lo,I2-'~,Y.I I :~ + "'~ "'~ " a3~ A' JI +5V I!H ~ 41- +::XNTF'C. ENeL -sv ~'tf!N ~ rfJfjJ.,~ "210 I-- - -sv ~h R~ ~/{1V 'NS -H1V ::h m.o !f' .,... J5V 2.71< : -12V -f '>HI -' I VRI J!-i2. 30. sit' 7905'1' -12V :h :1 C:~ I I ~ 1! "e&l ! C9.q,~ ~. CAL GND P)~ +1 ~t r~" ~ "1+ 1':1 ..,0R" ~ " INS2.!}68 '=' ~ c ~t= C RIO IU , ' , 1:.80 II< 76 ~E .. ~~ GND ..... R5 QI 2.71(.· ':' I a:- ~N.3'tHR6 JI I ,4 ':I:N'TFC. ENBL 27# 3C1 PUP RI? ,...... f ~ I I ~&GRO LOCATOR CHART IO~ JI I~ '2 REF R:N.IER PINS .. ~2' PlC,Y-/ DESIG GND .. S V7"1Ob -s, .'. ":" ' R3 ~--" i.J!HO,I1.IS.l4,~ 8 IZ. 13~ 12 2.2.\\ I" -tSV 1 .~,59 '3E~ DISABLE/ U 3-6." 16 is , I UIZ,13,17, Ie. ~'3I."'" q""" '" I-- I 10.12-'19, 5e..~'-Z.~ lit-,. 1O • f-- f>&-75,87.98·10, r 1.7"7106 , U 1,2,7',19. 20, :lo2.3~.S~S> !G, D PA.T-F/ O"T-E/ T»..T-D/ sw-~ DAT-...,D"T:fJ S~AI Dt.T-A/ .sW-S'1 J)l'.T-SY .S~81 bAT-l?y' c c , 5WF/ 17 ·5W-~ t:lA-T-DA..-7!~l '\ SW-G flA..T-5/ DAi-A/l "6 D"T-~ sw- PAT-2/ i ,?; OAT-I/ ! DIIT-~/ I ~53~hA&--+------+~1'"'93Y, >--- /DAT-F/l-{OAT-¢/J "f8S: I --- I OAT-7/ D.4T-6/ OAT-51 DAHl DAT-3/ p"-',-2/ pi'\i-I! 1_---'S~W:!:~:.rL(J/__!:/3"_1 DE ~ DAT~/ 1'"19'1' WAKE upl 3f3 e, 5D6 I. 81T sv~ 8U!>j 506 A A Iowcl !iel IAOR-t// Se.1 rAOR-t/ 5(:.1 GATE SW'S/ ...... • 'I 6 5 4 3 , D D "IAI LOCK/ 1J8!l . u86 "2e~ 8288 ....., S Ie sl/I"- 12 I-AIOWC/ ~I 19;. so s~ AIOItC 588, b/>a 4AI S Sf 5fF ~ SI AMWC 'I I 13 S21/fJ. 'lAI .s 2/ 16: 52 A£N S2 rowe P:1. pj. LOCI( MWrc ~ 20 MWTr:./ s 7 BCLK/ 13"- BeLl< 8REQ .7 MROC 19 NADel BPRN/ 1..2 9 ePRN ePRO 8 rORC 13 ,. Ilf :~.3 !5Bet bAS "IbB INIT/ 14"'- INfT +5'1 INTA :::r:-:IORC! CBRQ/ ..... 12; CBRQ 'I Busyl '7 eU!3Y I.Cl./( CTr/P. or/R '1A!!!> "4- REse 6 AEN ALE 5 ALE RI" 17 'f8",588 IOB II<. f!J aN POCN POEN/ W2~i~ L;i . 16 "AB ,,, CRQLCK I IOB OEN DEN BOB ANYRQ5T f "IDI 5MH2a.J( 17 CLI( ,! C '.' syse PUP R~ 113~ C ! A£N/ 'lC6,5D8 XI l'i- IB 8R£Q/ IG BPRO/ reI PUP R21 - P/- 6(;.1 BOAT-B 70 ).36 INT 7/ 60 !SAl woc/fl/ 50 .35).38 5 6 "'., 1./0 ).37 ~"II Co I .tIDI PWRRST/ 7400 30 )4Jf 20 ) .39 11 .(/3' 7'1L5139 10 ) '12 II (110 ) "It:rt-lT ¢/ aM WAK£IIP/ G CNTL.R RSi/ '/D8 8 • ~Ae. DAT-~/ .. A ~M DAr-II· S C1/NLATTN I/~ i sel ROC~/ I I A ~ Rli Ra' ...... 1 ISEE ~IEET I j '" --- '~K 11\ I; 10- '>01 CNTI-R R5ill ~_2 .....I 8 7 6 5 ~ 4 3 I ,...... Ie.203.3 ,.~ l"g I I I I I oms, .... 21Y.:1-.5 ...... on ...... IADR-A !S .... SEE SHEET 1 - 1'-- A "-.J I IT - :IADR-' A !~ii- :rAPR-8 2 If I IAbR-7 ~ A I J:ADR-6 I ., IOAT -f: 1 . A Itf> 1/ 13 IOAT.-E , D ~~DR-5 If I/O D 7 /2. 1eAT -0 ..:IAOR-" If ItO i ;lADR-!J ,., I A " 1DAT-C .::t"'I>R-2 1tb ! "A' (:I.T;IU"-F)-(I.[)fI;T-8) , ~ If :IAPR-I I. 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