Isbc 220™ SMD DISK CONTROLLER HARDWARE REFERENCE MANUAL
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iSBC 220™ SMD DISK CONTROLLER HARDWARE REFERENCE MANUAL Manual Order Number: 121597-001, REV A Copyright © 1980 Intel Corporation I Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051 I Additional copies of this manual or other Intel literature may be obtained from: Literature Department Intel Corporation 3065 Bowers Avenue Santa Clara, CA 95051 The information in this document is subject to change without notice. Intel Corporation makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Intel Corporation assumes no responsibility for any errors that may appear in this document. Intel Corporation makes no commitment to update nor to keep current the information contained in this document. Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subject to restrictions stated in Intel's software license, or as defined in ASPR 7-104.9(a)(9). No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Intel Corporation. The following are trademarks of Intel Corporation and its affiliates and may be used only to identify Intel products: BXP Intel Megachassis CREDIT Intelevision Micromap i Intellec Multibus ICE iRMX Multimodule iCS iSBC PROMPT im iSBX Promware Insite Library Manager RMXlBO Intel MCS System 2000 UPI pScope and the combination of ICE, iCS, iRMX, iSBC, iSBX, MCS, or RMX and a numerical suffix. ii CONTENTS CHAPTER 1 Page Page GENERAL INFORMATION Interrupts ...................................... 3·20 Introduction 1·1 Example Controller I/O Program .............. 3·20 Description .................................... 1·1 Specifications .................................. 1·2 CHAPTER 4 PRINCIPLES OF OPERATION Introduction .................................... 4·1 CHAPTER 2 Schematic Interpretation ........................ 4·1 PREPARATION FOR USE Functional Overview ............................ 4·1 Introduction .................................... 2·1 Detailed Functional Description . .. 4·5 Unpacking and Inspection ...................... 2·1 Controller to Host Communications ............. 4·5 Board Installation Considerations .............. 2·1 Multibus Interface .............................. 4·6 Power Requirement ........................... 2·1 8089 I/O Processor (lOP) ....................... 4·6 Cooling Requirement ......................... 2·2 Clock Circuit ................................... 4·6 Multibus Connector ............................. 2·2 Bus Arbiter ..................................... 4·6 Switch/Jumper Configurations ................. 2·6 Bus Controller Logic ............................ 4·6 Wake· U p Address Selection ................... 2·6 Multibus Interface Wake·Up I/O Port Address Selection ......... 2·6 Data Transfer Logic ........................ 4·8 System Data Bus Selection ................... 2·7 Controller Initialization ......................... 4·8 Interrupt Priority Level ....................... 2·7 Wake-Up Address Comparator .................. 4·8 Any Request Selection ........................ 2·7 Controller Reset and Clear ................... 4·9 Voltage Selection ............................. 2· 7 Establishing A Linlv With Drive Interface ................................. 2·7 I/O Communications Blocks ................ 4·9 Cabling Requirements .......................... 2·7 Interrupt Priority Logic ........................ 4·11 Drive Pin Assignments ....................... 2·7 Local Memory Map ............................ 4·11 Single Drive Installations . .. 2·7 ROM .......................................... 4·11 Multiple Drive Installations .................... 2·7 RAM .......................................... 4·11 Power Up/Down Considerations ................ 2·9 Local Memory Mapped I/O Ports .............. 4·11 Diagnostic Check ............................... 2·9 Controller to Disk Drive Communications ..... 4·12 Controller to Disk Drive Interface ............. 4·12 CHAPTER 3 Control Cable Signals ......................... 4·12 PROGRAMMING INFORMATION Selection Lines ........ .. 4·12 Introduction .................................... 3·1 Function Tags and Bus·Out Lines ........... 4·13 Disk Organization .............................. 3·1 Status lines .................................. 4·15 Track Sectoring Format ........................ 3·2 Read/Write Cable Signals ..................... 4·16 Controller I/O Communications Blocks ......... 3·2 Controller to Disk Drive Interface Timing ..... 4·16 Host CPU·Controller·Disk Drive Interaction .... 3·3 DMA Mode .................................. 4·17 Wake·Up I/O Port .............................. 3·3 Disk Formatting ............................. 4·18 Wake·Up Block ................................. 3·4 Write Data Transfer ......................... 4·19 Channel Control Block ......................... 3·4 Read Data Transfers .... .. 4·20 Controller Invocation Block ..................... 3·4 SER/DES Logic ............................... 4·20 I/O Parameter Block ........................... 3·4 Sync Byte Comparator Logic ................ 4·21 Typical Controller Operations ................... 3·5 32·Bit ID Comparator Logic ................... 4·21 Initializing the Controller ..................... 3·5 ECC Generator Logic .......................... 4·22 Track Formatting ............................ 3·10 Status Register Logic .......................... 4·22 Alternate and Defective Track Handling ..... 3·10 Line Drivers and Receivers .................... 4·22 Data Transfer and Verification .............. 3·10 CHAPTER 5 Read Sector ID .............................. 3·12 SERVICE INFORMATION Read Data ................................... 3·12 Introduction .................................... 5·1 Read Data Into Controller Buffer and Verify 3·14 Service Diagrams ............................... 5·1 Write Data . .. 3·15 Service and Repair Assistance .................. 5·1 Write Data from Controller Buffer to Disk '" 3·15 Self Diagnostic ................................. 5·1 Initiate Track Seek .......................... 3·16 Replaceable Components ........................ 5-1 Buffer I/O ............ '....................... 3·16 Diagnostic ................................... 3·17 APPENDIX A Posting Status ................................. 3·18 EXAMPLE HOST PROCESSOR Transfer Error Status .......................... 3·19 DISK CONTROL PROGRAM iii TABLESi Table Title Page Table Title Page 1-1. Board Specifications ................... 1-2 3-2. Error Status Buffer ............ .. .. 3-20 1-2. Drive Characteristics (Typical) ......... 1-3 3-3. Bit Functions in Hard 2-1. Multibus Connector PI Pin Assignment 2-2 and Soft Error Bytes ................ 3-21 2-2. iSBC 220 Controller/Multibus 4-1. 8089 Status Line Decodes .............. 4-8 Interface Signal Descriptions ......... 2-3 4-2. Host Wake-Up Commands ............. 4-9 2-3. iSBC 220 Controller/Multibus 4-3. Local 110 Ports ....................... 4-12 Interface Signal Characteristics ...... 2-3 4-4. Function Tag/Bus-Out Definitions .... 4-13 2-4. Configuration Linkages and Switches .. 2-6 4-5. Control Tag' and Bus Out Functions .. 4-14 2-5. Interrupt Priority Level Selection .,.... 2-9 4-6. Status Line Definitions ............... 4-15 2-6. Control Cable Signal/Pin List ......... 2-9 4-7. Status Register Bits ................... 4-22 2-7. Read/Write Cable Signal/Pin List ..... 2-9 5-1. Code for Manufacturers ................ 5-2 3-1. Data Block Length vs. 5-2. Controller Board Electrical Parts List .. 5-2 Sectors Per Track .................... 3-1 ILLUSTRATIONS Figure Title Page Figure Title Page 1-1. Typical Multiple Drive System ......... 1-1 3-14. Write Data ............................ 3-15 2-1. Serial Priority Resolution . .. 2-1 3-15. Write Data from Controller Buffer 2-2. iSBC 220 Controller/Multibus to Disk .............................. 3-16 Interface Signal Timing .............. 2-4 3-16. Initiate Track Seek .................... 3-17 2-3. Location of Jumpers and Switches 3-17. Buffer 110 ............................ 3-18 on Controller Board .................. 2-6 3-18. Diagnostic ........................... 3-19 2-4. Interconnecting Cable Requirements ... 2-8 3-19. Transfer Error Status ................ 3-20 2-5. Pertec Drive Interconnecting 4-1. Logic Conventions .................... 4-1 Cable Requirements ................. 2-17 4-2. Simplified Block Diagram 2-6. Priam Drive Interconnecting of iSBC 220 Controller .............. 4-2 Cable Requirements ................. 2-19 4-3. iSBC 220™ Controller Functional 2-7. ,Controller to Drive Interfacing ........ 2-22 Block Diagram ....................... 4-3 2-8. Installing the iSBX 218 Board 4-4. Bus Arbitor and Bus Controller Logic 4-7 on the iSBC 215 Controller Board ... 2-25 4-5. Data Transmission Between Multibus 3-1. Disk Drive Organization and Interface and Controller Multibus Terminology ........................... 3-1 Data Transceivers .................... 4-9 3-2. Sector Data Format .................... 3-2 4-6. Wake-Up Address Logic ............... 4-10 3-3. Host CPU-Disk Controller- 4-7. Address Fetches in Interaction Through the Initialization Sequence .............. 4-10 110 Communications Blocks ......... 3-3 4-8. Local