DOCSLIB.ORG

Illiac Programming

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Illiac Programming t^^J^^m^,#' ^ . • V L I E) R_ARY OF THE UN IVER5ITY Of ILLl NOIS 6(0-84 -mtStOS: The person charging this material is re- sponsible for its return on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University, University of Illinois Library AyS2 6 1<68 NOV 2 5 m NOV 9 1ii95 OCT 0CT2 4199(> L161—O-1096 Digitized by the Internet Archive in 2011 with funding from University of Illinois Urbana-Champaign http://www.archive.org/details/illiacprogramnninOOuniv DIGITAL COMPUTER LABORATORY GRADUATE COLLEGE UNIVERSITY OF ILLINOIS ILLIAC PROGRAMMING A Guide to the Preparation of Problems ^ for Solution by the University of Illinois Digital Computer -0 URBANA, ILLINOIS March 1, 19 5^)- PREFACE The Digital Computer Laboratory of the University of Illinois has a three-fold program which is concerned with re- search in the field of digital computers, with maintenance for University use of a high-speed digital computer, and with teaching of design and use of digital computers. The preparation of pro- grams for the Illiac is the responsibility of the person who wishes 3 his problem solved. But since each prospective user cannot always in at a attend the courses on programming offered by the University, it r ^ has seemed desirable to help make it possible for him to learn a: the elements of Illiac use by himself. The result has been this book, which makes use of a year's experience in operating the Illiac for University research and several years experience in the teaching of programming. Many of the chapters were used in preliminary form as supplementary material in Mathematics 3^5, the basic course on programming. The book, like most of the work of the Digital Computer Laboratory, is the result of a group effort by many different people, The chapters were written by S. Gill, R. E. Meagher, D. E. Muller, J. P. Nash, J. E. Robertson, T. Shapin and D. J. Wheeler. Other members of the laboratory staff read the material and offered K valuable criticism. The typewritten copy was prepared by Natalie R. House and Caroline M. Brown; the drawings were made by George Ehrlich. Ill 1^ WKi i l'illHrKMlflHi'1'liii I- LU a. o UJ < LU a. LU < irraiTTit^a^n CONTENTS PREFACE iii PHOTOGRAPHS iv Chapter 1. INTRODUCTION 1-1 2. THE ARITHMETIC . Chapter OF THE ILLIAC , 2-1 2.1 Representation of Numbers 2-1 2.2 Fundamental Operations of the Illiac Arithmetic Unit 2-3 2.3 The Illiac Arithmetic Unit 2-5 2.k Additions 2-5 2.5 Subtractions 2-6 2.6 Absolute Value Addition and Subtraction. 2-7 2.7 Increment Add Orders 2-8 2.8 Add from Q and Increment Add from Q. 2-8 2.9 The Shift Orders 2-9 2.10 Multiplication 2-11 2.11 Division, 2-12 2.12 Precise Calculation of the Division Remainder 2-15 2.13 The Division Hangup. Special Cases of Division 2-l6 2.1U Memory to Q and Store Instructions , , . 2-17 2.15 Illustrative Examples 2-17 2.16 Integer Operations 2-20 Vlll 2.17 Summary 2-21 Chapter 3. THE ORDER CODE 3-1 3.1 The Makeup of Orders 3-1 3.2 Execution of Orders 3-^ 3.3 Stop Orders 3-6 S.k Order Types 3-6 3.5 Order Variants 3-8 Left Shift 3-12 Right Shift 3-13 Unconditional Control Transfer ...... 3-1^ Conditional Control Transfer 3-I6 Store 3-17 Memory to Q 3-I8 Divide 3-I9 Multiply 3-20 Input-Output 3-21 Special Input-Ouput 3-23 Increment Add from Q 3-25 Add from Q 3_26 Extract 3-27 Increment Add 3-28 Add 3-29 Abbreviated Order List 3-30 IX '\\VX\V»Hi Chapter k. ROUTIKBS k-1 ij-.l Closed Subroutines k-2 k,2 Entering a Closed Subroutine k-^ U.3 Returning Control to the Master Routine . U-3 k-.h Placing the Argument k-'^ ^•5 Program Parameters ^-7 h-.6 Interpretive Routines U-9 ^•7 Preset Parameters U-11 Chapter 5. THE DECIMAL ORDER INPUT 5-1 5.1 Relative and Fixed Addresses 5-2 5.2 Directives. 5-U 5.3 Assembling of Orders 5-^ 5.^ Decimal Addresses ....... 5-5 5.5 Starting the Program. 5-6 5.6 Input of Decimal Fractions 5-6 5.7 Pre-set Parameters. Modification of Orders. ........... 5-7 5.8 Example of Use of Decimal Order Input . 5-8 5.9 Use with Interludes. Retained Directive. 5-11 5.10 Stopping the Tape. 5-12 5.11 Placing the Decimal Order Input 5-12 Chapter 6. SCALING 6-1 6.1 Scaling by Shifting 6-1 6.2 Numbers with Binary Point Shifted 6-1 6.3 Scaling a Full Problem 6-5 6.1^ Adjustable Scaling Factors 6-10 6.5 Continuous Scaling. Floating Point Routines. 6-10 Chapter 7- MACHINE METHODS AND CODING TRICKS 7-1 7.1 The Summation of Products 7-I 7.2 Reversing the Control Transfer 7-3 7-3 Binary Switches 'J-k 7.i^ Tests for and -1 7-6 7.i^ Use of Orders and Addresses as Constants. 7-7 7.6 Resetting and Starting of Cycles of Orders. 7-8 7.7 Use of the Quotient Register for Inter- changes 7-II 7.8 Testing if Numbers are Greater than One- Half 7-11 7.9 Convergence Criteria 7-12 7.10 Marking 7-13 7.11 Remainder in Integer Division f-lk 7.12 Binary Chopping , . , 7-15 7.13 Evaluation of Polynomials 7-I6 7.1^ Shifting A Left Without Shifting Q 7- 17 XI Chapter 8, CHECKING METHODS. 8-1 8.1 Common Blunders ............. 8-1 8.2 The Discovery of Errors ......... 8-2 8.3 Sources of Information. ......... 8-U 8.li Modifications to Programs ........ 8-5 8.5 Blocking Orders. ..... ....... 8-6 Types of Checking Routines. ....... 8-7 8-8 8 • 7 Post Mortem Routines .... ...... 8 .8 Post Mortem Version of the Decimal Order Input ............... 8-9 8 .9 The Address Search Routine. ....... 8-11 8 .10 Sequence Checking Codes. ....... 8-11 8 .11 Control Transfer Check. ......... 8-12 8 .12 The Check Point Routine ......... 8-12 8 .13 Conclusion. ......... 8-13 Chapter 9. TAPE PREPARATION , ............. 9-1 9. 1 The Tlliac Input. ............. 9-1 9. 2 The Illiac Output .............. 9-1 9. 3 The Perforated Tape. Sexadecimal Tape Code Characters ................. 9-1 9. k Classification of Operations. ....... 9-7 9. 5 Description of Equipment. .,......„ 9-7 9. 6 General Remarks ..... ......... 9-16 Xll Chapter 10. CALCULATION OF RUITOTWG TIME. 10-1 10.1 Order Times . 10-1 10.2 Example of Running Time Calculation. 10-2 10.3 A Simple Running Time Formula 10-i; Chapter 11. PREPARATION OF A COMPLETE PROGRAM . , 11-1 11.1 General Statement of the Problem .... 11-1 11.2 Trajectory Equations .......... 11-5 11.3 Processing of Equations for Solutions by the Illiac ..... .......... 11-8 11. J^ Scaling of the Quantities for Illiac Solution. , 11 -10 11.5 Coding of the Problem. ........... 11 -15 11.6 Checking the Program 11 -36 11.7 Conclusion ................. 11 -38 Chapter 12. TEE CATHODE RAY TUBE DISPLAY ........ 12-1 12.1 General Description ..... ....... 12-•1 12.2 Orders Controlling the Cathode Ray Tube Display. .................. 12- 3 12.3 Programming for the Cathode Ray Tube Display. 12- 5 Chapter 13. THE PROGRAM LIBRARY . ............ 13- 1 li^. Chapter DEFINITION OF TERMS. ........ lk~ 1 Index Xlll . CHAPTER 1 INTRODUCTION In 19^8 the University of Illinois "began to look into the possibility of acquiring an automatic digital computer. When attempts to buy one or to have one built failed, the University decided to build one of its own, and the Digital Computer Laboratory was organized in February 19^9- Shortly thereafter an agreement was made to build a second computer for the Army to be used at the Aberdeen Proving Ground It was decided to build the two machines following the de- sign of a computer then being designed and built at the Institute for Advanced Study. While many modifications were later made, both machines built by the University owe much to the early designs ob- tained from Princeton. The two ma-chines were built more or less together so that advantage could be taken of the savings obtainable by paralleling the design and construction work, but work on the Army machine, called the ORDVAC, was emphasized, and it was finished first. It passed its acceptance tests in February 1952 at Aberdeen and i,t has been in use there since that time. Work on the University computer (later named the Illiac) was completed in September 1952 and the computer was first made available for University use when classes began on Monday, September 22, 1952. 1-1 . The Illiac is an automEtic elect3ronic digital cou^juter. It is digital because it h:^r""-- -.v.rrfrs ss sexs cf digits which have discrete values, rather than as scale reading or measure- ments, which are contir i'aTia'ble. Apparatus for handling digits is :i'-" - ---li rrTff. ""r.T. t'::'" frr "-.".r.ilir.g rr-tlr.urus quantities, but it is capable of giving urlini-fi. accuracy by using suitable numbers of digits The Illiac is electronic. In the last ten years electronic circuits for storing, transmitting, adding, subtracting, multiplying and dividing numbers in digital f :rt: at extremely high speeds have been devised. The actual addition cf tvc nonhers in the Illiac takes only accut Such speed is useless unless the machine can be made to go ahead cr.
Load more

Recommended publications
  • Early Stored Program Computers
    Stored Program Computers Thomas J. Bergin Computing History Museum American University 7/9/2012 1 Early Thoughts about Stored Programming • January 1944 Moore School team thinks of better ways to do things; leverages delay line memories from War research • September 1944 John von Neumann visits project – Goldstine’s meeting at Aberdeen Train Station • October 1944 Army extends the ENIAC contract research on EDVAC stored-program concept • Spring 1945 ENIAC working well • June 1945 First Draft of a Report on the EDVAC 7/9/2012 2 First Draft Report (June 1945) • John von Neumann prepares (?) a report on the EDVAC which identifies how the machine could be programmed (unfinished very rough draft) – academic: publish for the good of science – engineers: patents, patents, patents • von Neumann never repudiates the myth that he wrote it; most members of the ENIAC team contribute ideas; Goldstine note about “bashing” summer7/9/2012 letters together 3 • 1.0 Definitions – The considerations which follow deal with the structure of a very high speed automatic digital computing system, and in particular with its logical control…. – The instructions which govern this operation must be given to the device in absolutely exhaustive detail. They include all numerical information which is required to solve the problem…. – Once these instructions are given to the device, it must be be able to carry them out completely and without any need for further intelligent human intervention…. • 2.0 Main Subdivision of the System – First: since the device is a computor, it will have to perform the elementary operations of arithmetics…. – Second: the logical control of the device is the proper sequencing of its operations (by…a control organ.
    [Show full text]
  • Computer Development at the National Bureau of Standards
    Computer Development at the National Bureau of Standards The first fully operational stored-program electronic individual computations could be performed at elec- computer in the United States was built at the National tronic speed, but the instructions (the program) that Bureau of Standards. The Standards Electronic drove these computations could not be modified and Automatic Computer (SEAC) [1] (Fig. 1.) began useful sequenced at the same electronic speed as the computa- computation in May 1950. The stored program was held tions. Other early computers in academia, government, in the machine’s internal memory where the machine and industry, such as Edvac, Ordvac, Illiac I, the Von itself could modify it for successive stages of a compu- Neumann IAS computer, and the IBM 701, would not tation. This made a dramatic increase in the power of begin productive operation until 1952. programming. In 1947, the U.S. Bureau of the Census, in coopera- Although originally intended as an “interim” com- tion with the Departments of the Army and Air Force, puter, SEAC had a productive life of 14 years, with a decided to contract with Eckert and Mauchly, who had profound effect on all U.S. Government computing, the developed the ENIAC, to create a computer that extension of the use of computers into previously would have an internally stored program which unknown applications, and the further development of could be run at electronic speeds. Because of a demon- computing machines in industry and academia. strated competence in designing electronic components, In earlier developments, the possibility of doing the National Bureau of Standards was asked to be electronic computation had been demonstrated by technical monitor of the contract that was issued, Atanasoff at Iowa State University in 1937.
    [Show full text]
  • P the Pioneers and Their Computers
    The Videotape Sources: The Pioneers and their Computers • Lectures at The Compp,uter Museum, Marlboro, MA, September 1979-1983 • Goal: Capture data at the source • The first 4: Atanasoff (ABC), Zuse, Hopper (IBM/Harvard), Grosch (IBM), Stibitz (BTL) • Flowers (Colossus) • ENIAC: Eckert, Mauchley, Burks • Wilkes (EDSAC … LEO), Edwards (Manchester), Wilkinson (NPL ACE), Huskey (SWAC), Rajchman (IAS), Forrester (MIT) What did it feel like then? • What were th e comput ers? • Why did their inventors build them? • What materials (technology) did they build from? • What were their speed and memory size specs? • How did they work? • How were they used or programmed? • What were they used for? • What did each contribute to future computing? • What were the by-products? and alumni/ae? The “classic” five boxes of a stored ppgrogram dig ital comp uter Memory M Central Input Output Control I O CC Central Arithmetic CA How was programming done before programming languages and O/Ss? • ENIAC was programmed by routing control pulse cables f ormi ng th e “ program count er” • Clippinger and von Neumann made “function codes” for the tables of ENIAC • Kilburn at Manchester ran the first 17 word program • Wilkes, Wheeler, and Gill wrote the first book on programmiidbBbbIiSiing, reprinted by Babbage Institute Series • Parallel versus Serial • Pre-programming languages and operating systems • Big idea: compatibility for program investment – EDSAC was transferred to Leo – The IAS Computers built at Universities Time Line of First Computers Year 1935 1940 1945 1950 1955 ••••• BTL ---------o o o o Zuse ----------------o Atanasoff ------------------o IBM ASCC,SSEC ------------o-----------o >CPC ENIAC ?--------------o EDVAC s------------------o UNIVAC I IAS --?s------------o Colossus -------?---?----o Manchester ?--------o ?>Ferranti EDSAC ?-----------o ?>Leo ACE ?--------------o ?>DEUCE Whirl wi nd SEAC & SWAC ENIAC Project Time Line & Descendants IBM 701, Philco S2000, ERA..
    [Show full text]
  • SIMD1 Ñ Illiac IV
    Illiac IV History Illiac IV n First massively parallel computer ● SIMD (duplicate the PE, not the CU) ● First large system with semiconductor- based primary memory n Three earlier designs (vacuum tubes and transistors) culminating in the Illiac IV design, all at the University of Illinois ● Logical organization similar to the Solomon (prototyped by Westinghouse) ● Sponsored by DARPA, built by various companies, assembled by Burroughs ● Plan was for 256 PEs, in 4 quadrants of 64 PEs, but only one quadrant was built ● Used at NASA Ames Research Center in mid-1970s 1 Fall 2001, Lecture SIMD1 2 Fall 2001, Lecture SIMD1 Illiac IV Architectural Overview Programming Issues n One CU (control unit), n Consider the following FORTRAN code: 64 64-bit PEs (processing elements), DO 10 I = 1, 64 each PE has a PEM (PE memory) 10 A(I) = B(I) + C(I) ● Put A(1), B(1), C(1) on PU 1, etc. n CU operates on scalars, PEs on vector- n Each PE loads RGA from base+1, aligned arrays adds base+2, stores into base, ● All PEs execute the instruction broadcast where “base” is base of data in PEM by the CU, if they are in active mode n Each PE does this simultaneously, giving a speedup of 64 ● Each PE can perform various arithmetic ● and logical instructions For less than 64 array elements, some processors will sit idle ● Each PE has a memory with 2048 64-bit ● words, accessed in less than 188 ns For more than 64 array elements, some processors might have to do more work ● PEs can operate on data in 64-bit, 32-bit, and 8-bit formats n For some algorithms, it may be desirable to turn off PEs n Data routed between PEs various ways ● 64 PEs compute, then one half passes data to other half, then 32 PEs compute, n I/O is handled by a separate Burroughs etc.
    [Show full text]
  • Oral History Interview with David J. Wheeler
    An Interview with DAVID J. WHEELER OH 132 Conducted by William Aspray on 14 May 1987 Princeton, NJ Charles Babbage Institute The Center for the History of Information Processing University of Minnesota, Minneapolis Copyright, Charles Babbage Institute 1 David J. Wheeler Interview 14 May 1987 Abstract Wheeler, who was a research student at the University Mathematical Laboratory at Cambridge from 1948-51, begins with a discussion of the EDSAC project during his tenure. He compares the research orientation and the programming methods at Cambridge with those at the Institute for Advanced Study. He points out that, while the Cambridge group was motivated to process many smaller projects from the larger university community, the Institute was involved with a smaller number of larger projects. Wheeler mentions some of the projects that were run on the EDSAC, the user-oriented programming methods that developed at the laboratory, and the influence of the EDSAC model on the ILLIAC, the ORDVAC, and the IBM 701. He also discusses the weekly meetings held in conjunction with the National Physical Laboratory, the University of Birmingham, and the Telecommunications Research Establishment. These were attended by visitors from other British institutions as well as from the continent and the United States. Wheeler notes visits by Douglas Hartree (of Cavendish Laboratory), Nelson Blackman (of ONR), Peter Naur, Aad van Wijngarden, Arthur van der Poel, Friedrich L. Bauer, and Louis Couffignal. In the final part of the interview Wheeler discusses his visit to Illinois where he worked on the ILLIAC and taught from September 1951 to September 1953. 2 DAVID J.
    [Show full text]
  • Markov Chain Monte Carlo Methods
    Introduction to Machine Learning CMU-10701 Markov Chain Monte Carlo Methods Barnabás Póczos Contents Markov Chain Monte Carlo Methods Sampling • Rejection • Importance • Hastings-Metropolis • Gibbs Markov Chains • Properties Particle Filtering • Condensation 2 Monte Carlo Methods 3 Markov Chain Monte Carlo History A recent survey places the Metropolis algorithm among the 10 algorithms that have had the greatest influence on the development and practice of science and engineering in the 20th century (Beichl&Sullivan, 2000). The Metropolis algorithm is an instance of a large class of sampling algorithms, known as Markov chain Monte Carlo (MCMC) MCMC plays significant role in statistics, econometrics, physics and computing science. There are several high-dimensional problems, such as computing the volume of a convex body in d dimensions and other high-dim integrals, for which MCMC simulation is the only known general approach for providing a solution within a reasonable time. 4 Markov Chain Monte Carlo History While convalescing from an illness in 1946, Stanislaw Ulam was playing solitaire. It, then, occurred to him to try to compute the chances that a particular solitaire laid out with 52 cards would come out successfully (Eckhard, 1987). Exhaustive combinatorial calculations are very difficult. New, more practical approach: laying out several solitaires at random and then observing and counting the number of successful plays. This idea of selecting a statistical sample to approximate a hard combinatorial problem by a much simpler problem is at the heart of modern Monte Carlo simulation. 5 FERMIAC FERMIAC: The beginning of Monte Carlo Methods Developed in the Early 1930’s The Monte Carlo trolley, or FERMIAC, was an analog computer invented by physicist Enrico Fermi to aid in his studies of neutron transport.
    [Show full text]
  • Parallel Architecture Hardware and General Purpose Operating System
    Parallel Architecture Hardware and General Purpose Operating System Co-design Oskar Schirmer G¨ottingen, 2018-07-10 Abstract Because most optimisations to achieve higher computational performance eventually are limited, parallelism that scales is required. Parallelised hard- ware alone is not sufficient, but software that matches the architecture is required to gain best performance. For decades now, hardware design has been guided by the basic design of existing software, to avoid the higher cost to redesign the latter. In doing so, however, quite a variety of supe- rior concepts is excluded a priori. Consequently, co-design of both hardware and software is crucial where highest performance is the goal. For special purpose application, this co-design is common practice. For general purpose application, however, a precondition for usability of a computer system is an arXiv:1807.03546v1 [cs.DC] 10 Jul 2018 operating system which is both comprehensive and dynamic. As no such op- erating system has ever been designed, a sketch for a comprehensive dynamic operating system is presented, based on a straightforward hardware architec- ture to demonstrate how design decisions regarding software and hardware do coexist and harmonise. 1 Contents 1 Origin 4 1.1 Performance............................ 4 1.2 Limits ............................... 5 1.3 TransparentStructuralOptimisation . 8 1.4 VectorProcessing......................... 9 1.5 Asymmetric Multiprocessing . 10 1.6 SymmetricMulticore ....................... 11 1.7 MultinodeComputer ....................... 12 2 Review 14 2.1 SharedMemory.......................... 14 2.2 Cache ............................... 15 2.3 Synchronisation .......................... 15 2.4 Time-Shared Multitasking . 15 2.5 Interrupts ............................. 16 2.6 Exceptions............................. 16 2.7 PrivilegedMode.......................... 17 2.8 PeripheralI/O .........................
    [Show full text]
  • 11/15/20 Engineering Computer Science James E. Robertson
    The materials listed in this document are available for research at the University of Record Series Number Illinois Archives. For more information, email [email protected] or search http://www.library.illinois.edu/archives/archon for the record series number. 11/15/20 Engineering Computer Science James E. Robertson Papers, 1942-93 TABLE OF CONTENTS Material Box Biographical 1 Publications 1 Correspondence 1-3 Photography 3 Subject Files 1942-62 3 1962-65 4 1965-72 5 1972-88 6-7 1948-53 11 1953-58 12 1958-70 13 Course Material 8-9, 13 Research Papers, Publications, and Reports 9-10, 13 Computer Logbooks and Manuals 14-15 Computer Codes 16 Oversize 10, 16 11/15/20 2 Box 1: BIOGRAPHICAL Biographical and vitas, ca. 1950s, 1966, 1981, 1993 Appointments, 1949-72 PUBLICATIONS 1952-59 1960-67 1973-79 1980-83 1985-87 CORRESPONDENCE 1947, 1949 (4 folders), 1950-54 (4 folders), 1955-56 (2 folders), 1957-58 (18 folders), 1959-74 Box 2: Correspondence (9 folders), 1975-79 DCL Correspondence (13 folders), 1980-82 Box 3: DCL Correspondence (7 folders), 1983-July 1984 Correspondence (2 folders), 1985-90 PHOTOGRAPHY, J.E. ROBERTSON Drum Photos, Sept. 1953 Old Photos (Ordvac and Illiac), 1954 Pacific Travel Photo listing, 1962-63 Computer Panels & U of I photos, ca. 1965-70 Arithmetic Unit Glass Slides Fast Switching Experiment Glass Slides SUBJECT FILE, 1942-62 Certificates, 1942-51 Burks, Goldstine & von Neumann, Logical Design of an Electronic Computer 1946-47 Computer Memory Improvement article in C-U Gazette, Feb. 8, 1949 "Preliminary Design of an Arithmetic Unit for...Binary Digital Computer," by J.E.R., June 23, 1950 Ordvac article in Daily Oklahoman, Jan.
    [Show full text]
  • ILLIAC IV Is the Most Powerful by As Much As a Factor of Four
    The ILLl AC IV System represents a fundamentally different approach to data processing. The limitation imposed by the velocity of light, once thought to be an absolute upper bound on computing power, has been stepped over by several approaches to computer architecture, of which the ILLIAC IV is the most powerful by as much as a factor of four. The conquest of the limitations of the velocity of light was foreseen by Herman Kahn and A.J. Wiener in 1967, when they wrote: ". .over the past fifteen years this basic criterion of computer performance has increased by a factor of ten every two or three years . While some will argue that we are beginning to reach limits set by basic physical constants, such as the speed of light, this may not be true, especially when one considers new techniques in time sharing, segmentation of programs to add flexibility, and parallel processing computers. .(such as). .the ILLIAC IV #I .a. ILLIAC IV represents a significant step forward in computer systems architecture offering - greatly improved performances: 200 MIPS computation speed 109 bitslsec I10 transfer rate 106 bytes of high-speed integrated circuit memories 2.5 X 109bits of parallel disk storage - contemporary technology: ECL circuits semiconductor memories belted cables - and a new approach to the art of computing using parallelism, which offers an opportunity to programmers to utilize the vast ILLIAC 1 V Quadrant power of the system as effectively as possible. MAJOR SYSTEM ELEMENTS As shown in the accompanying system diagram, the major elements of the ILLIAC IV System are the Array Subsystem, the I10 Subsystem, the Disk File Subsystem, and the B 6700 Control Computer Subsystem.
    [Show full text]
  • John (Janos Lajos) Von Neumann (1903-1957)
    John (Janos Lajos) von Neumann (1903-1957) Hungarian-American Scientist who pioneered the modern computer architecture, game theory, mathematics (set theory, group theory, ergodic theory, operator theory), physics (hydrodynamics), cellular automata.... The son of Max Neumann (lawyer and financier) who acquired a noble title in 1913 and subsequently his son used the German honorific form von. Man of warm personality: courteous, charming and jovial. Born in Budapest (1903), naturalized citizen of the United States in 1937, died of cancer at the age of 53 in Washington (1957) Education chemistry,mathematics:universities(Budapest, Berlin, Swiss Federal Institute of Technology). 1926 doctorate in mathematics from Budapest Univ. 1927-1930 lecturer in Berlin Univ.and Hamburg Univ. 1930-invited to lecture on quantum theory at Princeton University, one year later - youngest professor at the Institute for Advanced Study, Computer Science achievements John von Neumann. was the main (along with A. Turing1) conceptual inventor of the stored- program digital computer. His computer architecture was described in 1945 "First Draft of a Report on the EDVAC": computer consists of 6 parts: arithmetic(dealing with binary digits),central control, memory(delay line& iconoscope tube), input, output, external memory (punched cards, tape, magnetic wire, steel tape). Instructions (called "orders") and data should be stored in the memory and both are subject of processing. Circuits are to be synchronous with a master system clock derived from a vacuum tube oscillator, possibly crystal controlled. Memory will be the largest subdivision of the system and he proposes 8,192 minor cycles (words) of 32-bits as a design goal, with 2,048 minor cycles still being useful.
    [Show full text]
  • Illiac IV History First Massively Parallel Computer Three Earlier Designs
    Illiac IV History Illiac IV I First massively parallel computer ● SIMD (duplicate the PE, not the CU) ● First large system with semiconductor- based primary memory I Three earlier designs (vacuum tubes and transistors) culminating in the Illiac IV design, all at the University of Illinois ● Logical organization similar to the Solomon (prototyped by Westinghouse) ● Sponsored by DARPA, built by various companies, assembled by Burroughs ● Plan was for 256 PEs, in 4 quadrants of 64 PEs, but only one quadrant was built ● Used at NASA Ames Research Center in mid-1970s 1 Fall 2003, SIMD 2 Fall 2003, SIMD Illiac IV Architectural Overview Programming Issues I One CU (control unit), I Consider the following FORTRAN code: 64 64-bit PEs (processing elements), DO 10 I = 1, 64 each PE has a PEM (PE memory) 10 A(I) = B(I) + C(I) ● Put A(1), B(1), C(1) on PU 1, etc. I CU operates on scalars, PEs on vector- I Each PE loads RGA from base+1, aligned arrays adds base+2, stores into base, ● All PEs execute the instruction broadcast where “base” is base of data in PEM by the CU, if they are in active mode I Each PE does this simultaneously, giving a speedup of 64 ● Each PE can perform various arithmetic ● and logical instructions For less than 64 array elements, some processors will sit idle ● Each PE has a memory with 2048 64-bit ● words, accessed in less than 188 ns For more than 64 array elements, some processors might have to do more work ● PEs can operate on data in 64-bit, 32-bit, and 8-bit formats I For some algorithms, it may be desirable to turn off PEs I Data routed between PEs various ways ● 64 PEs compute, then one half passes I I/O is handled by a separate Burroughs data to other half, then 32 PEs compute, etc.
    [Show full text]
  • A Survey of Concurrent Architectures Technical Report: CSL-TR-86-307
    COMPUTER SYSTEMS LABORATORY I STANFORD IJNlVERSl-lY - STANFORD, CA 943054055 A Survey of Concurrent Architectures Victor W. K. Mak Technical Report: CSL-TR-86-307 September 1986 The work described herein was supported by’ NASA Ames Research Center under contracts NAG 2-248 and NAGW 419. A Survey of Concurrent Architectures bY Victor W. K. Mak Technical Report: CSL-TR-86-307 September 1986 Computer Systems Laboratory Department of Electrical Engineering Stanford University Stanford, California 94305 Abstract A survey of 18 different concurrent architectures is presented in this report. Although this is by no means complete, it does cover a wide spectrum of both commercial and research architectures. A scheme is proposed to describe concurrent architectures using different dimensions: models of computation, interconnection network, processing element, memory system, and application areas. Key Words and Phrases: Concurrent Architecture, Interconnection Network, Model of Computation, Parallel Processing, Survey, Taxonomy. Copyright @ 1986 bY Victor W. K. Mak Contents 1 Introduction 1 2 Taxonomy of Concurrent Architectures 1 3 Architectures Studied 3 3.1 Systolic Array ................................... 3 3.2 STARAN ..................................... 4 3.3 Illiac IV ...................................... 4 3.4 BSP ........................................ 7 3.5 MPP ........................................ 8 3.6 CHiP ....................................... 9 3.7 NON-VON .................................... 9 3.8 DDSP ......................................
    [Show full text]