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Eight Key Ideas in Computer Architecture, from Eight Decades of Innovation 2020s 2000s 2010s 1990s 1980s 1970s 1960s 1950s 1940s Behrooz Parhami University of California, Santa Barbara Mar. 2021 Eight Key Ideas in Computer Architecture Slide 1 About This Presentation This slide show was first developed as a keynote talk for remote delivery at CSICC-2016, Computer Society of Iran Computer Conference, held in Tehran on March 8-10. The talk was presented at a special session on March 9, 11:30 AM to 12:30 PM Tehran time (12:00-1:00 AM PST). An updated version of the talk was prepared and used within B. Parhami’s suite of lectures for IEEE Computer Society’s Distinguished Visitors Program, 2021-2023. All rights reserved for the author. ©2021 Behrooz Parhami Edition Released Revised Revised Revised First Mar. 2016 July 2017 Second Mar. 2021 Mar. 2021 Eight Key Ideas in Computer Architecture Slide 2 My Personal Academic Journey 1988 1986 Grad 1968 1970 1969 1974 My children, 1973 PhD ages 27-37 2023 Fifty years in academia Mar. 2021 Eight Key Ideas in Computer Architecture Slide 3 Some of the material in this talk come from, or will appear in updated versions of, my two computer architecture textbooks Mar. 2021 Eight Key Ideas in Computer Architecture Slide 4 Eight Key Ideas in Computer Architecture, from Eight Decades of Innovation Computer architecture became an established discipline when the stored-program concept was incorporated into bare- bones computers of the 1940s. Since then, the field has seen multiple minor and major innovations in each decade. I will present my pick of the most-important innovation in each of the eight decades, from the 1940s to the 2010s, and show how these ideas, when connected to each other and allowed to interact and cross-fertilize, produced the phenomenal growth of computer performance, now approaching exa-op/s (billion billion operations per second) level, as well as to ultra-low-energy and single-chip systems. I will also offer predictions for what to expect in the 2020s and beyond. Mar. 2021 Eight Key Ideas in Computer Architecture Slide 5 Background: Analytical Engine 1820s-1930s Difference Engine Punched Cards Program (Instructions) Data (Variable values) Mar. 2021 Eight Key Ideas in Computer Architecture Slide 6 Difference Engine: Fixed Program D(2) D(1) f(x) x x2+x+41 2nd-degree polynomial evaluation Babbage’s Difference Engine 2 Babbage used 7th-degree f(x) Mar. 2021 Eight Key Ideas in Computer Architecture Slide 7 Analytical Engine: Programmable Ada Lovelace, world’s first programmer Sample program > Mar. 2021 Eight Key Ideas in Computer Architecture Slide 8 The Programs of Charles Babbage IEEE Annals of the History of Computing, January-March 2021 (article by Raul Rojas) Mar. 2021 Eight Key Ideas in Computer Architecture Slide 9 Electromechanical and Turing’s Collosus Plug-Programmable Computing Machines Punched-card device Zuse’s Z3 ENIAC Mar. 2021 Eight Key Ideas in Computer Architecture Slide 10 The Eight Key Ideas 2010s Specialization 2000s GPUs 1990s FPGAs 1980s Pipelining 1970s Cache memory 1960s Parallel processing 1950s Microprogramming 1940s Stored program Come back in 2040, Mar. 2021for my top-10 Eight Key Ideas list! in Computer Architecture Slide 11 1940s: Stored Program Exactly who came up with the stored-program concept is unclear Legally, John Vincent Atanasoff is designated as inventor, but many others deserve to share the credit Babbage Turing Atanasoff Eckert Mauchly von Neumann Mar. 2021 Eight Key Ideas in Computer Architecture Slide 12 First Stored-Program Computer Manchester Small-Scale Experimental Machine Ran a stored program on June 21, 1948 (Its successor, Manchester Mark 1, operational in April 1949) EDSAC (Cambridge University; Wilkes et al.) Fully operational on May 6, 1949 EDVAC (IAS, Princeton University; von Neumann et al.) Conceived in 1945 but not delivered until August 1949 BINAC (Binary Automatic Computer, Eckert & Mauchly) Delivered on August 22, 1949, but did not function correctly Source: Wikipedia Eight Key Ideas in Computer Architecture Slide 13 von Neumann vs. Harvard Architecture von Neumann architecture (unified memory for code & data) Programs can be modified like data More efficient use of memory space Harvard architecture (separate memories for code & data) Better protection of programs Higher aggregate memory bandwidth Memory optimization for access type Mar. 2021 Eight Key Ideas in Computer Architecture Slide 14 1950s: Microprogramming Traditional control unit design (multicycle): Specify which control signals are to be asserted in each cycle and synthesize Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Gives rise to Notes for State 5: random logic % 0 for j or jal, 1 for syscall, State 5 State 6 don’t-care for other instr’s Jump/ ALUSrcX = 1 @ 0 for , , and , j jal syscall Branch ALUSrcY = 1 InstData = 1 1 for jr, 2 for branches ALUFunc = ‘’ MemWrite = 1 Error-prone # 1 for j, jr, jal, and syscall, JumpAddr = % ALUZero () for beq (bne), PCSrc = @ bit 31 of ALUout for bltz PCWrite = # and inflexible For jal, RegDst = 2, RegInSrc = 1, RegWrite = 1 sw State 0 State 1 State 2 State 3 State 4 InstData = 0 lw/ Hardware MemRead = 1 IRWrite = 1 ALUSrcX = 0 sw ALUSrcX = 1 lw InstData = 1 RegDst = 0 bugs hard to ALUSrcX = 0 ALUSrcY = 3 ALUSrcY = 2 MemRead = 1 RegInSrc = 0 ALUSrcY = 0 ALUFunc = ‘+’ ALUFunc = ‘+’ ALUFunc = ‘+’ RegWrite = 1 PCSrc = 3 fix after PCWrite = 1 deployment Start State 7 State 8 ALUSrcX = 1 RegDst = 0 or 1 Design from Note for State 7: ALUSrcY = 1 or 2 RegInSrc = 1 ALUFunc is determined based ALU- ALUFunc = Varies RegWrite = 1 scratch for on the op and fn fields type each system Mar. 2021 Eight Key Ideas in Computer Architecture Slide 15 The Birth of Microprogramming The control state machine resembles a program (microprogram) comprised of instructions (microinstructions) and sequencing PC Cache Regis ter ALU ALU Sequence control control control inputs function control Every minstruction contains a JumpAddr FnType PCSrc LogicFn branch field PCWrite AddSub ALUSrcY InstData ALUSrcX MemRead RegInSrc MemWrite RegDst Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Notes for State 5: % 0 for j or jal, 1 for syscall, State 5 State 6 RegWrite don’t-care for other instr’s IRWrite Jump/ ALUSrcX = 1 @ 0 for , , and , j jal syscall Branch ALUSrcY = 1 InstData = 1 1 for jr, 2 for branches ALUFunc = ‘’ MemWrite = 1 # 1 for j, jr, jal, and syscall, JumpAddr = % ALUZero () for beq (bne), PCSrc = @ bit 31 of ALUout for bltz PCWrite = # For jal, RegDst = 2, RegInSrc = 1, RegWrite = 1 sw State 0 State 1 State 2 State 3 State 4 InstData = 0 lw/ MemRead = 1 IRWrite = 1 ALUSrcX = 0 sw ALUSrcX = 1 lw InstData = 1 RegDst = 0 ALUSrcX = 0 ALUSrcY = 3 ALUSrcY = 2 MemRead = 1 RegInSrc = 0 ALUSrcY = 0 ALUFunc = ‘+’ ALUFunc = ‘+’ ALUFunc = ‘+’ RegWrite = 1 Maurice V. Wilkes PCSrc = 3 PCWrite = 1 Start (1913-2010) State 7 State 8 ALUSrcX = 1 RegDst = 0 or 1 Note for State 7: ALUSrcY = 1 or 2 RegInSrc = 1 ALUFunc is determined based ALU- ALUFunc = Varies RegWrite = 1 on the op and fn fields type Mar. 2021 Eight Key Ideas in Computer Architecture Slide 16 Microprogramming Implementation Each microinstruction controls the data path for one clock cycle Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Notes for State 5: % 0 for j or jal, 1 for syscall, State 5 State 6 don’t-care for other instr’s Jump/ ALUSrcX = 1 @ 0 for , , and , fetch: ----- j jal syscall Branch ALUSrcY = 1 InstData = 1 1 for jr, 2 for branches ALUFunc = ‘’ MemWrite = 1 # 1 for j, jr, jal, and syscall, JumpAddr = % ALUZero () for beq (bne), PCSrc = @ ----- bit 31 of ALUout for bltz PCWrite = # For jal, RegDst = 2, RegInSrc = 1, RegWrite = 1 sw ----- State 0 State 1 State 2 State 3 State 4 InstData = 0 lw/ MemRead = 1 IRWrite = 1 ALUSrcX = 0 sw ALUSrcX = 1 lw InstData = 1 RegDst = 0 ALUSrcX = 0 ALUSrcY = 3 ALUSrcY = 2 MemRead = 1 RegInSrc = 0 ALUSrcY = 0 ALUFunc = ‘+’ ALUFunc = ‘+’ ALUFunc = ‘+’ RegWrite = 1 PCSrc = 3 PCWrite = 1 Multiway andi: ----- Start State 7 State 8 branch ----- ALUSrcX = 1 RegDst = 0 or 1 Note for State 7: ALUSrcY = 1 or 2 RegInSrc = 1 ALUFunc is determined based ALU- ALUFunc = Varies RegWrite = 1 on the op and fn fields type Program Dispatch Instr table 1 0 MicroPC 1 Microprogram Instr 2 1 memory or PLA 3 Address Dispatch 0 Instr table 2 Incr Data mInstr Instr Microinstruction register mInstr op (from instruction mInstr Sequence register) Control signals to data path control mInstr Mar. 2021 Eight Key Ideas in Computer Architecture Slide 17 1960s: Parallel Processing Associative (content-addressed) memories and other forms of parallelism (compute-I/O overlap, functional parallelism) had been in existence since the 1940s SRAM Binary CAM Ternary CAM Highly parallel machine, proposed by Daniel Slotnick in 1964, later morphed into ILLIAC IV in 1968 (operational in 1975) Michael J. Flynn devised his now-famous 4-way taxonomy (SISD, SIMD, MISD, MIMD) in 1966 and Amdahl formulated his speed-up law and rules for system balance in 1967 Mar. 2021 Eight Key Ideas in Computer Architecture Slide 18 The ILLIAC IV Concept: SIMD Parallelism Control Unit Host Common control unit Fetch data or (B6700) instructions fetches and decodes Data Control Mode instructions, broadcasting the To Proc. 63 Proc. Proc. Proc. Proc. To Proc. 0 control signals 0 1 2 63 to all PEs Mem. Mem. Mem. Mem. 0 1 2 63 Each PE executes or ignores the instruction based on local, data- dependent conditions 3 3 3 3 2 2 2 2 1 1 1 . 1 The interprocessor Synchronized 0 0 0 0 routing network is Disks 299 299 299 299 (Main Memory) 298 298 298 298 only partially shown Band 0 Band 1 Band 2 Band 51 Mar.
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