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'CPU Specific Tronchip Commands' in 'Tricore Debugger and Trace'

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'CPU Specific Tronchip Commands' in 'Tricore Debugger and Trace' TriCore Debugger and Trace TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents ...................................................................................................................... ICD In-Circuit Debugger ................................................................................................................ Processor Architecture Manuals .............................................................................................. TriCore ...................................................................................................................................... TriCore Debugger and Trace ............................................................................................... 1 History ................................................................................................................................ 7 Safety Precautions ............................................................................................................ 8 Introduction ....................................................................................................................... 9 Brief Overview of Documents for New Users 9 Available Tools 10 Debugger 10 Software-only Debugger for XCP 10 On-chip Trace 10 Serial Off-chip Trace (AGBT) 11 Parallel Off-chip Trace 11 Co-Processor Debugging (PCP/GTM) 11 Multicore Debugging and Tracing 11 Software Installation 12 Configuration 12 System Overview 12 Related Documents 13 Demo and Start-up Scripts 13 OCDS Levels 14 Debugging .......................................................................................................................... 15 Single-Core Debugging (AUDO) 16 Single-Core Debugging - Quick Start 16 Multicore Debugging (AURIX) 18 SMP Debugging - Quick Start 18 AMP Debugging - Quick Start 20 AMP vs. SMP 22 Selecting the right AURIX CPU 23 Understanding Multicore Startup by Application Code 23 About Ambiguous Symbols 24 ©1989-2021 Lauterbach GmbH TriCore Debugger and Trace 1 Access Classes 25 Breakpoints 26 Software Breakpoints 26 On-chip Breakpoints 26 MAP.BOnchip Command 27 Advanced Breakpoints 27 Single Stepping 28 Assembler Level 28 HLL Level 28 Flash 29 Onchip Triggers (TrOnchip Window) 31 BenchMarkCounter 32 Example: Measuring Instructions and Stalls per Clock Cycle 33 Example: A-to-B Mode (single shot) 34 Example: A-to-B Mode (average) 35 Example: Record Counters Periodically 36 Watchpins 37 AUDO 37 AURIX 37 Accessing Cached Memory Areas and Cache Inspection 41 AUDO Devices 41 AURIX Devices 42 Parallel Usage of a 3rd-Party Tool 46 Physical Sharing of the Debug Port 46 Debugging an Application with the Memory Protection Unit Enabled 48 TriCore v1.6 and Later 48 TriCore v1.3.1 and Earlier 48 Debugging with MPU Enabled in RAM 48 Debugging with MPU Enabled in FLASH 49 Debugging through Resets and Power Cycles 50 Soft Resets 50 Hard Resets 51 Power Cycles 52 Suspending the System Timers of TC3xx 54 Suspending the Watchdogs 54 Cerberus Access Protection 55 Target Code Execution 55 Internal Break Bus (JTAG) 55 Troubleshooting 56 SYStem.Up Errors 56 Debugging Optimized Code 56 FAQ ..................................................................................................................................... 57 Tracing ............................................................................................................................... 58 ©1989-2021 Lauterbach GmbH TriCore Debugger and Trace 2 On-chip Trace (OCDS-L3) 58 Quick Start for Tracing with On-chip Trace (OCDS-L3) 58 Supported Features 59 Trace Control 60 Trace Evaluation 60 Impact of the Debugger on FPI Bus Tracing 60 Simple Trace Control 61 Examples 61 CPU specific Commands .................................................................................................. 65 CPU specific BMC Commands 65 BMC.SELect Select counter for statistic analysis 65 BMC.<counter>.ATOB Control A-to-B mode 65 BMC.<counter>.TRIGMODE BMC trigger mode 66 BMC.<counter>.TRIGVAL BMC trigger value 66 CPU specific SYStem.CONFIG Commands 67 SYStem.CONFIG.state Display target configuration 67 SYStem.CONFIG Configure debugger according to target topology 68 Daisy-Chain Example 70 TapStates 71 SYStem.CONFIG.CORE Assign core to TRACE32 instance 72 SYStem.CONFIG BreakPIN Define mapping of break pins 73 SYStem.CONFIG CAN Configure CAN interface 74 SYStem.CONFIG CAN.BaseCLOCK Base clock for CAN interface 74 SYStem.CONFIG CAN.NominalBRP Set CAN nominal baud rate prescaler 75 SYStem.CONFIG CAN.NominalTSEG1 Set CAN nominal Phase_seg1 75 SYStem.CONFIG CAN.NominalTSEG2 Set CAN nominal Phase_seg2 75 SYStem.CONFIG CAN.NominalSJW Set CAN nominal SJW parameter 75 SYStem.CONFIG CAN.DataBRP Set CAN data baud rate prescaler 76 SYStem.CONFIG CAN.DataTSEG1 Set CAN data Phase_seg1 76 SYStem.CONFIG CAN.DataTSEG2 Set CAN data Phase_seg2 76 SYStem.CONFIG CAN.DataSJW Set CAN data SJW 77 SYStem.CONFIG DAP Configure DAP interface 78 SYStem.CONFIG DAP.BreakPIN Define mapping of break pins 78 SYStem.CONFIG DAP.DAPENable Enable DAP mode on PORST 78 SYStem.CONFIG DAP.USERn Configure and set USER pins 79 SYStem.CONFIG.DEBUGPORT Select target interface 80 SYStem.CONFIG.DEBUGPORTTYPE Set debug cable interface mode 80 SYStem.CONFIG DXCM Configure DXCM 81 SYStem.CONFIG DXCM.TXID Control frame message ID 81 SYStem.CONFIG DXCM.TXIDE Control frame format 82 SYStem.CONFIG DXCM.TXFDF Control frame format 82 SYStem.CONFIG DXCM.TXBRS Control the use of baud rate switching 82 SYStem.CONFIG DXCM.RXID Set ID for frames from target 82 ©1989-2021 Lauterbach GmbH TriCore Debugger and Trace 3 SYStem.CONFIG DXCM.RXIDE Expect extended frames from target 83 SYStem.CONFIG DXCPL Configure DXCPL 84 SYStem.CONFIG DXCPL.Timing Configure SPD timing for DXCPL 84 SYStem.CONFIG.EXTWDTDIS Disable external watchdog 84 SYStem.CONFIG PortSHaRing Control sharing of debug port with other tool 85 SYStem.CPU Select CPU 86 SYStem.JtagClock Set the JTAG frequency 87 SYStem.LOCK Tristate the JTAG port 88 SYStem.MemAccess Run-time memory access (non-intrusive) 89 SYStem.Mode Establish the communication with the CPU 90 CPU and Architecture specific SYStem.Option Commands 92 SYStem.Option BREAKFIX Enable workaround for asynchronous breaking 92 SYStem.Option CBSACCEN<x> Cerberus access protection 93 SYStem.Option DCFREEZE Do not modify cache structure 94 SYStem.Option DCREAD Control cache behavior of reads 94 SYStem.Option DSYNC Force data synchronization 95 SYStem.Option DOWNMODE Behavior of SYStem.Mode Down 96 SYStem.Option DUALPORT Implicitly use run-time memory access 96 SYStem.Option DataTrace Enable data tracing 97 SYStem.Option EndInitProtectionOverride Override ENDINIT protection 97 SYStem.Option ETK Debugging together with ETK from ETAS 97 SYStem.Option HeartBeat Bug fix to avoid FPI bus conflict 98 SYStem.Option HoldReset Reset duration 98 SYStem.Option HSMRESTART Restart HSM on connect 99 SYStem.Option ICFLUSH Flush instruction cache at 'Go' or 'Step' 99 SYStem.Option IMASKASM Disable interrupts while single stepping 99 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 100 SYStem.Option INTSTART Start address of interrupt routines 100 SYStem.Option INTUSE Number of implemented interrupts 100 SYStem.Option JTAGENSEQ Use JTAG initialization sequence 101 SYStem.Option KEYCODE Set debug interface password 101 SYStem.Option KEYCODEWarnNotAccepted Set warning level 101 SYStem.Option LBIST LBIST gap handling 102 SYStem.Option MACHINESPACES Address extension for guest OSes 103 SYStem.Option MAPCACHE Map cache automatically 103 SYStem.Option OCDSELOW Set OCDS line to low 104 SYStem.Option OVC Enable OVERLAY memory access 104 SYStem.Option OVERLAY Enable overlay support 105 SYStem.Option PERSTOP Enable global peripheral suspend 106 SYStem.Option PMILBFIX Enable PMI line buffer invalidation workaround 107 SYStem.Option PostResetDELAY Delay after RESET is released 108 SYStem.Option ReadOnly Block all write accesses 108 SYStem.Option RESetBehavior Set behavior when a reset occurs 109 ©1989-2021 Lauterbach GmbH TriCore Debugger and Trace 4 SYStem.Option ResetDetection Set how hard resets are detected 109 SYStem.Option ResetMode Select reset method 110 SYStem.Option RESetTMS State of TMS line at reset 110 SYStem.Option SLOWRESET Long timeout for resets 110 SYStem.Option SOFTLONG Set 32 bit software breakpoints 111 SYStem.Option STEPONCHIP Step with onchip breakpoints 111 SYStem.Option STEPSOFT Step with software breakpoints 111 SYStem.Option TB1766FIX Bug fix for some TC1766 TriBoards 112 SYStem.Option TRAPSTART Start address of trap vectors 112 SYStem.Option WDTFIX Disables the watchdog on SYStem.Up 112 SYStem.Option WDTSUS Link the watchdog timer to the suspend bus 113 SYStem.RESetOut In-target reset 113 SYStem.state Open SYStem.state window 113 CPU specific TrOnchip Commands .................................................................................114 TrOnchip.BreakBusN.BreakIN Configure break pin of 'BreakBus N' 114 TrOnchip.BreakBusN.BreakOUT Configure break pin of 'BreakBus N' 114 TrOnchip.BreakIN.<target> Connect break <target> to BreakBus 115 TrOnchip.BreakOUT.<source> Connect break <source> to BreakBus 115 <source> 116 HaLTEN 116 TrOnchip.CONVert Adjust range breakpoint in on-chip resource 117 TrOnchip.CountX Event X counter value 117 TrOnchip.CountY Event Y counter value 117 TrOnchip.EXTernal Configure TriCore break on BreakBus event 118 TrOnchip.PERSTOPOUT Route suspend signal to pin 118 TrOnchip.RESet Reset settings for the on-chip trigger unit 118 TrOnchip.SoftWare Configure 'TriCore' break on debug
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