A Software Guide to Universal Debug Engine for C166, ST10, XC166, XE166 XC2000, Tricore, Powerpc ARM, Xscale, Superh
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Chapter 8 Instruction Set
Chapter 8 Instruction Set 80 80 This chapter lists the PowerPC instruction set in alphabetical order by mnemonic. Note that each entry includes the instruction formats and a quick reference ‘legend’ that provides such information as the level(s) of the PowerPC architecture in which the instruction may be found—user instruction set architecture (UISA), virtual environment architecture U (VEA), and operating environment architecture (OEA); and the privilege level of the V instruction—user- or supervisor-level (an instruction is assumed to be user-level unless the O legend specifies that it is supervisor-level); and the instruction formats. The format diagrams show, horizontally, all valid combinations of instruction fields; for a graphical representation of these instruction formats, see Appendix A, “PowerPC Instruction Set Listings.” The legend also indicates if the instruction is 64-bit, , 64-bit bridge, and/or optional. A description of the instruction fields and pseudocode conventions are also provided. For more information on the PowerPC instruction set, refer to Chapter 4, “Addressing Modes and Instruction Set Summary.” Note that the architecture specification refers to user-level and supervisor-level as problem state and privileged state, respectively. 8.1 Instruction Formats Instructions are four bytes long and word-aligned, so when instruction addresses are U presented to the processor (as in branch instructions) the two low-order bits are ignored. Similarly, whenever the processor develops an instruction address, its two low-order bits are zero. Bits 0–5 always specify the primary opcode. Many instructions also have an extended opcode. The remaining bits of the instruction contain one or more fields for the different instruction formats. -
Book E: Enhanced Powerpc™ Architecture
Book E: Enhanced PowerPC Architecture Version 1.0 May 7, 2002 Third Edition (Dec 2001) The following paragraph does not apply to the United Kingdom or any country where such provisions are inconsistent with local law: INTERNATIONAL BUSINESS MACHINES CORPORATION PROVIDES THIS DOCUMENT “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer of express or implied warranties in certain transactions; therefore, this statement may not apply to you. IBM does not warrant that the use of the information herein shall be free from third party intellectual property claims. IBM does not warrant that the contents of this document will meet your requirements or that the document is error-free. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the document. IBM may make improvements and or changes in the product(s) and/or program(s) described in this document at any time. This document does not imply a commitment by IBM to supply or make generally available the product(s) described herein. No part of this document may be reproduced or distributed in any form or by any means, or stored in a data base or retrieval system, without the written permission of IBM. Address comments about this document to: IBM Corporation Department B5H / Building 667 3039 Cornwallis Road P.O. Box 12195 Research Triangle Park, NC 27709 Portions of the information in this document may have been published previously in the following related documents: The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition (1994) The IBM PowerPC Embedded Environment: Architectural Specifications for IBM PowerPC Embedded Controllers, Second Edition (1998) IBM may have patents or pending patent applications covering the subject matter in this document. -
Xilinx XAPP545 Statistical Profiler for Embedded IBM Powerpc, Application Note
Product Not Recommended for New Designs Application Note: Virtex-II Pro R Statistical Profiler for Embedded IBM PowerPC XAPP545 (v1.0) September 15, 2004 Author: Njuguna Njoroge Summary This application note describes how to generate statistical profiling information from the IBM PowerPC 405D, which is embedded in some Virtex-II Pro™ FPGAs. Specifically, the application note details how to convert trace output files generated from the Agilent Technologies Trace Port Analyzer into a gprof (GNU profiler) readable format. The gprof tool is capable of generating a histogram of a program's functions and a call-graph table of those functions. Introduction Profiling allows a programmer to assess where a program is spending most of its time and how frequently functions are being called. With this information, a programmer can gain insight as to what optimizations to make. In some cases, a programmer can identify bugs that would be otherwise undetectable. Using the RISCWatch application is a first step in profiling a program. Nonetheless, manually mulling through approximately 350 MB (or 8 million cycles) of trace data to discern the run-time profile of the program is a fruitless endeavor. In fact, the designers of RISCWatch realized this, so they standardized the trace output format to enable post processing of the trace. The regular format of the trace files allows scripts to parse through the trace and convert it to the gprof format. By converting the trace files into the gprof format, the widespread use of gprof in the profiling community -
Schedule 14A Employee Slides Supertex Sunnyvale
UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 SCHEDULE 14A Proxy Statement Pursuant to Section 14(a) of the Securities Exchange Act of 1934 Filed by the Registrant Filed by a Party other than the Registrant Check the appropriate box: Preliminary Proxy Statement Confidential, for Use of the Commission Only (as permitted by Rule 14a-6(e)(2)) Definitive Proxy Statement Definitive Additional Materials Soliciting Material Pursuant to §240.14a-12 Supertex, Inc. (Name of Registrant as Specified In Its Charter) Microchip Technology Incorporated (Name of Person(s) Filing Proxy Statement, if other than the Registrant) Payment of Filing Fee (Check the appropriate box): No fee required. Fee computed on table below per Exchange Act Rules 14a-6(i)(1) and 0-11. (1) Title of each class of securities to which transaction applies: (2) Aggregate number of securities to which transaction applies: (3) Per unit price or other underlying value of transaction computed pursuant to Exchange Act Rule 0-11 (set forth the amount on which the filing fee is calculated and state how it was determined): (4) Proposed maximum aggregate value of transaction: (5) Total fee paid: Fee paid previously with preliminary materials. Check box if any part of the fee is offset as provided by Exchange Act Rule 0-11(a)(2) and identify the filing for which the offsetting fee was paid previously. Identify the previous filing by registration statement number, or the Form or Schedule and the date of its filing. (1) Amount Previously Paid: (2) Form, Schedule or Registration Statement No.: (3) Filing Party: (4) Date Filed: Filed by Microchip Technology Incorporated Pursuant to Rule 14a-12 of the Securities Exchange Act of 1934 Subject Company: Supertex, Inc. -
Tanium™ Client Deployment Guide
Tanium™ Client Deployment Guide Version 6.0.314.XXXX February 05, 2018 The information in this document is subject to change without notice. Further, the information provided in this document is provided “as is” and is believed to be accurate, but is presented without any warranty of any kind, express or implied, except as provided in Tanium’s customer sales terms and conditions. Unless so otherwise provided, Tanium assumes no liability whatsoever, and in no event shall Tanium or its suppliers be liable for any indirect, special, consequential, or incidental damages, including without limitation, lost profits or loss or damage to data arising out of the use or inability to use this document, even if Tanium Inc. has been advised of the possibility of such damages. Any IP addresses used in this document are not intended to be actual addresses. Any examples, command display output, network topology diagrams, and other figures included in this document are shown for illustrative purposes only. Any use of actual IP addresses in illustrative content is unintentional and coincidental. Please visit https://docs.tanium.com for the most current Tanium product documentation. Tanium is a trademark of Tanium, Inc. in the U.S. and other countries. Third-party trademarks mentioned are the property of their respective owners. © 2018 Tanium Inc. All rights reserved. © 2018 Tanium Inc. All Rights Reserved Page 2 Table of contents Overview 8 What is the Tanium Client? 8 Registration 9 Client peering 9 File distribution 11 Prerequisites 14 Host system requirements 14 Admin account 15 Network connectivity and firewall 16 Host system security exceptions 16 Deployment options summary 18 Using the Tanium Client Deployment Tool 21 Methods 21 Before you begin 21 Install the Client Deployment Tool 23 Deploy the Tanium Client 25 Check for Tanium Client updates 32 Troubleshooting 33 Logs 34 Advanced settings 34 Deploying the Tanium Client to Windows endpoints 36 Step 1: Create the installer 36 Step 2: Execute the installer 37 © 2018 Tanium Inc. -
An Efficient and Portable SIMD Algorithm for Charge/Current Deposition in Particle-In-Cell Codes✩
Computer Physics Communications 210 (2017) 145–154 Contents lists available at ScienceDirect Computer Physics Communications journal homepage: www.elsevier.com/locate/cpc An efficient and portable SIMD algorithm for charge/current deposition in Particle-In-Cell codesI H. Vincenti a,b,∗, M. Lobet a, R. Lehe a, R. Sasanka c, J.-L. Vay a a Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA, USA b Lasers Interactions and Dynamics Laboratory (LIDyL), Commissariat À l'Energie Atomique, Gif-Sur-Yvette, France c Intel Corporation, OR, USA a r t i c l e i n f o a b s t r a c t Article history: In current computer architectures, data movement (from die to network) is by far the most energy Received 9 January 2016 consuming part of an algorithm (≈20 pJ=word on-die to ≈10,000 pJ/word on the network). To increase Received in revised form memory locality at the hardware level and reduce energy consumption related to data movement, 10 August 2016 future exascale computers tend to use many-core processors on each compute nodes that will have Accepted 19 August 2016 a reduced clock speed to allow for efficient cooling. To compensate for frequency decrease, machine Available online 19 September 2016 vendors are making use of long SIMD instruction registers that are able to process multiple data with one arithmetic operator in one clock cycle. SIMD register length is expected to double every four years. As Keywords: Particle-In-Cell method a consequence, Particle-In-Cell (PIC) codes will have to achieve good vectorization to fully take advantage OpenMP of these upcoming architectures. -
UDE Memtool FLASH/OTP Memory Programming Tool UDE Memtool Is a Tool for Programming On-Chip As Well As External FLASH/OTP and EPROM's
UDE MemTool FLASH/OTP Memory Programming Tool UDE MemTool is a tool for programming on-chip as well as external FLASH/OTP and EPROM's. It integrates seamlessly with the UDE Universal Debug Engine Integrated Development Environment. UDE MemTool comes as add-in for the Universal Debug Engine (UDE) and allows the FLASH/OTP programming during the development cycle inside of UDE. UDE MemTool is aware of the memory map and runs the programming algorithm when required. UDE MemTool can be used with a separate frontend interface as tool. All programming functions are available via standard COM automation interfaces, too. Using these interfaces, the features of UDE MemTool may be integrated into automatic production and testsystems or started via scripts. Additionally, UDE MemTool offers a batch mode and a command line interface for automation purposes. UDE GangProgrammer can program FLASH memory devices simultaneously to save time and optimize the resource usage in a production environment. Functions of UDE MemTool UDE MemTool offers the following functions (depending on the type of memory): Erasing the entire memory module or selected sectors of the memory module Loading Intel Hex and Motorola S-Record files Programming all or selected portions of the file into the memory module Comparing all or selected portions of the file to the current contents of the memory module Read back and save-to-disk of the current memory content Setting and Resetting the Chip/Sector Protection if applicable (on-chip only) UCB (User Configuration Blocks), ABM (Alternate Boot Mode), BMI (Boot Mode Index) header handling for some derivatives. UDE MemTool can handle more than one memory module, and is using on-chip RAM. -
Implementing Powerpc Linux on System I Platform
Front cover Implementing POWER Linux on IBM System i Platform Planning and configuring Linux servers on IBM System i platform Linux distribution on IBM System i Platform installation guide Tips to run Linux servers on IBM System i platform Yessong Johng Erwin Earley Rico Franke Vlatko Kosturjak ibm.com/redbooks International Technical Support Organization Implementing POWER Linux on IBM System i Platform February 2007 SG24-6388-01 Note: Before using this information and the product it supports, read the information in “Notices” on page vii. Second Edition (February 2007) This edition applies to i5/OS V5R4, SLES10 and RHEL4. © Copyright International Business Machines Corporation 2005, 2007. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Notices . vii Trademarks . viii Preface . ix The team that wrote this redbook. ix Become a published author . xi Comments welcome. xi Chapter 1. Introduction to Linux on System i platform . 1 1.1 Concepts and terminology . 2 1.1.1 System i platform . 2 1.1.2 Hardware management console . 4 1.1.3 Virtual Partition Manager (VPM) . 10 1.2 Brief introduction to Linux and Linux on System i platform . 12 1.2.1 Linux on System i platform . 12 1.3 Differences between existing Power5-based System i and previous System i models 13 1.3.1 Linux enhancements on Power5 / Power5+ . 14 1.4 Where to go for more information . 15 Chapter 2. Configuration planning . 17 2.1 Concepts and terminology . 18 2.1.1 Processor concepts . -
A Developer's Guide to the POWER Architecture
http://www.ibm.com/developerworks/linux/library/l-powarch/ 7/26/2011 10:53 AM English Sign in (or register) Technical topics Evaluation software Community Events A developer's guide to the POWER architecture POWER programming by the book Brett Olsson , Processor architect, IBM Anthony Marsala , Software engineer, IBM Summary: POWER® processors are found in everything from supercomputers to game consoles and from servers to cell phones -- and they all share a common architecture. This introduction to the PowerPC application-level programming model will give you an overview of the instruction set, important registers, and other details necessary for developing reliable, high performing POWER applications and maintaining code compatibility among processors. Date: 30 Mar 2004 Level: Intermediate Also available in: Japanese Activity: 22383 views Comments: The POWER architecture and the application-level programming model are common across all branches of the POWER architecture family tree. For detailed information, see the product user's manuals available in the IBM® POWER Web site technical library (see Resources for a link). The POWER architecture is a Reduced Instruction Set Computer (RISC) architecture, with over two hundred defined instructions. POWER is RISC in that most instructions execute in a single cycle and typically perform a single operation (such as loading storage to a register, or storing a register to memory). The POWER architecture is broken up into three levels, or "books." By segmenting the architecture in this way, code compatibility can be maintained across implementations while leaving room for implementations to choose levels of complexity for price/performances trade-offs. The levels are: Book I. -
IBM Powerpc 970 (A.K.A. G5)
IBM PowerPC 970 (a.k.a. G5) Ref 1 David Benham and Yu-Chung Chen UIC – Department of Computer Science CS 466 PPC 970FX overview ● 64-bit RISC ● 58 million transistors ● 512 KB of L2 cache and 96KB of L1 cache ● 90um process with a die size of 65 sq. mm ● Native 32 bit compatibility ● Maximum clock speed of 2.7 Ghz ● SIMD instruction set (Altivec) ● 42 watts @ 1.8 Ghz (1.3 volts) ● Peak data bandwidth of 6.4 GB per second A picture is worth a 2^10 words (approx.) Ref 2 A little history ● PowerPC processor line is a product of the AIM alliance formed in 1991. (Apple, IBM, and Motorola) ● PPC 601 (G1) - 1993 ● PPC 603 (G2) - 1995 ● PPC 750 (G3) - 1997 ● PPC 7400 (G4) - 1999 ● PPC 970 (G5) - 2002 ● AIM alliance dissolved in 2005 Processor Ref 3 Ref 3 Core details ● 16(int)-25(vector) stage pipeline ● Large number of 'in flight' instructions (various stages of execution) - theoretical limit of 215 instructions ● 512 KB L2 cache ● 96 KB L1 cache – 64 KB I-Cache – 32 KB D-Cache Core details continued ● 10 execution units – 2 load/store operations – 2 fixed-point register-register operations – 2 floating-point operations – 1 branch operation – 1 condition register operation – 1 vector permute operation – 1 vector ALU operation ● 32 64 bit general purpose registers, 32 64 bit floating point registers, 32 128 vector registers Pipeline Ref 4 Benchmarks ● SPEC2000 ● BLAST – Bioinformatics ● Amber / jac - Structure biology ● CFD lab code SPEC CPU2000 ● IBM eServer BladeCenter JS20 ● PPC 970 2.2Ghz ● SPECint2000 ● Base: 986 Peak: 1040 ● SPECfp2000 ● Base: 1178 Peak: 1241 ● Dell PowerEdge 1750 Xeon 3.06Ghz ● SPECint2000 ● Base: 1031 Peak: 1067 Apple’s SPEC Results*2 ● SPECfp2000 ● Base: 1030 Peak: 1044 BLAST Ref. -
32-Bit TC1797
32-Bit TC1797 32-Bit Single-Chip Microcontroller Data Sheet V1.3 2014-08 Microcontrollers Edition 2014-08 Published by Infineon Technologies AG 81726 Munich, Germany © 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 32-Bit TC1797 32-Bit Single-Chip Microcontroller Data Sheet V1.3 2014-08 Microcontrollers TC1797 TC1797 Data Sheet Revision History: V1.3, 2014-08 Previous Version: V1.2, 2009-09 Page Subjects (major changes since last revision) 6 add SAK-TC1797-512F180EF and SAK-TC1797-384F150EF. -
16/32-Bit XC2238M, XC2237M
16/32-Bit Architecture XC2238M, XC2237M 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Base Line Data Sheet V2.1 2011-07 Microcontrollers Edition 2011-07 Published by Infineon Technologies AG 81726 Munich, Germany © 2011 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.