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Instruction Set User Guide, v1.6.4, January 2003 TriCoreTM 32-bit Unified Processor DSP Optimization Guide Part 1: Instruction Set IP Cores Never stop thinking. Edition 2003-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. User Guide, v1.6.4, January 2003 TriCoreTM 32-bit Unified Processor DSP Optimization Guide Part 1: Instruction Set DSP Optimization Guide Revision History: 2003-01 v1.6.4 Previous Version: v1.6.3 Page Subjects (major changes since last revision) All Revised following internal review We Listen to Your Comments Is there any information within this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your comments (referencing this document) to: [email protected] TriCore™ 32-bit Unified Processor DSP Optimization Guide Part 1: Instruction Set Table of Contents Page 1 General Information . 16 1.1 Block Diagram Overview . 17 1.2 Parallel Execution of Instructions . 18 1.3 Programming Model . 19 1.4 Memory Space . 20 1.5 Little-endian . 20 1.6 Interrupt Latency and Context-Switch . 21 1.7 Fraction . 21 1.8 Overflow and Sticky Overflow . 21 1.9 Saturation . 22 1.10 Advanced Overflow . 23 1.11 Packed Arithmetic . 24 1.12 16-bit Opcode . 25 1.13 Notation . 26 1.14 Document Conventions . 27 1.14.1 TriCore Instruction Syntax . 27 1.14.2 TriCore Instruction Characteristics . 27 1.14.3 Examples . 27 1.14.4 Symbolic Addresses . 28 2 Simple Arithmetic . 29 2.1 Addition . 30 2.1.1 32-bit Addition (ADD, ADDS, ADDS.U) . 30 2.1.2 32-bit Addition with 8, 16 & 32-bit Signed Constant (ADD, ADDI, ADDIH) . 31 2.1.3 16-bit Addition . 33 2.1.4 16-bit Addition using Packed Arithmetic (ADD.H, ADDS.H, ADDS.HU) 34 2.1.5 8-bit Addition using Packed Arithmetic (ADD.B) . 35 2.1.6 64-bit Addition (ADDC, ADDX) . 35 2.1.7 64-bit Addition with 64-bit Constant . 36 2.1.8 Carry Flag Table . 36 2.2 Subtraction . 37 2.2.1 32-bit Subtraction (SUB, SUBS, SUBS.U) . 37 2.2.2 32-bit Subtraction with Constant . 37 2.2.3 16-bit Subtraction . 38 2.2.4 16-bit Subtraction using Packed Arithmetic (SUB.H, SUBS.H, SUBS.HU) . 39 2.2.5 8-bit Subtraction Using Packed Arithmetic (SUB.B) . 39 2.2.6 64-bit Subtraction (SUBC, SUBX) . 40 2.2.7 64-bit Subtraction with Constant . 41 2.2.8 Reverse Subtraction (RSUB) . 42 2.3 Negate . 42 2.4 Move . 43 User Guide 5 v1.6.4, 2003-01 TriCore™ 32-bit Unified Processor DSP Optimization Guide Part 1: Instruction Set Table of Contents Page 2.4.1 Moves between Data Registers (MOV) . 43 2.4.2 16-bit Constant into a Data Register (MOV.U, MOV, MOVH) . 43 2.4.3 32-bit Constant into a Data Register . 44 2.5 Applications . 45 2.5.1 Arithmetic Series . 45 2.5.2 Multi Byte Operations . 46 3 Further Arithmetic . 47 3.1 Absolute Value . 47 3.1.1 32-bit (ABS, ABSS) . 48 3.1.2 Packed 16-bit (ABS.H, ABSS.H) . 49 3.1.3 Packed 8-bit (ABS.B) . 49 3.2 Absolute Difference . 50 3.2.1 32-bit Value (ABSDIF, ABSDIFS) . 50 3.2.2 Packed 16-bit (ABSDIF.H, ABSDIFS.H) . 51 3.2.3 Packed 8-bit (ABSDIF.B) . 51 3.3 Minimum, Maximum . 52 3.3.1 32-bit Signed/Unsigned (MIN, MIN.U, MAX, MAX.U) . 52 3.3.2 Packed 16-bit Signed/Unsigned (MIN.H, MAX.H, MIN.HU, MAX.HU) . 53 3.3.3 Packed 8-bit Signed/Unsigned (MIN.B, MAX.B, MIN.BU, MAX.BU) . 53 3.4 Saturate . 54 3.4.1 32-bit Saturation . 54 3.4.2 16-bit and 8-bit Saturation (SAT.H, SAT.HU, SAT.B, SAT.BU) . 54 3.5 Multiplication . 55 3.5.1 32 * 32-bit Multiplication (MUL, MULS, MULS.U) . 55 3.5.2 32 * 32-bit Multiplication with a 64-bit Result (MUL, MUL.U) . 57 3.5.3 16 * 16-bit Multiplication . 57 3.5.4 8 * 8-bit Multiplication . 58 3.5.5 Multiplication by a Power of 2 . 58 3.5.6 Multiplication/Addition (MADD, MADDS) . 58 3.5.7 Multiplication/Subtraction (MSUB, MSUBS) . 59 3.6 Division . 60 3.6.1 32 / 32-bit Division (DVINIT, DVSTEP, DVADJ) . 60 3.6.2 16 / 16-bit Division (DVINIT.H, DVSTEP) . 61 3.6.3 8 / 8-bit Division (DVINIT.B, DVSTEP) . 61 3.6.4 32 / 16-bit Division . 62 3.6.5 Division By a Power of 2 . 62 3.7 Applications . 63 3.7.1 Find Maximum of Value in an Unsigned Array . 63 3.7.2 Template Matching . 63 3.7.3 40 * 40-bit Multiplication . 65 3.7.4 Leapyear . 66 User Guide 6 v1.6.4, 2003-01 TriCore™ 32-bit Unified Processor DSP Optimization Guide Part 1: Instruction Set Table of Contents Page 4 Conditional Instructions . 68 4.1 ‘Hidden’ Conditional Instructions . ..
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