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The Design Warrior's Guide to Fpgas The Design Warrior’s Guide to FPGAs The Design Warrior’s Guide to FPGAs Clive “Max” Maxfield Newnes is an imprint of Elsevier 200 Wheeler Road, Burlington, MA 01803, USA Linacre House, Jordan Hill, Oxford OX2 8DP, UK Copyright © 2004, Mentor Graphics Corporation and Xilinx, Inc. All rights reserved. Illustrations by Clive “Max” Maxfield No part of this publication may be reproduced, stored in a retrieval system, or trans- mitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher. Permissions may be sought directly from Elsevier’s Science & Technology Rights Department in Oxford, UK: phone: (+44) 1865 843830, fax: (+44) 1865 853333, e-mail: [email protected]. You may also complete your request on-line via the Elsevier homepage (http://elsevier.com), by selecting “Customer Support” and then “Obtaining Permissions.” Recognizing the importance of preserving what has been written, Elsevier prints its books on acid-free paper whenever possible. Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the Library of Congress. ISBN: 0-7506-7604-3 British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library. For information on all Newnes publications visit our Web site at www.newnespress.com 04050607080910987654321 Printed in the United States of America To my wife Gina—the yummy-scrummy caramel, chocolate fudge, and rainbow-colored sprinkles on the ice cream sundae of my life Also, to my stepson Joseph and my grandchildren Willow, Gaige, Keegan, and Karma, all of whom will be tickled pink to see their names in a real book! For your delectation and delight, the CD accompanying this book contains a fully- searchable copy of The Design Warrior’s Guide to FPGAs in Adobe® Acrobat® (PDF) format. You can copy this PDF to your computer so as to be able to access The Design Warrior’s Guide to FPGAs as required (this is particularly useful if you travel a lot and use a notebook computer). The CD also contains a set of Microsoft® PowerPoint® files—one for each chapter and appendix—containing copies of the illustrations that are festooned throughout the book. This will be of particular interest for educators at colleges and universities when it comes to giving lectures or creating handouts based on The Design Warrior’s Guide to FPGAs Last but not least, the CD contains a smorgasbord of datasheets, technical articles, and useful web links provided by Mentor and Xilinx. Contents Preface ...............ix SRAMs, DRAMs, and microprocessors.........28 Acknowledgments ..........xi SPLDs and CPLDs ........28 Chapter 1 ASICs (gate arrays, etc.) .....42 Introduction ..........1 FPGAs ..............49 What are FPGAs? .........1 Why are FPGAs of interest? ....1 Chapter 4 What can FPGAs be used for?. 4 Alternative FPGA Architectures 57 A word of warning ........57 What’s in this book? ........6 A little background information . 57 What’s not in this book?......7 Antifuse versus SRAM Who’s this book for? ........8 versus … ............59 Chapter 2 Fine-, medium-, and coarse-grained Fundamental Concepts .....9 architectures ..........66 The key thing about FPGAs....9 MUX- versus LUT-based A simple programmable function . 9 logic blocks ...........68 Fusible link technologies .....10 CLBs versus LABs versus slices. 73 Antifuse technologies ......12 Fast carry chains .........77 Mask-programmed devices ....14 Embedded RAMs.........78 PROMs ..............15 Embedded multipliers, adders, EPROM-based technologies . 17 MACs, etc. ...........79 EEPROM-based technologies . 19 Embedded processor cores FLASH-based technologies . 20 (hard and soft) .........80 SRAM-based technologies ....21 Clock trees and clock managers . 84 Summary .............22 General-purpose I/O .......89 Gigabit transceivers .......92 Chapter 3 The Origin of FPGAs ......25 Hard IP, soft IP, and firm IP . 93 Related technologies .......25 System gates versus real gates . 95 Transistors ............26 FPGA years ............98 Integrated circuits ........27 viii I The Design Warrior's Guide to FPGAs Chapter 5 Chapter 8 Programming (Configuring) Schematic-Based Design Flows 133 an FPGA ............99 In the days of yore........133 Weasel words ...........99 The early days of EDA .....134 Configuration files, etc. .....99 A simple (early) schematic-driven Configuration cells .......100 ASIC flow...........141 Antifuse-based FPGAs .....101 A simple (early) schematic-driven SRAM-based FPGAs ......102 FPGA flow ..........143 Using the configuration port . 105 Flat versus hierarchical schematics Using the JTAG port ......111 ................148 Using an embedded processor. 113 Schematic-driven FPGA design flows today.......151 Chapter 6 Who Are All the Players? ...115 Chapter 9 Introduction...........115 HDL-Based Design Flows ...153 FPGA and FPAA vendors . 115 Schematic-based flows grind to a halt .........153 FPNA vendors .........116 The advent of HDL-based flows 153 Full-line EDA vendors .....116 Graphical design entry lives on . 161 FPGA-specialist and independent EDA vendors ............117 A positive plethora of HDLs . 163 FPGA design consultants with special Points to ponder.........172 tools ..............118 Chapter 10 Open-source, free, and low-cost design Silicon Virtual Prototyping tools ..............118 for FPGAs ..........179 Just what is an SVP? ......179 Chapter 7 FPGA Versus ASIC ASIC-based SVP approaches . 180 Design Styles .........121 FPGA-based SVPs .......187 Introduction...........121 Chaper 11 Coding styles ..........122 C/C++ etc.–Based Design Flows Pipelining and levels of logic . 122 ................193 Asynchronous design practices . 126 Problems with traditional Clock considerations ......127 HDL-based flows .......193 Register and latch considerations129 C versus C++ and concurrent versus sequential .......196 Resource sharing (time-division multi- plexing) ............130 SystemC-based flows ......198 State machine encoding ....131 Augmented C/C++-based flows 205 Test methodologies .......131 Pure C/C++-based flows ....209 Different levels of synthesis abstraction ..........213 Contents I ix Mixed-language design and Chapter 15 verification environments . 214 High-Speed Design and Other PCB Considerations .....267 Chapter 12 Before we start..........267 DSP-Based Design Flows ...217 We were all so much younger Introducing DSP ........217 then ..............267 Alternative DSP implementations The times they are a-changing . 269 ................218 Other things to think about . 272 FPGA-centric design flows for DSPs ............225 Chapter 16 Observing Internal Nodes in Mixed DSP and VHDL/ an FPGA ...........277 Verilog etc. environments . 236 Lack of visibility.........277 Chapter 13 Multiplexing as a solution . 278 Embedded Processor-Based Special debugging circuitry . 280 Design Flows .........239 Virtual logic analyzers......280 Introduction...........239 VirtualWires ..........282 Hard versus soft cores ......241 Partitioning a design into its Chapter 17 hardware and software components Intellectual Property .....287 245 Sources of IP ..........287 Hardware versus software views Handcrafted IP .........287 of the world ..........247 IP core generators ........290 Using an FPGA as its own Miscellaneous stuff .......291 development environment . 249 Chapter 18 Improving visibility in Migrating ASIC Designs to FPGAs the design ...........250 and Vice Versa ........293 A few coverification alternatives 251 Alternative design scenarios . 293 A rather cunning design environment .........257 Chapter 19 Simulation, Synthesis, Verification, Chapter 14 etc. Design Tools .......299 Modular and Incremental Introduction...........299 Design ............259 Simulation (cycle-based, Handling things as one event-driven, etc.) ......299 big chunk ...........259 Synthesis (logic/HDL versus Partitioning things into physically aware) .......314 smaller chunks ........261 Timing analysis (static There’s always another way . 264 versus dynamic) ........319 Verification in general .....322 Formal verification .......326 x I The Design Warrior's Guide to FPGAs Miscellaneous ..........338 Introduction...........381 Algorithmic evaluation .....383 Chapter 20 Choosing the Right Device . 343 picoChip’s picoArray technology384 So many choices ........343 QuickSilver’s ACM technology 388 If only there were a tool.....343 It’s silicon, Jim, but not Technology ...........345 as we know it!.........395 Basic resources and packaging . 346 Chapter 24 General-purpose I/O interfaces . 347 Independent Design Tools . 397 Embedded multipliers, Introduction...........397 RAMs, etc. ..........348 ParaCore Architect .......397 Embedded processor cores....348 The Confluence system Gigabit I/O capabilities .....349 design language ........401 IP availability ..........349 Do you have a tool? .......406 Speed grades...........350 Chapter 25 On a happier note........351 Creating an Open-Source-Based Design Flow .........407 Chapter 21 How to start an FPGA design Gigabit Transceivers .....353 shop for next to nothing . 407 Introduction...........353 The development platform: Linux Differential pairs ........354 ................407 Multiple standards .......357 The verification environment . 411 8-bit/10-bit encoding, etc. 358 Formal verification .......413 Delving into the transceiver Access to common IP components blocks .............361 ................416 Ganging multiple transceiver Synthesis and implementation
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