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Open Core Platform Based on Openrisc Processor and DE2-70 Board

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Open Core Platform Based on Openrisc Processor and DE2-70 Board Master Thesis Open Core Platform based on OpenRISC Processor and DE2-70 Board Xiang LI Company: ENEA University: Royal Institute of Technology, School of Information and Communication Technology, Stockholm, Sweden Industry Supervisor: Johan J¨orgensen KTH Supervisor & Examiner: Ingo Sander Master Thesis Number: TRITA-ICT-EX-2011:62 This page is intentionally left blank Abstract The trend of IP core reuse has been accelerating for years because of the increasing complexity in the System-on-Chip (SoC) designs. As a result, many IP cores of different types have been produced. Meanwhile, similar to the free software movement, an open core community has emerged because some designers choose to share their IP cores by using open source licenses. The open cores are growing fast due to their inherently attractive properties like accessible internal structure and usually no cost for license. Under this background, the master thesis was proposed by the company ENEA (Malm¨o/Lund branch), Sweden. It intended to evaluate the qualities of the open cores, as well as the difficulty and the feasibility of building an embedded platform by exclusively using the open cores. We contributed such an open core platform. It includes 5 open cores from the OpenCores organization: OpenRISC OR1200 processor, CONMAX WISH- BONE interconnection IP core, Memory Controller IP core, UART16550, and General Purpose IOs (GPIO) IP core. More than that, we added the supports to DM9000A and WM8731 ICs for Ethernet and Audio features. On the software side, uC/OS-II RTOS and uC/TCP-IP stack have been ported to the platform. The OpenRISC toolchain for software development was tested. And a MP3 music player application has created to demonstrate the system. The open core platform is targeted to the Terasic’s DE2-70 board with ALTERA Cyclone II FPGA. It aims to have high flexibility for a wide range of embedded applications and at the same time with very low costs. The design of the thesis project are fully open and available online. We hope our work can be useful in the future as a starting point or a reference both for academic research or for commercial purposes. Keywords: SoC, OpenCores, OpenRISC, WISHBONE, DE-70, uC/OS-II i This page is intentionally left blank Acknowledgement This master thesis was started in January, 2008. It cost me and my partner Lin Zuo more than 6 months to implement the project. There were lots of difficulties when solving the technical issues, but the writing of the thesis was even a greater challenge that I ever had. Finally the writing was completed in January, 2011. During the time, many people generously gave considerable help to me. Without those supports the thesis wouldn’t have been come to this far. So hereby I’d take the opportunity to express my deepest gratitude to the following people: Johan J¨orgensen, the ENEA hardware team leader and our industry su- pervisor. Johan is the best supervisor that I can expect. He is knowledgeable, experienced and full of brilliant ideas. He is good at communicating and en- couraging people. With a short conversation he can take my pressures away. As a supervisor, he participated almost in all aspects during the thesis. He proposed the topic, made the detailed plan together with us, helped to setup the working environment, and kept checking our progress. When we were in trouble, he provided not only useful suggestions but sometimes even looked down to the source code level. When I was upset because the thesis writing went slow, he was always supportive. It is my pleasure to have Johan as a supervisor. Ingo Sander, our KTH supervisor and examiner. Ingo’s lectures were very impressive and valuable to me, which opened many windows to the new fields. This was the reason I wanted to be his thesis student. Ingo actively monitored the thesis although we were in different cities. He followed our weekly reports and replied with advice and guidance. He tried to set higher requirements to us, which created bigger challenges but I also gained more experiences at the same time. And I especially appreciate his patience when the thesis writing was failed to finish on time. The knowledge learnt from Ingo truly benefits me, which I am using it everyday now in my career life. iii iv Lin Zuo, my thesis partner and good friend. As a partner he contributed a solid part to the thesis. He worked really hard and took over many heavy tasks. For some of them I was not confident but Lin made them come true. As a friend he is a very funny guy. When our work seemed going to a dead end, Lin can easily amuse me in his special way and ease the anxieties. Thanks to him the thesis becomes a successful and interesting memory when we look back to the life in Malm¨o. And my parents. Without their love and supports throughout my life, I would never get this chance to write a master thesis acknowledgement. Sincerely thanks to all the people who helped me on the way to my today’s achievements. Thank you all! Contents Abstract i Acknowledgement iii List of Figures xi List of Tables xv 1 Introduction 1 1.1 Background and Motivation . 1 1.2 Thesis Objectives . 3 1.3 Chapter Overview . 5 References................................ 6 2 Open Cores in a Commercial Perspective 7 2.1 Basic Concepts . 8 2.1.1 What is Open Core? . 8 2.1.2 Formal Definition of Open Source . 8 2.1.3 Licenses Involved to Evaluate . 9 2.1.4 GNU and FSF . 9 2.1.5 Free Software 6= Free of Charge . 10 v vi 2.2 BSD License . 10 2.3 GNU Licenses . 13 2.3.1 GPL . 13 2.3.2 LGPL . 15 2.3.3 Evaluations on the GNU Licenses . 17 2.4 The Price for Freedom — Comments on the GNU Philosophy 19 2.5 Developing Open Cores or Not — How Open Source Products could Benefit . 22 2.6 Utilizing Open Cores or Not — Pros and Cons . 23 2.7 The Future of Open Cores . 25 2.8 Conclusion . 26 References................................ 27 3 Platform Overview 31 3.1 DE2-70 Board . 32 3.2 Digital System with Open Cores . 33 3.2.1 System Block Diagram . 33 3.2.2 Summary of Addresses . 35 3.3 Software Development and Operating System Layer . 36 3.3.1 Software Development . 37 3.3.2 Operating System and uC/OS-II RTOS . 41 3.3.3 uC/TCP-IP Protocol Stack . 42 3.3.4 Hardware Abstraction Layer (HAL) Library . 42 3.4 Demo Application: A MP3 Music Player . 43 3.5 Summary . 44 References................................ 45 vii 4 OpenRISC 1200 Processor 47 4.1 Introduction . 47 4.2 OR1200 Features and Architecture . 49 4.3 OR1200 Registers . 51 4.4 Interrupt Vectors . 53 4.5 Tick Timer (TT) . 55 4.6 Programmable Interrupt Controller (PIC) . 56 4.7 Porting uC/OS-II to OR1200 . 58 4.7.1 Introduction . 58 4.7.2 uC/OS-II Context Switching . 58 4.7.3 Context Switching in OR1200 Timer Interrupt . 59 4.7.4 Summary . 61 References................................ 61 5 WISHBONE Specification and CONMAX IP Core 63 5.1 Importance of Interconnection Standard . 64 5.2 WISHBONE in a Nutshell . 66 5.2.1 Overview . 67 5.2.2 WISHBONE Interface Signals . 68 5.2.3 WISHBONE Bus Transactions . 72 5.2.3.1 Single Read/Write Transaction . 73 5.2.3.2 Block Read/Write Transaction . 76 5.2.3.3 Read-Modify-Write (RMW) Transaction . 78 5.2.3.4 Burst Transaction . 79 5.3 CONMAX IP Core . 89 5.3.1 Introduction . 89 viii 5.3.2 CONMAX Architecture . 90 5.3.3 Register File . 90 5.3.4 Parameters and Address Allocation . 91 5.3.5 Functional Notices . 92 5.3.6 Arbitration . 93 References................................ 95 6 Memory Blocks and Peripherals 97 6.1 On-chip RAM and its Interface . 99 6.1.1 On-chip RAM Pros and Cons . 100 6.1.2 ALTERA 1-Port RAM IP Core and its Parameters . 100 6.1.3 Interface Logic to the WISHBONE bus . 101 6.1.4 Data Organization and Address Line Connection . 102 6.1.5 Memory Alignment and Programming Tips . 106 6.1.6 Miscellaneous . 108 6.2 Memory Controller IP Core . 109 6.2.1 Introduction and Highlights . 110 6.2.2 Hardware Configurations . 112 6.2.2.1 Address Allocation . 112 6.2.2.2 Power-On Configuration (POC) . 114 6.2.2.3 Tri-state Bus . 115 6.2.2.4 Miscellaneous SDRAM Configurations . 116 6.2.2.5 Use Same Type of Devices on One Memory Controller . 116 6.2.3 Configurations for SSRAM and SDRAM . 116 6.2.4 Performance Improvement by Burst Transactions . 118 ix 6.3 UART16550 IP Core . 120 6.4 GPIO IP Core . 122 6.5 WM8731 Interface . 123 6.5.1 Introduction . 123 6.5.2 Structure of the WM8731 Interface . 123 6.5.3 HDL Source Files and Software Programming . 125 6.6 DM9000A Interface . 126 6.7 Summary . 126 References . 127 7 Conclusion and Future Work 129 7.1 Conclusions . 129 7.2 Future Works . 132 7.2.1 Improve and Optimize the Existing System . 132 7.2.2 Extension and Research Topics . 132 7.3 What’s New Since 2008 . 133 References . 134 A Thesis Announcement 135 A.1 Building a reconfigurable SoC using open source IP . 135 A.2 Further information . 136 B A Step-by-Step Instruction to Repeat the Thesis Project 137 B.1 Hardware / Software Developing Environment .
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