Intel Optane DC Persistent Memory
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Intel® Omni-Path Architecture (Intel® OPA) for Machine Learning
Big Data ® The Intel Omni-Path Architecture (OPA) for Machine Learning Big Data Sponsored by Intel Srini Chari, Ph.D., MBA and M. R. Pamidi Ph.D. December 2017 mailto:[email protected] Executive Summary Machine Learning (ML), a major component of Artificial Intelligence (AI), is rapidly evolving and significantly improving growth, profits and operational efficiencies in virtually every industry. This is being driven – in large part – by continuing improvements in High Performance Computing (HPC) systems and related innovations in software and algorithms to harness these HPC systems. However, there are several barriers to implement Machine Learning (particularly Deep Learning – DL, a subset of ML) at scale: • It is hard for HPC systems to perform and scale to handle the massive growth of the volume, velocity and variety of data that must be processed. • Implementing DL requires deploying several technologies: applications, frameworks, libraries, development tools and reliable HPC processors, fabrics and storage. This is www.cabotpartners.com hard, laborious and very time-consuming. • Training followed by Inference are two separate ML steps. Training traditionally took days/weeks, whereas Inference was near real-time. Increasingly, to make more accurate inferences, faster re-Training on new data is required. So, Training must now be done in a few hours. This requires novel parallel computing methods and large-scale high- performance systems/fabrics. To help clients overcome these barriers and unleash AI/ML innovation, Intel provides a comprehensive ML solution stack with multiple technology options. Intel’s pioneering research in parallel ML algorithms and the Intel® Omni-Path Architecture (OPA) fabric minimize communications overhead and improve ML computational efficiency at scale. -
Intel Server Board SE7320EP2 and SE7525RP2
Intel® Server Board SE7320EP2 and SE7525RP2 Tested Hardware and Operating System List Revision 1.0 June, 2005 Enterprise Platforms and Services Marketing Revision History IntelP®P Server Board SE7320EP2 and SE7525RP2 Revision History Revision Date Number Modifications June 2005 1.0 First Release ii Revision 1.0 IntelP®P Server Board SE7320EP2 and SE7525RP2 Disclaimers Disclaimers THE INFORMATION IN THIS DOCUMENT IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to its test specifications at any time, without notice. The hardware vendor remains solely responsible for the design, sale and functionality of its product, including any liability arising from product infringement or product warranty. Copyright © Intel Corporation 2005. All rights reserved. Intel, the Intel logo, and EtherExpress are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. -
Configuring and Using DDR3 Memory with HP Proliant Gen8 Servers Best Practice Guidelines for Proliant Servers with Intel® Xeon® Processors
Engineering white paper, 2nd Edition Configuring and using DDR3 memory with HP ProLiant Gen8 Servers Best Practice Guidelines for ProLiant servers with Intel® Xeon® processors Table of contents Introduction 3 Overview of DDR3 memory technology 3 Basics of DDR3 memory technology 3 Basics of DIMMs 4 DDR3 DIMM types 5 HP SmartMemory 6 HP Advanced Memory Error Detection 6 ProLiant Gen8 memory architecture for servers with Intel® Xeon® E5-2600 series processors 6 Overview 6 ProLiant Gen8 servers using the Intel® Xeon® E5-2600 series processors 7 ProLiant Gen8 Intel® Xeon® E5-2600 series processors 7 ProLiant Gen8 memory architecture for servers using Intel® Xeon® E5-2400 series processors 8 Overview 8 ProLiant Gen8 servers using Intel® Xeon® E5-2400 series processors 9 ProLiant Gen8 Intel® Xeon® E5-2400 series processors 9 DDR3 DIMMs for ProLiant Gen8 servers 10 Populating memory in ProLiant Gen8 servers 11 ProLiant Gen8 memory slot configurations 11 Population rules for ProLiant Gen8 servers 11 DIMM Population Order 12 Memory system operating speeds 14 General population guidelines 14 Optimizing memory configurations 15 Optimizing for capacity 15 Optimizing for performance 15 Optimizing for lowest power consumption 20 Optimizing for Resiliency 22 Understanding unbalanced memory configurations 23 Memory configurations that are unbalanced across channels 23 Memory configurations that are unbalanced across Processors 23 BIOS Settings for memory 24 Controlling Memory Speed 24 Setting Memory Interleave 25 For more information 26 Appendix A - Sample Configurations for 2P ProLiant Gen8 servers 27 24 DIMM slot servers using Intel® Xeon® E5-2600 processor series 27 16 DIMM Slot Servers using Intel® Xeon® E5-2600 series processors 28 12 DIMM Slot Servers using Intel® Xeon® E5-2400 series processors 29 2 Introduction This paper provides an overview of the new DDR3 memory and its use in the 2 socket HP ProLiant Gen8 servers using the latest Intel® Xeon® E5-2600 series processor family. -
Intel® Omni-Path Fabric Software in Red Hat* Enterprise Linux* 8.1 Release Notes
Intel® Omni-Path Fabric Software in Red Hat* Enterprise Linux* 8.1 Release Notes Rev. 3.0 April 2020 Doc. No.: K65222, Rev.: 3.0 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All product plans and roadmaps are subject to change without notice. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. Copyright © 2019–2020, Intel Corporation. All rights reserved. Intel® Omni-Path Fabric Software in Red Hat* Enterprise Linux* 8.1 Release Notes April 2020 2 Doc. No.: K65222, Rev.: 3.0 Contents—Intel® Omni-Path Fabric Contents 1.0 Overview of the Release............................................................................................... 5 1.1 Audience.............................................................................................................. -
Pro Processor Workstation Performance Brief
Pentium Pro Processor Workstation Performance Brief June 1997 Order Number: 242999-003 Pentium® Pro Processor Workstation Performance Brief Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® Pro processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-7641 or call 1-800-879-4683 or visit Intel’s website at http:\\www.intel.com Copyright © Intel Corporation 1996, 1997. -
Intel® Omni-Path Architecture Overview-Partner.Sales.Training
Intel® Omni-Path Architecture: Overview August 2017 Legal Notices and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life-saving, life- sustaining, critical control or safety systems, or in nuclear facility applications. Intel products may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel may make changes to dates, specifications, product descriptions, and plans referenced in this document at any time, without notice. This document may contain information on products in the design phase of development. The information herein is subject to change without notice. Do not finalize a design with this information. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel Corporation or its subsidiaries in the United States and other countries may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. -
Non-ECC Unbuffered DIMM Non-ECC Vs
Quick Guide to DRAM for Industrial Applications 2019 by SQRAM What’s the difference between DRAM & Flash? DRAM (Dynamic Random Access Memory) and Flash are key components in PC systems, but they are different types of semiconductor products with different speeds/capacity/power-off data storage. High Small Type DRAM Flash Cache data transfer through Location close to CPU PCIe BUS Speed/Cost IC Density low high SRAM Capacity Module 32~64GB 2~8TB Capacity DRAM by ns Speed by ms (faster than flash) non-volatile memory: Power-Off volatile memory: data can be stored if NAND Flash data will lost if powered off Status powered off Low Large What are the features of DRAM? High Data Processing Speed Volatile Memory Extremely fast with low latency by RAM is a type of volatile memory. nanoseconds(10-9) access time. Much faster than It retains its data while powered on, but the data will HDD or SSD data speeds. vanish once the power is off. CPU DRAM HDD Extremely Fast Transfer Higher Capacity, Better Performance DRAM is closely connected to the CPU with short DRAM of higher capacity can process more data to access time. The system performance will drop if increase system performance. The more data data is processed directly by storage without DRAM. processed by DRAM, the less HDD processing time. What are the DDR specifications (DDR, DDR2, DDR3, DDR4)? The prefetch length of DDR SDRAM is 2 bits. On DDR2 the prefetch length is increased to 4 bits, and on DDR3 and on DDR DDR 4 it was raised to 8 bits and 16 bits respectively. -
Initial Experience with 3D Xpoint Main Memory
Initial Experience with 3D XPoint Main Memory Jihang Liu Shimin Chen* State Key Laboratory of Computer Architecture State Key Laboratory of Computer Architecture Institute of Computing Technology, CAS Institute of Computing Technology, CAS University of Chinese Academy of Sciences University of Chinese Academy of Sciences [email protected] [email protected] Abstract—3D XPoint will likely be the first commercially available main memory NVM solution targeting mainstream computer systems. Previous database studies on NVM memory evaluate their proposed techniques mainly on simulated or emulated NVM hardware. In this paper, we report our initial experience experimenting with the real 3D XPoint main memory hardware. I. INTRODUCTION A new generation of Non-Volatile Memory (NVM) tech- nologies, including PCM [1], STT-RAM [2], and Memris- tor [3], are expected to address the DRAM scaling problem and become the next generation main memory technology Fig. 1. AEP machine. in future computer systems [4]–[7]. NVM has become a hot topic in database research in recent years. However, previous First, there are two CPUs in the machine. From the studies evaluate their proposed techniques mainly on simulated /proc/cpuinfo, the CPU model is listed as “Genuine In- or emulated hardware. In this paper, we report our initial tel(R) CPU 0000%@”. Our guess is that the CPU is a test experience with real NVM main memory hardware. model and/or not yet recognized by the Linux kernel. The 3D XPoint is an NVM technology jointly developed by CPU supports the new clwb instruction [9]. Given a memory Intel and Micron [8]. Intel first announced the technology address, clwb writes back to memory the associated cache in 2015. -
Intel® Omni-Path Software — Release Notes for V10.9.2
Intel® Omni-Path Software Release Notes for V10.9.2 Rev. 1.0 March 2019 Doc. No.: K54191, Rev.: 1.0 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. Intel, the Intel logo, Intel Xeon Phi, and Xeon are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2019, Intel Corporation. All rights reserved. Intel® Omni-Path Software Release Notes for V10.9.2 March 2019 2 Doc. No.: K54191, Rev.: 1.0 Contents—Intel® Omni-Path Fabric Contents 1.0 Overview of the Release............................................................................................... 5 1.1 Audience.............................................................................................................. -
Intel® Omni-Path Software — Release Notes for V10.8.0.2
Intel® Omni-Path Software Release Notes for V10.8.0.2 Rev. 1.0 January 2019 Doc. No.: K48500, Rev.: 1.0 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. Intel, the Intel logo, Intel Xeon Phi, and Xeon are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2019, Intel Corporation. All rights reserved. Intel® Omni-Path Software Release Notes for V10.8.0.2 January 2019 2 Doc. No.: K48500, Rev.: 1.0 Contents—Intel® Omni-Path Fabric Contents 1.0 Overview of the Release............................................................................................... 5 1.1 Important Information........................................................................................... -
"Low-Power Support Using Texas Instruments SN74SSTV16857 and SN74SSTV16859"
Application Report SCEA020 - February 2001 Low-Power Support Using Texas Instruments SN74SSTV16857 and SN74SSTV16859 DDR-DIMM Registers Stephen M. Nolan Standard Linear & Logic ABSTRACT The Texas Instruments SN74SSTV16857 and SN74SSTV16859 registers support the low-power mode of the DDR-DIMM. This application report explains the low-power mode and the features of the registers that support the low-power mode. Also, the considerations that the system designer must be aware of when implementing the low-power state of a registered memory module are explained. The sequence that must be followed to utilize the register properly is detailed, including the interpretation of the associated register timing specifications. Finally, the different static- and dynamic-current specifications are analyzed, along with examples of how to calculate the dynamic operating current requirement of the registers. Contents Introduction . 2 Background and Features of Registers. 5 Sequence of Entering and Exiting the Low-Power State. 6 Considerations of Register. 6 How tinact and tact Are Characterized. 9 Dynamic- and Static-Current Specifications. 9 ICC Static Standby Current. 9 ICC Static Operating Current. 10 ICCD Dynamic Operating Current – Clock Only. 10 ICCD Dynamic Operating Current – Each Data Input. 11 Calculating Power Consumption in the Application. 11 Summary . 12 Glossary . 12 List of Figures 1 SN74SSTV16857 . 3 2 SN74SSTV16859 . 4 3 Parameter Measurement Information (VDD = 2.5 V ± 0.2 V). 9 1 SCEA020 Introduction The widespread demand for more main-memory capacity and bandwidth in computer systems has lead to the development of the JEDEC standard for DDR-SDRAM-based, 184-pin, registered memory modules. These DDR DIMMs provide twice the data-bus bandwidth of previous-generation single-data-rate (SDR) memory systems. -
Product Change Notification 104637 – 00
Product Change Notification 104637 – 00 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel® products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Should you have any issues with the timeline or content of this change, please contact the Intel Representative(s) for your geography location listed below. No response from customers will be deemed as acceptance of the change and the change will be implemented pursuant to the key milestones set forth in this attached PCN. Americas Contact: [email protected] Asia Pacific Contact: [email protected] Europe Email: [email protected] Japan Email: [email protected] Copyright © Intel Corporation 2004. Other names and brands may be claimed as the property of others. AlertVIEW, AnyPoint, AppChoice, EtherExpress, FlashFile, i386, i486, i960, Intel, Celeron, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Itanium, LANDesk, LanRover, Pentium, Xeon, Intel Xeon, NetMerge, NetStructure, OverDrive, Paragon, PDCharm, StrataFlash is a trademark or registered trademarks of Intel corporation or its subsidiaries in the United States and other countries.