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Double Data Rate (DDR3) SDRAM Controller IP Core User Guide

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Double Data Rate (DDR3) SDRAM Controller IP Core User Guide Double Data Rate (DDR3) SDRAM Controller IP Core User Guide FPGA-IPUG-02047-2.2 September 2020 Double Data Rate (DDR3) SDRAM Controller IP Core User Guide Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. © 2010-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-IPUG-02047-2.2 Double Data Rate (DDR3) SDRAM Controller IP Core User Guide Contents Acronyms in This Document ................................................................................................................................................. 6 1. Introduction .................................................................................................................................................................. 7 1.1. Quick Facts .......................................................................................................................................................... 7 1.2. Features .............................................................................................................................................................. 9 2. Functional Description ................................................................................................................................................ 10 2.1. Overview ........................................................................................................................................................... 10 2.2. DDR3 MC Module .............................................................................................................................................. 11 2.2.1. Command Decode Logic ............................................................................................................................... 11 2.2.2. Command Application Logic ......................................................................................................................... 11 2.2.3. On-Die Termination ...................................................................................................................................... 11 2.3. DDR3 PHY Module ............................................................................................................................................. 12 2.3.1. Initialization Module .................................................................................................................................... 12 2.3.2. Write Leveling .............................................................................................................................................. 12 2.3.3. Read Training ................................................................................................................................................ 12 2.4. Selecting READ_PULSE_TAP Value (Only for LatticeECP3 Device) .................................................................... 14 2.4.1. Data Path Logic ............................................................................................................................................. 14 2.5. Signal Descriptions ............................................................................................................................................ 15 2.6. Using the Local User Interface .......................................................................................................................... 18 2.6.1. Initialization Control ..................................................................................................................................... 18 2.6.2. Command and Address ................................................................................................................................ 19 2.6.3. User Commands ........................................................................................................................................... 20 2.6.4. WRITE ........................................................................................................................................................... 21 2.6.5. WRITEA ......................................................................................................................................................... 22 2.6.6. READ ............................................................................................................................................................. 22 2.6.7. READA ........................................................................................................................................................... 23 2.6.8. REFRESH Support .......................................................................................................................................... 23 2.7. Local-to-Memory Address Mapping .................................................................................................................. 24 2.8. Mode Register Programming ............................................................................................................................ 25 3. Parameter Settings ..................................................................................................................................................... 27 3.1. Type Tab ............................................................................................................................................................ 29 3.1.1. Device Information ....................................................................................................................................... 30 3.1.2. Memory Configuration ................................................................................................................................. 30 3.1.3. Additional Configuration .............................................................................................................................. 31 3.1.4. Data_rdy to Write Data Delay ...................................................................................................................... 31 3.1.5. Write Leveling ............................................................................................................................................... 31 3.1.6. Controller Reset to Memory......................................................................................................................... 31 3.2. Setting Tab ........................................................................................................................................................ 32 3.2.1. Address ......................................................................................................................................................... 32 3.2.2. Auto Refresh Control .................................................................................................................................... 32 3.2.3. Mode Register initial Setting ........................................................................................................................ 33 3.2.4. Burst Length ................................................................................................................................................. 33 3.3. Memory Device Timing Tab .............................................................................................................................. 34 3.3.1. Manually Adjust ........................................................................................................................................... 34 3.3.2. tCLK - Memory clock ..................................................................................................................................... 34 3.4. Pin Selection Tab ................................................................................................................................................ 36 3.4.1. Manually Adjust ............................................................................................................................................ 36 3.4.2. Pin Side ......................................................................................................................................................... 36 3.4.3. clk_in/PLL Locations ....................................................................................................................................
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