DOCSLIB.ORG

Technical Note Is to Provide an Figure 9: DQS WRITE Postamble and Preamble

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Technical Note Is to Provide an Figure 9: DQS WRITE Postamble and Preamble TN-46-05 GENERAL DDR SDRAM FUNCTIONALITY TECHNICAL GENERAL DDR SDRAM NOTE FUNCTIONALITY INTRODUCTION The migration from single data rate synchronous Table of Contents DRAM (SDR) to double data rate synchronous DRAM DDR vs. SDR Functionality ............................... 2 (DDR) memory is upon us. Although there are many Table 1: SDR to DDR Quick Reference ................. 1 similarities, DDR technology also provides notable Figure 1: Functional Block Diagram .................... 2 product enhancements. Figure 4: Example of DDR Command Bus .......... 3 In general, double data rate memory provides 2n-Prefetch Architecture ................................. 3 source-synchronous data capture at a rate of twice the Figure 2: Block Diagram 2n-Prefetch READ ........ 3 clock frequency. Therefore, a DDR266 device with a Figure 3: Block Diagram 2n-Prefetch WRITE ....... 3 clock frequency of 133 MHz has a peak data transfer rate of 266 Mb/s or 2.1 GB/s for a x64 DIMM. This is Minimum Time Slots ........................................ 3 accomplished by utilizing a 2n-prefetch architecture Figure 5: 2n-Prefetch READ Slot Timing ............. 4 where the internal data bus is twice the width of the Figure 6: 2n-Prefetch WRITE Slot Timing ............ 5 external data bus and data capture occurs twice per Figure 7: READ Command Slots ........................... 6 clock cycle. To provide high-speed signal integrity, the Strobe-Based Data Bus ..................................... 4 DDR SDRAM utilizes a bidirectional data strobe, Preamble and Postamble ................................. 7 SSTL_2 interface with differential inputs and clocks. Figure 8: DQS READ Postamble and Preamble ... 7 The objective of this technical note is to provide an Figure 9: DQS WRITE Postamble and Preamble . 8 overview of the 2n-prefetch architecture, a strobe-based SSTL_2 Interface ............................................... 9 data bus, and the SSTL_2 interface used with DDR Drivers and Receivers ...................................... 9 SDRAM. It will also highlight the functional differences Figure 10: Typical LVCMOS Receiver ................... 9 between SDR and the improved DDR memory technol- Figure 11: Typical SSTL_2 Receiver ...................... 9 ogy. For detailed design and timing criteria for DDR SDRAM-based systems, see Micron's DDR SDRAM data I/O Signaling .................................................... 10 sheets.(http://www.micron.com/ddrsdram.) Figure 12: Typical SSTL_2 Interface and Input Levels ....................................... 10 Clock Inputs ..................................................... 11 Figure 13: SSTL_2 Clocks ..................................... 11 Summary ......................................................... 11 Table 1 SDR to DDR Quick Reference PARAMETER SDR DDR NOTES DQM Yes No Used for write data mask and read OE DM (Data Mask) No Yes Replaces DQM, used to mask write data only DQS (Data Strobe) No Yes New, used to capture data CK# (System Clock) No Yes New, DDR utilizes differential clocks VREF No Yes Reference voltage for differential inputs (1/2 VDD) VDD and VDDQ 3.3 Volts 2.5 Volts Reduced supply and power for DDR Signal Interface LVTTL SSTL_2 DDR utilizes differential I/O Output Drive Fixed Variable x16 DDR devices offer a reduced drive option Data Rate 1x Clock 2x Clock Data transfer is twice the clock rate for DDR Architecture Synchronous Source-Synchronous DDR utilizes a bidirectional data strobe General DDR SDRAM Functionality Micron Technology, Inc., reserves the right to change products or specifications without notice. TN4605.p65 – Rev. A; Pub. 7/01 1 ©2001, Micron Technology, Inc. TN-46-05 GENERAL DDR SDRAM FUNCTIONALITY Figure 1 Functional Block Diagram 2 Meg x 4 Memory Array with SDR and DDR Interface CKE CK# 1 1 DQM CK SDR I/O Interface CS# CONTROL LOGIC WE# DATA Generic Memory Array 4 BANK3 OUTPUT CAS# BANK2 DQM REGISTER DECODE BANK1 Not Used for DDR RAS# COMMAND DQM (SDR) DQ0- Internal Data Bus 4 4 DQ3 REFRESH 12 DATA MODE REGISTERS COUNTER INPUT ROW- BANK0 12 REGISTER ADDRESS ROW- BANK0 MUX ADDRESS 12 4,096 MEMORY 4 LATCH ARRAY 12 AND (4,096 x 1,024 x 8) DECODER SENSE AMPLIFIERS CK 4,096 DDR I/O Interface DATA DLL Internal Data Bus 2 4 I/O GATING x4 for SDR 8 4 READ x8 for DDR MUX A0-A11, ADDRESS LATCH 4 DRVRS 14 BANK BA0, BA1 REGISTER CONTROL 2 DQS 1 LOGIC GENERATOR 1,024 DQ0- (x8) Internal Data Bus COL0 DQ3, DM DQS (DDR) INPUT 8 REGISTERS COLUMN DQS DECODER 1 1 MASK COLUMN- 1 ADDRESS WRITE 1 1 11 COUNTER/ 8 FIFO 2 AND RCVRS LATCH 4 4 COL0 DRIVERS 8 4 1 Not Used for SDR 4 4 ck ck out in DATA COL0 CK 1 DDR VS. SDR FUNCTIONALITY SDR SDRAM is well established and generally un- employs a 2n-prefetch architecture, where the inter- derstood, so questions tend to focus where DDR dif- nal data bus is twice the width of the external bus. This fers from SDR. allows the internal memory cell to pass data to the I/O An examination of the 32 Meg x 4 SDR and DDR buffers in pairs. With DDR, there is no output enable functional block diagrams reveals that the memory core for READ operations, but DDR does support a BURST is essentially the same (see Figure 1). Both have an TERMINATE command to quickly end a READ in pro- identical addressing and command control interface; cess. During a WRITE operation, the DM signal is avail- both have a four-bank memory array; and both incor- able to allow the masking of nonvalid write data. porate the same refresh requirements. The fundamen- The DDR command bus consists of a clock enable, tal differences are found in the data interface. chip select, row and column addresses, bank address, The SDR memory data interface is a fully synchro- and a write enable as shown in Figure 4. Commands are nous design where the data is only captured on the entered on the positive edges of clock, and data occurs positive clock edge. The internal bus is the same width on both positive and negative edges of the clock. as the external data bus and data latches into the inter- The double data rate memory utilizes a differential nal memory array sequentially as it passes through the pair for the system clock and therefore will have both a I/O buffers. SDR memory also supports a DQM signal true clock (CK) and complementary clock (CK#) signal. that acts as a data mask during a WRITE operation or The positive clock edge for DDR refers to the point an output enable for a READ. where the rising clock signal crosses with the falling The DDR memory data is a true source-synchro- complementary clock signal, and the term negative nous design, where the data is captured twice per clock clock edge indicates the transition of the falling clock cycle with a bidirectional data strobe. This architecture and rising complementary clock signals. General DDR SDRAM Functionality Micron Technology, Inc., reserves the right to change products or specifications without notice. TN4605.p65 – Rev. A; Pub. 7/01 2 ©2001, Micron Technology, Inc. TN-46-05 GENERAL DDR SDRAM FUNCTIONALITY 2n-Prefetch Architecture Figure 4 The term DDR (or DDRI) should be specifically as- Example of the DDR Command Bus sociated with the 2n-prefetch device, as future memory designs (DDRII) will use the 4n-prefetch architecture. for a WRITE Cycle To the DRAM vendor, 2n-prefetch means that the internal data bus can be twice the width of the external CK# data bus, and therefore the internal column access CK frequency can be half of the external data transfer rate. That is, for each single read access cycle internal to the CKE HIGH device, two external data words are provided (as shown in Figure 2). Similarly, two external data words written CS# to the device are internally combined and written in one internal access (as shown in Figure 3). RAS# Figure 2 Simplified Block Diagram CAS# of 2n-Prefetch READ WE# n-bit DQS n-bit data Data Register 2n-bit n-bit data CA From data D0 plus DQS All DQ A0–Ai DRAM MUX Q and DQS Core Outputs D1 C n-bit A0–Ai RA Data CLKD Register n-bit DQS data EN AP A10 To the user, from a high-level view, 2n-prefetch DIS AP means that data accesses occur in pairs; i.e., a single read access fetches two data words; and for a single BA0, 1 write access, two data words (and/or data mask bits) BA must be provided. This affects both the minimum burst size and nonminimum burst interruptions. The mini- CA = Column Address mum burst size of a 2n-prefetch architecture is two RA = Row Address external data transfers. Ai = Most Significant Address BA = Bank Address EN AP = Enable Auto Precharge Figure 3 DIS AP = Disable Auto Precharge Simplified Block Diagram of 2n-Prefetch WRITE DON’T CARE n-bit data Minimum Time Slots DQ0-DQi D Q For READs, the controller can choose to ignore ei- n-bit Data ther of the two words, but the time slots for both will be Register occupied (see Figure 5). Similarly, for WRITEs, the con- troller can mask either of the two words, but again, the 2n-bit time slots are occupied (see Figure 6). For each READ or data To D Q D Q DRAM WRITE command (and column address) applied, two n-bit n-bit 2n-bit Core data words are provided. Because the device is double Data data Data Register Register data rate as well as 2n-prefetch, a minimum of two data DQS words is optimal (since commands cannot be applied CK more frequently). General DDR SDRAM Functionality Micron Technology, Inc., reserves the right to change products or specifications without notice. TN4605.p65 – Rev. A; Pub. 7/01 3 ©2001, Micron Technology, Inc. TN-46-05 GENERAL DDR SDRAM FUNCTIONALITY Figure 5 Minimum Data Time Slot for 2n-Prefetch READ CK# CK COMMAND READ READ READ READ NOP NOP ADDRESS Bank, Bank, Bank, Bank, Col n Col x Col b Col g CL = 2 DQS DO DO DO DO DO DO DO DQ n n' x x' b b' g NOTES: 1.
Load more

Recommended publications
  • Double-Data Rate DDR Memory Review
    International Journal of Advanced Engineering and Nano Technology (IJAENT) ISSN: 2347-6389, Volume-2 Issue-2, January 2015 Double-Data Rate DDR Memory Review Ahmed Shamil Mustafa, Mohammed Jabbar Mohammed, Muthana Najim Abdulleh technique became DDR. The technology, synchronous Abstract —Computer is one most important twenty-first century dynamic random access memory (SDRAM) was discovered technology, the large volume of data and store it makes of old in the beginning 1990s to make the computer more powerful, memories are not enough. In this paper we offer a historical in that time was used Traditional DRAM an asynchronous overview of Double Data Rate (DDR) memory being play a key interface it means work independently of the processor. With role in the development of computer with also who passed him in the end of the nineties of the last century and the beginning of addition to the basics of their work and develop in the future. 2000s, specifically in 2000 became a priority for developers Index Terms —Double-Data Rate DDR, Synchronous Dynamic and manufacturers is to produce or something development Random Access Memory (SDRAM) new to increase the performance of the computer, DDR double data rate ( also called DDR 1) is a new interface I. INTRODUCTION method was developed, this made data transfer on both the In the twenty-first century with technology developments, rising and falling edges of the clock signal it has the ability to the entry of the computer at all areas of scientific and social transfer data twice faster than earlier versions, such as life. With the increased demand for computer and the large SDRAM, the had used lower clock rate (100-200MHz), less volume of data has become the task of manufacturing power (2.5v) and high speed(1600-3200 MB/s).
    [Show full text]
  • Design and Implementation of High Speed DDR SDRAM Controller on FPGA
    International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 4 Issue 07, July-2015 Design and Implementation of High Speed DDR SDRAM Controller on FPGA Veena H K Dr. A H Masthan Ali M.Tech Student, Department of ECE, Associate Professor, Department of ECE, Sambhram Institute of Technology, Bangalore, Sambhram Institute of Technology, Bangalore, Karnataka, India Karnataka, India Abstract — The dedicated memory controller is important is and column. To point to a location in the memory these three the applications in high end applications where it doesn’t are mandatory. The ACTIVE command signal along with contains microprocessors. Command signals for memory registered address bits point to the specific bank and row to be refresh, read and write operation and SDRAM initialisation has accessed. And column is given by READ/WRITE signal been provided by memory controller. Our work will focus on along with the registered address bits that shall point to a FPGA implementation of Double Data Rate (DDR) SDRAM location for burst access. The DDR SDRAM interface makes controller. The DDR SDRAM controller is located in between higher transfer rates possible compared to single data rate the DDR SDRAM and bus master. The operations of DDR (SDR) SDRAM, by more firm control of the timing of the SDRAM controller is to simplify the SDRAM command data and clock signals. Implementations frequently have to use interface to the standard system read/ write interface and also schemes such as phase-locked loops (PLL) and self- optimization of the access time of read/write cycle. The proposed design will offers effective power utilization, reduce the gate calibration to reach the required timing precision [1][2].
    [Show full text]
  • "Low-Power Support Using Texas Instruments SN74SSTV16857 and SN74SSTV16859"
    Application Report SCEA020 - February 2001 Low-Power Support Using Texas Instruments SN74SSTV16857 and SN74SSTV16859 DDR-DIMM Registers Stephen M. Nolan Standard Linear & Logic ABSTRACT The Texas Instruments SN74SSTV16857 and SN74SSTV16859 registers support the low-power mode of the DDR-DIMM. This application report explains the low-power mode and the features of the registers that support the low-power mode. Also, the considerations that the system designer must be aware of when implementing the low-power state of a registered memory module are explained. The sequence that must be followed to utilize the register properly is detailed, including the interpretation of the associated register timing specifications. Finally, the different static- and dynamic-current specifications are analyzed, along with examples of how to calculate the dynamic operating current requirement of the registers. Contents Introduction . 2 Background and Features of Registers. 5 Sequence of Entering and Exiting the Low-Power State. 6 Considerations of Register. 6 How tinact and tact Are Characterized. 9 Dynamic- and Static-Current Specifications. 9 ICC Static Standby Current. 9 ICC Static Operating Current. 10 ICCD Dynamic Operating Current – Clock Only. 10 ICCD Dynamic Operating Current – Each Data Input. 11 Calculating Power Consumption in the Application. 11 Summary . 12 Glossary . 12 List of Figures 1 SN74SSTV16857 . 3 2 SN74SSTV16859 . 4 3 Parameter Measurement Information (VDD = 2.5 V ± 0.2 V). 9 1 SCEA020 Introduction The widespread demand for more main-memory capacity and bandwidth in computer systems has lead to the development of the JEDEC standard for DDR-SDRAM-based, 184-pin, registered memory modules. These DDR DIMMs provide twice the data-bus bandwidth of previous-generation single-data-rate (SDR) memory systems.
    [Show full text]
  • AMD Athlon Northbridge with 4X AGP and Next Generation Memory
    AMD AthlonTM Northbridge with 4x AGP and Next Generation Memory Subsystem Chetana Keltcher, Jim Kelly, Ramani Krishnan, John Peck, Steve Polzin, Sridhar Subramanian, Fred Weber Advanced Micro Devices, Sunnyvale, CA * AMD Athlon was formerly code-named AMD-K7 1 Outline of the Talk • Introduction • Architecture • Clocking and Gearbox • Performance • Silicon Statistics • Conclusion 2 Introduction • NorthBridge: “Electronic traffic cop” that directs data flow between the main memory and the rest of the system • Bridge the gap between processor speed and memory speed – Higher bandwidth busses • Example: AGP 2.0, EV6 and AMD Athlon system bus – Better memory technology • Example: Double data rate SDRAM, RDRAM 3 System Block Diagram 100MHz for PC-100 SDRAM AMD Athlon 200MHz for DDR SDRAM System Bus 533-800MHz for RDRAM DRAM CPU 200 MHz, 64 bits NorthBridge Scaleable to 400 MHz 66MHz, 32 bits (1x,2x,4x) Graphics CPU AGP Bus Device 33MHz, 32 bits PCI PCI Bus Devices SouthBridge ISA Bus IDE USBSerial Printer Port Port 4 Features of the AMD Athlon Northbridge • Can support one or two AMD Athlon or EV6 processors • 200MHz data rate (scaleable to 400MHz), 64-bit processor interface • 33MHz, 32-bit PCI 2.2 compliant interface • 66MHz, 32-bit AGP 2.0 compliant interface supports 1x, 2x and 4x data transfer modes • Versions for SDRAM, DDR SDRAM and RDRAM memory • Single bit error correction and multiple bit error detection (ECC) • Distributed Graphics Aperture Remapping Table (GART) • Power management features including powerdown self-refresh of SDRAM
    [Show full text]
  • Powerpc 440GP Embedded Processor
    PRODUCT BRIEF PowerPC 440GP Embedded Processor With speeds of up to 500 MHz and a rich peripheral mix, the PowerPC 440GP embedded processor offers exceptional performance, design flexibility, and robust features for demanding networking, storage and other embedded applications. Its high level of integration — including on-chip SRAM, low power dissipation and small footprint simplify board design and help reduce manufacturing costs. Benefits • Delivers 400 MHz to 500 MHz per- The PowerPC 440 Core link speed of 10 or 100 Mbytes/s in full- or half- To enhance overall throughput, the PowerPC 440 duplex mode, and supports one MII, two RMII or formance (CPU) superscalar core incorporates a 7-stage pipeline two SMII ports. • State-of -the-art peripherals and executes up to two instructions per cycle. Its External Interface including DDR SDRAM and PCI-X large 32-Kbyte data cache and 32-Kbyte instruction cache are 64-way set-associative. To accommodate connectivity with other devices, • On-chip Ethernet for built-in Versatile configurations enhance performance the PowerPC 440GP offers a 32-bit bus supporting up to eight ROM, EPROM, SRAM, Flash, or slave networking tuning while optional parity protection preserves data integrity. For additional system performance, peripheral I/O devices. External bus mastering is • Performance-enhancing features the PowerPC 440 core includes dynamic branch also supported. including superscalar operation, prediction and 24 digital signal processing (DSP) Standard Peripherals large L1 caches, and high-speed bus instructions, as well as non-blocking caches that Functionality is further enhanced with a variety of can be managed in either write-through or write- technology on-chip peripherals.
    [Show full text]
  • Dynamic Random Access Memory Topics
    Dynamic Random Access Memory Topics Simple DRAM Fast Page Mode (FPM) DRAM Extended Data Out (EDO) DRAM Burst EDO (BEDO) DRAM Synchronous DRAM (SDRAM) Rambus DRAM (RDRAM) Double Data Rate (DDR) SDRAM One capacitor and transistor of power, the discharge y Leaks a smallcapacitor amount slowly Simplicit refresh Requires top sk de in ed Us le ti la o v General DRAM Formats • DRAM is produced as integrated circuits (ICs) bonded and mounted into plastic packages with metal pins for connection to control signals and buses • In early use individual DRAM ICs were usually either installed directly to the motherboard or on ISA expansion cards • later they were assembled into multi-chip plug-in modules (DIMMs, SIMMs, etc.) General DRAM formats • Some Standard Module Type: • DRAM chips (Integrated Circuit or IC) • Dual in-line Package (DIP) • DRAM (memory) modules • Single in-line in Package(SIPP) • Single In-line Memory Module (SIMM) • Dual In-line Memory Module (DIMM) • Rambus In-line Memory Module (RIMM) • Small outline DIMM (SO-DIMM) Dual in-line Package (DIP) • is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins • 14 pins Single in-line in Package (SIPP) • It consisted of a small printed circuit board upon which were mounted a number of memory chips. • It had 30 pins along one edge which mated with matching holes in the motherboard of the computer. Single In-line Memory Module (SIMM) SIMM can be a 30 pin memory module or a 72 pin Dual In-line Memory Module (DIMM) Two types of DIMMs: a 168-pin SDRAM module and a 184-pin DDR SDRAM module.
    [Show full text]
  • SDRAM Memory Systems: Architecture Overview and Design Verification SDRAM Memory Systems: Architecture Overview and Design Verification Primer
    Primer SDRAM Memory Systems: Architecture Overview and Design Verification SDRAM Memory Systems: Architecture Overview and Design Verification Primer Table of Contents Introduction . 3 - 4 DRAM Trends . .3 DRAM . 4 - 6 SDRAM . 6 - 9 DDR SDRAM . .6 DDR2 SDRAM . .7 DDR3 SDRAM . .8 DDR4 SDRAM . .9 GDDR and LPDDR . .9 DIMMs . 9 - 13 DIMM Physical Size . 9 DIMM Data Width . 9 DIMM Rank . .10 DIMM Memory Size & Speed . .10 DIMM Architecture . .10 Serial Presence Detect . .12 Memory System Design . .13 - 15 Design Simulation . .13 Design Verification . .13 Verification Strategy . .13 SDRAM Verification . .14 Glossary . .16 - 19 2 www.tektronix.com/memory SDRAM Memory Systems: Architecture Overview and Design Verification Primer Introduction Memory needs to be compatible with a wide variety of memory controller hubs used by the computer DRAM (Dynamic Random Access Memory) is attractive to manufacturers. designers because it provides a broad range of performance Memory needs to work when a mixture of different and is used in a wide variety of memory system designs for manufacturer’s memories is used in the same memory computers and embedded systems. This DRAM memory system of the computer. primer provides an overview of DRAM concepts, presents potential future DRAM developments and offers an overview Open memory standards are useful in helping to ensure for memory design improvement through verification. memory compatibility. DRAM Trends On the other hand, embedded systems typically use a fixed There is a continual demand for computer memories to be memory configuration, meaning the user does not modify larger, faster, lower powered and physically smaller. These the memory system after purchasing the product.
    [Show full text]
  • Double Data Rate (DDR3) SDRAM Controller IP Core User Guide
    Double Data Rate (DDR3) SDRAM Controller IP Core User Guide FPGA-IPUG-02047-2.2 September 2020 Double Data Rate (DDR3) SDRAM Controller IP Core User Guide Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. © 2010-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-IPUG-02047-2.2 Double Data Rate (DDR3) SDRAM Controller IP Core User Guide Contents Acronyms in This Document ................................................................................................................................................
    [Show full text]
  • (ALTDDIO IN, ALTDDIO OUT, and ALTDDIO BIDIR) IP Cores User Guide 2017.06.19
    Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide 2017.06.19 UG-DDRMGAFCTN Subscribe Send Feedback The ALTDDIO IP cores configure the DDR I/O registers in APEX™ II, Arria® II, Arria V, Cyclone® IV, Cyclone V, Cyclone 10 LP, HardCopy®, Stratix® IV, and Stratix V devices. You can also use these IP cores to implement DDR registers in the logic elements (LEs). In Arria GX, Stratix series, HardCopy II, HardCopy Stratix, and APEX II devices, the DDR registers are implemented in the I/O element (IOE). In Cyclone series devices, the IP cores automatically implement the DDR registers in the LEs closest to the pin. The ALTDDIO_IN IP core implements the interface for DDR inputs. The ALTDDIO_OUT IP core implements the interface for DDR outputs. The ALTDDIO_BIDIR IP core implements the interface for bidirectional DDR inputs and outputs. Related Information Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives on page 21 Provides a list of user guides for previous versions of the ALTDDIO IP cores. ALTDDIO Features The ALTDDIO IP cores implement a DDR interface and offer the following additional features: • The ALTDDIO_IN IP core receives data on both edges of the reference clock • The ALTDDIO_OUT IP core transmits data on both edges of the reference clock • The ALTDDIO_BIDIR IP core transmits and receives data on both edges of the reference clock • Asynchronous clear and asynchronous set input options available • Synchronous clear and synchronous set input options available for Arrix GX and Stratix series devices. • inclock signal to sample the DDR input • outclock signal to register the data output • Clock enable signals • Bidirectional port for the ALTDDIO_BIDIR IP core • An output enable input for the ALTDDIO_OUT and ALTDDIO_BIDIR IP cores ALTDDIO Common Applications DDR registers capture and/or send data at twice the rate of the clock or data strobe to interface with a memory device or other high-speed interface application in which the data is clocked at both edges of the clock.
    [Show full text]
  • Jedec Standard
    JEDEC STANDARD Double Data Rate (DDR) SDRAM Specification JESD79C (Revision of JESD79B) MARCH 2003 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an EIA standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org.
    [Show full text]
  • 3.0V SPI Flash Memory Document Number: 001-98284 Orig
    S25FL512S 512 Mbit (64 Mbyte), 3.0 V SPI Flash Memory Features CMOS 3.0 Volt Core with Versatile I/O Data Retention Serial Peripheral Interface with Multi-I/O – 20 Year Data Retention, minimum Density Security features – 512 Mbits (64 Mbytes) – One Time Program (OTP) array of 1024 bytes Serial Peripheral Interface (SPI) – Block Protection: – SPI Clock polarity and phase modes 0 and 3 – Status Register bits to control protection against – Double Data Rate (DDR) option program or erase of a contiguous range of sectors. – Extended Addressing: 32-bit address – Hardware and software control options – Serial Command set and footprint compatible with S25FL- – Advanced Sector Protection (ASP) A, – Individual sector protection controlled by boot code or S25FL-K, and S25FL-P SPI families password – Multi I/O Command set and footprint compatible with Cypress® 65 nm MirrorBit® Technology with Eclipse™ S25FL-P SPI family Architecture READ Commands Core Supply Voltage: 2.7 V to 3.6 V – Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad I/O Supply Voltage: 1.65 V to 3.6 V DDR – SO16 and FBGA packages – AutoBoot - power up or reset and execute a Normal or Temperature Range: Quad read command automatically at a preselected – Industrial (–40 °C to +85 °C) address – Industrial Plus (–40 °C to +105 °C) – Common Flash Interface (CFI) data for configuration – Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C) information. – Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C) Programming (1.5 MB/s) – Automotive, AEC-Q100 Grade 1 (–40 °C to +125 °C) –
    [Show full text]
  • New Features of DDR3 SDRAM
    USER'S MANUAL New Features of DDR3 SDRAM Document No. E1503E10 (Ver.1.0) Date Published March 2009 (K) Japan URL: http://www.elpida.com © Elpida Memory, Inc. 2009 User's Manual E1503E10 (Ver.1.0) 2 Descriptions in this document are provided only for illustrative purpose in semiconductor product operation and application examples. Use these information under the full responsibility of the customer. For details about the functions of individual products, refer to the corresponding data sheet. INTRODUCTION Readers This manual is intended for users who design application systems using double data rate 3 synchronous DRAM (DDR3 SDRAM). Readers of this manual are required to have general knowledge in the fields of electrical engineering, logic circuits, as well as detailed knowledge of the functions and usage of conventional synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), and double data rate 2 synchronous DRAM (DDR2 SDRAM). Explanatory Notes Caution: Information requiring particular attention Note: Footnote for items marked with Note in the text Remarks: Supplementary information Related Documents Related documents indicated in this manual may include preliminary versions, but they may not be explicitly marked as preliminary. Document Name Document No. HOW TO USE SDRAM USER'S MANUAL E0123N HOW TO USE DDR SDRAM USER'S MANUAL E0234E HOW TO USE DDR2 SDRAM USER'S MANUAL E0437E Notice This document is intended to give users understanding of basic functions and usage of DDR3 SDRAM. Descriptions in this document are provided only for illustrative purpose in semiconductor product operation and application examples. And numerical values are not guaranteed values.
    [Show full text]