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2GB DDR3 SDRAM 72Bit SO-DIMM
Apacer Memory Product Specification 2GB DDR3 SDRAM 72bit SO-DIMM Speed Max CAS Component Number of Part Number Bandwidth Density Organization Grade Frequency Latency Composition Rank 0C 78.A2GCB.AF10C 8.5GB/sec 1066Mbps 533MHz CL7 2GB 256Mx72 256Mx8 * 9 1 Specifications z Support ECC error detection and correction z On DIMM Thermal Sensor: YES z Density:2GB z Organization – 256 word x 72 bits, 1rank z Mounting 9 pieces of 2G bits DDR3 SDRAM sealed FBGA z Package: 204-pin socket type small outline dual in line memory module (SO-DIMM) --- PCB height: 30.0mm --- Lead pitch: 0.6mm (pin) --- Lead-free (RoHS compliant) z Power supply: VDD = 1.5V + 0.075V z Eight internal banks for concurrent operation ( components) z Interface: SSTL_15 z Burst lengths (BL): 8 and 4 with Burst Chop (BC) z /CAS Latency (CL): 6,7,8,9 z /CAS Write latency (CWL): 5,6,7 z Precharge: Auto precharge option for each burst access z Refresh: Auto-refresh, self-refresh z Refresh cycles --- Average refresh period 7.8㎲ at 0℃ < TC < +85℃ 3.9㎲ at +85℃ < TC < +95℃ z Operating case temperature range --- TC = 0℃ to +95℃ z Serial presence detect (SPD) z VDDSPD = 3.0V to 3.6V Apacer Memory Product Specification Features z Double-data-rate architecture; two data transfers per clock cycle. z The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. z Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver. z DQS is edge-aligned with data for READs; center aligned with data for WRITEs. -
Product Guide SAMSUNG ELECTRONICS RESERVES the RIGHT to CHANGE PRODUCTS, INFORMATION and SPECIFICATIONS WITHOUT NOTICE
May. 2018 DDR4 SDRAM Memory Product Guide SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2018 Samsung Electronics Co., Ltd. All rights reserved. - 1 - May. 2018 Product Guide DDR4 SDRAM Memory 1. DDR4 SDRAM MEMORY ORDERING INFORMATION 1 2 3 4 5 6 7 8 9 10 11 K 4 A X X X X X X X - X X X X SAMSUNG Memory Speed DRAM Temp & Power DRAM Type Package Type Density Revision Bit Organization Interface (VDD, VDDQ) # of Internal Banks 1. SAMSUNG Memory : K 8. Revision M: 1st Gen. A: 2nd Gen. 2. DRAM : 4 B: 3rd Gen. C: 4th Gen. D: 5th Gen. -
DDR and DDR2 SDRAM Controller Compiler User Guide
DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive Software Version: 9.0 San Jose, CA 95134 Document Date: March 2009 www.altera.com Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap- plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. UG-DDRSDRAM-10.0 Contents Chapter 1. About This Compiler Release Information . 1–1 Device Family Support . 1–1 Features . 1–2 General Description . 1–2 Performance and Resource Utilization . 1–4 Installation and Licensing . 1–5 OpenCore Plus Evaluation . 1–6 Chapter 2. Getting Started Design Flow . 2–1 SOPC Builder Design Flow . 2–1 DDR & DDR2 SDRAM Controller Walkthrough . -
You Need to Know About Ddr4
Overcoming DDR Challenges in High-Performance Designs Mazyar Razzaz, Applications Engineering Jeff Steinheider, Product Marketing September 2018 | AMF-NET-T3267 Company Public – NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2018 NXP B.V. Agenda • Basic DDR SDRAM Structure • DDR3 vs. DDR4 SDRAM Differences • DDR Bring up Issues • Configurations and Validation via QCVS Tool COMPANY PUBLIC 1 BASIC DDR SDRAM STRUCTURE COMPANY PUBLIC 2 Single Transistor Memory Cell Access Transistor Column (bit) line Row (word) line G S D “1” => Vcc “0” => Gnd “precharged” to Vcc/2 Cbit Ccol Storage Parasitic Line Capacitor Vcc/2 Capacitance COMPANY PUBLIC 3 Memory Arrays B0 B1 B2 B3 B4 B5 B6 B7 ROW ADDRESS DECODER ADDRESS ROW W0 W1 W2 SENSE AMPS & WRITE DRIVERS COLUMN ADDRESS DECODER COMPANY PUBLIC 4 Internal Memory Banks • Multiple arrays organized into banks • Multiple banks per memory device − DDR3 – 8 banks, and 3 bank address (BA) bits − DDR4 – 16 banks with 4 banks in each of 4 sub bank groups − Can have one active row in each bank at any given time • Concurrency − Can be opening or closing a row in one bank while accessing another bank Bank 0 Bank 1 Bank 2 Bank 3 Row 0 Row 1 Row 2 Row 3 Row … Row Buffers COMPANY PUBLIC 5 Memory Access • A requested row is ACTIVATED and made accessible through the bank’s row buffers • READ and/or WRITE are issued to the active row in the row buffers • The row is PRECHARGED and is no longer -
Improving DRAM Performance by Parallelizing Refreshes
Improving DRAM Performance by Parallelizing Refreshes with Accesses Kevin Kai-Wei Chang Donghyuk Lee Zeshan Chishti† [email protected] [email protected] [email protected] Alaa R. Alameldeen† Chris Wilkerson† Yoongu Kim Onur Mutlu [email protected] [email protected] [email protected] [email protected] Carnegie Mellon University †Intel Labs Abstract Each DRAM cell must be refreshed periodically every re- fresh interval as specified by the DRAM standards [11, 14]. Modern DRAM cells are periodically refreshed to prevent The exact refresh interval time depends on the DRAM type data loss due to leakage. Commodity DDR (double data rate) (e.g., DDR or LPDDR) and the operating temperature. While DRAM refreshes cells at the rank level. This degrades perfor- DRAM is being refreshed, it becomes unavailable to serve mance significantly because it prevents an entire DRAM rank memory requests. As a result, refresh latency significantly de- from serving memory requests while being refreshed. DRAM de- grades system performance [24, 31, 33, 41] by delaying in- signed for mobile platforms, LPDDR (low power DDR) DRAM, flight memory requests. This problem will become more preva- supports an enhanced mode, called per-bank refresh, that re- lent as DRAM density increases, leading to more DRAM rows freshes cells at the bank level. This enables a bank to be ac- to be refreshed within the same refresh interval. DRAM chip cessed while another in the same rank is being refreshed, alle- density is expected to increase from 8Gb to 32Gb by 2020 as viating part of the negative performance impact of refreshes. -
Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines, External
5. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines June 2012 EMI_DG_005-4.1 EMI_DG_005-4.1 This chapter describes guidelines for implementing dual unbuffered DIMM (UDIMM) DDR2 and DDR3 SDRAM interfaces. This chapter discusses the impact on signal integrity of the data signal with the following conditions in a dual-DIMM configuration: ■ Populating just one slot versus populating both slots ■ Populating slot 1 versus slot 2 when only one DIMM is used ■ On-die termination (ODT) setting of 75 Ω versus an ODT setting of 150 Ω f For detailed information about a single-DIMM DDR2 SDRAM interface, refer to the DDR2 and DDR3 SDRAM Board Design Guidelines chapter. DDR2 SDRAM This section describes guidelines for implementing a dual slot unbuffered DDR2 SDRAM interface, operating at up to 400-MHz and 800-Mbps data rates. Figure 5–1 shows a typical DQS, DQ, and DM signal topology for a dual-DIMM interface configuration using the ODT feature of the DDR2 SDRAM components. Figure 5–1. Dual-DIMM DDR2 SDRAM Interface Configuration (1) VTT Ω RT = 54 DDR2 SDRAM DIMMs (Receiver) Board Trace FPGA Slot 1 Slot 2 (Driver) Board Trace Board Trace Note to Figure 5–1: (1) The parallel termination resistor RT = 54 Ω to VTT at the FPGA end of the line is optional for devices that support dynamic on-chip termination (OCT). © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. -
Datasheet DDR4 SDRAM Revision History
Rev. 1.4, Apr. 2018 M378A5244CB0 M378A1K43CB2 M378A2K43CB1 288pin Unbuffered DIMM based on 8Gb C-die 78FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2018 Samsung Electronics Co., Ltd.GG All rights reserved. - 1 - Rev. 1.4 Unbuffered DIMM datasheet DDR4 SDRAM Revision History Revision No. History Draft Date Remark Editor 1.0 - First SPEC. Release 27th Jun. 2016 - J.Y.Lee 1.1 - Deletion of Function Block Diagram [M378A1K43CB2] on page 11 29th Jun. 2016 - J.Y.Lee - Change of Physical Dimensions [M378A1K43CB1] on page 41 1.11 - Correction of Typo 7th Mar. 2017 - J.Y.Lee 1.2 - Change of Physical Dimensions [M378A1K43CB1] on page 41 23h Mar. -
Double-Data Rate DDR Memory Review
International Journal of Advanced Engineering and Nano Technology (IJAENT) ISSN: 2347-6389, Volume-2 Issue-2, January 2015 Double-Data Rate DDR Memory Review Ahmed Shamil Mustafa, Mohammed Jabbar Mohammed, Muthana Najim Abdulleh technique became DDR. The technology, synchronous Abstract —Computer is one most important twenty-first century dynamic random access memory (SDRAM) was discovered technology, the large volume of data and store it makes of old in the beginning 1990s to make the computer more powerful, memories are not enough. In this paper we offer a historical in that time was used Traditional DRAM an asynchronous overview of Double Data Rate (DDR) memory being play a key interface it means work independently of the processor. With role in the development of computer with also who passed him in the end of the nineties of the last century and the beginning of addition to the basics of their work and develop in the future. 2000s, specifically in 2000 became a priority for developers Index Terms —Double-Data Rate DDR, Synchronous Dynamic and manufacturers is to produce or something development Random Access Memory (SDRAM) new to increase the performance of the computer, DDR double data rate ( also called DDR 1) is a new interface I. INTRODUCTION method was developed, this made data transfer on both the In the twenty-first century with technology developments, rising and falling edges of the clock signal it has the ability to the entry of the computer at all areas of scientific and social transfer data twice faster than earlier versions, such as life. With the increased demand for computer and the large SDRAM, the had used lower clock rate (100-200MHz), less volume of data has become the task of manufacturing power (2.5v) and high speed(1600-3200 MB/s). -
Technical Note Is to Provide an Figure 9: DQS WRITE Postamble and Preamble
TN-46-05 GENERAL DDR SDRAM FUNCTIONALITY TECHNICAL GENERAL DDR SDRAM NOTE FUNCTIONALITY INTRODUCTION The migration from single data rate synchronous Table of Contents DRAM (SDR) to double data rate synchronous DRAM DDR vs. SDR Functionality ............................... 2 (DDR) memory is upon us. Although there are many Table 1: SDR to DDR Quick Reference ................. 1 similarities, DDR technology also provides notable Figure 1: Functional Block Diagram .................... 2 product enhancements. Figure 4: Example of DDR Command Bus .......... 3 In general, double data rate memory provides 2n-Prefetch Architecture ................................. 3 source-synchronous data capture at a rate of twice the Figure 2: Block Diagram 2n-Prefetch READ ........ 3 clock frequency. Therefore, a DDR266 device with a Figure 3: Block Diagram 2n-Prefetch WRITE ....... 3 clock frequency of 133 MHz has a peak data transfer rate of 266 Mb/s or 2.1 GB/s for a x64 DIMM. This is Minimum Time Slots ........................................ 3 accomplished by utilizing a 2n-prefetch architecture Figure 5: 2n-Prefetch READ Slot Timing ............. 4 where the internal data bus is twice the width of the Figure 6: 2n-Prefetch WRITE Slot Timing ............ 5 external data bus and data capture occurs twice per Figure 7: READ Command Slots ........................... 6 clock cycle. To provide high-speed signal integrity, the Strobe-Based Data Bus ..................................... 4 DDR SDRAM utilizes a bidirectional data strobe, Preamble and Postamble ................................. 7 SSTL_2 interface with differential inputs and clocks. Figure 8: DQS READ Postamble and Preamble ... 7 The objective of this technical note is to provide an Figure 9: DQS WRITE Postamble and Preamble . 8 overview of the 2n-prefetch architecture, a strobe-based SSTL_2 Interface .............................................. -
Design and Implementation of High Speed DDR SDRAM Controller on FPGA
International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 4 Issue 07, July-2015 Design and Implementation of High Speed DDR SDRAM Controller on FPGA Veena H K Dr. A H Masthan Ali M.Tech Student, Department of ECE, Associate Professor, Department of ECE, Sambhram Institute of Technology, Bangalore, Sambhram Institute of Technology, Bangalore, Karnataka, India Karnataka, India Abstract — The dedicated memory controller is important is and column. To point to a location in the memory these three the applications in high end applications where it doesn’t are mandatory. The ACTIVE command signal along with contains microprocessors. Command signals for memory registered address bits point to the specific bank and row to be refresh, read and write operation and SDRAM initialisation has accessed. And column is given by READ/WRITE signal been provided by memory controller. Our work will focus on along with the registered address bits that shall point to a FPGA implementation of Double Data Rate (DDR) SDRAM location for burst access. The DDR SDRAM interface makes controller. The DDR SDRAM controller is located in between higher transfer rates possible compared to single data rate the DDR SDRAM and bus master. The operations of DDR (SDR) SDRAM, by more firm control of the timing of the SDRAM controller is to simplify the SDRAM command data and clock signals. Implementations frequently have to use interface to the standard system read/ write interface and also schemes such as phase-locked loops (PLL) and self- optimization of the access time of read/write cycle. The proposed design will offers effective power utilization, reduce the gate calibration to reach the required timing precision [1][2]. -
64M X 16 Bit DDRII Synchronous DRAM (SDRAM) Advance (Rev
AS4C64M16D2A-25BAN Revision History 1Gb Auto-AS4C64M16D2A - 84 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Jan 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 62 - Rev.1.0 Jan. 2018 AS4C64M16D2A-25BAN 64M x 16 bit DDRII Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Jan. /2018) Features Overview JEDEC Standard Compliant The AS4C64M16D2A is a high-speed CMOS Double- AEC-Q100 Compliant Data-Rate-Two (DDR2), synchronous dynamic random- JEDEC standard 1.8V I/O (SSTL_18-compatible) access memory (SDRAM) containing 1024 Mbits in a 16-bit wide data I/Os. It is internally configured as a 8- Power supplies: V & V = +1.8V 0.1V DD DDQ bank DRAM, 8 banks x 8Mb addresses x 16 I/Os. The Operating temperature: TC = -40~105°C (Automotive) device is designed to comply with DDR2 DRAM key Supports JEDEC clock jitter specification features such as posted CAS# with additive latency, Fully synchronous operation Write latency = Read latency -1, Off-Chip Driver (OCD) Fast clock rate: 400 MHz impedance adjustment, and On Die Termination(ODT). Differential Clock, CK & CK# All of the control and address inputs are synchronized Bidirectional single/differential data strobe with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK - DQS & DQS# rising and CK# falling) All I/Os are synchronized with a 8 internal banks for concurrent operation pair of bidirectional strobes (DQS and DQS#) in a source 4-bit prefetch architecture synchronous fashion. -
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices.Pdf
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 AN-436-4.0 Introduction DDR3 SDRAM is the latest generation of DDR SDRAM technology, with improvements that include lower power consumption, higher data bandwidth, enhanced signal quality with multiple on-die termination (ODT) selection and output driver impedance control. DDR3 SDRAM brings higher memory performance to a broad range of applications, such as PCs, embedded processor systems, image processing, storage, communications, and networking. Although DDR2 SDRAM is currently the more popular SDRAM, to save system power and increase system performance you should consider using DDR3 SDRAM. DDR3 SDRAM offers lower power by using 1.5 V for the supply and I/O voltage compared to the 1.8-V supply and I/O voltage used by DDR2 SDRAM. DDR3 SDRAM also has better maximum throughput compared to DDR2 SDRAM by increasing the data rate per pin and the number of banks (8 banks are standard). 1 The Altera® ALTMEMPHY megafunction and DDR3 SDRAM high-performance controller only support local interfaces running at half the rate of the memory interface. Altera Stratix® III and Stratix IV devices support DDR3 SDRAM interfaces with dedicated DQS, write-, and read-leveling circuitry. Table 1 displays the maximum clock frequency for DDR3 SDRAM in Stratix III devices. Table 1. DDR3 SDRAM Maximum Clock Frequency Supported in Stratix III Devices (Note 1), (2) Speed Grade fMAX (MHz) –2 533 (3) –3 and I3 400 –4, 4L, and I4L at 1.1 V 333 (4), (5) –4, 4L, and I4L at 0.9 V Not supported Notes to Table 1: (1) Numbers are preliminary until characterization is final.