INTRODUCTION TO ISA

INTRODUCTION TO • The Instruction Set Architecture of a Instruction Set Architecture microprocessor include the followings: – Instruction specific set , instruction formats and (ISA) types – Supported data types by the instruction set, and – Operating context for the instructions.

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ISA Main desirable features of an ISA interface between software and hardware • Regularity (Orthogonality) - Common set of formats, few special cases . The ability to use all relevant addressing modes in a uniform and consistent way with all opcodes of an instruction set or C program ASM program assembly language. – Orthogonal instruction sets simplify programming (reduced number of ASM program assembled distinct opcodes and simplified rules for operand address C program compiled to ISA program specification) to ISA program – Most computers have very little orthogonality ( reduce processor costs Software at the expense of programming costs ) ISA level • Completeness - Support for a wide range of operations and target applications Hardware ISA program executed by – Operators have different frequency of utilization microprogram or hardware – There must censor the set of operators – The rule for design an ISA is: “ Execute fast the frequent operations Hardware and correct the infrequent one ”.

3 4 MICROPROCESSORS MICROPROCESSORS INSTRUCTION FORMAT INSTRUCTION FORMAT • Length: – fixed length for the entire Typical fields: • Operation code field - specifies the operation to be performed. instruction set • Operand specifications - specify the mode to compute addresses to operands

– variable length for the OPCODE OP1 OP2 OP3 recognized instruction set

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Conventions for ordering and addressing DIFFERENT INSTRUCTION FORMATS the bytes within a word in memory

• For multiple-byte words stored in Main Memory there are OPCODE Zero address instruction two different conventions: – Little Endian Big Indian OPCODE ADDRESS One-address instruction – Big Endian Little Indian

OPCODE ADDRESS1 ADDRESS2 Two-address instruction

OPCODE ADDR1 ADDR2 ADDR3 Three-address instruction

7 8 MICROPROCESSORS MICROPROCESSORS Conventions for ordering and addressing Conventions for ordering and addressing the bytes within a word in memory the bytes within a word in memory

• For multiple-byte words stored in Main Memory there are two different conventions: – Little Endian • Little Endian byte order puts the byte whose address is – Big Endian "x...x00" at the least significant position in the word (the little end) Big Indian File (Indian queue): Little Indian File (Indian queue): • In Little Endian, the address of a datum is the address of The big one is the first The little one is the first the least significant byte (LSB)

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Conventions for ordering and addressing Little vs. Big Endian the bytes within a word in memory Example word: 6A0244FFh (on 32 bits) Little Endian Big Endian

Most significant memory address Least significant memory address byte in word 1 byte in word 1

x0000 FF x0000 6A

• Big Endian byte order puts the byte whose address x0001 44 x0001 02 word 1 word 1 is "x...x00" at the most significant position in the x0002 02 x0002 44

word (the big end) x0003 6A x0003 FF Most significant Least significant • In Big Endian addressing, the address of a datum x0004 byte in word 1 x0004 byte in word 1 is the address of the most significant byte (MSB) x0005 x0005 word 2 word 2 x0006 x0006

x0007 x0007

x0008 x0008

11 12 MICROPROCESSORS MICROPROCESSORS ALIGNED INFORMATION IN MEMORY A 4 byte word in a little endian memory Aligned vs. not-aligned

• In some machines accesses to objects (instructions, data, addresses) larger Data bus than a byte must be aligned • Misalignment causes hardware complications , since the memory is typically aligned on a word boundary . A misaligned memory access will, therefore, 32 bits take multiple aligned memory references memory address 8 bits 8 bits 8 bits 8 bits • The information stored at address A having the dimension D bytes , is aligned if: x0000 Byte 0 Byte 1 Byte 2 Byte 3 word 1 aligned at A modulo D = 0 address x0000h x0004 • For example, if D=4 Bytes Address 0: 0 modulo 4 = 0 x0008 Byte 0 Byte 1 word 2 misaligned at Address 1: 1 modulo 4 = 1 x000C address x000Ah Address 2: 2 modulo 4 = 2 Byte 2 Byte 3 Address 3: 3 modulo 4 = 3 x0010 Address 4: 4 modulo 4 = 0 Address 5: 5 modulo 4 = 1

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Number of explicit addresses: Example Classifying ISAs Number of Instruction Comment Operand storage in the CPU Where are operands kept other than in memory? addresses Format Number of explicit operands How many operands are named explicitly in a per instruction typical instruction? 3 add z,x,y ; z ← x+y or y ← z + x

Operand location Can any ALU instruction operand be located in memory or must some or all of the operands be 2 add x,y ;x ←x+y or Ac ← x+y in internal storage in the CPU? If an operand is located in memory, how is the memory location specified? 1 add x ; Ac ← Ac+x Operations What operations are provided in the instruction set? ; add the two articles from the 0 add ;Top of the Stack (ToS) and store the result in Type and size of operands What is the type and size of each operand and ;the new ToS how is it specified?

15 16 MICROPROCESSORS MICROPROCESSORS Classifying ISAs Example of instructions

(type of internal storage) Organization Instruction Comment Type Format

AC add x ;Ac ← Ac + x or Ac ← Ac + @x

‹ stack machine (stack organization) add r1,r2,r3 ; r1 ← r2 + r3 add r1,r2 ; r1 ← r1 + r2 or r2 ← r1 + r2 ‹ accumulator machine (acc. organization) RG mov r1,r2 ; r1 ← r2 ‹ general-purpose register machine (GPR add r1,x ; r1 ← r1 + @x organization) ;ToS ← @x push x ST ;the top two operands in the stack are add ;extracted, added, and then the result pushed ;on the stack

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Advantages and disadvantages Example GPR architecture program • AC: short instructions, high cod • AC: Since accumulator is only x = a*(b+c) density temporary storage, memory traffic is highest for this approach • 3 address instructions (CISC): • RG: Most general model for code • RG : All operands must be named, add r1,b,c ;r1 ← @b + @c leading to longer instructions generation mul x,r1,a ;@x ← r1 * @a • 3 address instructions (RISC - load/store architecture) • SP: Simple model of expression • SP: A stack cannot be randomly ← evaluation (reverse polish). Short accessed, difficult to generate load r1,a ; r1 @a) instructions can yield good code efficient code, stack becomes a load r2,b ; r2 ← @b) bottleneck density load r3,c ; add r2,r2,r3 ; r2 ← (r2 + r3) mul r1,r1,r2 ; r1 ← (r1 * r2) • x=a*(b+c)written abc+* storex,r1 ; @x ← r1 • x = (a+b)*(c+d) written ab+cd+* • x = (a+b)*(c+d)*(e+f) written ab+cd+ef+** 19 20 MICROPROCESSORS MICROPROCESSORS Example GPRA program (con’t) Example Accumulator architecture x = a*(b+c) program for: x = a*(b+c)

load b ; ac ← @b • 2 address instructions: add c ; ac ← ac + @c movr1,b ;r1 ← @b storet ; @t ← ac add r1,c ;r1 ← r1 + @c ← mulr1,a ;r1 ← r1 * @a load a ; ac @a movx,r1 ;@x ← r1 mul t ; ac ← ac * @t store x ; @x ← ac

where t is a temporary memory location.

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Example Stack architecture program for: x = a*(b+c) Polish notation (suffix notation)

push a ;TopS ← @a, let adr be the current address • x*y writed as xy * ;of the top of stack (TopS) • x = a*(b+c) = abc+* push b ;TopS ← @b, at adr-1 Remember: push, push, push, add, mul push c ;TopS ← @c, at adr -2 • Other examples: add ;TopS ← (b + c), stored at adr-1 mul ;TopS ← a*(b+c), stored at adr . x = (a+b)*(c+d) = ab+cd+* pop x ;@x ← TopS, TopS point at address adr+1 x = (a+b)*(c+d)*(e+f) = ab+cd+ef+**

23 24 MICROPROCESSORS MICROPROCESSORS RISC versus CISC

• Load-and-store architecture. Only • Instructions address operands in LOAD and STORE instructions reference data in memory memory • Instructions are of fixed length and • Variable length instructions uniform format • Control unit microprogrammed • Control unit hardwired • Complex instructions, many instruction Instruction Set Architecture • The instruction set include only simple types and addressing modes instructions, few instruction types and • More difficult administration of (ISA) addressing modes pipelines • Efficient pipelines (instructions are simple and of similar execution time. • Relatively low number of internal registers. • A large number of registers is available • Use compilers to optimize object code •Addressing modes performance, by resolving pipeline hazards (situations that prevent the next •Instruction Types instruction in the instruction stream from executing during its designated clock cycle).

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ADDRESSING MODES ADDRESSING MODES

• Addressing modes = how architectures specify the address • We shall use the following notation for describing EA: of an object they will access. ° #value = Immediate data • Addressing modes refer not only to operands , but also to ° x = Memory location instructions (sequencing of instructions) ° d = displacement, a signed number • Operands can be located in different places: in the ° Rn = Register n instruction format (one binary field), internal registers, ° (Rn) = Register deferred main memory, input / output ports. ° (Rn)+ = Auto (post)increment • For every addressing mode recognized, the Control Unit ° -(Rn) = Auto (pre)decrement compute an Effective Address (EA) for the operand ° @Rn = address contained in Rn ° @x = address contained in memory location X – EA is used to find an object in the main memory

27 28 MICROPROCESSORS MICROPROCESSORS Classification of addressing modes TYPES OF OPERANDS

• We classify the addressing modes in the • Immediate following types: • In (internal) registers 1. immediate addressing • In (main) memory 2. direct addressing • In I/O port registers 3. indirect addressing 4. relative addressing 5. index addressing

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1. Immediate addressing 1. Immediate addressing Examples: Instruction format main memory • Intel 8086 opcode immediate data address LDI #853 ß and al,0FFh a: opcode ß mov ax,3A40h

a+1: Data low byte ß mov al,5

Data high byte ß mov ax,5 a+2: • Atmel 89C51 family: a+3: ß mov r1,#0ffh ß add a,#10111011b

31 32 MICROPROCESSORS MICROPROCESSORS 2. Direct addressing Direct to register addressing

• EA = X ; direct to memory (absolute or extended) • EA = R ; direct to register (explicit or implicit) Instruction format address • EA = adr_port; direct to IO port REG address a: Op-code

a+1: Instruction format main memory op -code EA a+2: opcode address a+3: Opcode address REG operand

EA operand

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2. Direct addressing 3. Indirect addressing Examples:

• EA = @Rn ; indirect by means of register (register deferred) • Intel x86 – out p8,al • EA = @X ; indirect by means of memory (memory deferred) – in ax,p8 – mov ax,[3a40h] ;ds:[3a40] →AL, ds:[3a41] →AH – mov ax, there • Atmel 89C51 family: – mov 44h,058h

35 36 MICROPROCESSORS MICROPROCESSORS 3. Indirect addressing 3. Indirect addressing - Examples

Example: indirect by register – mov r2,@r3 – mov @r3,r1 Main memory – add r1,@r5 Opcode • Intel x86 Address of a – mov ax,[bx] register R – mov al,[si] – in ax,dx

Operand address operand – out dx,al

R = addressing register – out dx,ax

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3. Indirect addressing - Variants 3. Indirect addressing to the stack (through SP) • a. auto-post-incremented register indirect • push Source can be written – Ex: mov R1,@R4+ mov −−−@SP,Source • b. auto-post-decremented register indirect SP ← SP – N (N=number of bytes pushed in stack by the current – Ex: mov R1,@R4 - operation) @SP ← Source • c. auto-pre-incremented register indirect – Ex: mov R1,+@R4 • pop Destination can be written • d. auto-pre-decremented register indirect mov Destination,@SP+ – Ex: mov R1,-@R4 Destination ← @SP SP ← SP + N

39 40 MICROPROCESSORS MICROPROCESSORS Instruction’s indirect addressing 4. Relative addressing (through PC – sequential addressing ) a) Base register addressing (indirect by register and displacement). R is called a "base register ” EA = @(R + d) • Ex: mov ax,[bx]+8 also written mov ax,[bx+8] • When executing a linear instruction sequence the b) Program Counter (PC) relative addressing . PC microprocessor use an indirect auto-post-incrementing symbolized by * addressing, called sequential addressing mode EA = @(PC+d) addr1: mov dx,there ; 3 bytes AE = @PC+ mov ax,1732h ;3 bytes mov bx,cx ;2 bytes jmp *-9 ;2 bytes

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4. Relative addressing 5. Indexed addressing

• Only partial addressing information is included in the • Similar with the relative addressing. instruction, so the processor must construct the complete • EA = @(Ri + d), or (absolute) operand address • EA = @(Ri + X), or • The instruction contain a (signed) displacement d. • EA = @(Ri + Rn) • Since all the address information need not be included in • but the instructions, instruction length is reduced. - it applies only to data addresses • By changing the contents of R, the processor can change - Ri store indices (not base address) - index register . The the absolute address referred to by a block of instructions instruction address field d contains the address of the first item B. This permits the processor to move (relocate) the entire X(0), while the index register Ri contains the index i. The address of item X(i) is D+Ri. block B from one region of main memory to another - R change = autoincrement, autodecrement without invalidating the address in B

43 44 MICROPROCESSORS MICROPROCESSORS 5. Indexed addressing INSTRUCTION TYPES – requirements

• It should be complete in the sense that one should be able to • The number of index registers of a processor construct a machine-language program to evaluate any function suggests the number of potential vectors in that is computable using a reasonable amount of memory space. • The instruction set should be efficient in that frequently required memory, and the dimension of displacement functions can be performed rapidly using relatively few indicates the maximum dimension of vectors. instructions. • It should be regular in that the instruction set should contain • There are also some combination in index expected opcodes and addressing modes, e.g., if there is a left addressing, with pre or post incrementing / shift, there should be a right shift. The instruction set should also be reasonably orthogonal with respect to the addressing decrementing. modes. • To reduce both hardware and software design costs, the instructions may be required to be compatible with those of existing machines, e.g. previous members of the same computer family. 45 46 MICROPROCESSORS MICROPROCESSORS

INSTRUCTION TYPES 1. DATA TRANSFER INSTRUCTIONS

• Usually a data transfer is a copy operation . Execution of data transfer instructions does not modify the condition flags (sign, carry, auxiliary carry, • Data transfer instructions overflow, parity, and zero). • The data-transfer instructions, particularly load and store, are the most • Arithmetic instructions frequently used instructions in computer programs, despite the fact that they • Logical instructions involve no explicit computation • MOVE Transfer word or block from S to D • Shift and Rotate instructions (Arithmetic & • STORE Transfer word from processor to external memory • LOAD Transfer word from external memory to processor Logic) • EXCHANGE Swap contents of source and destination • Program control instructions (branch • CLEAR Transfer word of 0s to destination • SET Transfer word of 1s to destination instructions) • PUSH Transfer word from source to top of stack • Processor control instructions • POP (PULL) Transfer word from top of stack to source • IN / OUT Transfer with IO ports

47 48 MICROPROCESSORS MICROPROCESSORS 1. Examples: Data transfers (I8086) 2. ARITHMETIC INSTRUCTIONS

• These instructions modify condition flags according to the result of the executed arithmetic instruction. ← • general purpose MOV D,S ;D S • ADD Compute sum of two operands ↔ XCHG D,S ;D S • SUBTRACT Compute difference of two operands • stack transfer PUSH S / POP D • MULTIPLY Compute product of two operands PUSHF / POPF • DIVIDE Compute quotient (and remainder) of two operands ← • address transfer LEA r16,adr ;(r16) ad r • ABSOLUTE Replace operand by its absolute value ← LDS r16,adr ;r16Low [DS:adr] • NEGATE Change sign of operand (in two's complement!) ← ;r16High [DS:(adr+1)] • INCREMENT Add 1 to operand ;DSLow ← [DS:(adr+2)] • DECREMENT Subtract 1 from operand ;DSHigh ← [DS:(adr+3)] • COMPARE Arithmetic comparison (subtraction); set flag(s) based • I/Otransfer IN AL,adr ; AL ← adr (port) on outcome IN AX,adr ; AL ← adr (port), 16 bits IN AL,DX ; AL ← (DX) OUT adr,AL OUT DX,AL 49 50 MICROPROCESSORS MICROPROCESSORS

2. Examples: ARITHMETIC (Intel 8086) 3. LOGICAL INSTRUCTIONS

ADD D,S MUL S • The logical instructions usually include the basic word- based Boolean operations ADC D,S IMUL S • The logical instructions perform the specified logical SUB D,S DIV S operation bitwise • These instructions modify condition flags according to the SBB D,S IDIV S result of the executed logical instruction INC D NEG D • AND DEC D CMP D,S • OR • NOT (COMPLEMENT) DAA DAS • EXCLUSIV-OR • CONVERT (EDIT)

51 52 MICROPROCESSORS MICROPROCESSORS 3. Examples: LOGICAL (Intel 8086) 4. Shift and Rotate instructions

• AND D,S • Shift operations can be logical (Boolean operations bit oriented, for entire words), or Arithmetic • OR D,S • XOR D,S • Rotates are closed shifts and are only logical operations • NOT D • Shift and Rotate instructions modify the condition flags • TEST D,S according to the result of the executed instruction

• All operations use Carry Flag

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4. Examples: Shift (I 8086) 4. Examples: Rotate (I 8086)

• SAL D,1 • ROL D,1 • SHL D,1 CF CF CF 0 ……..

D D D

CF • RCL D,1 …….. 0 CF CF D ……..

D 55 D 56 MICROPROCESSORS MICROPROCESSORS 4. Examples: Shift (I 8086) 4. Examples: Rotate (I 8086)

CF • ROR D,1 CF • SAR D,1

D D Semn CF

CF • SHR D,1 0 • RCR D,1

D

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5. PROGRAM CONTROL BRANCHES INSTRUCTIONS

• These instructions change the flow of control. Usually it is used the name jump when the change of control is unconditional and branch when the change is conditional • We can distinguish two main types of control-flow change: • Unconditional branches – procedure calls = CALL op – absolute jump = JMP op – procedure returns = RET • Conditional branches – Jcc - Jump if condition TRUE – CALL if condition TRUE – repeat if condition TRUE

59 60 MICROPROCESSORS MICROPROCESSORS Example I8086 6. Processor control (for conditional jump instructions that test the condition flags after the operation A-B: instructions

• Above, Below, Equal, Not, Greater, Less, Carry, Zero, Overflow, Parity (PEven, POdd), Sign (semn) • Control the operation of the processor and act either as control flags / registers , or by introducing a special states for the processor in order to synchronize the processor with external events

Conditional Jump Instructions unsigned numbers signed numbers • CMC • CLI A > B JA/JNBE (CF = 0 and ZF = 0) JG/JNLE (ZF = 0 and SF = OF) • CLC • STI • STC • HLT A ≥ B JAE/JNB/JNC (CF = 0) JGE/JNL (SF = OF) • NOP • WAIT A = B JE/JZ (ZF = 1) • CLD • ESC A ≤ B JBE/JNA (CF = 1 or ZF = 1) JLE/JNG (if SF != OF or ZF = 1) • STD • LOCK A < B JB/JNAE/JC (CF = 1) JL/JNGE (SF != OF)

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