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Microcontrollers S12CPUV2 Reference Manual HCS12 Microcontrollers S12CPUV2/D Rev. 0 7/2003 MOTOROLA.COM/SEMICONDUCTORS S12CPUV2 Reference Manual To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://motorola.com/semiconductors The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. This product incorporates SuperFlash® technology licensed from SST. © Motorola, Inc., 2003 S12CPUV2 Reference Manual MOTOROLA 3 Revision History Revision History Revision Page Date Description Level Number(s) July, 0 Initial release N/A 2003 Reference Manual S12CPUV2 4 Revision History MOTOROLA Reference Manual — S12CPUV2 List of Sections Revision History 4 List of Sections 5 Table of Contents 7 List of Figures 15 List of Tables 17 Section 1. Introduction . .19 Section 2. Overview . .25 Section 3. Addressing Modes . .33 Section 4. Instruction Queue . .51 Section 5. Instruction Set Overview . .59 Section 6. Instruction Glossary . .91 Section 7. Exception Processing. .315 Section 8. Instruction Queue . .327 Section 9. Fuzzy Logic Support. .341 Appendix A. Instruction Reference . .381 Appendix B. M68HC11 to CPU12 Upgrade Path. .409 Appendix C. High-Level Language Support . .431 Index 439 S12CPUV2 Reference Manual MOTOROLA List of Sections 5 List of Sections Reference Manual S12CPUV2 6 List of Sections MOTOROLA Reference Manual — S12CPUV2 Table of Contents Revision History 4 List of Sections 5 Table of Contents 7 List of Figures 15 List of Tables 17 Section 1. Introduction 1.1 Introduction. .19 1.2 Features . .19 1.3 Symbols and Notation. .20 1.3.1 Abbreviations for System Resources . .20 1.3.2 Memory and Addressing . .21 1.3.3 Operators . .22 1.3.4 Definitions. .23 Section 2. Overview 2.1 Introduction. .25 2.2 Programming Model . .25 2.2.1 Accumulators . .26 2.2.2 Index Registers . .26 2.2.3 Stack Pointer . .26 2.2.4 Program Counter . .27 2.2.5 Condition Code Register . .27 2.2.5.1 S Control Bit . .28 2.2.5.2 X Mask Bit. .29 2.2.5.3 H Status Bit. .29 2.2.5.4 I Mask Bit . .30 2.2.5.5 N Status Bit. .30 2.2.5.6 Z Status Bit . .30 2.2.5.7 V Status Bit. .31 S12CPUV2 Reference Manual MOTOROLA Table of Contents 7 Table of Contents 2.2.5.8 C Status Bit. .31 2.3 Data Types . .31 2.4 Memory Organization . .32 2.5 Instruction Queue . .32 Section 3. Addressing Modes 3.1 Introduction. .33 3.2 Mode Summary . .33 3.3 Effective Address . .33 3.4 Inherent Addressing Mode . .35 3.5 Immediate Addressing Mode . .35 3.6 Direct Addressing Mode . .36 3.7 Extended Addressing Mode . .37 3.8 Relative Addressing Mode . .37 3.9 Indexed Addressing Modes . .38 3.9.1 5-Bit Constant Offset Indexed Addressing . .41 3.9.2 9-Bit Constant Offset Indexed Addressing . .41 3.9.3 16-Bit Constant Offset Indexed Addressing . .42 3.9.4 16-Bit Constant Indirect Indexed Addressing . .42 3.9.5 Auto Pre/Post Decrement/Increment Indexed Addressing. .43 3.9.6 Accumulator Offset Indexed Addressing . .44 3.9.7 Accumulator D Indirect Indexed Addressing . .45 3.10 Instructions Using Multiple Modes . .45 3.10.1 Move Instructions . .45 3.10.2 Bit Manipulation Instructions . .47 3.11 Addressing More than 64 Kbytes . .48 Section 4. Instruction Queue 4.1 Introduction. .51 4.2 Queue Description . .51 4.2.1 Original M68HC12 Queue Implementation . .52 4.2.2 HCS12 Queue Implementation . .52 4.3 Data Movement in the Queue. .52 4.3.1 No Movement . .53 Reference Manual S12CPUV2 8 Table of Contents MOTOROLA Table of Contents 4.3.2 Latch Data from Bus (Applies Only to the M68HC12 Queue Implementation)53 4.3.3 Advance and Load from Data Bus . .53 4.3.4 Advance and Load from Buffer (Applies Only to M68HC12 Queue Implementation)53 4.4 Changes in Execution Flow . .53 4.4.1 Exceptions . .54 4.4.2 Subroutines . .54 4.4.3 Branches . .55 4.4.3.1 Short Branches . .56 4.4.3.2 Long Branches. .56 4.4.3.3 Bit Condition Branches. .57 4.4.3.4 Loop Primitives. .57 4.4.4 Jumps. .58 Section 5. Instruction Set Overview 5.1 Introduction. .59 5.2 Instruction Set Description . .59 5.3 Load and Store Instructions . .60 5.4 Transfer and Exchange Instructions . .61 5.5 Move Instructions . .62 5.6 Addition and Subtraction Instructions . .63 5.7 Binary-Coded Decimal Instructions . .64 5.8 Decrement and Increment Instructions. .65 5.9 Compare and Test Instructions. .66 5.10 Boolean Logic Instructions . .67 5.11 Clear, Complement, and Negate Instructions. .68 5.12 Multiplication and Division Instructions . .69 5.13 Bit Test and Manipulation Instructions . .70 5.14 Shift and Rotate Instructions. .71 5.15 Fuzzy Logic Instructions . .72 5.15.1 Fuzzy Logic Membership Instruction . .72 5.15.2 Fuzzy Logic Rule Evaluation Instructions. .72 5.15.3 Fuzzy Logic Weighted Average Instruction . .73 S12CPUV2 Reference Manual MOTOROLA Table of Contents 9 Table of Contents 5.16 Maximum and Minimum Instructions . .75 5.17 Multiply and Accumulate Instruction . .76 5.18 Table Interpolation Instructions. .76 5.19 Branch Instructions. .77 5.19.1 Short Branch Instructions . .78 5.19.2 Long Branch Instructions . .79 5.19.3 Bit Condition Branch Instructions . .80 5.20 Loop Primitive Instructions . .81 5.21 Jump and Subroutine Instructions . .82 5.22 Interrupt Instructions. .83 5.23 Index Manipulation Instructions . .85 5.24 Stacking Instructions. .86 5.25 Pointer and Index Calculation Instructions . .87 5.26 Condition Code Instructions . .88 5.27 Stop and Wait Instructions . .89 5.28 Background Mode and Null Operations . .90 Section 6. Instruction Glossary 6.1 Introduction. ..
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