INTRODUCTION TO ISA INTRODUCTION TO • The Instruction Set Architecture of a Instruction Set Architecture microprocessor include the followings: – Instruction specific set , instruction formats and (ISA) types – Supported data types by the instruction set, and – Operating context for the instructions. 1 2 MICROPROCESSORS MICROPROCESSORS ISA Main desirable features of an ISA interface between software and hardware • Regularity (Orthogonality) - Common set of formats, few special cases . The ability to use all relevant addressing modes in a uniform and consistent way with all opcodes of an instruction set or C program ASM program assembly language. – Orthogonal instruction sets simplify programming (reduced number of ASM program assembled distinct opcodes and simplified rules for operand address C program compiled to ISA program specification) to ISA program – Most computers have very little orthogonality ( reduce processor costs Software at the expense of programming costs ) ISA level • Completeness - Support for a wide range of operations and target applications Hardware ISA program executed by – Operators have different frequency of utilization microprogram or hardware – There must censor the set of operators – The rule for design an ISA is: “ Execute fast the frequent operations Hardware and correct the infrequent one ”. 3 4 MICROPROCESSORS MICROPROCESSORS INSTRUCTION FORMAT INSTRUCTION FORMAT • Length: – fixed length for the entire Typical fields: • Operation code field - specifies the operation to be performed. instruction set • Operand specifications - specify the mode to compute addresses to operands – variable length for the OPCODE OP1 OP2 OP3 recognized instruction set 5 6 MICROPROCESSORS MICROPROCESSORS Conventions for ordering and addressing DIFFERENT INSTRUCTION FORMATS the bytes within a word in memory • For multiple-byte words stored in Main Memory there are OPCODE Zero address instruction two different conventions: – Little Endian Big Indian OPCODE ADDRESS One-address instruction – Big Endian Little Indian OPCODE ADDRESS1 ADDRESS2 Two-address instruction OPCODE ADDR1 ADDR2 ADDR3 Three-address instruction 7 8 MICROPROCESSORS MICROPROCESSORS Conventions for ordering and addressing Conventions for ordering and addressing the bytes within a word in memory the bytes within a word in memory • For multiple-byte words stored in Main Memory there are two different conventions: – Little Endian • Little Endian byte order puts the byte whose address is – Big Endian "x...x00" at the least significant position in the word (the little end) Big Indian File (Indian queue): Little Indian File (Indian queue): • In Little Endian, the address of a datum is the address of The big one is the first The little one is the first the least significant byte (LSB) 9 10 MICROPROCESSORS MICROPROCESSORS Conventions for ordering and addressing Little vs. Big Endian the bytes within a word in memory Example word: 6A0244FFh (on 32 bits) Little Endian Big Endian Most significant memory address Least significant memory address byte in word 1 byte in word 1 x0000 FF x0000 6A • Big Endian byte order puts the byte whose address x0001 44 x0001 02 word 1 word 1 is "x...x00" at the most significant position in the x0002 02 x0002 44 word (the big end) x0003 6A x0003 FF Most significant Least significant • In Big Endian addressing, the address of a datum x0004 byte in word 1 x0004 byte in word 1 is the address of the most significant byte (MSB) x0005 x0005 word 2 word 2 x0006 x0006 x0007 x0007 x0008 x0008 11 12 MICROPROCESSORS MICROPROCESSORS ALIGNED INFORMATION IN MEMORY A 4 byte word in a little endian memory Aligned vs. not-aligned • In some machines accesses to objects (instructions, data, addresses) larger Data bus than a byte must be aligned • Misalignment causes hardware complications , since the memory is typically aligned on a word boundary . A misaligned memory access will, therefore, 32 bits take multiple aligned memory references memory address 8 bits 8 bits 8 bits 8 bits • The information stored at address A having the dimension D bytes , is aligned if: x0000 Byte 0 Byte 1 Byte 2 Byte 3 word 1 aligned at A modulo D = 0 address x0000h x0004 • For example, if D=4 Bytes Address 0: 0 modulo 4 = 0 x0008 Byte 0 Byte 1 word 2 misaligned at Address 1: 1 modulo 4 = 1 x000C address x000Ah Address 2: 2 modulo 4 = 2 Byte 2 Byte 3 Address 3: 3 modulo 4 = 3 x0010 Address 4: 4 modulo 4 = 0 Address 5: 5 modulo 4 = 1 13 14 MICROPROCESSORS MICROPROCESSORS Number of explicit addresses: Example Classifying ISAs Number of Instruction Comment Operand storage in the CPU Where are operands kept other than in memory? addresses Format Number of explicit operands How many operands are named explicitly in a per instruction typical instruction? 3 add z,x,y ; z ← x+y or y ← z + x Operand location Can any ALU instruction operand be located in memory or must some or all of the operands be 2 add x,y ;x ←x+y or Ac ← x+y in internal storage in the CPU? If an operand is located in memory, how is the memory location specified? 1 add x ; Ac ← Ac+x Operations What operations are provided in the instruction set? ; add the two articles from the 0 add ;Top of the Stack (ToS) and store the result in Type and size of operands What is the type and size of each operand and ;the new ToS how is it specified? 15 16 MICROPROCESSORS MICROPROCESSORS Classifying ISAs Example of instructions (type of internal storage) Organization Instruction Comment Type Format AC add x ;Ac ← Ac + x or Ac ← Ac + @x stack machine (stack organization) add r1,r2,r3 ; r1 ← r2 + r3 add r1,r2 ; r1 ← r1 + r2 or r2 ← r1 + r2 accumulator machine (acc. organization) RG mov r1,r2 ; r1 ← r2 general-purpose register machine (GPR add r1,x ; r1 ← r1 + @x organization) ;ToS ← @x push x ST ;the top two operands in the stack are add ;extracted, added, and then the result pushed ;on the stack 17 18 MICROPROCESSORS MICROPROCESSORS Advantages and disadvantages Example GPR architecture program • AC: short instructions, high cod • AC: Since accumulator is only x = a*(b+c) density temporary storage, memory traffic is highest for this approach • 3 address instructions (CISC): • RG: Most general model for code • RG : All operands must be named, add r1,b,c ;r1 ← @b + @c leading to longer instructions generation mul x,r1,a ;@x ← r1 * @a • 3 address instructions (RISC - load/store architecture) • SP: Simple model of expression • SP: A stack cannot be randomly ← evaluation (reverse polish). Short accessed, difficult to generate load r1,a ; r1 @a) instructions can yield good code efficient code, stack becomes a load r2,b ; r2 ← @b) bottleneck density load r3,c ; add r2,r2,r3 ; r2 ← (r2 + r3) mul r1,r1,r2 ; r1 ← (r1 * r2) • x=a*(b+c)written abc+* storex,r1 ; @x ← r1 • x = (a+b)*(c+d) written ab+cd+* • x = (a+b)*(c+d)*(e+f) written ab+cd+ef+** 19 20 MICROPROCESSORS MICROPROCESSORS Example GPRA program (con’t) Example Accumulator architecture x = a*(b+c) program for: x = a*(b+c) load b ; ac ← @b • 2 address instructions: add c ; ac ← ac + @c movr1,b ;r1 ← @b storet ; @t ← ac add r1,c ;r1 ← r1 + @c ← mulr1,a ;r1 ← r1 * @a load a ; ac @a movx,r1 ;@x ← r1 mul t ; ac ← ac * @t store x ; @x ← ac where t is a temporary memory location. 21 22 MICROPROCESSORS MICROPROCESSORS Example Stack architecture program for: x = a*(b+c) Polish notation (suffix notation) push a ;TopS ← @a, let adr be the current address • x*y writed as xy * ;of the top of stack (TopS) • x = a*(b+c) = abc+* push b ;TopS ← @b, at adr-1 Remember: push, push, push, add, mul push c ;TopS ← @c, at adr -2 • Other examples: add ;TopS ← (b + c), stored at adr-1 mul ;TopS ← a*(b+c), stored at adr . x = (a+b)*(c+d) = ab+cd+* pop x ;@x ← TopS, TopS point at address adr+1 x = (a+b)*(c+d)*(e+f) = ab+cd+ef+** 23 24 MICROPROCESSORS MICROPROCESSORS RISC versus CISC • Load-and-store architecture. Only • Instructions address operands in LOAD and STORE instructions reference data in memory memory • Instructions are of fixed length and • Variable length instructions uniform format • Control unit microprogrammed • Control unit hardwired • Complex instructions, many instruction Instruction Set Architecture • The instruction set include only simple types and addressing modes instructions, few instruction types and • More difficult administration of (ISA) addressing modes pipelines • Efficient pipelines (instructions are simple and of similar execution time. • Relatively low number of internal registers. • A large number of registers is available • Use compilers to optimize object code •Addressing modes performance, by resolving pipeline hazards (situations that prevent the next •Instruction Types instruction in the instruction stream from executing during its designated clock cycle). 25 26 MICROPROCESSORS MICROPROCESSORS ADDRESSING MODES ADDRESSING MODES • Addressing modes = how architectures specify the address • We shall use the following notation for describing EA: of an object they will access. ° #value = Immediate data • Addressing modes refer not only to operands , but also to ° x = Memory location instructions (sequencing of instructions) ° d = displacement, a signed number • Operands can be located in different places: in the ° Rn = Register n instruction format (one binary field), internal registers, ° (Rn) = Register deferred main memory, input / output ports. ° (Rn)+ = Auto (post)increment • For every addressing mode recognized, the Control Unit ° -(Rn) = Auto (pre)decrement compute an Effective Address (EA) for the operand ° @Rn = address contained in Rn ° @x = address contained in memory location X – EA is used to find an object in the main memory 27 28 MICROPROCESSORS MICROPROCESSORS Classification of addressing modes TYPES OF OPERANDS • We classify the addressing modes in the • Immediate following types: • In (internal) registers 1. immediate addressing • In (main) memory 2.