Serial Bus Communication Protocols
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Rs-232 Rs-422 Rs-485
ConceptConcept ofof SerialSerial CommunicationCommunication AgendaAgenda Serial v.s. Parallel Simplex , Half Duplex , Full Duplex Communication RS-485 Advantage over RS-232 SerialSerial v.s.v.s. ParallelParallel Application: How to Measure the temperature in a long distance? Measuring with a DAC card: 1200 m Remote sensor Control room T/C wire T/C A/D noise Application: How to Measure the temperature in a long distance? Measuring with a remote I/O module: 1200 m Remote sensor Control room T/C Remote I/O Standard Serial Communication T/C signal, 4-20mA, 0-5V… Noise rejection (Differential signal) MostMost PopularPopular 33 typestypes ofof SerialSerial Comm.Comm. z Most commonly available Tx Rx Rx Tx z Simple wiring CTS RTS z Low cost RTS CTS RS-232 z Short length (40 ft) DTR DSR DSR DTR Bar code reader z Slow data rates GND GND z Subject to noise Tx+ z High data rates Tx- z Longer cable lengths (4000 ft) Rx+ Rx- RS-422 z Full-duplex GND z Noise rejection PLC z Multipoint application (Up to 32 units) z Low cost Data+ z Longer cable lengths (4000 ft) Data- RS-485 zNoise immunity GND zHalf-duplex PLC SerialSerial V.S.V.S. ParallelParallel CommunicationCommunication Serial Communication Transfer the data bit by bit Synchronous Data Transfer Bit Send Data Receive Data Parallel Communication Transfer the all data simultaneously Asynchronous Data Transfer Bit Bit Bit Bit Bit Bit Bit Bit Send Data Receive Data SimplexSimplex ,, HalfHalf DuplexDuplex ,, FullFull DuplexDuplex CommunicationCommunication SimplexSimplex CommunicationCommunication Simplex Communication : – Data in a simplex channel is always one way. -
Distributed Systems
14-760: ADVANCED REAL-WORLD NETWORKS LECTURE 17 * SPRING 2019 * KESDEN SERIAL COMMUNICATION Courtesy 18-349 SERIAL VS. PARALLEL TX Serial MCU 1 RX MCU 2 signal Data[0:7] Parallel MCU 1 MCU 2 3 WHY SERIAL COMMUNICATION? 4 • Serial communication is a pin-efficient way of sending and receiving bits of data • Sends and receives data one bit at a time over one wire • While it takes eight times as long to transfer each byte of data this way (as compared to parallel communication), only a few wires are required • Typically one to send, one to receive (for full-duplex), and a common signal ground wire • Simplistic way to visualize serial port • Two 8-bit shift registers connected together • Output of one shift register (transmitter) connected to the input of the other shift register (receiver) • Common clock so that as a bit exits the transmitting shift register, the bit enters the receiving shift register • Data rate depends on clock frequency SIMPLISTIC VIEW OF SERIAL PORT OPERATION Transmitter Receiver n 0 1 2 3 4 5 6 7 n n+1 0 1 2 3 4 5 6 n+1 7 n+2 0 1 2 3 4 5 n+2 6 7 n+3 0 1 2 3 4 n+3 5 6 7 n+4 0 1 2 3 n+4 4 5 6 7 n+5 0 1 2 n+5 3 4 5 6 7 n+6 0 1 n+6 2 3 4 5 6 7 n+7 0 n+7 1 2 3 4 5 6 7 n+8 n+8 0 1 2 3 4 5 6 7 Interrupt raised when Interrupt raised when Transmitter (Tx) is empty Receiver (Rx) is full a Byte has been transmitted a Byte has been received and next byte ready for loading and is ready for reading SIMPLE SERIAL PORT Receive Buffer Register 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Receive Shift Register Transmit Shift Register 0 1 2 3 4 5 -
Enhanced Communications Protocol Serial Port
Enhanced Communications Protocol Serial Port Huey lope below. Shakier Muffin may very threefold while Andrej remains bloody-minded and hypertonic. Foreordained Bartlett overshoots excellently. Why degaussing is missing the linux, it is connected to have various commands from serial communications control signals going into digital Specifies the stac algorithm on the CAIM card for the port. Enhanced communication protocols there is ready for access control equipment costs, required for this interface configuration mode is also occurs waiting for other. The protocol such a real plant as a standard ports for wio lte module can be a single instrument approaches built around, said serial manager. Scanner 1131 Sensia. This communications option uses the NITP protocol to communication with the serial. Its serial manager is installed handlers should be improved accuracy of remote device in some way is processed. Hart communication port interface also values that. Moreover our enhanced security features and mass device management. Homeyduino allows you. Modbus communication problems. However, we recommend that you configure the working interface first. ASCII character key string or byte value serial communication protocols. This allows additional watchdog logic to monitor multiple slave devices for communication faults not detected by the Serial Interface. These protocols are called a protocol for controlling train simulator on device which would still often erred in parallel process to be included a communications in. Data Transmission Parallel vs Serial Transmission Quantil. This prompt type is standard Ethernet protocol; the same used on an empty internal computer network. LZS and MPPC data compression algorithms. For communications with Modbus devices any way these methods can be utilized. -
PCI20EX PCI Express (Pcie)
PCI20EX PCI Express (PCIe) Bus ARCNET® Network Interface Modules INSTALLATION GUIDE INTRODUCTION The PCI20EX series of ARCNET network interface modules (NIMs) links PCI Express (PCIe) bus compatible computers with the ARCNET local area network (LAN). Since most PC motherboards have migrated from the legacy PCI and PCI-X Bus, a PCI Express style NIM is required. The PCI20EX series is compliant to the PCI Express Card Electromechanical Specification Revision 2.0 and both standard height and low-profile brackets are provided. The PCI Express interface allows for jumperless configuration and Plug and Play operation. The module operates with either an NDIS driver or a null stack driver in a Windows® environment. The PCI20EX incorporates the COM20022 ARCNET controller chip with enhanced features over the earlier generation ARCNET chips. New features include command chaining, sequential access to internal RAM, duplicate node ID detection and variable data rates up to 10 Mbps. Bus contention problems are minimized since the module’s interrupt and I/O base address are assigned through Plug and Play. The PCI20EX exploits the new features of the COM20022 which includes 10 Mbps communications utilizing the various EIA-485 transceiver options. Each PCI20EX module has two LEDs on the board for monitoring network operation and bus access to the module. It is equipped with an 8 position, general purpose DIP switch typically used to assign the ARCNET node address. Ultimately, the node address is configured via software so the DIP switch can also indicate user-defined functions such as data rate, cable interface, or master/slave status of the system. -
Serial Communication Buses
Computer Architecture 10 Serial Communication Buses Made wi th OpenOffi ce.org 1 Serial Communication SendingSending datadata oneone bitbit atat oneone time,time, sequentiallysequentially SerialSerial vsvs parallelparallel communicationcommunication cable cost (or PCB space), synchronization, distance ! speed ? ImprovedImproved serialserial communicationcommunication technologytechnology allowsallows forfor transfertransfer atat higherhigher speedsspeeds andand isis dominatingdominating thethe modernmodern digitaldigital technology:technology: RS232, RS-485, I2C, SPI, 1-Wire, USB, FireWire, Ethernet, Fibre Channel, MIDI, Serial Attached SCSI, Serial ATA, PCI Express, etc. Made wi th OpenOffi ce.org 2 RS232, EIA232 TheThe ElectronicElectronic IndustriesIndustries AllianceAlliance (EIA)(EIA) standardstandard RS-232-CRS-232-C (1969)(1969) definition of physical layer (electrical signal characteristics: voltage levels, signaling rate, timing, short-circuit behavior, cable length, etc.) 25 or (more often) 9-pin connector serial transmission (bit-by-bit) asynchronous operation (no clock signal) truly bi-directional transfer (full-duplex) only limited power can be supplied to another device numerous handshake lines (seldom used) many protocols use RS232 (e.g. Modbus) Made wi th OpenOffi ce.org 3 Voltage Levels RS-232RS-232 standardstandard convertconvert TTL/CMOS-levelTTL/CMOS-level signalssignals intointo bipolarbipolar voltagevoltage levelslevels toto improveimprove noisenoise immunityimmunity andand supportsupport longlong cablecable lengthslengths TTL/CMOS → RS232: 0V = logic zero → +3V…+12V (SPACE) +5V (+3.3V) = logic one → −3V…−12V (MARK) Some equipment ignores the negative level and accepts a zero voltage level as the "OFF" state The "dead area" between +3V and -3V may vary, many receivers are sensitive to differentials of 1V or less Made wi th OpenOffi ce.org 4 Data frame CompleteComplete one-byteone-byte frameframe consistsconsists of:of: start-bit (SPACE), data bits (7, 8), stop-bits (MARK) e.g. -
Datasheet for Onenand Power Ramp and Stabilization Times and for Onenand Boot Copy Times
TMS320DM365 www.ti.com SPRS457E–MARCH 2009–REVISED JUNE 2011 TMS320DM365 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM365 1 TMS320DM365 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • Highlights – Support for 32-Bit and 16-Bit – High-Performance Digital Media (Thumb® Mode) Instruction Sets System-on-Chip (DMSoC) – DSP Instruction Extensions and Single Cycle – Up to 300-MHz ARM926EJ-S Clock Rate MAC – Two Video Image Co-processors – ARM® Jazelle® Technology (HDVICP, MJCP) Engines – Embedded ICE-RT Logic for Real-Time – Supports a Range of Encode, Decode, and Debug Video Quality Operations • ARM9 Memory Architecture – Video Processing Subsystem – 16K-Byte Instruction Cache • HW Face Detect Engine – 8K-Byte Data Cache • Resize Engine from 1/16x to 8x – 32K-Byte RAM • 16-Bit Parallel AFE (Analog Front-End) – 16K-Byte ROM Interface Up to 120 MHz – Little Endian • 4:2:2 (8-/16-bit) Interface • Two Video Image Co-processors • 8-/16-bit YCC and Up to 24-Bit RGB888 (HDVICP, MJCP) Engines Digital Output – Support a Range of Encode and Decode • 3 DACs for HD Analog Video Output Operations, up to D1 on 216-MHz device and • Hardware On-Screen Display (OSD) up to 720p on the 270- and 300-MHz parts – Capable of 720p 30fps H.264 video – H.264, MPEG4, MPEG2, MJPEG, JPEG, processing WMV9/VC1 Note: 216-MHz is only capable of D1 • Video Processing Subsystem processing – Front End Provides: – Peripherals include EMAC, USB 2.0 OTG, • HW Face Detect Engine DDR2/NAND, 5 SPIs, 2 UARTs, 2 • Hardware IPIPE for Real-Time Image MMC/SD/SDIO, -
Wishbone Bus Architecture – a Survey and Comparison
International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012 WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON Mohandeep Sharma 1 and Dilip Kumar 2 1Department of VLSI Design, Center for Development of Advanced Computing, Mohali, India [email protected] 2ACS - Division, Center for Development of Advanced Computing, Mohali, India [email protected] ABSTRACT The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license. KEYWORDS SoC buses, WISHBONE Bus, WISHBONE Interface 1. INTRODUCTION The introduction and advancement of multimillion-gate chips technology with new levels of integration in the form of the system-on-chip (SoC) design has brought a revolution in the modern electronics industry. With the evolution of shrinking process technologies and increasing design sizes [1], manufacturers are integrating increasing numbers of components on a chip. -
VICTORIA UNIVERSITY of WELLINGTON Te Whare W
VICTORIAUNIVERSITYOFWELLINGTON Te Whare Wananga¯ o te UpokooteIkaaM¯ aui¯ School of Engineering and Computer Science Te Kura Matai¯ Pukaha,¯ Purorohiko¯ PO Box 600 Tel: +64 4 463 5341 Wellington Fax: +64 4 463 5045 New Zealand Internet: offi[email protected] Development of an IoT System for Environmental Monitoring Jolon Behrent Supervisor: James Quilty Submitted in partial fulfilment of the requirements for Bachelor of Engineering with Honours. Abstract The Greater Wellington Regional Council currently uses data loggers to mon- itor the environment. These loggers and accompanying software are provided by a single supplier which effectively locks the Council into using them for all monitoring. The Council wants to develop a low-cost, open-source Internet of Things solution with a connection to a cloud platform. This report looks at the development of a successful proof-of-concept device capable of reading from sensors and transmitting the data to Azure. Contents 1 Introduction and Background 1 1.1 Introduction . .1 1.1.1 Objective . .1 1.1.2 Overview . .2 1.2 Background . .2 1.2.1 HyQuest Solutions Data Loggers . .2 1.2.2 SDI-12 . .3 2 Design 5 2.1 Design Constraints . .5 2.1.1 Power Consumption . .5 2.1.2 Size . .6 2.1.3 Cost . .6 2.2 Microcontroller Selection . .6 2.3 Modem Selection . .7 2.4 Capacitor Selection . .8 2.5 Regulator Selection . .9 2.6 PCB Design . .9 2.7 Enabling Local Wireless Connection . 10 2.7.1 Reed Switches . 11 2.7.2 Hall Effect Sensors . 11 2.8 SDI-12 Design . -
GS3 Greenhouse Sensor 2365 NE Hopkins Ct / Pullman, WA 99163 USA Volumetric Water Content, Electrical Conductivity, and Temperature
GS3 Greenhouse Sensor 2365 NE Hopkins Ct / Pullman, WA 99163 USA Volumetric Water Content, Electrical Conductivity, and Temperature APPLICATIONS DESCRIPTION . Greenhouse substrate monitoring. The Decagon GS3 sensor is an accurate tool for . Volumetric water content measurement. monitoring electrical conductivity, volumetric water . Soil/Substrate water balance. content, and temperature in soil and soilless . Irrigation management. substrates. The GS3 determines volumetric water . Electrical Conductivity measurement. content (VWC) by measuring the dielectric constant . Salt management. (εa) of the medium using capacitance / frequency- . Fertilizer movement. domain technology. The sensor uses a 70 MHz . Soil/Substrate temperature measurement. frequency, which minimizes textural and salinity . Modeling processes that are affected by effects, making the GS3 accurate in most soilless temperature. substrates. The GS3 measures temperature using an onboard thermistor, and electrical conductivity using a stainless steel electrode array. ADVANTAGES For a more detailed description of how this sensor . Digital sensor communicates three makes measurements, refer to the User Manual. measurements over a serial interface. 2-probe EC measurement. Robust thermistor for accurate temperature AUDIENCE measurements. Decagon provides the information in this integrators . Low input voltage requirements. guide to help GS3 customers establish . Low power design supports battery-operated communication between these sensors and their data loggers. data acquisition equipment or field data loggers. Robust epoxy encapsulation and stainless Customers using data loggers that support SDI-12 steel needles to resist corrosive environments. sensor communications should consult the user's . Supports SDI-12 or DDI-Serial 1-wire serial manual for their data logger. These sensors are fully communications protocols. integrated into Decagon's system of plug-and-play . -
Parallel I/O Interface
從微算機原理到系統 宋開泰教授 國立交通大學電機與控制系 工程五館 EE709 Phone:5731865(校內分機:31865) E-mail:[email protected] URL:http://isci.cn.nctu.edu.tw Microcomputer Systems & Lab Microcomputer bus 1 Digital Signal Waveform 1 0 Single-signal waveform 1 0 Multiple-signal waveform Microcomputer Systems & Lab Microcomputer bus 2 Read Timing for External Code Memory Microcomputer Systems & Lab Microcomputer bus 3 Microcomputer BUS • A bus is a set of conducting wires interconnecting the CPU, memory, and I/O devices. • There are three types of bus: Address bus, Data bus and Control bus. There are also utilities in a bus system, such as Vcc and ground lines. • To drive a bus, a bus driver is needed. To receive data from the bus, a bus receiver is needed. The bus driver and bus receiver can be combined to form a bus transceiver. Microcomputer Systems & Lab Microcomputer bus 4 Connecting to a bus • A bus should be driven by no more than one device at any time. Otherwise, bus contention will occur. When bus contention occurs, the devices that are involved in bus contention could be damaged. • A device is disconnected from the bus when the driver-enable and receiver-enable signals are deasserted. When the enable signal is deasserted, the output of the driver or the receiver is in a high-impedance state in which no current flow into or out the device involved. Microcomputer Systems & Lab Microcomputer bus 5 Interconnecting the CPU, Memory, and I/O Devices Memory unit 8 bits 1,048,575 Clock generator 64 672,356 Address Instruction pointer (IP) System address bus Selector/ z System 6 memory 672 356 decoder 5 4 Instruction register 3 2 64 1 Location 0 INC AX Instruction decoder Internal databus System control bus Arithmetic logic unit Memory read Memory write Accumulator I/O write I/O read I/O write I/O read I/O write 26+1=27 System data bus Video monitor I/O devices: Printer keyboard Floppy disk drive z General-purpose registers I/O port Selector/decoder Central processing unit (CPU) Microcomputer Systems & Lab Microcomputer bus 6 System Bus • Internal data bus is used to classify a microprocessor. -
Teros 21 Gen 1 Integrator Guide
18204-06 6.30.2020 TEROS 21 GEN 1 INTEGRATOR GUIDE SENSOR DESCRIPTION The TEROS 21 Soil Water Potential Sensor measures a wide range of soil water potentials without user maintenance. This dielectric water potential sensor can be packed into a hole, plugged into a data logger, and left to log water potential data. While the TEROS 21 sensor does not have the accuracy of tensiometers, its extended range makes this sensor ideal for measuring the water potential in natural systems or other drier systems where cavitation of tensiometers is a concern. The added temperature measurements can be used to determine approximate soil water potential in frozen soils. NOTE: The TEROS 21 measures the matric component of water potential. For more information on matric potential and the other components of water potential visit Defining water potential. APPLICATIONS • Deficit irrigation monitoring and control • Water potential monitoring in the vadose zone • Crop stress • Waste water drainage studies • Plant water availability • SDI-12 implementation ADVANTAGES • Three-wire sensor interface: power, ground, and data • Digital sensor communicates multiple measurements over a serial interface • Robust thermistor for accurate temperature measurements • Low-input voltage requirements • Low-power design supports battery-operated data loggers • Robust epoxy encapsulation resists corrosive environments • Supports SDI-12 or DDI serial communications protocols • Modern design optimized for low-cost sensing • Does not require a skilled operator • Can measure drier systems where tensiometer cavitation is a concern • Needs no user maintenance Figure 1 TEROS 21 sensor PURPOSE OF THIS GUIDE METER provides the information in this integrator guide to help TEROS 21 Soil Water Potential Sensor customers establish communication between these sensors and their data acquisition equipment or field data loggers. -
SAM2634 Datasheet
SAM2634 LOW-POWER SYNTHESIZER WITH EFFECTS The SAM2634 integrates into a single chip a proprietary DREAM® DSP core (64-slots DSP + 16-bit microcontroller), a 32k x 16 RAM and an LCD display interface. With addition of a single external ROM or FLASH, a complete low cost sound module can be built, including reverb and chorus effects, parametric equalizer, surround effects, without compromising on sound quality. Key features . Single chip synthesizer + effects, typical application includes: o Wavetable synthesis, serial MIDI in & out, parallel MIDI o Effects: reverb + chorus, on MIDI and/or audio in o Surround on 2 or 4 speakers with intensity/delay control o Equalizer: 4 bands, parametric o Audio in processing through echo, equalizer, surround . Low chip count o Synthesizer, ROM/Flash, DAC o Effects RAM is built-in (32k x 16) . Low power o 14 mA typ. operating o Single 3.3V supply o Built-in 1.2V regulator with power down mode . High quality wavetable synthesis o 16 bits samples, 48 KHz sampling rate, 24dB digital filter per voice o Up to 64 voices polyphony o Up to 64MByte ROM/Flash and RAM for firmware, and PCM data . Available wavetable firmwares and sample sets o CleanWave8® low cost General MIDI 1 megabyte firmware + sample set o CleanWave32® high quality 4 megabyte firmware + sample set o CleanWave64® top quality 8 megabyte firmware + sample set o Other sample sets available under special conditions. Fast product to market o Enhanced P16 processor with C compiler o Built-in ROM debugger o Flash programmer through dedicated pins. Small footprint o 100-pin LQFP package .