Assembly Language for X86 Processors

Total Page:16

File Type:pdf, Size:1020Kb

Assembly Language for X86 Processors Assembly Language for x86 Processors Sixth Edition KIP R. IRVINE Florida International University School of Computing and Information Sciences Upper Saddle River Boston Columbus San Francisco New York Indianapolis London Toronto Sydney Singapore Tokyo Montreal Dubai Madrid Hong Kong Mexico City Munich Paris Amsterdam Cape Town Vice President and Editorial Director, ECS: Marcia J. Horton Editor-in-Chief: Michael Hirsch Executive Editor: Tracy Dunkelberger Assistant Editor: Melinda Haggerty Editorial Assistant: Allison Michael Vice President, Production: Vince O’Brien Senior Managing Editor: Scott Disanno Production Liaison: Jane Bonnell Production Editor: Maheswari PonSaravanan, TexTech International Senior Operations Supervisor: Alan Fischer Marketing Manager: Erin Davis Marketing Assistant: Mack Patterson Art Director: Kenny Beck Cover Designer: Laura C. Ierardi Cover Image: Color enhanced x-ray of nautilus shell / Bert Myers / Science Photo Library Art Editor: Greg Dulles Media Editor: Daniel Sandin Media Project Manager: Danielle Leone Composition/Full-Service Project Management: TexTech International IA-32, Pentium, i486, Intel64, Celeron, and Intel 386 are trademarks of Intel Corporation. Athlon, Phenom, and Opteron are trademarks of Advanced Micro Devices. TASM and Turbo Debugger are trademarks of Borland International. Microsoft Assembler (MASM), Windows Vista, Windows 7, Windows NT, Windows Me, Windows 95, Windows 98, Windows 2000, Windows XP, MS-Windows, PowerPoint, Win32, DEBUG, WinDbg, MS-DOS, Visual Studio, Visual C++, and CodeView are registered trademarks of Microsoft Corporation. Autocad is a trademark of Autodesk. Java is a trademark of Sun Microsystems. PartitionMagic is a trademark of Symantec. All other trademarks or product names are the property of their respective owners. Copyright © 2011, 2007, 2003, 1999 by Pearson Education, Inc., Upper Saddle River, New Jersey 07458. All rights reserved. Manufactured in the United States of America. This publication is protected by Copyright and permissions should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise. To obtain permission(s) to use materials from this work, please submit a written request to Pearson Higher Education, Permissions Department, 1 Lake Street, Upper Saddle River, NJ 07458. Previously published as Assembly Language for Intel-Based Computers. The author and publisher of this book have used their best efforts in preparing this book. These efforts include the development, research, and testing of the theories and programs to determine their effectiveness. The author and pub- lisher make no warranty of any kind, expressed or implied, with regard to these programs or the documentation contained in this book. The author and publisher shall not be liable in any event for incidental or consequential damages in connection with, or arising out of, the furnishing, performance, or use of these programs. Library of Congress Cataloging-in-Publication Data Irvine, Kip R. Assembly language for x86 processors / Kip R. Irvine. -- 6th ed. p. cm. Rev. ed. of: Assembly language for intel-based computers, 5th ed., 2007. ISBN 0-13-602212-X (alk. paper) 1. IBM microcomputers--Programming. 2. Assembler language (Computer program language) I. Irvine, Kip R. - Assembly language for intel-based computers. II. Title. QA76.8.I77 2011 005.265--dc22 2009049014 10987654321 ISBN-13: 978-0-13-602212-1 ISBN-10: 0-13-602212-X To Jack and Candy Irvine This page intentionally left blank Contents Preface xix 1 Basic Concepts 1 1.1 Welcome to Assembly Language 1 1.1.1 Good Questions to Ask 2 1.1.2 Assembly Language Applications 5 1.1.3 Section Review 6 1.2 Virtual Machine Concept 7 1.2.1 Section Review 9 1.3 Data Representation 9 1.3.1 Binary Integers 9 1.3.2 Binary Addition 11 1.3.3 Integer Storage Sizes 12 1.3.4 Hexadecimal Integers 13 1.3.5 Signed Integers 15 1.3.6 Character Storage 17 1.3.7 Section Review 19 1.4 Boolean Operations 22 1.4.1 Truth Tables for Boolean Functions 24 1.4.2 Section Review 26 1.5 Chapter Summary 26 1.6 Exercises 27 1.6.1 Programming Tasks 27 1.6.2 Nonprogramming Tasks 27 2 x86 Processor Architecture 29 2.1 General Concepts 29 2.1.1 Basic Microcomputer Design 30 2.1.2 Instruction Execution Cycle 31 2.1.3 Reading from Memory 33 2.1.4 How Programs Run 34 2.1.5 Section Review 35 v vi Contents 2.2 x86 Architecture Details 36 2.2.1 Modes of Operation 36 2.2.2 Basic Execution Environment 36 2.2.3 Floating-Point Unit 39 2.2.4 Overview of Intel Microprocessors 39 2.2.5 Section Review 42 2.3 x86 Memory Management 43 2.3.1 Real-Address Mode 43 2.3.2 Protected Mode 45 2.3.3 Section Review 47 2.4 Components of a Typical x86 Computer 48 2.4.1 Motherboard 48 2.4.2 Video Output 50 2.4.3 Memory 50 2.4.4 Input-Output Ports and Device Interfaces 50 2.4.5 Section Review 52 2.5 Input-Output System 52 2.5.1 Levels of I/O Access 52 2.5.2 Section Review 55 2.6 Chapter Summary 55 2.7 Chapter Exercises 57 3 Assembly Language Fundamentals 58 3.1 Basic Elements of Assembly Language 58 3.1.1 Integer Constants 59 3.1.2 Integer Expressions 60 3.1.3 Real Number Constants 61 3.1.4 Character Constants 61 3.1.5 String Constants 61 3.1.6 Reserved Words 62 3.1.7 Identifiers 62 3.1.8 Directives 62 3.1.9 Instructions 63 3.1.10 The NOP (No Operation) Instruction 65 3.1.11 Section Review 66 3.2 Example: Adding and Subtracting Integers 66 3.2.1 Alternative Version of AddSub 69 3.2.2 Program Template 70 3.2.3 Section Review 70 3.3 Assembling, Linking, and Running Programs 71 3.3.1 The Assemble-Link-Execute Cycle 71 3.3.2 Section Review 77 Contents vii 3.4 Defining Data 77 3.4.1 Intrinsic Data Types 77 3.4.2 Data Definition Statement 77 3.4.3 Defining BYTE and SBYTE Data 78 3.4.4 Defining WORD and SWORD Data 80 3.4.5 Defining DWORD and SDWORD Data 81 3.4.6 Defining QWORD Data 81 3.4.7 Defining Packed Binary Coded Decimal (TBYTE) Data 82 3.4.8 Defining Real Number Data 83 3.4.9 Little Endian Order 83 3.4.10 Adding Variables to the AddSub Program 84 3.4.11 Declaring Uninitialized Data 85 3.4.12 Section Review 85 3.5 Symbolic Constants 86 3.5.1 Equal-Sign Directive 86 3.5.2 Calculating the Sizes of Arrays and Strings 87 3.5.3 EQU Directive 88 3.5.4 TEXTEQU Directive 89 3.5.5 Section Review 90 3.6 Real-Address Mode Programming (Optional) 90 3.6.1 Basic Changes 90 3.7 Chapter Summary 91 3.8 Programming Exercises 92 4 Data Transfers, Addressing, and Arithmetic 94 4.1 Data Transfer Instructions 94 4.1.1 Introduction 94 4.1.2 Operand Types 95 4.1.3 Direct Memory Operands 96 4.1.4 MOV Instruction 96 4.1.5 Zero/Sign Extension of Integers 98 4.1.6 LAHF and SAHF Instructions 100 4.1.7 XCHG Instruction 100 4.1.8 Direct-Offset Operands 101 4.1.9 Example Program (Moves) 102 4.1.10 Section Review 103 4.2 Addition and Subtraction 104 4.2.1 INC and DEC Instructions 104 4.2.2 ADD Instruction 104 4.2.3 SUB Instruction 105 4.2.4 NEG Instruction 105 viii Contents 4.2.5 Implementing Arithmetic Expressions 106 4.2.6 Flags Affected by Addition and Subtraction 106 4.2.7 Example Program (AddSub3) 110 4.2.8 Section Review 111 4.3 Data-Related Operators and Directives 112 4.3.1 OFFSET Operator 112 4.3.2 ALIGN Directive 113 4.3.3 PTR Operator 114 4.3.4 TYPE Operator 115 4.3.5 LENGTHOF Operator 115 4.3.6 SIZEOF Operator 116 4.3.7 LABEL Directive 116 4.3.8 Section Review 117 4.4 Indirect Addressing 117 4.4.1 Indirect Operands 118 4.4.2 Arrays 119 4.4.3 Indexed Operands 120 4.4.4 Pointers 121 4.4.5 Section Review 123 4.5 JMP and LOOP Instructions 124 4.5.1 JMP Instruction 124 4.5.2 LOOP Instruction 124 4.5.3 Summing an Integer Array 126 4.5.4 Copying a String 126 4.5.5 Section Review 127 4.6 Chapter Summary 128 4.7 Programming Exercises 129 5 Procedures 132 5.1 Introduction 132 5.2 Linking to an External Library 132 5.2.1 Background Information 133 5.2.2 Section Review 134 5.3 The Book’s Link Library 134 5.3.1 Overview 136 5.3.2 Individual Procedure Descriptions 137 5.3.3 Library Test Programs 149 5.3.4 Section Review 157 5.4 Stack Operations 157 5.4.1 Runtime Stack 158 5.4.2 PUSH and POP Instructions 160 5.4.3 Section Review 162 Contents ix 5.5 Defining and Using Procedures 163 5.5.1 PROC Directive 163 5.5.2 CALL and RET Instructions 165 5.5.3 Example: Summing an Integer Array 168 5.5.4 Flowcharts 169 5.5.5 Saving and Restoring Registers 170 5.5.6 Section Review 171 5.6 Program Design Using Procedures 172 5.6.1 Integer Summation Program (Design) 173 5.6.2 Integer Summation Implementation 175 5.6.3 Section Review 177 5.7 Chapter Summary 177 5.8 Programming Exercises 178 6 Conditional Processing 180 6.1 Introduction 180 6.2 Boolean and Comparison Instructions 181 6.2.1 The CPU Flags 182 6.2.2 AND Instruction 182 6.2.3 OR Instruction 183 6.2.4 Bit-Mapped Sets 184 6.2.5 XOR Instruction 186 6.2.6 NOT Instruction 187 6.2.7 TEST Instruction 187 6.2.8 CMP Instruction 188 6.2.9 Setting and Clearing Individual CPU Flags 189 6.2.10 Section Review 189 6.3 Conditional Jumps 190 6.3.1 Conditional Structures 190 6.3.2 Jcond Instruction 191 6.3.3 Types of Conditional Jump Instructions 192 6.3.4 Conditional Jump Applications 195 6.3.5 Section Review 199 6.4 Conditional Loop Instructions 200 6.4.1 LOOPZ and LOOPE Instructions 200 6.4.2 LOOPNZ and LOOPNE Instructions 201 6.4.3 Section Review 201 6.5 Conditional Structures 202 6.5.1 Block-Structured IF Statements 202 6.5.2 Compound Expressions 204 6.5.3 WHILE Loops 206 6.5.4 Table-Driven Selection 208 6.5.5 Section Review 210 x Contents 6.6 Application:
Recommended publications
  • E0C88 CORE CPU MANUAL NOTICE No Part of This Material May Be Reproduced Or Duplicated in Any Form Or by Any Means Without the Written Permission of Seiko Epson
    MF658-04 CMOS 8-BIT SINGLE CHIP MICROCOMPUTER E0C88 Family E0C88 CORE CPU MANUAL NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. Please note that "E0C" is the new name for the old product "SMC". If "SMC" appears in other manuals understand that it now reads "E0C". © SEIKO EPSON CORPORATION 1999 All rights reserved. CONTENTS E0C88 Core CPU Manual PREFACE This manual explains the architecture, operation and instruction of the core CPU E0C88 of the CMOS 8-bit single chip microcomputer E0C88 Family. Also, since the memory configuration and the peripheral circuit configuration is different for each device of the E0C88 Family, you should refer to the respective manuals for specific details other than the basic functions.
    [Show full text]
  • Technical Report TR-2020-10
    Simulation-Based Engineering Lab University of Wisconsin-Madison Technical Report TR-2020-10 CryptoEmu: An Instruction Set Emulator for Computation Over Ciphers Xiaoyang Gong and Dan Negrut December 28, 2020 Abstract Fully homomorphic encryption (FHE) allows computations over encrypted data. This technique makes privacy-preserving cloud computing a reality. Users can send their encrypted sensitive data to a cloud server, get encrypted results returned and decrypt them, without worrying about data breaches. This project report presents a homomorphic instruction set emulator, CryptoEmu, that enables fully homomorphic computation over encrypted data. The software-based instruction set emulator is built upon an open-source, state-of-the-art homomorphic encryption library that supports gate-level homomorphic evaluation. The instruction set architecture supports multiple instructions that belong to the subset of ARMv8 instruction set architecture. The instruction set emulator utilizes parallel computing techniques to emulate every functional unit for minimum latency. This project re- port includes details on design considerations, instruction set emulator architecture, and datapath and control unit implementation. We evaluated and demonstrated the instruction set emulator's performance and scalability on a 48-core workstation. Cryp- toEmu shown a significant speed up in homomorphic computation performance when compared with HELib, a state-of-the-art homomorphic encryption library. Keywords: Fully Homomorphic Encryption, Parallel Computing, Homomorphic Instruction Set, Homomorphic Processor, Computer Architecture 1 Contents 1 Introduction 3 2 Background 4 3 TFHE Library 5 4 CryptoEmu Architecture Overview 7 4.1 Data Processing . .8 4.2 Branch and Control Flow . .9 5 Data Processing Units 9 5.1 Load/Store Unit . .9 5.2 Adder .
    [Show full text]
  • ADSP-21065L SHARC User's Manual; Chapter 2, Computation
    &20387$7,2181,76 Figure 2-0. Table 2-0. Listing 2-0. The processor’s computation units provide the numeric processing power for performing DSP algorithms, performing operations on both fixed-point and floating-point numbers. Each computation unit executes instructions in a single cycle. The processor contains three computation units: • An arithmetic/logic unit (ALU) Performs a standard set of arithmetic and logic operations in both fixed-point and floating-point formats. • A multiplier Performs floating-point and fixed-point multiplication as well as fixed-point dual multiply/add or multiply/subtract operations. •A shifter Performs logical and arithmetic shifts, bit manipulation, field deposit and extraction operations on 32-bit operands and can derive exponents as well. ADSP-21065L SHARC User’s Manual 2-1 PM Data Bus DM Data Bus Register File Multiplier Shifter ALU 16 × 40-bit MR2 MR1 MR0 Figure 2-1. Computation units block diagram The computation units are architecturally arranged in parallel, as shown in Figure 2-1. The output from any computation unit can be input to any computation unit on the next cycle. The computation units store input operands and results locally in a ten-port register file. The Register File is accessible to the processor’s pro- gram memory data (PMD) bus and its data memory data (DMD) bus. Both of these buses transfer data between the computation units and internal memory, external memory, or other parts of the processor. This chapter covers these topics: • Data formats • Register File data storage and transfers
    [Show full text]
  • Most Computer Instructions Can Be Classified Into Three Categories
    Introduction: Data Transfer and Manipulation Most computer instructions can be classified into three categories: 1) Data transfer, 2) Data manipulation, 3) Program control instructions » Data transfer instruction cause transfer of data from one location to another » Data manipulation performs arithmatic, logic and shift operations. » Program control instructions provide decision making capabilities and change the path taken by the program when executed in computer. Data Transfer Instruction Typical Data Transfer Instruction : LD » Load : transfer from memory to a processor register, usually an AC (memory read) ST » Store : transfer from a processor register into memory (memory write) MOV » Move : transfer from one register to another register XCH » Exchange : swap information between two registers or a register and a memory word IN/OUT » Input/Output : transfer data among processor registers and input/output device PUSH/POP » Push/Pop : transfer data between processor registers and a memory stack MODE ASSEMBLY REGISTER TRANSFER CONVENTION Direct Address LD ADR ACM[ADR] Indirect Address LD @ADR ACM[M[ADR]] Relative Address LD $ADR ACM[PC+ADR] Immediate Address LD #NBR ACNBR Index Address LD ADR(X) ACM[ADR+XR] Register LD R1 ACR1 Register Indirect LD (R1) ACM[R1] Autoincrement LD (R1)+ ACM[R1], R1R1+1 8 Addressing Mode for the LOAD Instruction Data Manipulation Instruction 1) Arithmetic, 2) Logical and bit manipulation, 3) Shift Instruction Arithmetic Instructions : NAME MNEMONIC Increment INC Decrement DEC Add ADD Subtract SUB Multiply
    [Show full text]
  • Lecture Notes in Assembly Language
    Lecture Notes in Assembly Language Short introduction to low-level programming Piotr Fulmański Łódź, 12 czerwca 2015 Spis treści Spis treści iii 1 Before we begin1 1.1 Simple assembler.................................... 1 1.1.1 Excercise 1 ................................... 2 1.1.2 Excercise 2 ................................... 3 1.1.3 Excercise 3 ................................... 3 1.1.4 Excercise 4 ................................... 5 1.1.5 Excercise 5 ................................... 6 1.2 Improvements, part I: addressing........................... 8 1.2.1 Excercise 6 ................................... 11 1.3 Improvements, part II: indirect addressing...................... 11 1.4 Improvements, part III: labels............................. 18 1.4.1 Excercise 7: find substring in a string .................... 19 1.4.2 Excercise 8: improved polynomial....................... 21 1.5 Improvements, part IV: flag register ......................... 23 1.6 Improvements, part V: the stack ........................... 24 1.6.1 Excercise 12................................... 26 1.7 Improvements, part VI – function stack frame.................... 29 1.8 Finall excercises..................................... 34 1.8.1 Excercise 13................................... 34 1.8.2 Excercise 14................................... 34 1.8.3 Excercise 15................................... 34 1.8.4 Excercise 16................................... 34 iii iv SPIS TREŚCI 1.8.5 Excercise 17................................... 34 2 First program 37 2.1 Compiling,
    [Show full text]
  • 2. Assembly Language Assembly Language Is a Programming Language That Is Very Similar to Machine Language, but Uses Symbols Instead of Binary Numbers
    2. Assembly Language Assembly Language is a programming language that is very similar to machine language, but uses symbols instead of binary numbers. It is converted by the assembler into executable machine- language programs. Assembly language is machine-dependent; an assembly program can only be executed on a particular machine. 2.1 Introduction to Assembly Language Tools Practical assembly language programs can, in general, be written using one of the two following methods: 1- The full-segment definition form 2- The simplified segment definition form In both methods, the source program includes two types of instructions: real instructions, and pseudo instructions. Real instructions such as MOV and ADD are the actual instructions that are translated by the assembler into machine code for execution by the CPU. Pseudo instructions, on the other hand, don’t generate machine code and are only used to give directions to the assembler about how it should translate the assembly language instructions into machine code. The assembler program converts the written assembly language file (called source file) into machine code file (called object file). Another program, known as the linker, converts the object file into an executable file for practical run. It also generates a special file called the map file which is used to get the offset addresses of the segments in the main assembly program as shown in figure 1. Other tools needed in assembling coding include a debugger, and an editor as shown in figure 2 Figure 2. Program Development Procedure There are several commercial assemblers available like the Microsoft Macro Assembler (MASM), and the Borland Turbo Assembler (TASM).
    [Show full text]
  • X86 Assembly Language Syllabus for Subject: Assembly (Machine) Language
    VŠB - Technical University of Ostrava Department of Computer Science, FEECS x86 Assembly Language Syllabus for Subject: Assembly (Machine) Language Ing. Petr Olivka, Ph.D. 2021 e-mail: [email protected] http://poli.cs.vsb.cz Contents 1 Processor Intel i486 and Higher – 32-bit Mode3 1.1 Registers of i486.........................3 1.2 Addressing............................6 1.3 Assembly Language, Machine Code...............6 1.4 Data Types............................6 2 Linking Assembly and C Language Programs7 2.1 Linking C and C Module....................7 2.2 Linking C and ASM Module................... 10 2.3 Variables in Assembly Language................ 11 3 Instruction Set 14 3.1 Moving Instruction........................ 14 3.2 Logical and Bitwise Instruction................. 16 3.3 Arithmetical Instruction..................... 18 3.4 Jump Instructions........................ 20 3.5 String Instructions........................ 21 3.6 Control and Auxiliary Instructions............... 23 3.7 Multiplication and Division Instructions............ 24 4 32-bit Interfacing to C Language 25 4.1 Return Values from Functions.................. 25 4.2 Rules of Registers Usage..................... 25 4.3 Calling Function with Arguments................ 26 4.3.1 Order of Passed Arguments............... 26 4.3.2 Calling the Function and Set Register EBP...... 27 4.3.3 Access to Arguments and Local Variables....... 28 4.3.4 Return from Function, the Stack Cleanup....... 28 4.3.5 Function Example.................... 29 4.4 Typical Examples of Arguments Passed to Functions..... 30 4.5 The Example of Using String Instructions........... 34 5 AMD and Intel x86 Processors – 64-bit Mode 36 5.1 Registers.............................. 36 5.2 Addressing in 64-bit Mode.................... 37 6 64-bit Interfacing to C Language 37 6.1 Return Values..........................
    [Show full text]
  • Bitwise Operators in C Examples
    Bitwise Operators In C Examples Alphonse misworships discommodiously. Epigastric Thorvald perishes changefully while Oliver always intercut accusatively.his anthology plumps bravely, he shown so cheerlessly. Baillie argufying her lashkar coweringly, she mass it Find the program below table which is c operators associate from star from the positive Left shift shifts each bit in its left operand to the left. Tying up some Arduino loose ends before moving on. The next example shows you how to do this. We can understand this better using the following Example. These operators move each bit either left or right a specified number of times. Amazon and the Amazon logo are trademarks of Amazon. Binary form of these values are given below. Shifting the bits of the string of bitwise operators in c examples and does not show the result of this means the truth table for making. Mommy, security and web. When integers are divided, it shifts the bits to the right. Operators are the basic concept of any programming language, subtraction, we are going to see how to use bitwise operators for counting number of trailing zeros in the binary representation of an integer? Adding a negative and positive number together never means the overflow indicates an exception! Not valid for string or complex operands. Les cookies essentiels sont absolument necessaires au bon fonctionnement du site. Like the assembly in C language, unlike other magazines, you may treat this as true. Bitwise OR operator is used to turn bits ON. To me this looks clearer as is. We will talk more about operator overloading in a future section, and the second specifies the number of bit positions by which the first operand is to be shifted.
    [Show full text]
  • Introduction to X86 Assembly
    CS342 Computer Security Handout # 5 Prof. Lyn Turbak Monday, Oct. 04, 2010 Wellesley College Lab 4: Introduction to x86 Assembly Reading: Hacking, 0x250, 0x270 Overview Today, we continue to cover low-level programming details that are essential for understanding software vulnerabilities like buffer overflow attacks and format string exploits. You will get exposure to the following: • Understanding conventions used by compiler to translate high-level programs to low-level assembly code (in our case, using Gnu C Compiler (gcc) to compile C programs). • The ability to read low-level assembly code (in our case, Intel x86). • Understanding how assembly code instructions are represented as machine code. • Being able to use gdb (the Gnu Debugger) to read the low-level code produced by gcc and understand its execution. In tutorials based on this handout, we will learn about all of the above in the context of some simple examples. Intel x86 Assembly Language Since Intel x86 processors are ubiquitous, it is helpful to know how to read assembly code for these processors. We will use the following terms: byte refers to 8-bit quantities; short word refers to 16-bit quantities; word refers to 32-bit quantities; and long word refers to 64-bit quantities. There are many registers, but we mostly care about the following: • EAX, EBX, ECX, EDX are 32-bit registers used for general storage. • ESI and EDI are 32-bit indexing registers that are sometimes used for general storage. • ESP is the 32-bit register for the stack pointer, which holds the address of the element currently at the top of the stack.
    [Show full text]
  • NASM – the Netwide Assembler
    NASM – The Netwide Assembler version 2.14rc7 © 1996−2017 The NASM Development Team — All Rights Reserved This document is redistributable under the license given in the file "LICENSE" distributed in the NASM archive. Contents Chapter 1: Introduction . 17 1.1 What Is NASM?. 17 1.1.1 License Conditions . 17 Chapter 2: Running NASM . 19 2.1 NASM Command−Line Syntax . 19 2.1.1 The −o Option: Specifying the Output File Name . 19 2.1.2 The −f Option: Specifying the Output File Format . 20 2.1.3 The −l Option: Generating a Listing File . 20 2.1.4 The −M Option: Generate Makefile Dependencies. 20 2.1.5 The −MG Option: Generate Makefile Dependencies . 20 2.1.6 The −MF Option: Set Makefile Dependency File. 20 2.1.7 The −MD Option: Assemble and Generate Dependencies . 20 2.1.8 The −MT Option: Dependency Target Name . 21 2.1.9 The −MQ Option: Dependency Target Name (Quoted) . 21 2.1.10 The −MP Option: Emit phony targets . 21 2.1.11 The −MW Option: Watcom Make quoting style . 21 2.1.12 The −F Option: Selecting a Debug Information Format . 21 2.1.13 The −g Option: Enabling Debug Information. 21 2.1.14 The −X Option: Selecting an Error Reporting Format . 21 2.1.15 The −Z Option: Send Errors to a File. 22 2.1.16 The −s Option: Send Errors to stdout ..........................22 2.1.17 The −i Option: Include File Search Directories . 22 2.1.18 The −p Option: Pre−Include a File . 22 2.1.19 The −d Option: Pre−Define a Macro .
    [Show full text]
  • OCTANE Technical Report
    OCTANE Technical Report Silicon Graphics, Inc. ANY DUPLICATION, MODIFICATION, DISTRIBUTION, PUBLIC PERFORMANCE, OR PUBLIC DISPLAY OF THIS DOCUMENT WITHOUT THE EXPRESS WRITTEN CONSENT OF SILICON GRAPHICS, INC. IS STRICTLY PROHIBITED. THE RECEIPT OR POSSESSION OF THIS DOCUMENT DOES NOT CONVEY ANY RIGHTS TO REPRODUCE, DISCLOSE OR DISTRIBUTE ITS CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN PART. Cop VED Table of Contents Section 1 Introduction .....................................................................................................1-1 1.1 Manufacturing.............................................................................................................. 1-3 1.1.1 Industrial Design .....................................................................................1-3 1.1.2 CAD/CAM Solid Modeling ....................................................................1-4 1.1.3 Analysis...................................................................................................1-5 1.1.4 Digital Prototyping..................................................................................1-6 1.2 Entertainment............................................................................................................... 1-8 1.2.1 3D Animation..........................................................................................1-8 1.2.2 Film/Video/Audio ...................................................................................1-9 1.2.3 Publishing..............................................................................................1-10
    [Show full text]
  • (PSW). Seven Bits Remain Unused While the Rest Nine Are Used
    8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI The Flags Register It is a 16-bit register, also called Program Status Word (PSW). Seven bits remain unused while the rest nine are used. Six are status flags and three are control flags. The control flags can be set/reset by the programmer. 1. DF (Direction Flag) : controls the direction of operation of string instructions. (DF=0 Ascending order DF=1 Descending order) 2. IF (Interrupt Flag): controls the interrupt operation in 8086µP. (IF=0 Disable interrupt IF=1 Enable interrupt) 3. TF (Trap Flag): controls the operation of the microprocessor. (TF=0 Normal operation TF=1 Single Step operation) The status flags are set/reset depending on the results of some arithmetic or logical operations during program execution. 1. CF (Carry Flag) is set (CF=1) if there is a carry out of the MSB position resulting from an addition operation or subtraction. 2. AF (Auxiliary Carry Flag) AF is set if there is a carry out of bit 3 resulting from an addition operation. 3. SF (Sign Flag) set to 1 when result is negative. When result is positive it is set to 0. 4. ZF (Zero Flag) is set (ZF=1) when result of an arithmetic or logical operation is zero. For non-zero result this flag is reset (ZF=0). 5. PF (Parity Flag) this flag is set to 1 when there is even number of one bits in result, and to 0 when there is odd number of one bits. 6. OF (Overflow Flag) set to 1 when there is a signed overflow.
    [Show full text]