DOCSLIB.ORG

OCTANE Technical Report

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
OCTANE Technical Report OCTANE Technical Report Silicon Graphics, Inc. ANY DUPLICATION, MODIFICATION, DISTRIBUTION, PUBLIC PERFORMANCE, OR PUBLIC DISPLAY OF THIS DOCUMENT WITHOUT THE EXPRESS WRITTEN CONSENT OF SILICON GRAPHICS, INC. IS STRICTLY PROHIBITED. THE RECEIPT OR POSSESSION OF THIS DOCUMENT DOES NOT CONVEY ANY RIGHTS TO REPRODUCE, DISCLOSE OR DISTRIBUTE ITS CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN PART. Cop VED Table of Contents Section 1 Introduction .....................................................................................................1-1 1.1 Manufacturing.............................................................................................................. 1-3 1.1.1 Industrial Design .....................................................................................1-3 1.1.2 CAD/CAM Solid Modeling ....................................................................1-4 1.1.3 Analysis...................................................................................................1-5 1.1.4 Digital Prototyping..................................................................................1-6 1.2 Entertainment............................................................................................................... 1-8 1.2.1 3D Animation..........................................................................................1-8 1.2.2 Film/Video/Audio ...................................................................................1-9 1.2.3 Publishing..............................................................................................1-10 1.3 Defense/SImulation.................................................................................................... 1-12 1.3.1 Defense Imaging ...................................................................................1-12 1.3.2 Visual Simulation..................................................................................1-13 1.3.3 Geographic Information Systems (GIS) ...............................................1-14 1.4 Sciences...................................................................................................................... 1-15 1.4.1 Oil and Gas............................................................................................1-15 1.4.2 Chemistry ..............................................................................................1-15 1.4.3 Medical Imaging ...................................................................................1-17 Section 2 System Architecture ........................................................................................2-1 2.1 Architectural Overview................................................................................................ 2-1 2.1.1 Bus Bandwidth and Frequency ...............................................................2-1 2.1.2 OCTANE Board Layout .........................................................................2-3 2.1.3 Packet Switching.....................................................................................2-4 2.1.4 Unfair Arbitration ...................................................................................2-4 2.1.5 Guaranteed Bandwidth and Latency .......................................................2-5 2.1.6 Data Transfer Types................................................................................2-5 2.1.7 Link Level Protocol ................................................................................2-6 2.1.8 System Modularity..................................................................................2-6 2.2 R10000 Processor ........................................................................................................ 2-7 2.2.1 Register Renaming..................................................................................2-8 2.2.2 Out-of-Order Execution ..........................................................................2-9 2.2.3 Non-Blocking Caches .............................................................................2-9 2.2.4 Branch Prediction....................................................................................2-9 2.2.5 Primary Data Cache ..............................................................................2-11 2.2.6 Primary Instruction Cache ....................................................................2-11 2.2.7 Secondary Cache Interface....................................................................2-11 2.2.8 Instruction Queues ................................................................................2-11 2.2.9 System Interface....................................................................................2-12 2.3 System ASICs ............................................................................................................ 2-12 2.3.1 Crossbow ASIC.....................................................................................2-12 2.3.2 Heart ASIC............................................................................................2-15 2.3.3 Bridge ASIC..........................................................................................2-19 2.4 Memory System......................................................................................................... 2-21 2.4.1 Synchronous DRAMs ...........................................................................2-23 2.4.2 Memory Data Integrity..........................................................................2-24 2.5 I/O Subsystem............................................................................................................ 2-25 2.5.1 SCSI Interface .......................................................................................2-26 2.5.2 Keyboard and Mouse ............................................................................2-27 2.5.3 Ethernet Interface..................................................................................2-28 2.5.4 Serial Port Interface ..............................................................................2-28 2.5.5 Parallel Port Interface............................................................................2-28 Section 3 Audio Architecture..........................................................................................3-1 3.1 Audio System............................................................................................................... 3-1 3.1.1 Software Compatibility ...........................................................................3-2 3.1.2 Synchronization ......................................................................................3-3 3.1.3 Scalability................................................................................................3-3 3.1.4 Architectural Overview...........................................................................3-4 3.1.5 Audio Configurations..............................................................................3-6 3.1.6 The RAD ASIC.....................................................................................3-10 3.1.7 Standard Audio Peripherals ..................................................................3-11 Section 4 Graphics Architecture .....................................................................................4-1 4.1 Graphics Configurations .............................................................................................. 4-1 4.1.1 Solid Impact (SI).....................................................................................4-2 4.1.2 Solid Impact with Texture Option ..........................................................4-3 4.1.3 Super Solid Impact (SSI) ........................................................................4-4 4.1.4 Maximum Impact Option (MXI) ............................................................4-5 4.2 Graphics Subsystem Components................................................................................ 4-6 4.2.1 HQ4 - Bus Interface ASIC ......................................................................4-6 4.2.2 GE11 - Geometry Engine ASIC..............................................................4-7 4.2.3 RE4 - Raster Engine................................................................................4-7 4.2.4 TE1 - Texture Engine..............................................................................4-8 4.2.5 TRAM - Texture RAM ...........................................................................4-9 4.2.6 HRBE - High Resolution Back End Circuitry ......................................4-11 4.3 Graphics Data Flow ................................................................................................... 4-11 4.4 OCTANE Graphics Features...................................................................................... 4-13 4.4.1 MicroPixel Sub-Pixel Positioning.........................................................4-13 4.4.2 Blending ................................................................................................4-13 4.4.3 Point Anti-Aliasing ...............................................................................4-14 4.4.4 Line Anti-Aliasing ................................................................................4-14 4.4.5 Accumulation Buffer.............................................................................4-14 4.4.6 Lighting Features ..................................................................................4-15 4.4.7 Local Light and Viewer Positioning
Load more

Recommended publications
  • SGI® Octane III®
    Making ® ® Supercomputing SGI Octane III Personal™ KEY FEATURES Supercomputing Gets Personal Octane III takes high-performance computing out Office Ready of the data center and puts it at the deskside. It A pedestal, one foot by two combines the immense power and performance broad HPC application support and arrives ready foot form factor and capabilities of a high-performance cluster with the for immediate integration for a smooth out-of-the- quiet operation portability and usability of a workstation to enable box experience. a new era of personal innovation in strategic science, research, development and visualization. Octane III allows a wide variety of single and High Performance dual-socket node choices and a wide selection of Up to 120 high- In contrast with standard dual-processor performance, storage, integrated networking, and performance cores and workstations with only eight cores and moderate graphics and compute GPU options. The system nearly 2TB of memory memory capacity, the superior design of is available as an up to ten node deskside cluster Broad HPC Application Octane III permits up to 120 high-performance configuration or dual-node graphics workstation Support cores and nearly 2TB of memory. Octane III configurations. Accelerated time-to-results significantly accelerates time-to-results for over with support for over 50 50 HPC applications and supports the latest Supported operating systems include: ® ® ® HPC applications Intel processors to capitalize on greater levels SUSE Linux Enterprise Server and Red Hat of performance, flexibility and scalability. Pre- Enterprise Linux. All configurations are available configured with system software, cluster set up is with pre-loaded SGI® Performance Suite system Ease of Use a breeze.
    [Show full text]
  • Interactive Rendering with Coherent Ray Tracing
    EUROGRAPHICS 2001 / A. Chalmers and T.-M. Rhyne Volume 20 (2001), Number 3 (Guest Editors) Interactive Rendering with Coherent Ray Tracing Ingo Wald, Philipp Slusallek, Carsten Benthin, and Markus Wagner Computer Graphics Group, Saarland University Abstract For almost two decades researchers have argued that ray tracing will eventually become faster than the rasteri- zation technique that completely dominates todays graphics hardware. However, this has not happened yet. Ray tracing is still exclusively being used for off-line rendering of photorealistic images and it is commonly believed that ray tracing is simply too costly to ever challenge rasterization-based algorithms for interactive use. However, there is hardly any scientific analysis that supports either point of view. In particular there is no evidence of where the crossover point might be, at which ray tracing would eventually become faster, or if such a point does exist at all. This paper provides several contributions to this discussion: We first present a highly optimized implementation of a ray tracer that improves performance by more than an order of magnitude compared to currently available ray tracers. The new algorithm makes better use of computational resources such as caches and SIMD instructions and better exploits image and object space coherence. Secondly, we show that this software implementation can challenge and even outperform high-end graphics hardware in interactive rendering performance for complex environments. We also provide an brief overview of the benefits of ray tracing over rasterization algorithms and point out the potential of interactive ray tracing both in hardware and software. 1. Introduction Ray tracing is famous for its ability to generate high-quality images but is also well-known for long rendering times due to its high computational cost.
    [Show full text]
  • Computing @SERC Resources,Services and Policies
    Computing @SERC Resources,Services and Policies R.Krishna Murthy SERC - An Introduction • A state-of-the-art Computing facility • Caters to the computing needs of education and research at the institute • Comprehensive range of systems to cater to a wide spectrum of computing requirements. • Excellent infrastructure supports uninterrupted computing - anywhere, all times. SERC - Facilities • Computing - – Powerful hardware with adequate resources – Excellent Systems and Application Software,tools and libraries • Printing, Plotting and Scanning services • Help-Desk - User Consultancy and Support • Library - Books, Manuals, Software, Distribution of Systems • SERC has 5 floors - Basement,Ground,First,Second and Third • Basement - Power and Airconditioning • Ground - Compute & File servers, Supercomputing Cluster • First floor - Common facilities for Course and Research - Windows,NT,Linux,Mac and other workstations Distribution of Systems - contd. • Second Floor – Access Stations for Research students • Third Floor – Access Stations for Course students • Both the floors have similar facilities Computing Systems Systems at SERC • ACCESS STATIONS *SUN ULTRA 20 Workstations – dual core Opteron 4GHz cpu, 1GB memory * IBM INTELLISTATION EPRO – Intel P4 2.4GHz cpu, 512 MB memory Both are Linux based systems OLDER Access stations * COMPAQ XP 10000 * SUN ULTRA 60 * HP C200 * SGI O2 * IBM POWER PC 43p Contd... FILE SERVERS 5TB SAN storage IBM RS/6000 43P 260 : 32 * 18GB Swappable SSA Disks. Contd.... • HIGH PERFORMANCE SERVERS * SHARED MEMORY MULTI PROCESSOR • IBM P-series 690 Regatta (32proc.,256 GB) • SGI ALTIX 3700 (32proc.,256GB) • SGI Altix 350 ( 16 proc.,16GB – 64GB) Contd... * IBM SP3. NH2 - 16 Processors WH2 - 4 Processors * Six COMPAQ ALPHA SERVER ES40 4 CPU’s per server with 667 MHz.
    [Show full text]
  • OCTANE® Workstation Owner's Guide
    OCTANE® Workstation Owner’s Guide Document Number 007-3435-003 CONTRIBUTORS Written by Charmaine Moyer Production by Linda Rae Sande Illustrated by Kwong Liew Engineering contributions by Jim Bergman, Brian Bolich, Bob Cook, Mark Glusker, John Hahn, Steve Manzi, Ted Marsh, Donna McMaster, Jim Pagura, Michael Poimboeuf, Brad Reger, Jose Reinoso, Bob Sanders, Chris Wheaton, Michael Wright, and many others on the OCTANE engineering and business team. St. Peter’s Basilica image courtesy of ENEL SpA and InfoByte SpA. Disk Thrower image courtesy of Xavier Berenguer, Animatica. © 1997 - 1999, Silicon Graphics, Inc.— All Rights Reserved The contents of this document may not be copied or duplicated in any form, in whole or in part, without the prior written permission of Silicon Graphics, Inc. LIMITED AND RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictionsas set forth in the Rights in Data clause at FAR 52.227-14 and/or in similar orsuccessor clauses in the FAR, or in the DOD, DOE or NASA FAR Supplements.Unpublished rights reserved under the Copyright Laws of the United States.Contractor/manufacturer is Silicon Graphics, Inc., 2011 N. Shoreline Blvd., Mountain View, CA 94043-1389. Silicon Graphics, IRIS, IRIX, and OCTANE are registered trademarks and the Silicon Graphics logo, IRIX Interactive Desktop, Power Fortran Accelerator, IRIS InSight, and Stereoview are trademarks of Silicon Graphics, Inc. ADAT is a registered trademark of Alesis Corporation. Centronics is a registered trademark of Centronics Data Computer Corporation. Envi-ro-tech is a trademark of TECHSPRAY. Macintosh is a registered trademark of Apple Computer, Inc.
    [Show full text]
  • AVS on UNIX WORKSTATIONS INSTALLATION/ RELEASE NOTES
    _________ ____ AVS on UNIX WORKSTATIONS INSTALLATION/ RELEASE NOTES ____________ Release 5.5 Final (50.86 / 50.88) November, 1999 Advanced Visual Systems Inc.________ Part Number: 330-0120-02 Rev L NOTICE This document, and the software and other products described or referenced in it, are con®dential and proprietary products of Advanced Visual Systems Inc. or its licensors. They are provided under, and are subject to, the terms and conditions of a written license agreement between Advanced Visual Systems and its customer, and may not be transferred, disclosed or otherwise provided to third parties, unless oth- erwise permitted by that agreement. NO REPRESENTATION OR OTHER AFFIRMATION OF FACT CONTAINED IN THIS DOCUMENT, INCLUDING WITHOUT LIMITATION STATEMENTS REGARDING CAPACITY, PERFORMANCE, OR SUI- TABILITY FOR USE OF SOFTWARE DESCRIBED HEREIN, SHALL BE DEEMED TO BE A WARRANTY BY ADVANCED VISUAL SYSTEMS FOR ANY PURPOSE OR GIVE RISE TO ANY LIABILITY OF ADVANCED VISUAL SYSTEMS WHATSOEVER. ADVANCED VISUAL SYSTEMS MAKES NO WAR- RANTY OF ANY KIND IN OR WITH REGARD TO THIS DOCUMENT, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PUR- POSE. ADVANCED VISUAL SYSTEMS SHALL NOT BE RESPONSIBLE FOR ANY ERRORS THAT MAY APPEAR IN THIS DOCUMENT AND SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMI- TATION INCIDENTAL, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF OR RELATED TO THIS DOCUMENT OR THE INFORMATION CONTAINED IN IT, EVEN IF ADVANCED VISUAL SYSTEMS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. The speci®cations and other information contained in this document for some purposes may not be com- plete, current or correct, and are subject to change without notice.
    [Show full text]
  • Running.1997.2.Pdf
    SEMI-ANNUAL REPORT NASA CONTRACT NAS5-31368 FOR MODIS TEAM MEMBER STEVEN W. RUNNING ASSOC. TEAM MEMBER RAMAKRISHNA R. NEMANI SOFTWARE ENGINEER JOSEPH GLASSY July 15, 1997 PRE-LAUNCH TASKS PROPOSED IN OUR CONTRACT OF DECEMBER 1991 We propose, during the pre-EOS phase to: (1) develop, with other MODIS Team Members, a means of discriminating different major biome types with NDVI and other AVHRR-based data. (2) develop a simple ecosystem process model for each of these biomes, BIOME-BGC (3) relate the seasonal trend of weekly composite NDVI to vegetation phenology and temperature limits to develop a satellite defined growing season for vegetation; and (4) define physiologically based energy to mass conversion factors for carbon and water for each biome. Our final core at-launch product will be simplified, completely satellite driven biome specific models for net primary production. We will build these biome specific satellite driven algorithms using a family of simple ecosystem process models as calibration models, collectively called BIOME-BGC, and establish coordination with an existing network of ecological study sites in order to test and validate these products. Field datasets will then be available for both BIOME-BGC development and testing, use for algorithm developments of other MODIS Team Members, and ultimately be our first test point for MODIS land vegetation products upon launch. We will use field sites from the National Science Foundation Long-Term Ecological Research network, and develop Glacier National Park as a major site for intensive validation. OBJECTIVES: We have defined the following near-term objectives for our MODIS contract based on the long term objectives stated above: -Organization of an EOS ground monitoring network with collaborating U.S.
    [Show full text]
  • IRIX® Admin System Configuration and Operation
    IRIX® Admin System Configuration and Operation 007-2859-017 COPYRIGHT © 1992-2001 Silicon Graphics, Inc. All rights reserved; provided portions may be copyright in third parties, as indicated elsewhere herein. No permission is granted to copy, distribute, or create derivative works from the contents of this electronic documentation in any manner, in whole or in part, without the prior written permission of Silicon Graphics, Inc. LIMITED RIGHTS LEGEND The electronic (software) version of this document was developed at private expense; if acquired under an agreement with the USA government or any contractor thereto, it is acquired as "commercial computer software" subject to the provisions of its applicable license agreement, as specified in (a) 48 CFR 12.212 of the FAR; or, if acquired for Department of Defense units, (b) 48 CFR 227-7202 of the DoD FAR Supplement; or sections succeeding thereto. Contractor/manufacturer is Silicon Graphics, Inc., 1600 Amphitheatre Pkwy 2E, Mountain View, CA 94043-1351. TRADEMARKS AND ATTRIBUTIONS Challenge, Indigo, IRIS, IRIX, Octane, and Onyx are registered trademarks and SGI, Crimson, Indigo2, IRIS FailSafe, IRIS InSight, IRIS WorkSpace, IRIX Networker, NUMAlink, Origin, Performance Co-Pilot, Power Challenge, Power Indigo2, Power Onyx, the SGI logo, and XFS are trademarks of Silicon Graphics, Inc. Indy is a registered trademark, used under license in the United States and owned by Silicon Graphics, Inc., in other countries worldwide. Centronics is a trademark of Centronics Data Computer Corporation. Cray is a registered trademark of Cray, Inc. Documenter’s Workbench is a trademark of Novell, Inc. FrameMaker, Illustrator, and PostScript are trademarks of Adobe Systems, Incorporated.
    [Show full text]
  • Translating Research Into Business
    THE STATE OF SÃO PAULO RESEARCH FOUNDATION Translating Research into Business Ten years promoting technological innovation THE STATE OF SÃO PAULO RESEARCH FOUNDATION Carlos Vogt President Marcos Macari Vice-president BOARD OF TRUSTEES Adilson Avansi de Abreu Carlos Vogt Celso Lafer Hermann Wever Horácio Lafer Piva Hugo Aguirre Armelin José Arana Varela Marcos Macari Nilson Dias Vieira Júnior Vahan Agopyan Yoshiaki Nakano EXECUTIVE BOARD Ricardo Renzo Brentani Chief Executive Carlos Henrique de Brito Cruz Scientific Director Joaquim José de Camargo Engler Administrative Director Translating Research into Business Ten years promoting technological innovation Projects supported by FAPESP in the Partnership for Technological Innovation and Technological Innovation in Small Businesses Programs 2005 Catalogação-na-publicação elaborada pelo Centro de Documentação e Informação da FAPESP The State of São Paulo Research Foundation. Translating research into business : ten years promoting technological innovation : projects supported by FAPESP in the Partnership for Technological Innovation and Technological Innovation in Small Businesses programs / The State of São Paulo Research Foundation – São Paulo : FAPESP, 2005. 256 p. : il. ; 28 cm. Tradução de: A pesquisa traduzida em negócios : dez anos de incentivo à inovação tecnológica : projetos apoiados pela FAPESP nos programas Parceria para Inovação Tecnológica e Inovação Tecnológica em Pequenas Empresas. I. Título II. Título: Ten years promoting technological innovation. III. Título: Projects supported by FAPESP in the Partnership for Technological Innovation and Technological Innovation in Small Businesses programs. 1.FAPESP 2. Pesquisa e desenvolvimento – São Paulo 3. Ciência 4. Tecnologia 5. Inovação tecnológica 6. Inovação Tecnológica em Pequenas Empresas 7. PIPE 8. Parceria para Inovação Tecnológica 9. PITE 04/05 CDD 507.208161 Depósito Legal na Biblioteca Nacional, conforme Lei n.º 10.994, de 14 de dezembro de 2004.
    [Show full text]
  • From Classical to Runtime Aware Architectures
    From Classical to Runtime Aware Architectures Prof. Mateo Valero BSC Director Barcelona, July 4, 2018 Professor Tomas Lang Once upon a time … Our Origins… Parsys Multiprocessor Parsytec CCi-8D Compaq GS-160 Maricel 4.45 Gflop/s Compaq GS-140 BULL NovaScale 5160 12.5 Gflop/s 23.4 Gflop/s 48 Gflop/s 14.4 Tflops, 20 KW Transputer cluster Convex C3800 SGI Origin 2000 SGI Altix 4700 SL8500 32 Gflop/s 819.2 Gflops 6 Petabytes Connection Machine CM-200 Research prototypes 0,64 Gflop/s IBM RS-6000 SP & IBM p630 192+144 Gflop/s IBM PP970 / Myrinet MareNostrum 42.35, 94.21 Tflop/s 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 Barcelona Supercomputing Center Centro Nacional de Supercomputación BSC-CNS objectives Supercomputing services R&D in Computer, PhD programme, to Spanish and Life, Earth and technology transfer, EU researchers Engineering Sciences public engagement Spanish Government 60% BSC-CNS is a consortium Catalan Government 30% that includes Univ. Politècnica de Catalunya (UPC) 10% Mission of BSC Scientific Departments Computer Earth Sciences Sciences To influence the way machines are built, programmed To develop and implement global and and used: programming models, performance tools, regional state-of-the-art models for short- Big Data, computer architecture, energy efficiency term air quality forecast and long-term climate applications Life CASE Sciences To develop scientific and engineering software to To understand living organisms by means of efficiently
    [Show full text]
  • SGI™ Origin 3000 Series Technical Configuration Owner's Guide
    SGI™ Origin 3000 Series Technical Configuration Owner’s Guide Document Number 007-4311-002 CONTRIBUTORS Written by Dick Brownell Illustrated by Dan Young Production by Diane Ciardelli Engineering contributions by SN1 Electrical, Mechanical, Manufacturing, Marketing, and Site Planning teams COPYRIGHT © 2000 Silicon Graphics, Inc. All rights reserved; provided portions may be copyright in third parties, as indicated elsewhere herein. No permission is granted to copy, distribute, or create derivative works from the contents of this electronic documentation. The contents of this document may not be copied or duplicated in any form, in whole or in part, without the prior written permission of Silicon Graphics, Inc. LIMITED RIGHTS LEGEND The electronic (software) version of this document was developed at private expense; if acquired under an agreement with the USA government or any contractor thereto, it is acquired as “commercial computer software” subject to the provisions of its applicable license agreement, as specified in (a) 48 CFR 12.212 of the FAR; or if acquired for Department of Defense units, (b) 48 CFR 227-7202 of the DoD FAR Supplement; or sections succeeding thereto. Contractor/manufacturer is Silicon Graphics, Inc., 1600 Amphitheatre Pkwy. 2E, Mountain View, CA 94043-1351. TRADEMARKS AND ATTRIBUTIONS Silicon Graphics is a registered trademark and SGI, the SGI logo, Origin, Onyx3, and IRIS InSight are trademarks of Silicon Graphics, Inc. PostScript is a trademark of Adobe Systems, Inc. MIPS is a registered trademark of MIPS Technologies, Inc. Windows and Windows NT are registered trademarks of Microsoft Corporation. DVCPRO is a trademark of Panasonic, Inc. Linux is a registered trademark of Linus Torvalds.
    [Show full text]
  • 5.3.1 Chyby Na SGI O2
    VYSOKÉ UČENÍ TECHNICKÉ V BRNĚ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA INFORMAČNÍCH TECHNOLOGIÍ ÚSTAV INFORMAČNÍCH SYSTÉMŮ FACULTY OF INFORMATION TECHNOLOGY DEPARTMENT OF INFORMATION SYSTEMS TESTOVÁNÍ PAMĚTI NA ARCHITEKTUŘE SGI/MIPS BAKALÁŘSKÁ PRÁCE BACHELOR‘S THESIS AUTOR PRÁCE Karol Rydlo AUTHOR BRNO 2009 VYSOKÉ UČENÍ TECHNICKÉ V BRNĚ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA INFORMAČNÍCH TECHNOLOGIÍ ÚSTAV POČÍTAČOVÝCH SYSTÉMŮ FACULTY OF INFORMATION TECHNOLOGY DEPARTMENT OF COMPUTER SYSTEMS TESTOVÁNÍ PAMĚTI NA ARCHITEKTUŘE SGI/MIPS MEMORY TESTING ON SGI/MIPS ARCHITECTIRE BAKALÁŘSKÁ PRÁCE BACHELOR‘S THESIS AUTOR PRÁCE Karol Rydlo AUTHOR VEDOUCÍ PRÁCE Ing. Tomáš Kašpárek SUPERVISOR BRNO 2009 Abstrakt Moje bakalářská práce se zabývá zprovozněním a vytvořením vlastních testů paměti na grafických stanicích SGI O2, což sebou přináší seznámení se s architekturou procesorů MIPS a pokouší se najít ideální prostředí pro provádění těchto testů. S tím úzce souvisí hledání vhodného způsobu spouštění a překladu aplikací pro stanice SGI O2, kde se zabývá také využitím křížových kompilátorů. Abstract Work is engaged in making solution for creating own memory tests on graphical station SGI O2. This thesis produces work on MIPS processor architecture and it try to find the ideal environments for testing memory and with it is nearly related looking for chances of start and compile application for SGI O2. Part of my thesis is also target using cross-compilers, for effective and useful work with program for other architecture. Klíčová slova Testování paměti, RAM,
    [Show full text]
  • An Investigation Into the Cost Factors of Special Effects in Computer Graphics
    An Investigation into the Cost Factors Of Special Effects in Computer Graphics Submitted in partial fulfilment of degree Bachelor of Science (Honours) By Adrian Charteris Rhodes University Computer Science Honours Adrian Charteris Computer Science Honours 2000 November 2000 Abstract Here within we explore one of the current benchmarks that exist in the market place today, namely SPEC, we follow it up with a case study of their main benchmark products. We also explore and discuss the philosophies behind general benchmarking including some of the pitfalls or challenges that face benchmark developers and outline various benchmark categories identified throughout our research. After presenting the related work in this field, we move on to our own benchmark experiment. In our experiment we hope to gain a richer understanding or appreciation of the benchmarking process through the development of our own practical implementation. We identify a number of fields within performance measurement that we feel need further exploration. These fields include the measuring of cost factors incurred when introducing graphical special effects. We record the performance of local graphics accelerators when these special effects are introduced. This includes the related strengths and weaknesses of each accelerator. The tests introduce the following special effects z- buffering, blending, fog and light. We apply these effects to the rendering of three basic primitives, namely the point, the line and the polygon. We measure the increases in performance time with the introduction of these special effects in order to determine the performance of various graphics accelerators. We rank both the special effects and the graphics accelerators. We also measure the difference between 2D and 3D rendering.
    [Show full text]