OCTANE Technical Report Silicon Graphics, Inc. ANY DUPLICATION, MODIFICATION, DISTRIBUTION, PUBLIC PERFORMANCE, OR PUBLIC DISPLAY OF THIS DOCUMENT WITHOUT THE EXPRESS WRITTEN CONSENT OF SILICON GRAPHICS, INC. IS STRICTLY PROHIBITED. THE RECEIPT OR POSSESSION OF THIS DOCUMENT DOES NOT CONVEY ANY RIGHTS TO REPRODUCE, DISCLOSE OR DISTRIBUTE ITS CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN PART. Cop VED Table of Contents Section 1 Introduction .....................................................................................................1-1 1.1 Manufacturing.............................................................................................................. 1-3 1.1.1 Industrial Design .....................................................................................1-3 1.1.2 CAD/CAM Solid Modeling ....................................................................1-4 1.1.3 Analysis...................................................................................................1-5 1.1.4 Digital Prototyping..................................................................................1-6 1.2 Entertainment............................................................................................................... 1-8 1.2.1 3D Animation..........................................................................................1-8 1.2.2 Film/Video/Audio ...................................................................................1-9 1.2.3 Publishing..............................................................................................1-10 1.3 Defense/SImulation.................................................................................................... 1-12 1.3.1 Defense Imaging ...................................................................................1-12 1.3.2 Visual Simulation..................................................................................1-13 1.3.3 Geographic Information Systems (GIS) ...............................................1-14 1.4 Sciences...................................................................................................................... 1-15 1.4.1 Oil and Gas............................................................................................1-15 1.4.2 Chemistry ..............................................................................................1-15 1.4.3 Medical Imaging ...................................................................................1-17 Section 2 System Architecture ........................................................................................2-1 2.1 Architectural Overview................................................................................................ 2-1 2.1.1 Bus Bandwidth and Frequency ...............................................................2-1 2.1.2 OCTANE Board Layout .........................................................................2-3 2.1.3 Packet Switching.....................................................................................2-4 2.1.4 Unfair Arbitration ...................................................................................2-4 2.1.5 Guaranteed Bandwidth and Latency .......................................................2-5 2.1.6 Data Transfer Types................................................................................2-5 2.1.7 Link Level Protocol ................................................................................2-6 2.1.8 System Modularity..................................................................................2-6 2.2 R10000 Processor ........................................................................................................ 2-7 2.2.1 Register Renaming..................................................................................2-8 2.2.2 Out-of-Order Execution ..........................................................................2-9 2.2.3 Non-Blocking Caches .............................................................................2-9 2.2.4 Branch Prediction....................................................................................2-9 2.2.5 Primary Data Cache ..............................................................................2-11 2.2.6 Primary Instruction Cache ....................................................................2-11 2.2.7 Secondary Cache Interface....................................................................2-11 2.2.8 Instruction Queues ................................................................................2-11 2.2.9 System Interface....................................................................................2-12 2.3 System ASICs ............................................................................................................ 2-12 2.3.1 Crossbow ASIC.....................................................................................2-12 2.3.2 Heart ASIC............................................................................................2-15 2.3.3 Bridge ASIC..........................................................................................2-19 2.4 Memory System......................................................................................................... 2-21 2.4.1 Synchronous DRAMs ...........................................................................2-23 2.4.2 Memory Data Integrity..........................................................................2-24 2.5 I/O Subsystem............................................................................................................ 2-25 2.5.1 SCSI Interface .......................................................................................2-26 2.5.2 Keyboard and Mouse ............................................................................2-27 2.5.3 Ethernet Interface..................................................................................2-28 2.5.4 Serial Port Interface ..............................................................................2-28 2.5.5 Parallel Port Interface............................................................................2-28 Section 3 Audio Architecture..........................................................................................3-1 3.1 Audio System............................................................................................................... 3-1 3.1.1 Software Compatibility ...........................................................................3-2 3.1.2 Synchronization ......................................................................................3-3 3.1.3 Scalability................................................................................................3-3 3.1.4 Architectural Overview...........................................................................3-4 3.1.5 Audio Configurations..............................................................................3-6 3.1.6 The RAD ASIC.....................................................................................3-10 3.1.7 Standard Audio Peripherals ..................................................................3-11 Section 4 Graphics Architecture .....................................................................................4-1 4.1 Graphics Configurations .............................................................................................. 4-1 4.1.1 Solid Impact (SI).....................................................................................4-2 4.1.2 Solid Impact with Texture Option ..........................................................4-3 4.1.3 Super Solid Impact (SSI) ........................................................................4-4 4.1.4 Maximum Impact Option (MXI) ............................................................4-5 4.2 Graphics Subsystem Components................................................................................ 4-6 4.2.1 HQ4 - Bus Interface ASIC ......................................................................4-6 4.2.2 GE11 - Geometry Engine ASIC..............................................................4-7 4.2.3 RE4 - Raster Engine................................................................................4-7 4.2.4 TE1 - Texture Engine..............................................................................4-8 4.2.5 TRAM - Texture RAM ...........................................................................4-9 4.2.6 HRBE - High Resolution Back End Circuitry ......................................4-11 4.3 Graphics Data Flow ................................................................................................... 4-11 4.4 OCTANE Graphics Features...................................................................................... 4-13 4.4.1 MicroPixel Sub-Pixel Positioning.........................................................4-13 4.4.2 Blending ................................................................................................4-13 4.4.3 Point Anti-Aliasing ...............................................................................4-14 4.4.4 Line Anti-Aliasing ................................................................................4-14 4.4.5 Accumulation Buffer.............................................................................4-14 4.4.6 Lighting Features ..................................................................................4-15 4.4.7 Local Light and Viewer Positioning