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Flexnoc® Resilience Package Arteris Flexnoc Resilience Package IP

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Flexnoc® Resilience Package Arteris Flexnoc Resilience Package IP Arteris® ® FlexNoC Resilience Package Arteris FlexNoC Resilience Package IP The Arteris FlexNoC Resilience Package is a complementary product to Arteris FlexNoC fabric IP. It implements hardware resilience features essential for systems-on-chip (SoCs) targeted for mission- LEARN MORE critical uses, such as those requiring ISO 26262 / ASIL (automotive) or IEC 61508 compliance. www.Arteris.com END-TO-END HARDWARE RESILIENCE FOR SOCs Resilience and Functional Safety Currently developed systems-on-chip for safety-related applications in the automotive, industrial ® ® and medical markets use CPU cores like the ARM Cortex -R5 and Cortex-R7 processors. These HIGHLIGHTS types of CPU core IP implement techniques like ECC and parity data protection, dual-core lockstep (DCLS) redundancy, duplicated internal memories, safety checkers, and built-in self-tests (BIST). The 1st and only commer- cial interconnect fabric IP to provide built-in sup- port for ARM® Cortex®- R5 and Cortex-R7 pro- cessor port checking. End-to-End protection of any or all IP-to-IP commu- nications within the SoC, selectable by the user. Advanced Technology: Unit duplication and com- parison, custom transport protection, packet validity checking, transaction timeout, control register parity checking, BIST and fault controller. Supplements existing SoC fabric, making it easy However, this CPU-only approach neglects to provide end-to-end protection from master to slave. to add safety features to an End-to-end protection can only be provided by implementing resilience features in the on-chip existing SoC or partition an interconnect. SoC into safe and non-safe regions. The FlexNoC Resilience Package enables the implementation of data protection and control fea- tures like these within the on-chip interconnect fabric. Importantly, implementation does not re- Integrated, automated quire replacing an existing FlexNoC interconnect. In fact, it is possible and often desirable to parti- and flexible, taking ad- tion an existing SoC design into portions that have data protection enabled, and those that do not. vantage of the existing Arteris FlexNoC tool suite BENEFITS including user interface, ARM Cortex-R5 and Cortex–R7 Support: The Arteris FlexNoC Resilience Package is the simulation (FlexExplorer) only IP fabric that provides the out-of-the-box support for Cortex-R5 and Cortex–R7 Processor and verification Port Checking. (FlexVerifier). Arteris® ® FlexNoC Resilience Package Protection for Any IP: In addition to consuming CPU core-generated protection, the ADVANTAGES FlexNoC Resilience Package can generate custom data payload and control protection at the IP fabric edge to protect any IP block, and correct errors in any NoC packet-consuming units. Built-in support for ARM Cortex-R5 and Cortex- End-to-End Protection: FlexNoC Resilience Package is the only commercial IP fabric solu- R7 processor safety tion that enables protection of all data and signaling paths within an SoC, whether the con- features nected IP blocks generate their own data protection or not. Advanced hardware technology to meet ISO Duplication & Redundancy—Intelligent Protection: In addition to ECC and parity data 26262 / ASIL and IEC protection, the FlexNoC Resilience Package can implement unit duplication and comparison 61508 compliance similar to proven dual-core lockstep (DCLS) techniques. Data checkers can also be duplicated, Seamlessly integrated as can any IP fabric logic that can change the contents of on-chip data. with Arteris FlexNoC for Automation—More Productivity in Less Time: Adopting the FlexNoC Resilience Package short learning curve does not require the replacement of existing fabric IP or tools. Using it is as simple as select- and ease-of-use ing the type of protection desired for protected paths within the fabric using the existing, easy Built-in simulation and -to-use FlexNoC user interface. Users also benefit from existing FlexNoC capabilities, like verification test bench FlexExplorer and FlexVerifier. creation Easy partitioning of Partitioning—Safe and Non-Safe SoC regions: The FlexNoC Resilience Package was ar- SoCs chitected to enable user to easily specify which parts of an SoC require resilience, and which do not. This enables end users to quickly take an existing commercial SoC and create a deriv- ative product targeting a use case with safety compliance requirements. ANALYST PERSPECTIVE “A growing number (of semi- ARTERIS conductor vendors) are turn- ing to safety and security CUSTOMER “Altera SoC FPGAs are architected to ensure customers have a solid foundation upon which to build their embedded optimized network-on-chip SUCCESS systems, and using Arteris’ network-on-chip IP has helped subsystems for SoCs, such us create a superior SoC FPGA,” said Ty Garibay, Vice Presi- as the FlexNoC Resilience dent, IC Engineering at Altera. “The Arteris FlexNoC Resili- ence IP will make it easier for Altera to implement more package, to lower the devel- dependable SoC FPGAs for fault tolerant systems in the opment costs and time it future.” takes to achieve the ISO Ty Garibay, Vice President, IC Engineering, Altera 26262 certification enabling both media intense pro- “We have worked with Arteris cessing and certifiable mis- NoC technology since 2010, sion critical solutions in an and are excited that Arteris has “Arteris FlexNoC fabric IP has been our choice for SoC de- integrated SoC.” brought its significant engi- velopment since 2008. The data protection and redundancy neering prowess to help solve features included in the FlexNoC Resilience Package will Tom Hackenberg, Automotive the problems of fault tolerant help us design and implement our fault tolerant SoCs faster Embedded Processors Principle and reliable SoC design.” and at a higher quality level than possible before.” Analyst, HIS Technology Elchanan Rushinek, Vice Presi- Matthias Voigt, General Manager, Engineering Group, dent of Engineering, Mobileye Renesas Electronics Europe ABOUT ARTERIS LEARN MORE Arteris invented Network on Chip interconnect technology, offering the world’s first commercial solution in 2006. Arteris connects the IP blocks in semiconductors from Altera, Samsung, TI, Freescale, HiSilicon, Spread- www.Arteris.com trum, RDA, Renesas Electronics, NTT Electronics, Toshiba, LG and many others. Arteris and FlexNoC are trademarks of Arteris Inc. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other trademarks are the property of their respec- tive owners. © 2014 Arteris Inc. .
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