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MIPI Low Latency Interface (LLI) for Mobile Phone Bom Cost Savings MIPI Low Latency Interface (LLI) for Mobile Phone BoM Cost Savings Scott Yang Greater China Country Manger Arteris Inc 1 Copyright © 2012 MIPI Alliance. All rights reserved. Legal Disclaimer The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI. The material contained herein is provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. ALSO, THERE IS NO WARRANTY OR CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL. All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior written permission. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. 2 Copyright © 2012 MIPI Alliance. All rights reserved. Arteris: The NoC Interconnect IP Leader • Arteris NoC Milestones • Technical Founders from Tsquared in 2003 • Founded Network-on-Chip Interconnect in 2003 (250 man years of development) • NoC Solution = first released implementation of a Arteris NoC in 2005 • First Customer in early 2006. • FlexNoC® = second generation of Arteris NoC in 2009. • Investors: Qualcomm, ARM, DoCoMo, Synopsys, Ventech, TVM & Crescendo • Awards: EE Times ACE Finalist 2012, Red Herring “Global 100” 2010, MIT Technology Review “10 Private Companies to Watch” 2010, EE Times “60 Emerging Start-ups” 2009, World Economic Forum “Technology Pioneer 2008”, Red Herring “Europe 100” 2007 3 Copyright © 2012 MIPI Alliance. All rights reserved. 4 Copyright © 2012 MIPI Alliance. All rights reserved. What is MIPI LLI? LLI = Low Latency Interface • Enables companion chip use models • Fast enough for cache refills & DRAM sharing • No software drivers or stack • Minimal Pins • Uses low power MIPI M-PHY 5 Copyright © 2012 MIPI Alliance. All rights reserved. MIPI LLI enables Shared Memory and Companion Chip use cases Memory Memory Application Processor Baseband Modem M-PHY M-PHY LLI Controller LLI Din Din C C M-TX M-TX C C LLI M-RX M-RX LLI Controller LLI Dout Dout RMMI RMMI Removing an LPDDR2 saves $1-2 6 Copyright © 2012 MIPI Alliance. All rights reserved. MIPI LLI is less expensive than PoP Low Latency Interface Modem BB + DRAM PoP Removing modem baseband’s Using a modem baseband + RAM dedicated memory: in a PoP: • Saves $1-2 in BoM cost • Maintains $1-2 RAM BoM cost • Eliminates DRAM area from • Adds $0.50 to $1+ for PoP PCB floorplan packaging cost • Maintains vertical height • Increases chip vertical height clearance 7 Copyright © 2012 MIPI Alliance. All rights reserved. Arteris participation in MIPI LLI WG • Joined MIPI at creation of LLI Investigation Group • Attended LLI IG and WG conference calls and F2F meetings since creation • Mostly by Philippe Martin • Deeply involved in Transaction Layer (L5) definition • Protocol interoperability experience • Spec writing owned by TI, Arteris review • Main driver of Data Link Layer (L2) • Interchip-Link experience • Spec writing owned by Arteris • Significant contribution to PHY Adaptation layer (L1.5) • ARQ retry scheme • Major contributor to the upcoming LLI specification versions 8 Copyright © 2012 MIPI Alliance. All rights reserved. How Did We Get Here? • MIPI Low Latency Interface (LLI) Investigation group formed in December 2009 • LLI confirmed as Working Group in 18 March 2010 • MIPI LLI 1.0 spec approved 4 April 2012 • LLI WG Member Companies: • Analog Devices, ARM, Arteris, Broadcom, Cadence, Infineon, MCCI, Micron, Motorola, Nokia, Qualcomm, RIM, Samsung, SMSC, STMicroelectronics, ST- Ericsson, Texas Instruments 9 Copyright © 2012 MIPI Alliance. All rights reserved. LLI is a Layered Model LLI Controller LLI M - PHY 10 Copyright © 2012 MIPI Alliance. All rights reserved. LLI is Implemented in 2 IP components Chip #1 Chip #2 LLI Controller 1or more Tx/Rx Lanes LL NIU M-PHY BE Din NIU C DataLink M-TX LL NIU PA C NoC Controller µ BE M-RX NIU Dout SVC NIU Sideband RMMI 11 Copyright © 2012 MIPI Alliance. All rights reserved. Interconnect Adaptation Layer • IAL is implementation from Arteris • Required, but not defined in MIPI LLI spec because each SoC interconnect is different • Connects to SoC interconnect • Typically AXI, OCP for Low Latency (LL) and Best Effort (BE) Traffic Classes • APB or OCP for config • Supports any data width LL • Typically 32 bits to 128 bits NIU BE NIU • Mapping between interconnect Traffic LL Classes (BE, LL, SVC) NIU NoC µ BE • Power management, Connection/ NIU Disconnection, QoS, Clock SVC Management, Rate Matching, etc… NIU *FlexLLI Implementation 12 Copyright © 2012 MIPI Alliance. All rights reserved. Transaction & Data Link Layers • Arteris FlexLLI embeds Transaction and Data Link Layers in DataLink Controller • Usually same clock as interconnect • Optional Master/Slave LL and BE TC ports • Optional 40-bit LLI addressing DataLink • Handles LLI clock conversions Controller • Performance parameters Sideband *FlexLLI Implementation 13 Copyright © 2012 MIPI Alliance. All rights reserved. System Address translation • Typically configured by “system master” • Number of regions configurable at design time, per port • Offset configurable at runtime • Same mechanism for ingoing/outgoing transactions Remote chip Local Remote chip Local Interconnect mapping mapping mapping mapping DRAM space Segment 0 Base 1 Ex : 64MB to DRAM Address _ in + Offset 0 Segment 1 Base 2 Ex : 64MB to DRAM Address _ in Address _in Segment 2 + Offset 1 + Offset 0 Base 3 Ex : 32 MB to PER1 Segment 3 Ex : 64 MB to PER2 PER space Segment0 (LLI : 64 MB ) Address _ in + Offset 2 Address _ in + Offset 3 14 Copyright © 2012 MIPI Alliance. All rights reserved. Physical Adapter Layer • Interface to MIPI M-PHY • Configurable number of Rx and Tx lanes • Configurable RMMI data • Optional PHY test mode Din C PA C Dout RMMI *FlexLLI Implementation 15 Copyright © 2012 MIPI Alliance. All rights reserved. MIPI M-PHY • Industry standard • Optimized for mobile applications • High performance and scalability • Low power operation and modes • LLI M-PHY features • Type 1 • HS-Mode Gears G1, G2 or G3 • Up to 5.8 Gbps per lane 1or more Tx/Rx Lanes M-PHY Din C M-TX PA C M-RX Dout RMMI *FlexLLI Implementation 16 Copyright © 2012 MIPI Alliance. All rights reserved. Why MIPI LLI? • Link a chip and a companion chip together • Remove a memory chip from a mobile phone • No software complexity • Fewer pins than other standards • Scalable – Future-proof designs for high- throughput requirements • Low Power – Leverage M-PHY (< pwr than PCIe) Increase Flexibility, Reduce BoM cost 17 Copyright © 2012 MIPI Alliance. All rights reserved. Why Arteris FlexLLI? • First and only Silicon-proven LLI controller • Lowest risk, automated environment for fast configuration and verification setup • Industry-leading M-PHY / LLI joint solution with Synopsys 18 Copyright © 2012 MIPI Alliance. All rights reserved. MIPI LLI is implemented in TI OMAP5 Platform and other SoCs 19 Copyright © 2012 MIPI Alliance. All rights reserved. FlexLLI automated delivery environment Clock management AXI DL+PA controller APB AXI µNoC 20 Copyright © 2012 MIPI Alliance. All rights reserved. FlexLLI delivery environment • Provides same capabilities as FlexNoC environment • Parameterization of µNoC and LLI controller • RTL, synthesis scripts and SystemC exports • FlexVerifier VMM automated test bench export • Allows simulations of µNoC + LLI controller • Reverse LLI BFM automatically instantiated • Standard diagnostics provided • Open environment for user-defined diagnostics • Will incorporate M-PHY models • Will be tuned to Synopsys M-PHY specifics 21 Copyright © 2012 MIPI Alliance. All rights reserved. Flexibility: FlexLLI has Many Configuration Options • Configuration registers • Sideband and IRQ management, transaction user bit remapping, address translation, Req/Rsp Arbitration priority, credit frame arbitration • Clock gating and power management • Double-level clock gating (Units and reg levels) • Integrates into SoC power management • QoS, debug observability, buffering, clock management, traffic class mapping, custom protocols, etc. 22 Copyright © 2012 MIPI Alliance. All rights reserved. Why Arteris FlexLLI? • First: Silicon-proven with lowest risk • Easiest: Automated environment for fast
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