US Department of Justice Antitrust Division Notice

Total Page：16

File Type：pdf, Size：1020Kb

US Department of Justice Antitrust Division Notice

This document is scheduled to be published in the Federal Register on 11/06/2012 and available online at http://federalregister.gov/a/2012-27107, and on FDsys.gov U.S. Department of Justice Antitrust Division Notice Pursuant to the National Cooperative Research and Production Act of 1993 -- Heterogeneous System Architecture Foundation Notice is hereby given that, on October 9, 2012, pursuant to Section 6(a) of the National Cooperative Research and Production Act of 1993, 15 U.S.C. 301 et seq. (“the Act”), Heterogeneous System Architecture Foundation (“HSA Foundation”) has filed written notifications simultaneously with the Attorney General and the Federal Trade Commission disclosing changes in its membership. The notifications were filed for the purpose of extending the Act’s provisions limiting the recovery of antitrust plaintiffs to actual damages under specified circumstances. Specifically, Samsung Electronics Co., Ltd., Gyeonggi-do, REPUBLIC OF KOREA; Symbio, San Jose, CA; Arteris, Inc., Sunnyvale, CA; Vivante Corporation, Sunnyvale, CA; Apical Ltd., London, UNITED KINGDOM; MulticoreWare, Cupertino, CA; Sonics, Inc., Milpitas, CA; Qualcomm Incorporated, San Diego, CA; and LG Electronics, Inc., Seocho-gu, Seoul, REPUBLIC OF KOREA, have been added as parties to this venture. No other changes have been made in either the membership or planned activity of the group research project. Membership in this group research project remains open, and HSA Foundation intends to file additional written notifications disclosing all changes in membership. On August 31, 2012, HSA Foundation filed its original notification pursuant to Section 6(a) of the Act. The Department of Justice published a notice in the Federal Register pursuant to Section 6(b) of the Act on October 11, 2012 (77 FR 61786). Patricia A. Brink Director of Civil Enforcement Antitrust Division [FR Doc. 2012-27107 Filed 11/05/2012 at 8:45 am; Publication Date: 11/06/2012] 2 .

Copy Link

Recommended publications

Methods and Tools for Rapid and Efficient Parallel Implementation Of
Methods and tools for rapid and efficient parallel implementation of computer vision algorithms on embedded multiprocessors Vitor Schwambach To cite this version: Vitor Schwambach. Methods and tools for rapid and efficient parallel implementation of computer vision algorithms on embedded multiprocessors. Computer Vision and Pattern Recognition [cs.CV]. Université Grenoble Alpes, 2016. English. NNT : 2016GREAM022. tel-01523273 HAL Id: tel-01523273 https://tel.archives-ouvertes.fr/tel-01523273 Submitted on 16 May 2017 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. THÈSE Pour obtenir le grade de DOCTEUR DE L’UNIVERSITÉ DE GRENOBLE ALPES Spécialité : Informatique Arrêté ministériel du 7 août 2006 Présentée par Vítor Schwambach Thèse dirigée par Stéphane Mancini et codirigée par Sébastien Cleyet-Merle et Alain Issard préparée au sein du Laboratoire TIMA et STMicroelectronics et de l’École Doctorale Mathématiques, Sciences et Technologies de l’Information, Informatique (EDMSTII) Methods and Tools for Rapid and Efficient Parallel Implementation of Computer
[Show full text]
Simplifying Many-Core-Based Heterogeneous Soc Programming
IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 4, AUGUST 2015 957 Simplifying Many-Core-Based Heterogeneous SoC Programming With Ofﬂoad Directives Andrea Marongiu, Member, IEEE, Alessandro Capotondi, Student Member, IEEE, Giuseppe Tagliavini, and Luca Benini, Fellow, IEEE Abstract—Multiprocessor systems-on-chip (MPSoC) are evolv- performance/watt. Unfortunately, these advantages are traded ing into heterogeneous architectures based on one host processor off for an increased programming complexity: extensive and plus many-core accelerators. While heterogeneous SoCs promise time-consuming rewrite of applications is required, using spe- higher performance/watt, they are programmed at the cost of major code rewrites with low-level programming abstractions (e.g, cialized programming paradigms. For example, in the general- OpenCL). We present a programming model based on OpenMP, purpose and high-performance computing (HPC) domains, with additional directives to program the accelerator from a sin- Graphics Processing Unit (GPU)-based systems are pro- gle host program. As a test case, we evaluate an implementation grammed with OpenCL.1 OpenCL aims at providing a stan- of this programming model for the STMicroelectronics STHORM dardized way of programming such accelerators; however, it development board. We obtain near-ideal throughput for most benchmarks, very close performance to hand-optimized OpenCL offers a very low-level programming style. Programmers must codes at a signiﬁcantly lower programming complexity, and up to write and compile separate programs for the host system and for 30× speedup versus host execution time. the accelerator. Data transfers to/from the many-core and syn- Index Terms—Heterogeneous systems-on-chip (SoC), many chronization must also be manually orchestrated.
[Show full text]
Demand-Based Scheduling Using Noc Probes
Demand-based Scheduling using NoC Probes Kurt Shuler Jonah Probell Monica Tang Arteris, Inc. Sunnyvale, CA, USA www.arteris.com ABSTRACT Contention for shared resources, such as memory in a system-on-chip, is inefficient. It limits performance and requires initiator IPs, such as CPUs, to stay powered up and run at clock speeds higher than they would otherwise. When a system runs multiple tasks simultaneously, contention will vary depending on each task’s demand for shared resources. Scheduling in a conventional system does not consider how much each task will demand shared resources. Proposed is a demand-based method of scheduling tasks that have diverse demand for shared resources in a multi- processor system-on-chip. Tasks with extremes of high and low demand are scheduled to run simultaneously. Where tasks in a system are cyclical, knowledge of period, duty cycle, phase, and magnitude are considered in the scheduling algorithm. Using demand-based scheduling, the time variation of aggregate demand is reduced, as might be its maximum. The average access latency and resulting idle clock cycles are reduced. This allows initiator IPs to run at lower clock frequencies, finish their tasks sooner, and spend more time in powered down modes. Use of probes within a network-on-chip to gather demand statistics, application-specific algorithm considerations, operating system thread scheduler integration, and heterogeneous system middleware integration are discussed. Contents 1. Introduction ......................................................................................................................................................................
[Show full text]
A Multifrequency MAC Specially Designed for Wireless Sensor
HSAemu – A Full System Emulator for HSA Platforms JIUN-HUNG DING, ZHOUDONG GUO, CHUNG-MING KAO, National Tsing Hua University WEI-CHUNG HSU, National Chiao Tung University YEH-CHING CHUNG, National Tsing Hua University Heterogeneous system architecture is an open industry standard designed to support a large variety of data-parallel and task-parallel programming models. Many application processor vendors, including AMD, ARM, Imagination, MediaTek, Texas Instrument, Samsung and Qualcomm are members of the HSA Foundation. This paper presents the design of HSAemu, a full system emulator for the HSA platform. The design of HSAemu is based on PQEMU, a parallel version of QEMU, with supports for HSA defined features such as a) shared virtual memory between CPU and GPU, b) memory based signaling and synchronization, c) multiple user level command queues, d) preemptive GPU context switching, and e) concurrent execution of CPU threads and GPU threads, etc. In addition to the basic requirements of the HSA-compliant features, HSAemu also includes an LLVM based binary translation engine to efficiently support translating multiple different ISAs (e.g. ARM and HSAIL -- HSA Intermediate Language). Categories and Subject Descriptors: C.1.3 [Processor Architectures]: Other Architecture Styles— Heterogeneous (hybrid) Systems; C.1.6 [Simulation and Modeling]: Type of Simulation—Parallel General Terms: Design, Simulation Additional Key Words and Phrases: HSA, GPU simulation, parallel simulation 1. INTRODUCTION Over the last decade, there has been a growing interest in the use of graphics processing units (GPUs), originally designed to perform specialized graphics computations in parallel, to perform general purpose parallel computation tasks traditionally handled by the central processing units (CPUs).
[Show full text]
High-Level Programming Model for Heterogeneous Embedded Systems Using
HIGH-LEVEL PROGRAMMING MODEL FOR HETEROGENEOUS EMBEDDED SYSTEMS USING MULTICORE INDUSTRY STANDARD APIS A Dissertation Presented to the Faculty of the Department of Computer Science University of Houston In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy By Peng Sun August 2016 HIGH-LEVEL PROGRAMMING MODEL FOR HETEROGENEOUS EMBEDDED SYSTEMS USING MULTICORE INDUSTRY STANDARD APIS Peng Sun APPROVED: Dr. Chapman, Barbara Dept. of Computer Science, University of Houston Dr. Gabriel, Edgar Dept. of Computer Science, University of Houston Dr. Shah, Shishir Dept. of Computer Science, University of Houston Dr. Subhlok, Jaspal Dept. of Computer Science, University of Houston Dr. Chandrasekaran, Sunita Dept. of CIS, University of Delaware Dean, College of Natural Sciences and Mathematics ii Acknowledgements First and foremost, I would like to thank my advisor, Dr. Barbara Chapman, for her invaluable advice and guidance in my Ph.D. study. I appreciate all her dedi- cated guidance, and great opportunities to participate in those worthwhile academic projects, and the funding to complete my Ph.D. study. Her passion and excellence on academic and contributions to communities encourage me to finish my Ph.D. degree. Specifically, I am very grateful to Dr. Sunita Chandrasekaran for the mentoring and guidance for my research and publications. That help is paramount to my Ph.D. Journey. I truly could not achieve the degree without her mentoring and advisory. Special thanks to all my committee members: Dr. Edgar Gabriel, Dr. Shishir Shah, Dr. Jaspal Subhlok, for their time, insightful comments and help. I would also like to thank my fellow labmates of the HPCTools group: Dr.
[Show full text]
Notice Pursuant to the National Cooperative Research And
64248 Federal Register / Vol. 78, No. 208 / Monday, October 28, 2013 / Notices Trimonite. Federal Register pursuant to Section Hong Kong, HONG KONG–CHINA, have Trinitroanisole. 6(b) of the Act on November 10, 2004 been added as parties to this venture. Trinitrobenzene. (69 FR 65226). Also, Action Electronics Co., Ltd., Trinitrobenzoic acid. The last notification was filed with Chung Li, TAIWAN; and DAT H.K. Trinitrocresol. the Department on May 10, 2013. A Limited, Quarry Bay, Hong Kong, HONG Trinitro-meta-cresol. notice was published in the Federal KONG–CHINA, have withdrawn as Trinitronaphthalene. Register pursuant to Section 6(b) of the parties to this venture. Trinitrophenetol. Act on June 13, 2013 (78 FR 35646). No other changes have been made in Trinitrophloroglucinol. either the membership or planned Trinitroresorcinol. Patricia A. Brink, activity of the group research project. Tritonal. Director of Civil Enforcement, Antitrust Membership in this group research Division. project remains open, and DVD CCA U [FR Doc. 2013–25281 Filed 10–25–13; 8:45 am] intends to file additional written Urea nitrate. BILLING CODE P notifications disclosing all changes in W membership. On April 11, 2001, DVD CCA filed its Water-bearing explosives having salts of DEPARTMENT OF JUSTICE original notification pursuant to Section oxidizing acids and nitrogen bases, 6(a) of the Act. The Department of sulfates, or sulfamates (cap sensitive). Antitrust Division Justice published a notice in the Federal Water-in-oil emulsion explosive Register pursuant to Section 6(b) of the compositions. Notice Pursuant to The National Act on August 3, 2001 (66 FR 40727).
[Show full text]
MIPI Low Latency Interface (LLI) for Mobile Phone Bom Cost Savings
MIPI Low Latency Interface (LLI) for Mobile Phone BoM Cost Savings Scott Yang Greater China Country Manger Arteris Inc 1 Copyright © 2012 MIPI Alliance. All rights reserved. Legal Disclaimer The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI. The material contained herein is provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. ALSO, THERE IS NO WARRANTY OR CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL. All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior written permission. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.
[Show full text]
Flexnoc® Interconnect IP
FlexNoC® Interconnect IP Arteris IP FlexNoC network-on-chip (NoC) interconnect IP improves performance, development time, power consumption and die size of system on chip (SoC) devices for consumer electronics, mobile, automotive and other applications. Benefits Fast Facts SILICON PROVEN • Scales from 10s to 100s of IP blocks FlexNoC is the first commercial NoC interconnect and is shipping in over 1.5 Billion chips. • Protocol interoperability: It is the backbone SoC interconnect used by Samsung, Mobileye, Altera (Intel), Hisilicon AMBA AXI, AHB, APB; OCP; PIF; (Huawei) and other industry leaders for their most important projects. custom / proprietary • Lowest die area & congestion STATE-OF-THE-ART TECHNOLOGY FlexNoC is continually updated with the latest technologies, including support for new • Lowest latency & power protocols like AMBA® AHB5 and new capabilities like the FlexNoC Resilience Package for • Shortest design time automotive ISO 26262 compliance and the PIANO Timing Assistance Package. • Visual floorplan, area & timing SCALABILITY & PRODUCTIVITY closure estimation Create SoCs using IP with any protocol (AMBA, OCP, PIF or proprietary) and scale up • Integrated systemc simulation & UVM to 100s of IP blocks. Implement any topology (tree, ring, or mesh) while reducing verification support development time through the use of automated simulation and verification technology. • Optimal QOS—bandwidth & latency • Meet ISO 26262 ASIL D requirements CPU Subsystem Design-Speciﬁc Subsystem DSP Subsystem (A/V) Application IP Subsystem 2D A72 A72 A53 A53 IP IP IP IP IP IP CPU Subsystems GR. A72 A72 A53 A53 3D Graphics FlexWay Interconnect FlexWay Interconnect MPEG L2 Cache L2 Cache IP IP IP IP IP IP Ect. Ncore Cache Proxy $ FlexNoC Non-Coherent Interconnect Interchip Links CMC Coherent Interconnect CodaCache LLC WiFi CRI HDMI Crypto Firewall MIPI GSM (PCF+) Display LTE Memory Scheduler Subsystem Interconnect RSA-PSS PMU Cert.
[Show full text]
Download.Nvidia.Com/Pdf/Tegra/Tegra-X1-Whitepaper
Models and Techniques for Designing Mobile System-on-Chip Devices by Ayub Ahmed Gubran A DISSERTATION SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Doctor of Philosophy in THE FACULTY OF GRADUATE AND POSTDOCTORAL STUDIES (Electrical and Computer Engineering) The University of British Columbia (Vancouver) August 2020 © Ayub Ahmed Gubran, 2020 The following individuals certify that they have read, and recommend to the Fac- ulty of Graduate and Postdoctoral Studies for acceptance, the dissertation entitled: Models and Techniques for Designing Mobile System-on-Chip Devices submitted by Ayub Ahmed Gubran in partial fulﬁllment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering Examining Committee: Tor M. Aamodt, Electrical and Computer Engineering Supervisor Steve Wilton, Electrical and Computer Engineering Supervisory Committee Member Alan Hu, Computer Science University Examiner Andre Ivanov, Electrical and Computer Engineering University Examiner John Owens, The University of California-Davis, Electrical and Computer Engineering External Examiner Additional Supervisory Committee Members: Sidney Fels, Electrical and Computer Engineering Supervisory Committee Member ii Abstract Mobile SoCs have become ubiquitous computing platforms, and, in recent years, they have become increasingly heterogeneous and complex. A typical SoC to- day includes CPUs, GPUs, image processors, video encoders/decoders, and AI engines. This dissertation addresses some of the challenges associated with SoCs in three pieces of work. The ﬁrst piece of work develops a cycle-accurate model, Emerald, which pro- vides a platform for studying system-level SoC interactions while including the impact of graphics. Our cycle-accurate infrastructure builds upon well-established tools, GPGPU-Sim and gem5, with support for graphics and GPGPU workloads, and full system simulation with Android.
[Show full text]
Everything You Always Wanted to Know About HSA*
Everything You Always Wanted to Know About HSA* Explained by Nathan Brookwood Research Fellow, Insight 64 October, 2013 * But Were Afraid To Ask Abstract For several years, AMD and its technology partners have tossed around terms like HSA, FSA, APU, heterogeneous computing, GP/GPU computing and the like, leaving many innocent observers confused and bewildered. In this white paper, sponsored by AMD, Insight 64 lifts the veil on this important technology, and explains why, even if HSA doesn’t entirely change your life, it will change the way you use your desktop, laptop, tablet, smartphone and the cloud. Table of Contents 1. What is Heterogeneous Computing? .................................................................................................... 3 2. Why does Heterogeneous Computing matter? .................................................................................... 3 3. What is Heterogeneous Systems Architecture (HSA)? ......................................................................... 3 4. How can end-users take advantage of HSA? ........................................................................................ 4 5. How does HSA affect system power consumption? ............................................................................. 4 6. Will HSA make the smartphone, tablet or laptop I just bought run better? ........................................ 5 7. What workloads benefit the most from HSA? ...................................................................................... 5 8. How does HSA
[Show full text]
Arteris IP, On-Chip Interconnect Market Leader, Takes Full Control
“With insight, monitoring and troubleshooting my networks in my Austin and Paris locations has never been easier.” Stéphane Méhat, CFO, Arteris IP Arteris IP, On-Chip Interconnect Market Company name: Arteris IP Leader, Takes Full Control of its Network Company Size: 51-200 through NETGEAR Insight Industry: BACKGROUND Semiconductors Founded in February 2003, Arteris IP provides Network-on-Chip (NoC) interconnect Company website: semiconductor intellectual property (IP) to System on Chip (SoC) makers to help reduce chip www.arteris.com development time, increase margins, and accelerate performance. Being the industry leader, Arteris IP invented the first commercial NoC SoC interconnect IP solution, FlexNoC, and the first Geographic region: Silicon Valley, California highly-configurable cache coherent interconnect IP, Ncore, which are used by notable design teams such as Samsung, Toshiba, Huawei / HiSilicon, Mobileye (Intel), Altera (Intel), and Texas Instruments. With a focus on providing innovative SoC interconnect IP technologies for an array of applications from automobiles to mobile phones, strong network technology enables Arteris IP to serve its customers. Stéphane Méhat, Chief Financial Officer, manages Arteris IP’s financial strategy, accounting, taxes, HR, and administration, and also oversees the company’s IT management. His nimble team includes IT manager, Bhavin Vaidya, an accountants, and office managers to support both the California, France, and Texas locations. PROBLEM/OBJECTIVE: Similar to other thriving small businesses in the Silicon Valley, Arteris IP is based primarily in Campbell, California, but also operates on a global scale. Stéphane was using a competitor’s devices in the Arteris IP France office and was beginning to set up a new office in Austin, Texas.
[Show full text]
C 2016 MICHAEL GEOFFREY GRUESEN ALL RIGHTS RESERVED
c 2016 MICHAEL GEOFFREY GRUESEN ALL RIGHTS RESERVED TOWARDS AN IDEAL EXECUTION ENVIRONMENT FOR PROGRAMMABLE NETWORK SWITCHES A Thesis Presented to The Graduate Faculty of The University of Akron In Partial Fulfillment of the Requirements for the Degree Master of Science Michael Geoffrey Gruesen August, 2016 TOWARDS AN IDEAL EXECUTION ENVIRONMENT FOR PROGRAMMABLE NETWORK SWITCHES Michael Geoffrey Gruesen Thesis Approved: Accepted: Advisor Dean of the College Dr. Andrew Sutton Dr. John Green Faculty Reader Dean of the Graduate School Dr. Timothy O’Neil Dr. Chand Midha Faculty Reader Date Dr. Zhong-Hui Duan Department Chair Dr. David Steer ii ABSTRACT Software Defined Networking (SDN) aims to create more powerful, intelligent net- works that are managed using programmed switching devices. Applications for these SDN switches should be target independent, while being efficiently translated to the platform’s native machine code. However network switch vendors do not conform to any standard, and contain different capabilities and features that vary between manufacturers. The Freeflow Virtual Machine (FFVM) is a modular, fully programmable vir- tual switch that can host compiled network applications. Applications are compiled to native object libraries and dynamically loaded at run time. The FFVM provides the necessary data and computing resources required by applications to process packets. This work details the many implementation approaches investigated and evaluated in order to define a suitable execution environment for hosted network applications. iii ACKNOWLEDGEMENTS First, I would like to thank Dr. Andrew Sutton for being my advisor and giving me the opportunity to work as your research assistant during my graduate studies. I am truly grateful for all that I have learned while working with you.
[Show full text]