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Methods and Tools for Rapid and Efficient Parallel Implementation Of Methods and tools for rapid and efficient parallel implementation of computer vision algorithms on embedded multiprocessors Vitor Schwambach To cite this version: Vitor Schwambach. Methods and tools for rapid and efficient parallel implementation of computer vision algorithms on embedded multiprocessors. Computer Vision and Pattern Recognition [cs.CV]. Université Grenoble Alpes, 2016. English. NNT : 2016GREAM022. tel-01523273 HAL Id: tel-01523273 https://tel.archives-ouvertes.fr/tel-01523273 Submitted on 16 May 2017 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. THÈSE Pour obtenir le grade de DOCTEUR DE L’UNIVERSITÉ DE GRENOBLE ALPES Spécialité : Informatique Arrêté ministériel du 7 août 2006 Présentée par Vítor Schwambach Thèse dirigée par Stéphane Mancini et codirigée par Sébastien Cleyet-Merle et Alain Issard préparée au sein du Laboratoire TIMA et STMicroelectronics et de l’École Doctorale Mathématiques, Sciences et Technologies de l’Information, Informatique (EDMSTII) Methods and Tools for Rapid and Efficient Parallel Implementation of Computer Vision Algorithms on Embedded Multiprocessors Thèse soutenue publiquement le 30/03/2016 devant le jury composé de: Dominique Borrione Université de Grenoble, France, Président François Berry Université Blaise Pascal, Clermont-Ferrand, France, Rapporteur Steven Derrien Université de Rennes 1, France, Rapporteur Dietmar Fey Friedrich-Alexander Universität Erlangen-Nürnberg, Germany, Examinateur Stéphane Mancini Université de Grenoble, France, Directeur de thèse Sébastien Cleyet-Merle STMicroelectronics, France, Invité Abstract Embedded computer vision applications demand high system computational power and constitute one of the key drivers for application-specific multi- and many-core systems. A number of early system design choices can impact the system’s parallel performance – among which the parallel granularity, the number of processors and the balance between computation and communication. Their impact in the final system performance is difficult to assess in early design stages and there is a lack for tools that support designers in this task. The contributions of this thesis consist in two methods and associated tools that facilitate the selection of embed- ded multiprocessor’s architectural parameters and computer vision application parallelization strategies. The first consists of a Design Space Exploration (DSE) methodology that relies on Parana, a fast and accurate parallel performance estimation tool. Parana enables the evaluation of what-if parallelization scenarios and can determine their maximum achievable performance limits. The second contribution consists of a method for optimal 2D image tile sizing using constraint programming within the Tilana tool. The proposed method integrates non-linear DMA data transfer times and parallel scheduling overheads for increased accuracy. Vítor Schwambach TIMA Laboratory / STMicroelectronics i Résumé Les applications de vision par ordinateur embarquées demandent une forte capacité de calcul et poussent le développement des systèmes multi- et many-cores spécifiques à l’application. Les choix au départ de la conception du système peuvent impacter sa performance parallèle finale – parmi lesquelles la granularité de la parallélisation, le nombre de processeurs et l’équilibre entre calculs et l’acheminement des données. L’impact de ces choix est difficile à estimer dans les phases initiales de conception et il y a peu d’outils et méthodes pour aider les concepteurs dans cette tâche. Les contributions de cette thèse consistent en deux méthodes et les outils associés qui visent à faciliter la sélection des paramètres architecturaux d’un multiprocesseur embarqué et les stratégies de parallélisation des applications de vision embarquée. La première est une méthode d’exploration de l’espace de conception qui repose sur Parana, un outil fournissant une estimation rapide et précise de la performance parallèle. Parana permet l’évaluation de différents scénarios de parallélisation et peut déterminer la limite maximale de performance atteignable. La seconde contribution est une méthode pour l’optimisation du dimensionnement des tuiles d’images 2D utilisant la programmation par contraintes dans l’outil Tilana. La méthode proposée intègre pour plus de précision des facteurs non-linéaires comme les temps des transferts DMA et les surcoûts de l’ordonnancement parallèle. Vítor Schwambach TIMA Laboratory / STMicroelectronics iii Résumé Étendu Abstract Le développement d’une plateforme multiprocesseur pour une application spécifique, néces- site de répondre à deux questions essentielles : (i) comment tailler la plateforme multiprocesseur pour atteindre les pré-requis de l’application avec la surface minimum et la plus faible con- sommation ; et (ii) comment paralléliser l’application cible de façon à maximiser l’utilisation de la plateforme. Dans ce travail, nous présentons une méthodologie originale d’estimation de la performance parallèle et d’optimisation des transferts de données, à partir des traces d’une exécution de l’application séquentielle et d’un modèle d’optimisation par contraintes des transferts de données. L’estimation à la fois de la performance parallèle et du temps des transferts de données doit être rapide car elle est au coeur du processus d’exploration de l’espace de conception de la plateforme multiprocesseur. Cette méthodologie est implémentée dans les outils Parana, un simulateur abstrait très rapide, basé sur des traces, et Tilana, un outil pour optimisation des transferts de données selon une modélisation analytique dans le cadre d’une optimisation par contraintes. Les outils ciblent des applications OpenMP sur la plateforme STxP70 Application-Specific Multiprocessor (ASMP) de STMicroelectronics. Les résultats pour un benchmark du NAS Parallel Benchmark et une application de vision embarquée démontrent une marge d’erreur de l’estimation de performance inférieur à 10% en comparaison aux simula- teur ISS cycle-approximate de référence et à un prototype FGPA, avec un effort de modélisation réduit. Tilana permet de trouver des paramètres de transferts de données qui optimisent le temps de transferts de tuiles d’images pour une application donnée. Contents R.1 Introduction . vi R.2 Flot de conception proposé . viii R.2.1 Caractérisation de la plateforme . .x R.2.2 Instrumentation de l’application . .x R.2.3 Spécification des scénarios de parallélisation . .x R.3 Parana . .x R.3.1 Construction du graphe de tâches . xi R.3.2 Ordonnancement des tâches . xi R.3.3 Analyse de la parallélisation . xi R.4 Tilana . xii R.5 Configuration des expériences . xiii R.5.1 Architecture de la plateforme . xiii R.5.2 Outils d’exécution . xiv R.5.3 Applications . xiv R.6 Résultats . xv R.6.1 Estimations du facteur d’accélération . xv R.6.2 Temps d’exécution . xvi R.7 Travaux connexes . xvi R.7.1 Modélisation de la performance parallèle . xvi R.7.2 Techniques de Simulations Multiprocesseurs . xvii Vítor Schwambach TIMA Laboratory / STMicroelectronics v Résumé Étendu R.7.3 Principaux avantages . xvii R.7.4 Limitations connues . xvii R.8 Conclusion . xviii R.1 Introduction Grâce à leur flexibilité et leur puissance de calcul potentielle, les architectures multicoeurs massivement parallèles devraient être les supports de choix pour de nombreuses applications embarquées. Cependant, concevoir de tels systèmes efficaces nécessite de lever un certain nombres d’obstacles [29]. La difficulté de leur programmation efficace, qui maximise la puissance de calcul effective pour bien utiliser les ressources matérielles, réside non seulement dans la gestion des communications et synchronisations [83], mais aussi dans la prise en compte des ressources matérielles de mémorisation et de calcul de chaque noeud [183]. Dans le domaine de la vision embarquée sur plateforme multiprocesseur, les grandes quantités de données en jeu, la diversité des traitements et les dépendances des calculs aux données poussent ces systèmes à leurs limites. Dans un système hétérogène multicoeurs, il est envisagé d’intégrer des clusters multicoeurs adaptés aux besoins spécifiques des utilisateurs. Chaqu’un de ces accélérateur multicoeurs est taillé sur mesure pour la gamme d’applications ciblées. Définir les paramètres d’architecture tels que le nombre de coeurs, la topologie des communications et les ressources de mémorisation, nécessite de prédire les performances de l’accélérateur multicoeur au plus tôt lors du processus de conception, et ceci pour les applications typiques envisagées. La difficulté à estimer les performances d’une architecture multicoeurs exécutant un pro- gramme complexe, dont le déroulement dépend des données, provient de phénomènes d’attentes difficiles à prédire car ils sont d’une part liés aux communications et synchronisations des différentes tâches et d’autre part sont aussi dus au comportement de la plateforme matérielle. Ces surcoûts doivent être pris en compte lors de l’estimation de performance de l’application car, sinon, ils peuvent conduire à une sous-évaluation des performances réelles d’un circuit.
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