Design, Automation and Test in Europe

ADVANCE PROGRAMME

Design, Automation and Te s t in Europe

25 – 29 MARCH 2019, FLORENCE, ITALY (ESD) Alliance www.date-conference.com Russian Academy Academy Russian of Sciences Electronic System System Electronic Design Chips European Electronic design Initiative & Systems Design Automation ACM Special Interest Group Special Interest ACM on Design Automation IEEE Council on Electronic European Design and European Design Association Automation International Federation for Information Federation International (IFIP) Processing IEEE Solid-State Circuits Society (SSCS) IEEE Solid-State IEEE Computer Society test technology technology test Society IEEE Computer Council (tttC) technical C02 CORPORATE SPONSORS CORPORATE • EVENT SPONSORS • • TECHNICAL CO-SPONSORS DATE 2019 SPONSORSDATE

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com Venue Plan Detailed Index Committees & Topic Chairs EXHIBITION GUIDE AND CO-LOCATED WORKSHOPS FRINGE TECHNICAL MEETINGS UNIVERSITY BOOTH Free for exhibition visitors EXHIBITION THEATRE PROGRAMMEOVERVIEW CEDA byIEEE supported International F1/10Autonomous Racing Demo Ten full-day workshops FRIDAY WORKSHOPS ANDEVENTS Full listingofDATEtechnical programme andspecialsessions TECHNICAL SESSIONS ACM SIGDA, CEDA andIEEE Welcome Reception &PhDForum hostedbyEDAA, Six afternoontutorials MONDAY TUTORIALS ANDEVENTS A briefoverviewthe event of DATE 2019–AT AGLANCE Schoeberl,Martin Technical University ofDenmark, DK Tulika Mitra, National University ofSingapore, SG Andreas Herkersdorf, Technical University ofMunich, DE SPECIAL &EUSESSIONS Patricia Derler, National Instruments, US Sander Stuijk, Eindhoven University of Technology, NL Marc Geilen, Eindhoven University of Technology, NL MODEL-BASED DESIGNOFINTELLIGENTSYSTEMS Christian Plessl, Paderborn University, DE Christoph Hagleitner, Research IBM Zurich, CH EMBEDDED MEETSHYPERSCALE ANDHPC Marco Casale-Rossi, Synopsys, IT Giovanni DeMicheli, EPFLausanne, CH EXECUTIVE SESSIONS Edward A.Lee, University ofCalifornia, Berkeley, US David Pellerin, Amazon, US e della Tecnologia Leonardo da Vinci, Milano, IT Claudio Giorgione, MuseoNazionaledellaScienza Jürgen Bortolazzi, Porsche, DE Astrid Elbe, Intel LabsEurope, DE KEYNOTE SPEAKERS General Information Welcome Media Partners GUIDE PROGRAMME C04 208 204 171 164 146 142 169 109 109 039 164 029 029 020 018 017 016 015 010 009 008 007 006 011 004 002 1

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com - warm their to extend would like sponsors and organisation The DATE in the edi- coverage DATE journalists who give to all press est gratitude who publications the media houses and Listed below are torial pages. partnership a media with DATE. to form agree generously 2 - and Sys FPGA Thousands of IC, web portal. is the #1 EDA EDACafe.Com to learn and research the latest news tem designers visit EDACafé.com than 75,000 unique more The sites attract design tools and services. job to bring you TechJobsCafé.com and leverages visitors each month opportunities - targeted and design. And daily e-news to engineering than 40,000 engineering professionals. more letters reach and www.TechJobsCafe.com details visit more www.EDACafe.com For EDACafé Chip Design Magazine Chip all of the - and implementa technical challenges Chip Design covers of and manufacture in the development tion options engineers face Chip Design is circuits. the only media integrated complex today's www.chip Visit market.Design IC to network dedicated advanced the in aboutdesignmag.com informed the latest developments to stay EDA from test and manufacture, design, architecture, chip modeling, Design Level The System issues. tools to digital and analog hardware you content focused editorial offer Engineering Portals Power and Low - valu for to visit be sure www.eecatalog.com want to miss. And, won’t Media's outstanding abouttechnol- all of Extension able information ogy resources. www.chipdesignmag.com AUTOCAD & Inventor Magazin & Inventor AUTOCAD than just more IT subjects - we Magazin covers & Inventor AutoCAD - important con that are life for report on all aspects of professional especially on innovations focus We structing and planners. engineers construction connectivity, technology, automation technology, drive in electrical engineering and materials. fluid technology, components, www.autocad-magazin.de MEDIA PARTNERS

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com www.mdpi.com/journal/sensors tion eachyear. organizes special issues devotedto specific sensing areas and applica- sensor design,technology, proof and application. ofconcept Sensors theoreticalmental and papersare published, of including allaspects sensors, including remote sensing and sensor networks. Both experi- tific thehugearearesearch in ofphysical, chemicalandbiochemical achievementsthe latest of technological developments of andscien- published monthly onlinebyMDPI.Sensorsdevotesto fast publication Sensors (ISSN1424-8220; CODEN: SENSC9)isanopenaccessjournal Sensors www.elinor.se news, commentstechnical articles. andin-depth ies provesthis area. wearethe majorelectronics paperin We publish way andDenmark).Acirculation of25,800personallyaddressed cop information forthe Nordic (Sweden, electronic industry Finland, Nor try. We source of important wantthe most Elektronikto be iNorden Elektronik iNorden,tool forthe Nordic electronic indus- animportant Elektronik iNorden www.eandtmagazine.com toindustry,advice &briefings education &governments. conferences &otherevents providing eachyear whilst professional Engineering & Technology noworganises morethan 120 in2006.It Engineers,of Electrical dating from 1889,the Institutionof became aroundthe positivethe mote roletechnology of World. The Institution to facilitateglobal knowledgenetwork the exchange ofideas&pro - Asia-Pacific, theInstitutionofEngineering& providesTechnology a With itsHQinLondon ®ional officesinEurope, America& North planners, facilities managers&end-users. solutions providers & installers, engineering distributors, consultants, design &development engineers, systemdesigners&integrators, their membershippackage. of Readersceives acopy include aspart the InstitutionofEngineering& Each memberof Technology re- (IET) countries &ahighpass-onreadership. & offers a global circulation of over 140,000 to more than100 copies Europe’s circulation largest engineeringmagazine, publishedmonthly technology, electronics, IT, is It manufacturing &powerengineering. coveringnology the areas ofcommunications, control, consumer Engineering & Technologytech- the latest ispackedon witharticles Published byTheIET &TechnologyEngineering Magazine – PARTNERS MEDIA 3 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com 4 Dear Colleague, DATE 2019. of DATE Programme present the Advance proudly We and design systems electronic test favourite world’s the combines au- design, electronic for exhibition with an international conference - imple and software hardware system-level from and test, tomation circuit design. right down to integrated mentation (38%) share a large Out of a received, of 834 paper submissions total the from of submissions are 28% authors in Europe, from is coming This dis- and 1% from the rest of the world. Asia, from 33% Americas, global reach character, international DATE’s tribution demonstrates and impact. tech- an exciting has prepared DATE year, the 22nd successive For Technical the help of 326 members of the With nical programme. four (mostly outcarried who reviews 3276 Committee Programme for selected (24%) were 202 papers finally, per submission), reviews in- 35%, and 91 additional ones (cumulatively presentation regular presentation. interactive for cluding all papers) at25 2019 March 29 to from place the will take conference DATE The Italy. in Florence, Fiera Firenze in-depth five technical tutorials on week, DATE On the first of the day as well as industrytwo hands-on willtutorials the main topics of DATE cover The topics by leading experts fields. in be given their respective for OpenCL Design Flows Test, and Manufacturing for Machine Learning and Safety Security, Hardware-based Computing, Approximate FPGAs, while on Quan- the hands-on tutorials are and Security in Automotive, IBM with Zynq. tum Computing Q and Python Xilinx for Productivity lectures plenary keynote Tuesday, on During the Opening Ceremony Labs Europe, of Intel Managing Director by Astrid Elbe, will be given and Highly Assistance Systems Driver Director Bortolazzi, and Jürgen Track the Executive On the same day, Driving at Porsche. Automated - compa from speakers executive a series of business panels with offers discussing hot topics. nies leading industry, the design and automation De- of the Leonardo Curator a talk by Claudio Giorgione, Furthermore, Milano, Technology partment at Museum of Science and the National in line with the Vinci da and work of Leonardo life insight into will give in 2019. Florence in celebrated is which death, his of anniversary 500th includes Thursday to Tuesday from programme The main conference areas from the four tracks in parallel 58 technical sessions organized Tools D – Design Methods & Design A – Application and Dependability Test T – Systems E – Embedded and Cyber-physical Emerging such as Topics, special sessions on Hot several and from IoT Security, Systems, of Secure Test Design and Technologies, Design - Living and Person Augmented Deep Learning, for Embedded Systems and les- as well as results and Industry 4.0, Robotics Healthcare, alized numerous are there Additionally, projects. European learned from sons five sessions. IP into organized which are Presentations Interactive bringing new on areas will focus in the programme Special Days Two Embedded Meets Hyper challenges to community: the system design WELCOME 2019 TO DATE scale and HPC and Model-Based Design of Intelligent Systems. Each Each scale and HPC Systems. and Model-Based Design of Intelligent tutorials and of panels, programme full a have will of the Special Days keynote. and a lunchtime technical presentations and specialised processors with multiple, computing Heterogeneous for embedded systems to is vital accelerators application-specific

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI Jürgen Teich www.date-conference.com Nürnberg, DE Friedrich-Alexander-Universität Erlangen- Jürgen Teich DATE 2019General Chair DATE andanentertaining tion visit Party on Wednesday evening. We wishyou anexciting andmemorable DATE 2019, asuccessfulexhibi- take place, CEDA. byIEEE supported Furthermore, an International F1/10 Autonomous Racing Demo will EDA inapplication domainssuchas(d) Autonomous Systems and IoT. Hardware Design, Synthesis, and Approximate Computing, as well as niques for Memories, Interconnections, andQuantum Computing, (c) like (a) OpenSource andMachineLearning inEDA, (b)Emerging Tech- On Friday,ten full-day workshops cover severaltopics from areas hot future employers. foster university programme and especially for to meet PhDstudents venue university for professorsto meet the perfect industries and is to entations. The exhibition provides auniquenetworkingopportunity nies, andcollaborative research initiatives pres includingEUproject - days (Tuesday – Thursday), including exhibition booths from compa- The conference iscomplemented byanexhibition, runningforthree to introducetheir workandjob portfolios. the opportunity Session andacareer sessioncalledInspiringFutures, givingcompanies cial sessions. Twothe highlights willbeanewlycreated of Publisher’s conference designprojects andselected their latest leaderson try spe- presentations byexhibiting companies, best-practice byindus- reports will beafullprogrammethe Exhibition in Theatre, whichwillcombine To inform attendees on commercial and design-relatedtopics, there the DATEthis domainandinvite in communityto helpovercome them. systems. The special daythe upcoming will also emphasise challenges application ofmodel-based designinsafety-critical andautonomous sign frameworks for IoTsystems, model-basedmachinelearning, and systems. ligent Topics addressed are, amongothers, model-basedde- to liftthe era model-baseddesigninto isneeded plore that ofintel all - The special day on Model-Based Design of Intelligent Systems will ex the future ofhyperscale DCsandHPC. to betterunderstand,ogies howheterogeneous computing isshaping this confluence technol- to showcase ofmethodsand is scale andHPC efficiency gains. thespecial themeof day EmbeddedMeetsHyper The andMoore’scomputing (HPC) lawnolongerprovides the necessary the evolution of hyperscale data centre (DC) and high-performance fast, efficient, and cost-effective processing arealso gatingfactors for performance,meet latency, targets. and efficiency The same goals of DATE TO 2019 WELCOME Franco Fummi Università di Verona, IT Franco Fummi DATE 2019Programme Chair 5 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com Astrid Elbe The Internet of Things (IoT) will be the largest revolution Things (IoT) will be the largestThe Internet revolution of - we understand the expo Intel, At economy. in the data making it and practical we’re and of data, power nential to puteconomical it the edge to work from to the cloud. optimized IoT deliver Intel® technologies purpose-built for artifito use - ways practical point, performanceat every and a built-in support, connectivity broad cial intelligence, time determinism and se- of functional safety, foundation and data curity dependable your to help protect and make our partner can from solutions ecosystem systems. Proven By har and risk of IoT deployments. cost, the reduce time, 26 March 2019, 0915 – 0950, Auditorium 0915 – 0950, 2019, 26 March DE Labs Europe, Intel Astrid Elbe, connected by generated flood of data nessing the massive itusing things—and ac- actionablegain to insights—we’ll seen never to a degree business transformation celerate before. at- Managing servicesthe edge is a com and infrastructure act balancing plex that has to meet demand- much more and requires ing constraints timing and dependability than in a conventional speed and precision more vastly objectives Satisfying the competing center. cloud data - and workload con of stringent Quality of Service (QoS) new requires IoT environment in solidation this complex alone does Virtualization and advancements. approaches this IoT not for transformation. the full potential deliver and E.g. challenging industrial workloads an automatic for will be needed. approach self-managing Working with Safe, Deterministic and Secure Deterministic Safe, with Working to Edge from Cloud Intelligence 6 1.1.1 TUESDAY OPENING SESSION OPENING TUESDAY

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1.1.2 TUESDAY OPENING SESSION Assisted andAutomated Driving tion of the vehicletion of infrastructure. into anITbasedservice to providearchitecturethe seamlessintegra isnecessary - least, EE not anewend-to-end but Last realtesting. world to bereplaced bya combination andsystematic ofvirtual data whereastraditional random roadtesting has based bined withapproachesto process very large amounts of automated systems.Systemsto becom Engineeringhas - to develop,mandatory approve andrelease higherlevel processes,the necessary as arethat tools methods and of sensing, sensorfusion, planningandcontrol aswell technological fields competencythe necessary bothin tosystematically the build This offers theopportunity programsment to enableLevel3/4 automated driving. assistance systeminparallel indevelopto participating ofLevel1/2 andfunctionality the performance ing driver majority ofcars. Therefore, focuses onincreas PORSCHE - technologicalstate-of-the-art the nificant role being for a for decadeLevelthe next 1and2systemswillplay a sig- levels ofautomation from SAE Levelto Level 3 4, least at the commonAlthough discussionfocusesthe higher on Performance strategy. Intelligent the PORSCHE contributionprovidesto aperfect cruise control basedonsophisticated planningalgorithms likethe predictive Innodrive systemenablingefficient cupied parkingspaces.Furthermore, newfunctionalities situationstime-consuming liketraffic jams, orheavily oc- easeofdrivinginstressful,conditions significant expect their ownincaseofappropriatetrafficenjoy drivingon car:the philosophy that of to a sports customers diction lines. their product matedto driving There isnocontra - systematic driver strategy assistanceandauto- to adapt tive CruiseControlthe Mid 2000s, in follows PORSCHE a the introduction ofParkSince DistanceControl andAdap Porsche,Jürgen Bortolazzi, DE 26 March 2019, 0955–1030, Auditorium Jürgen Bortolazzi 7 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - www.date-conference.com Claudio Giorgione - by Leon drawn The machines and mechanical elements as engineer and of his itinerary ardo through the course high- technologist belong fields, to the most disparate his curiosity aboutlighting of his the technological culture the first times. Justthe other sectors as for of his activity, in of the follow tradition machines depicted by Leonardo character are and workshop Florentine the Renaissance 26 March 2019, 1350 – 1420, Room 1 Room 1350 – 1420, 2019, 26 March e della della Scienza Museo Nazionale Claudio Giorgione, Curator, IT Milano, Vinci, da Leonardo Tecnologia - aimed at resolu empirical approach by a practical, ized his During as arose. they progressively problems of tion experi- was Leonardo first Milanese period (1482-1499), graphical effective more ever and refining with, menting in which he would proceed systems of representation, architecture, anatomy, like applying also other sectors, to and prospect views, and military engineering. Sections, machines into used to decompose were views transparent automat for solutions finding elements, their constituent traditional efficient existingmore the rendering and ing new mecha- completely conceiving or for mechanisms, from particularly in the 1490s, moved, nisms. Leonardo - theoreti to a more problems of practical documentation functioning the of analysis cal regulating principles the from mechanical elements the study of to of machines, The studies on friction and on motion their inter-relation. which to be inserted are into this perspective, in general on mechanics, led him a to treatise of compiling the idea the so- based on the analysis of mechanisms and gears, called “elementi macchinali”. Leonardo da Vinci, Humanism and Humanism da Vinci, Leonardo and Milan Florence Engineering between 8 3.0 TUESDAY LUNCHTIME KEYNOTE LUNCHTIME TUESDAY

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 7.0 WEDNESDAY KEYNOTE LUNCHTIME Era ofIntelligent, Cloud-Connected Devices Heterogeneous, HighScale Computing inthe Supported by IEEE CEDA byIEEE Supported these samemethods. ing cloud-based semiconductor design is being enhanced us- products. talk willconcludeThe withexamples ofhow to createconnected devices next-generation intelligent tive computing methodsandcoupled withsmart, cloud- ers increasingly rely on AI/ML, accelerated using alterna- within Amazon, aswellexamples ofhowAmazon custom- nologies. talk presentsThis examples ofsuchuse-cases CPUs, GPUs, FPGAs, andotheremerging accelerationtech- alternative, heterogeneous computing methodsinclude arethe edge. being deployed the cloud and at in These workloads,important alternative methodsof computing these of the financialandhealthcare Insupport sectors. Alexa, factories andconsumer-facingto smart in services tonomous vehicles, products suchas to cloud-connected ics andIoTapplications, ranging from robotics andau- the newest, ofmany advanced most analyt the heart at IoTedgedevices. AI/MLas wellincloud-connected is This increasingthe publiccloud demandisbeingseenin tional, highly scalable computing and storage platforms. lytics, haveto anexplosion led indemandfor non-tradi- chine learningand “data lake” methodsofadvanced ana- Rapid advances inconnected devices, coupled withma- David Pellerin, Amazon, US 27 March 2019, 1345–1420, Room 1 David Pellerin 9 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - www.date-conference.com Edward A. Lee A. Edward Models are central to building confidence in complex soft complex in to building confidence central Models are 28 March 2019, 1320 – 1350, Room 1 Room 1320 – 1350, 2019, 28 March US Berkeley, of California, University Lee, A. Edward se- formal theories, interface systems, Type systems. ware component models of computation, concurrent mantics, all augment classical software and ontologies models, design engineering techniques such as object-oriented modular and more software and to make errors to catch - within a modeling frame model lives Every composable. and many ideally giving semantics to the model, work, that enable been developed have modeling frameworks of properties. such But analysis and proof every rigorous A imperfectan is reality. of framework modeling mirror or in world may the physical system operating computer by a model, predicted reflect behaviors notmay accurately notand the model may reflect critical that behaviors are a cyber- in Software of the software. operation correct to has timing properties that example, for system, physical artificialAs models. - intel formal in represented rarely are gets worse, problem the widely used, ligence gets more - seemingly evapo and explainability with predictability in the limitations the I will examine In rating. this talk, classes use of models. I will show that different two very - “scien classes that I call used in practice, of models are These two classes “engineering models.” and tific models” misuses of and many properties, complementary have about confusion which class is being models stem from very dif systems are models of intelligent used. Scientific engineering models. from ferent A Fundamental Look at Models and Models and at Look A Fundamental Intelligence 10 11.0 THURSDAY LUNCHTIME KEYNOTE LUNCHTIME THURSDAY

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com  Password: “DATE” the appandsearch forthe conference “DATE 2019” ple/Google stores for free: https://whova.com/download Pleaseinstall The Whovathe followingthe Ap appcanbedownloadedvia linkorin WHOVA ConferenceApp the following at link: www.date-conference.com/proceedings. throughthe DATE-WLAN for every fullyregistered conference delegate The conference proceedings are available for downloadon-site Proceedings be providedthe registration at deskupon arrival. congressthe entire center during DATE week. The logincodeWLAN will Free wireless accessisavailable internet the whole throughout on-site Internet Access tirethe programme detailsof andplanyour attendance inadvance. site technical conferenceThe full programme isalsoavailablethe web on Online Programme the coffeewhich alsohosts breaks. takethe Exhibitionand will placein Areathe conference of venue, The accompanying exhibitionto 28March isscheduledfrom 2019, 26 50123 Florence, IT Viale Filippo Strozzi no. 1. Friday) Monday – (Main conference venue Padiglione Spadolini, lower floor daBasso Fortezza www.firenzefiera.it Firenze Fiera Firenze Fiera, Florence, IT. The conferencetake will placefromto 29March 2019, 25 the at Dates andVenue ference websitewww.date-conference.com accommodation,travel offers andsocial events is available the on con- mation onawards, conference registration costs, information about ference informationtechnical programme includingall details, infor referencetheir attendance DATE during at document 2019.Full con- This printed programmeto provide isintended delegates withaneasy INFORMATIONGENERAL www .date-conference.com wherethe en- youto view willbeable 50123 Florence, IT Piazza Adua1 Tuesday (Opening Session Auditorium Palazzo deiCongressi morning) 11 - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 1030 – 1130 1300 – 1430 1350 – 1420 1600 – 1700 1000 – 1100 1230 – 1430 1345 – 1420 1600 – 1700 1000 – 1100 1230 – 1400 1320 – 1350 1530 – 1600 www.date-conference.com Monday, 25 March 2019 Monday,

12 Welcome Reception & PhD Forum Reception Welcome Lunch Break 1” “Room in Lecture Keynote Break Coffee 2019 27 March Wednesday, Break Coffee Lunch Break 1” “Room in Lecture Keynote Break Coffee 28 March 2019 Thursday, Break Coffee Lunch Break 1” “Room in Lecture Keynote Break Coffee Lunch Break (Lunch Area) Lunch Break (Lunch (lunch lunch seated a Thursday), to (Tuesday days all conference On conference registered Area infully to the Lunch will be offered buffet) at the entrance control will be a lunch voucher There only. delegates area. to the lunch break 26 March 2019 Tuesday, Break Coffee On all conference days (Tuesday to Thursday), coffee and will be tea coffee Thursday), to (Tuesday days On all conference at times in the the below-mentioned breaks during served the coffee da Basso. Spadolini of Fortezza in the Padiglione Area Exhibition Coffee Break in the Exhibition Area Exhibition Coffee Break in the A browser version can be accessed at be accessed can version A browser https://whova.com/webapp/e/date_201903/ button): App (“survey” WHOVA via the Evaluation Online Conference conference online the completes who delegate, registered fully Every collector DATE one of the exclusive will receive via the app, evaluation page). showing desk (when confirmation the mugs at registration the GENERAL INFORMATION hosted by EDAA, ACM SIGDA, and IEEE CEDA SIGDA, ACM hosted by EDAA, kindly visitors are and exhibition delegates conference All registered & subsequent PhD Reception Welcome 2019 invited to join the DATE 1800 –from 2019, 25 March Monday, on place will which take Forum, venue. of 2100 in the conference the Lunch Area

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI will beoffered. where free drinks for allconference delegates andexhibition visitors the Exhibitionto 1930in from Areathe conference 1830 of venue, The Exhibition Receptiontake will placeon Tuesday, 26March 2019, supported byDestination Florence Convention andVisitors Bureau tion process though). Additional ticketsthough). Additional tion process canbepurchased on-siteat the DATEto bebooked Partythe onlineregistra (whichneeds during - Eachticket. fullconferencevalid party registrationticket for includes a entrancethat networking event. Pleasenote is onlypossiblewitha All delegates, exhibitorstheir guests are and to attendthe invited aseated dinner. isnot it that Please kindlynote setting forthe DATE Party 2019. and pomp,the citycenter andwillofferto islocated close a special Nowadays Palazzo Borghese, splendor the ancient stillmaintaining he hadgivento many different jobs artisans. the people’scani and thePrincebecause, to affection withhis request, work: marbles, paintings, andantique furniture gaveto Bac- notoriety the Florentineand nobleswere really suchmagnificent surprisedat Gaetano Baccani. The inauguration 1822, wasthe 31January on party Saxony in May 1821,the youngto architect commendingthe work between Grand Duke andPrincessMariaFerdinanda Ferdinand of III rich Princerenovatedthe wedding the occasionof the buildingon here afterto Pauline (sisterofNapoleon). hismarriage Bonaparte The to PrinceCamillo Borghese, belonged It temporarytook residence who ofFirenzeheart andisabeautiful example ofneoclassicarchitecture. This year,take will Palazzo placeat it Borghese, whichislocatedthe in Paper Award.the Best Awards IP of andBest As in 2018,the DATE Party will again featurethe awards presentation March 2019, fromto 2300. 1930 laxed atmosphere is scheduledon27 whileenjoyinglocalamenities.It friendsandcolleagues inareto meet week,- occasion isaperfect it the DATE during the mainnetworkingopportunities week. Asoneof The DATE traditionallyParty statesthe the DATEhighlights one of of www.date-conference.com DATE |Networking Party Event Exhibition Reception  SeePage 164 feedbacktheir work. on for exposureto receivethe jobmarketto get and students on valuable tion and systemdesign community. represents It a goodopportunity thesis andresearchthe designautoma- their workwithpeopleof cuss the PhDForumpurpose of to offer is a forum todis- for PhDstudents DA), Council onElectronicthe IEEE Design Automation and (CEDA). The (EDAA),the ACM SpecialInterest Group onDesignAutomation (SIG- the Europeanstyle dinnerhostedby DesignAutomation Association The PhDForumthe DATE of Conference isapostersessionandbuffet INFORMATIONGENERAL Wednesday, 27March2019 Tuesday, 26March2019 13

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - 1600 – 1630 1530 – 1600 1000 – 1030 1000 – 1030 1600 – 1630 approx. 2100 approx. www.date-conference.com Party during the DATE Area Poster Area Poster Area Poster Area Poster Area Poster (Palazzo Borghese) (Palazzo of the Best IP Award Presentation IP Session 3 IP Session 5 Wednesday, 27 March 2019 27 March Wednesday, IP Session 2 14 Thursday, 28 March 2019 Thursday, IP Session 4 el ideas and work in progress, which may require additional research additional research require which may el ideas and work in progress, working in the same area. with other researchers work and discussion, and talk freely author to any around can walk attendees Interested will also be IP format. presentations in a vivid face-to-face want they in a IP Each will additionally be introduced by a poster. accompanied session prior to regular the IP- one-minute pres Session in a relevant entation. a displaying projection will be one central there an overview, give To going on at listthe same of all time in the presentations the IP area. in (IP) Area in held be will Sessions Poster the Presentation Interactive 30-minute days: time slots on the following 26 March 2019 Tuesday, IP Session 1 Interactive Presentations Interactive Academic Network) (sponsored by the Cadence discuss nov to interactively presenters allow presentations Interactive  https://www.palazzoborghese.it/en/contacts/ (Zona area within restricted the located is traffic Borghese The Palazzo protectcreated to been which has ZTL) of Florence, – limitato a traffico way to the best Hence, traffic. excessive from the historic city centre the historic centre. through is by walking get to the Palazzo distance: Walking da Basso Fortezza 25 minutes / ~2 km from Route description Route the registration desk (subject to availability of tickets). Price for extra extra Price for of (subject desk tickets). to availability the registration person. 70 € per ticket: GENERAL INFORMATION

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 4.1 3.1 3.0 2.1 SESSIONS EXECUTIVE

Executive Session: TheFuture ofTest theNextBig Surfing Wave Executive Panel: Semiconductor IP, Florence andMilan Humanism between andEngineering LUNCHTIME KEYNOTE: Leonardo daVinci, Executive Panel: LifeAfterCMOS research point-of-view. institutionsfromtechnology abusinessand informationthe visionandroadmaps ofleadingcompanies and about This year's Executive Track shouldoffer prospective attendees valuable gies andapplications. the futuretest, tives of withaspecialfocus about technolo- onemerging 5G, AI, ADAS, HPC, andIoT. topic sessionwilloffer newperspec- The hot wavethe next discuss ofinnovations willfuelapplicationsthat suchas The panelsgather auniquegroup from ofexperts to alloverthe world ing betweenFlorence andMilan. will provide an overview of Leonardo's many contributionsto engineer the National of Museum of Science and ment Technology, Milan, Italy, lunch keynote byDr. ClaudioGiorgione, Curatorthe Leonardo of Depart the 500thanniversary2019 marks ofLeonardo da Vinci'sthe death and topic session. and ahot conferencetracks. willbecomprisedtwo panels, of It alunchkeynote atelytechnical afterthe the OpeningSessionandwillruninparallelto held on Tuesday, 26March, day the of the first DATE conference immedi- andacademiarepresentatives.ing industry This one-day program willbe DATE 2019willagainfeature anExecutive Track ofpresentations bylead- Marco Casale-Rossi, Synopsys, IT Giovanni DeMicheli,EPFLausanne, CH Co-Chairs: Chair: SubhasishMitra, Stanford University, US Chair: RaulCamposano, SageDesignAutomation, US Tecnologia Leonardo da Vinci, Milano, IT Claudio Giorgione,Curator, MuseoNazionaledellaScienza edella Chair: G. DanHutcheson, VLSI Research, US " SeePage 55 " SeePage 47 " SeePage 41 " SeePage 8 15 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - - See Page 9 " See Page See Page 73 " See Page 80 " See Page See Page 60 " See Page 67 " See Page www.date-conference.com ded meets Hyperscale and HPC Hyperscale ded meets Co-Chairs: CH Zurich, IBM Research Christoph Hagleitner, DE University, Paderborn Christian Plessl, and ap processors specialized with multiple, computing Heterogeneous plication-specific accelerators is vital for embedded systems meet to is vital per accelerators plication-specific efficient, fast, of goals same The efficiency and targets. latency, formance, of forevolution factors the also gating are processing and cost-effective (HPC) high-performance (DC) and computing and center data hyperscale we the necessary efficiency gains. Hence, law no longer provides Moore's in embedded systems of pioneered technologies can witness a spread comput the use of specialized e.g., and HPC DCs to hyperscale systems, and domain-specific model-driven parallelism, massive ing resources, The of theme this and others. co-scheduling, task models, programming, is to highlightspecial day of methods and technologies this confluence is shaping the fu- computing how heterogeneous to better understand, and HPC. DCs of hyperscale ture Special Day Panel: What can HPC and What Panel: Special Day from embedded computing learn hyperscale Special Day Session: Tools and Runtime and Runtime Tools Session: Special Day Systems Special Day Session: Near-memory Session: Special Day computing High Heterogeneous, KEYNOTE: LUNCHTIME of Intelligent, in the Era Computing Scale Devices Cloud-Connected Special Day Session: Heterogeneous Session: Special Day and in HPC the Datacenter in Computing Embed

16 8.1 7.1 7.0 6.1 5.1

SPECIAL DAY – WEDNESDAY WEDNESDAY – SPECIAL DAY

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 12.1 11.1 11.0 10.1 9.1 DAYSPECIAL – THURSDAY Systems DaySpecial Session: MBDofSafeandSecure Systems DaySpecial Session: MBDofCyber-Physical at ModelsandIntelligence LUNCHTIME KEYNOTE: AFundamental Look Machine Learning DaySpecial Session: Hottopic: Model-Based trenches, model-baseddesignat work DaySpecial Session: fromthe Experiences Model-Based DesignofIntelligent Systems DATE communityto helpovercome them. the upcomingthis domainandinvite challengesin also highlight design insafety-critical andautonomoussystems. The specialday will systems, model-based machine learning, and application of model-based dressed are,things, amongother model-baseddesignframeworks for IoT to liftthe era model-baseddesigninto ofintelligent systems. Topics ad- generated automatically. This specialday willexplore isneeded that all alyzable models, from whichsoftware andhardware realizations canbe employedto develop embeddedsystems, from well-defined, starting an- centrethe development of cycle. hasbeensuccessfully This methodology time frames.the creasingly Model-baseddesignplacesmodelsat shorter the development undercontrol anddeliver highqualitysystemsin- plexity. Goodmodelsandassociated designprocesses areto keep needed acceleratethe riseofintelligent systemswillfurther the designcom - but The complexitytoday's of cyber-physical systems is already enormous, Patricia Derler, National Instruments, US Sander Stuijk,Eindhoven University of Technology, NL Marc Geilen,Eindhoven University of Technology, NL Co-Chairs: " SeePage 104 " SeePage 93 " SeePage 86 " SeePage 98 " SeePage 10 17

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - See Page 59 " See Page 61 " See Page 64 " See Page See Page 48 " See Page See Page 42 " See Page www.date-conference.com Karlsruhe Institute of Technology, DE Technology, Timo Institute of Sandmann, Karlsruhe Chair: Synopsys, US Synopsys, Jamil Kawa, Chair: DK of Denmark, University Technical MartinSchoeberl, Chair: Linköping University, SE University, Linköping Eles, Petru Chair: US University, State Colorado Sudeep Pasricha, Co-Chair: Synopsys, US Synopsys, Jamil Kawa, Chair: Special Session Chairs: Special Session DE München, Universität Technische Herkersdorf, Andreas SG of Singapore, University National Mitra, Tulika by special sessions organized excellent collection of a offers 2019 DATE - comple and are interest leading experts on topics general of that are of topics include super The range mentary paper session. to the regular conductive electronics, flexible electronics, quantum computers, 3D sen- computers, quantum electronics, flexible electronics, conductive safety-critical hardware, open-source processors, heterogeneous sors, rebooting and analytics, graph system-on-chip verification, applications, models. computing Chair: Projects European DK of Denmark, University Technical Martin Schoeberl, EU Projects II The ARAMiS Project – Special Session: for safety-critical Use of Multicore Efficient Applications Special Session: Smart Resource Smart Special Session: and Design Space Exploration Management for Heterogenous Processors for Very the Way Paving Embedded Tutorial: of Superconductive Integration Large Scale Electronics Special Session: Circuit design and design design and Circuit Special Session: electronics for flexible automation 18 5.8 5.3 4.8 3.2 2.3 SPECIAL & EU SESSIONS

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 11.3 10.2 9.8 9.3 8.2 6.2 SESSIONS &EU SPECIAL Models Session:Special RebootingourComputing and Opportunities Extreme Scales: Design Challenges, Advances, Session:Special Enabling Graph Analytics at Quantum Computers Developing for andWorking with Real Session:Special IBM’s Qiskit Tool Chain: Secure OpenHardware Session:Special RISC-VorRISK-V? Towards signal, security andsoftware verifying Systems-on-Chip: digital, mixed- Session:Special Innovative methodsfor 3D Sensor–Hardware toApplication Session:Special Co-Chair: IanO’Connor, Ecole Centrale ofLyon, FR Chair: Pierre-Emmanuel Gaillardon,University ofUtah, US Chair: ParthaPande, Washington State University, US Chair: Wille, JohannesKeplerRobert University Linz, AT Chair: GeorgSigl,TUM,DE Co-Chair: Giovanni DeMicheli,EPFL, CH Chair: Schlichtmann,TUM, Ulf DE Co-Chair:Pascal Vivet, CEA-Leti, FR Chair: Fabien Clermidy, CEA-Leti, FR " SeePage 99 " SeePage 93 " SeePage 90 " SeePage 87 " SeePage 81 " SeePage 67 19

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com

Special Workshops Interest Demo supported Racing IEEE by F1/10 Autonomous CEDA International Special Day on “Model-Based Design of Intelligent Systems” and Keynote Systems” Design of Intelligent “Model-Based on Special Day Conference Technical IP4 and IP5 Presentations Interactive Theatre & Exhibition Exhibition Vendor Booth University Workshops Meetings & Co-Located Fringe Special Day on “Embedded Meets Hyperscale and HPC” and Keynote “Embedded Meets Hyperscale and HPC” on Special Day IP2 and IP3 Presentations Interactive Conference Technical Theatre & Exhibition Exhibition Vendor Booth University Workshops Meetings & Co-Located Fringe | Networking Event Party DATE Opening Session: Plenary, Awards Ceremony & Keynote Addresses & Keynote Ceremony Awards Plenary, Opening Session: Keynote Sessions and Executive Conference Technical IP1 Presentation Interactive Theatre & Exhibition Exhibition Vendor Booth University Workshops Meetings & Co-Located Fringe Reception Exhibition Bureau Visitors and Convention supported Florence by Destination Monday Tutorials Monday and IEEE CEDA SIGDA, ACM hosted by EDAA, PhD Forum, & Reception Welcome

• • • • • • • • • • • • • • • • • • • • • • • • •

Fri Thu Wed Tue Mon 20 DATE 2019 Conference Organization Conference 2019 DATE GmbH Dresden Group K.I.T. c/o Bautzner Str. 117 – 119 Germany 01099 Dresden, [email protected] Email: Manager: Conference Smejkal Eva DE GmbH Dresden, Group K.I.T. +49 351 4967 312 Phone: Manager: Exhibition Schäfer Kathleen DE GmbH Dresden, Group K.I.T. +49 351 4842 964 Phone: & Accommodation: Registration Anja Zeun DE GmbH Dresden, Group K.I.T. +49 351 4842 975 Phone: [email protected] CONTACTS EVENT OVERVIEW EVENT

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com FM01 TS EN V E MONDAY 1400–1800 1530–1600 1300 MONDAY, 2019 MARCH 25 1800–2100 1400–1800 and Test Manufacturing in Semiconductor Machine Learning Applications of M01 Room 4 tutorials duringthesession. Registered participantscanattendanytutorialandmaymovebetween Tutorial CoffeeBreak Tutorial andConferenceRegistration CEDA, incl.Awards Presentation,LunchArea Welcome Reception&PhDForumhostedbyEDAA,ACMSIGDA,and IEEE 2.0 Era Automotive Security in Safety and M05 Room 8 EDAA, ACM SIGDA, CEDA andIEEE Welcome Reception &PhDForum, hostedby Organiser: Wille, JohannesKeplerRobert University Linz, AT 25 March 2019, 1800–2100, Lunch Area differences vendor-specific patterns and strategies, design optimization FPGAs –common and Xilinx flows forIntel OpenCL design M02 Room 9 Qiskit to IBMQand Computing, intro Quantum M07 Room 7 Application-Level Component- to Techniques: From Computing Approximate Analysis of A Comprehensive M03 Room 5 Things for theInternetof Security Solutions Hardware-based M04 Room 6 " SeePage 164 21

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 0730 0830 – 1030 1030 – 1130 1600 – 1700 1130 – 1300 1430 – 1600 1700 – 1830 1300 – 1430 1830 – 1930 Track 8 Track Exhibition Theatre 2.8 How Electronic Systems can benefit from Machine Learning and from ESD Alliance Exhibition Theatre 3.8 DFG Collaborative Funding Instruments Exhibition Theatre 4.8 Embedded Paving Tutorial: for Very the Way Large Scale Integration of Superconductive Electronics Track 7 Track Room 7 2.7 Analysis and optimization techniques for neural networks Room 7 3.7 Design Automation of Cyber-Physical Systems Room 7 4.7 Energy and power efficiency in GPU- based systems How to Publish Your Research Work, Exhibition Theatre Research Work, How to Publish Your 2.6 Computational and resource- efficiency in quantum and approximate computing Room 6 3.6 Software Solutions for Reliable Memories Room 6 4.6 Smart Communication Solutions for Automotive Systems Track 6 Track Room 6 IP1 Interactive Presentations, Poster Area 3ps.8 EXHIBITION RECEPTION in the Exhibition Area 2.5 Solutions for reliability and security of mixed- signal circuits Area Exhibition and Lunch Break, Lunch SESSION Room 1 1350 – 1420 3.0 LUNCHTIME KEYNOTE Room 5 3.5 Hardware authentication and attack prevention Exhibition and Coffee Break 1600 – 1630 1615 – 1645 Room 5 4.5 Hardware and Split Trojans Manufacturing Registration | Speaker’s Breakfast, Lunch Area Breakfast, | Speaker’s Registration Ceremony Awards Plenary, 1.1 Opening Session: Auditorium & Keynote Addresses, Break Exhibition and Coffee 5 Track Room 5 Room 4 Room 4 Track 4 Track Room 4 4.4 Digital processing with emerging memory technologies 2.4 Temperature and Variability Driven Modeling and Runtime Management 3.4 Physical Design, Extraction and Analysis Timing Exhibition Theatre www.date-conference.com 4.3 Improving test generation and coverage 2.3 Special Session: Circuit design and design automation for flexible electronics 3.3 Methods and Characterisation techniques for Reliability Room 3 Room 3 Track 3 Track Room 3 IP Session How to Publish Your Research Work, Exhibition Theatre Research Work, How to Publish Your Room 2 Room 2 Track 2 Track Room 2 4.2 Reconfigurable Architecture and Tools 3.2 Special Session: Smart Resource Management and Design Space Exploration for Heterogenous Processors 2.2 Physical Attacks IP1 Interactive Presentations, Poster Area 3ps.8 Special & EU Session Room 1 Room 1 Track 1 Track Room 1 EXHIBITION RECEPTION in the Exhibition Area Exhibition and Coffee Break 1600 – 1630 1615 – 1645 4.1 Executive Session: The Future of Test Exhibition and Lunch Break, Lunch Area Exhibition and Lunch Break, Lunch SESSION Room 1 1350 – 1420 3.0 LUNCHTIME KEYNOTE 3.1 Executive Panel: Semiconductor IP, Surfing the Next Big Wave 2.1 Executive Panel: Life After CMOS Registration | Speaker’s Breakfast, Lunch Area Breakfast, | Speaker’s Registration Ceremony Awards Plenary, 1.1 Opening Session: Auditorium & Keynote Addresses, Break Exhibition and Coffee Opening Session Executive Session TUE Keynote 22 1830 – 1930 1700 – 1830 1600 – 1700 1300 – 1430 1430 – 1600 1130 – 1300 0830 – 1030 1030 – 1130 0730 TUESDAY, 26 MARCH 2019 TUESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI 1830 – 1930 1830 – 1830 1700 – 1700 1600 – 1600 1430 – 1430 1300 – 1300 1130 1030 –1130 0830 –1030 0730 EXHIBITIONRECEPTIONintheExhibitionArea The FutureofTest Session: Executive 4.1 1615 –1645 1600 –1630 Exhibition andCoffeeBreak Big Wave Surfing theNext Semiconductor IP, Executive Panel: 3.1 1350 –14203.0LUNCHTIMEKEYNOTESESSIONRoom1 Exhibition andLunchBreak,Area Life AfterCMOS Executive Panel: 2.1 Exhibition andCoffeeBreak & KeynoteAddresses,Auditorium 1.1 OpeningSession:Plenary, Awards Ceremony Registration |Speaker’s Breakfast,LunchArea Room 1 Room 1 Room 1 Track 1 3ps.8 IP1 InteractivePresentations,PosterArea Tools Architecture and Reconfigurable 4.2 Processors Heterogenous Exploration for Design Space Management and Smart Resource Special Session: 3.2 Physical Attacks 2.2 Room 2 Room 2 Room 2 Track 2 How toPublishYour ResearchWork, ExhibitionTheatre Room 3 Room 3 Room 3 Track 3 coverage generation and Improving test 4.3 Reliability techniques for Characterisation Methods and 3.3 electronics for flexible automation and design Circuit design Special Session: 2.3 technologies memory with emerging Digital processing 4.4 Timing Analysis Extraction and Physical Design, 3.4 Management and Runtime Driven Modeling and Variability Temperature 2.4 Room 4 Room 4 Room 4 Track 4 www.date-conference.com TUESDAY, 2019 MARCH 26 D-Track EXHIBITIONRECEPTIONintheExhibitionArea Manufacturing Trojans andSplit Hardware 4.5 Room 5 1615 –1645 1600 –1630 Exhibition andCoffeeBreak prevention and attack authentication Hardware 3.5 Room 5 1350 –14203.0LUNCHTIMEKEYNOTESESSIONRoom1 Exhibition andLunchBreak,Area signal circuits security ofmixed- reliability and Solutions for 2.5 Room 5 Track 5 Exhibition andCoffeeBreak & KeynoteAddresses,Auditorium 1.1 OpeningSession:Plenary, Awards Ceremony Registration |Speaker’s Breakfast,LunchArea 3ps.8 IP1 InteractivePresentations,PosterArea Systems Automotive Solutions for Communication Smart 4.6 Room 6 Memories for Reliable Solutions Software 3.6 Room 6 computing approximate quantum and efficiency in and resource- Computational 2.6 Room 6 Track 6 How toPublishYour ResearchWork, ExhibitionTheatre A-Track based systems efficiency inGPU- Energy andpower 4.7 Room 7 Systems Cyber-Physical Automation of Design 3.7 Room 7 neural networks techniques for optimization Analysis and 2.7 Room 7 Track 7 T-Track Electronics Superconductive Integration of Large Scale the Way forVery Tutorial: Paving Embedded 4.8 Exhibition Theatre Instruments Funding DFG Collaborative 3.8 Exhibition Theatre Alliance and fromESD Machine Learning benefit from Systems can How Electronic 2.8 Exhibition Theatre Track 8 E-Track 1830 – 1930 1830 – 1430 1300 1700 – 1830 1700 – 1600 1430 – 1300 1130 1600 – 1700 1600 1030 –1130 0830 –1030 0730 23

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 0730 0830– 1000 1000 – 1100 1100 – 1230 1230 – 1430 1430 – 1600 1700 – 1830 1930 – 2300 1600 – 1700 Exhibition Theatre 6.8 TETRAMAX: Smart funding for digitalization of Industry Europe’s Exhibition Theatre Exhibition Theatre 8.8 Inspiring futures! Careers Session (part 2) @ DATE 7.8 Inspiring futures! Careers Session (part 1) @ DATE Track 8 Track Exhibition Theatre 5.8 Special Session: The ARAMiS II Project – Efficient Use of Multicore for safety-critical Applications Room 1 Poster Area Poster Area Room 7 6.7 How Secure and is your Verified Cyber-Physical System? Room 7 Room 7 8.7 Embedded hardware architectures for deep neural networks Palazzo Borghese & Best IP Award) (incl. Best Paper Awards 7.7 Correct Toward and Secure Embedded Systems Track 7 Track Room 7 5.7 Data-driven Acceleration Room 6 6.6 Intelligent and Wearable Implantable Sensors for Augmented Living Room 6 Room 6 8.6 Robotics and Industry 4.0 7.6 Optimization of Smart Energy Systems Track 6 Track Room 6 5.6 Energy efficiency in IoT – Edge to Cloud 7.0 LUNCHTIME KEYNOTE SESSION IP2 Interactive Presentations IP3 Interactive Presentations 8.5 Forget the Don’t Memory Party | Networking Event DATE Exhibition and Coffee Break 1000 – 1030 Room 5 6.5 System Level Security Exhibition and Lunch Break, Lunch Area 1345 – 1420 Room 5 7.5 Reliable and Persistent: From Cache to File system Exhibition and Coffee Break 1600–1630 Room 5 Registration | Speaker’s Breakfast, Lunch Area Breakfast, | Speaker’s Registration 5 Track Room 5 5.5 Hardware Obfuscation Room 4 Room 4 Room 4 Track 4 Track Room 4 8.4 Applications of Reconfigurable Computing 7.4 Low Power Design: From Highly-Optimized Power Delivery Networks to CNN Accelerators 6.4 Hardware support for microarchitecture performance 5.4 Emerging technologies for better NoCs Exhibition Theatre Room 1 www.date-conference.com Poster Area Poster Area 8.3 Preparation Test and Generation 7.3 CPU and GPU microarchitecture dependability 6.3 When Approximation Meets Dependability 5.3 EU Projects Room 3 Room 3 Room 3 Track 3 Track Room 3 Palazzo Borghese & Best IP Award) (incl. Best Paper Awards IP Session Room 2 Room 2 Room 2 Track 2 Track Room 2 8.2 Special Session: Innovative methods for verifying Systems-on-Chip: digital, mixed- signal, security and software 7.2 Accelerators using novel memory technologies 6.2 Special Session: 3D Sensor – Hardware to Application 5.2 Improving Formal and Verification Applications to GPUs and High- Level Synthesis 7.0 LUNCHTIME KEYNOTE SESSION IP2 Interactive Presentations IP3 Interactive Presentations Special & EU Session Room 1 Room 1 Room 1 Track 1 Track Room 1 DATE Party | Networking Event DATE 8.1 Special Day on “Embedded Meets Hyper scale and HPC” Panel: What can HPC and hyperscale learn from embedded computing 7.1 Special Day on “Embedded Meets Hyper scale and HPC” Session: and Runtime Tools Systems Exhibition and Coffee Break 1600–1630 Exhibition and Lunch Break, Lunch Area 1345 – 1420 Exhibition and Coffee Break 1000 – 1030 6.1 Special Day on “Embedded Meets Hyper scale and HPC” Session: Near-memory computing Registration | Speaker’s Breakfast, Lunch Area Breakfast, | Speaker’s Registration 5.1 Special Day on “Embedded Meets Hyper scale and HPC” Session: Heterogeneous Computing in the Datacenter and in HPC WED Keynote Special Day Session 24 1930 – 2300 1700 – 1830 1600 – 1700 1430 – 1600 1230 – 1430 1100 – 1230 1000 – 1100 0830– 1000 0730 WEDNESDAY, 27MARCH 2019WEDNESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI 1930 – 2300 1930 – 1830 1700 1600 –1700 – 1600 1430 – 1430 1230 – 1230 1100 – 1100 1000 0830– 1000 0730 DATE Party|NetworkingEvent computing from embedded hyperscale learn can HPCand Panel: What scale andHPC” Meets Hyper on “Embedded Special Day 8.1 1600–1630 Exhibition andCoffeeBreak Systems Tools andRuntime Session: scale andHPC” Meets Hyper on “Embedded Special Day 7.1 1345 –1420 Exhibition andLunchBreak,Area computing Near-memory HPC” Session: scale and Meets Hyper on “Embedded Special Day 6.1 1000 –1030 Exhibition andCoffeeBreak in HPC Datacenter and Computing inthe Heterogeneous Session: scale andHPC” Meets Hyper on “Embedded Special Day 5.1 Registration |Speaker’s Breakfast,LunchArea Room 1 Room 1 Room 1 Room 1 Track 1 IP3 InteractivePresentations IP2 InteractivePresentations 7.0 LUNCHTIMEKEYNOTESESSION and software signal, security digital, mixed- Systems-on-Chip: for verifying methods Innovative Special Session: 8.2 technologies memory using novel Accelerators 7.2 Application Hardware to 3D Sensor– Special Session: 6.2 Level Synthesis GPUs andHigh- Applications to Verification and Improving Formal 5.2 Room 2 Room 2 Room 2 Room 2 Track 2 (incl. BestPaperAwards &BestIPAward) Palazzo Borghese Room 3 Room 3 Room 3 Room 3 Track 3 and Generation Test Preparation 8.3 dependability microarchitecture CPU andGPU 7.3 Dependability Meets Approximation When 6.3 EU Projects 5.3 Poster Area Poster Area Room 1 Computing Reconfigurable Applications of 8.4 Accelerators Networks toCNN Power Delivery Highly-Optimized Design: From Low Power 7.4 performance microarchitecture support for Hardware 6.4 better NoCs technologies for Emerging 5.4 Room 4 Room 4 Room 4 Room 4 Track 4 www.date-conference.com WEDNESDAY, 2019 MARCH 27 D-Track DATE Party|NetworkingEvent Memory Don’t Forgetthe 8.5 Room 5 1600–1630 Exhibition andCoffeeBreak system Cache toFile Persistent: From Reliable and 7.5 Room 5 1345 –1420 Exhibition andLunchBreak,Area Security System Level 6.5 Room 5 1000 –1030 Exhibition andCoffeeBreak Obfuscation Hardware 5.5 Room 5 Track 5 Registration |Speaker’s Breakfast,LunchArea IP3 InteractivePresentations IP2 InteractivePresentations 7.0 LUNCHTIMEKEYNOTESESSION Industry 4.0 Robotics and 8.6 Room 6 Systems Smart Energy Optimization of 7.6 Room 6 Augmented Living Sensors for Implantable Wearable and Intelligent 6.6 Room 6 Cloud in IoT–Edgeto Energy efficiency 5.6 Room 6 Track 6 A-Track networks for deepneural architectures hardware Embedded 8.7 Room 7 Systems Embedded and Secure Toward Correct 7.7 Room 7 System? Cyber-Physical Verified isyour How Secureand 6.7 Room 7 Acceleration Data-driven 5.7 Room 7 Track 7 (incl. BestPaperAwards &BestIPAward) Palazzo Borghese Poster Area Poster Area T-Track Room 1 @ DATE (part2) Careers Session Inspiring futures! 8.8 Exhibition Theatre @ DATE (part1) Careers Session Inspiring futures! 7.8 Exhibition Theatre Europe’s Industry digitalization of Smart fundingfor TETRAMAX: 6.8 Exhibition Theatre Applications for safety-critical Use ofMulticore Project –Efficient The ARAMiSII Special Session: 5.8 Exhibition Theatre Track 8 E-Track 1600 –1700 1930 – 2300 1930 1230 – 1430 1230 1000 – 1100 1000 1700 – 1830 1700 – 1600 1430 – 1230 1100 0830– 1000 0730 25

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 0730 0830– 1000 1000 – 1100 1530 – 1600 1600 – 1730 1100 – 1230 1230 – 1400 1400 – 1530 12.8 An Industry Approach to FPGA / ARM System Development and Verification (part 2) Track 8 Track Exhibition Theatre Exhibition Theatre 10.8 Europe digitization: Smart Anything Everywhere Initiative & FED4SAE, open calls and success stories Exhibition Theatre 11.8 An Industry Approach to FPGA/ ARM System Development and Verification (part 1) Exhibition Theatre 9.8 Special Session: Qiskit IBM’s Chain: Tool Developing for with and Working Real Quantum Computers Room 1 Poster Area Poster Area 12.7 Emerging Strategies for Deep Neural Network Hardware Track 7 Track Room 7 Room 7 10.7 Architectures for emerging machine learning techniques Room 7 11.7 Extending Scheduling Schemes Room 7 9.7 Runtime Predictability 12.6 and Trojans public key implementation challenges Room 6 10.6 Self-adaptive resource management Room 6 11.6 Design Automation Solutions for Microfluidic Platforms and Tasks Room 6 Track 6 Track Room 6 9.6 Reliability of highly-parallel architectures: an industrial perspective IP4 Interactive Presentations 11.0 LUNCHTIME KEYNOTE SESSION IP5 Interactive Presentations 12.5 System Modelling for Analysis and Simulation Exhibition and Coffee Break 1000 – 1030 Room 5 10.5 SSD and data placement Exhibition and Lunch Break, Lunch Area 1320 – 1350 Room 5 11.5 e Vitello Mozzarella alla Fiorentina: Virtualization, Multicore, and Fault-Tolerance Exhibition and Coffee Break 1530–1600 Room 5 Registration | Speaker’s Breakfast, Lunch Area Breakfast, | Speaker’s Registration 5 Track Room 5 9.5 Attacking Memory and I/O Bottlenecks Room 4 Room 4 Room 4 Track 4 Track Room 4 11.4 Learning Gets Smarter 12.4 Design and Optimization for Low-Power Applications 10.4 Disruptive Technologies Fake News! Ain’t 9.4 Where do NoC and Machine Learning meet? Exhibition Theatre Room 1 www.date-conference.com Poster Area Poster Area 11.3 Special Session: Rebooting our Computing Models 12.3 Aging, calibration circuits and yield 10.3 System-level Dependability for Multicore and Real-time Systems 9.3 Special Session: RISC-V or RISK-V? Towards Secure Open Hardware Room 3 Room 3 Room 3 Track 3 Track Room 3 IP Session Room 2 Room 2 Room 2 Track 2 Track Room 2 12.2 The Art of Synthesizing Logic 11.2 Novel techniques in optimization and high-level modeling of mixed-signal circuits 10.2 Special Session: Enabling Graph Analytics at Extreme Scales: Design Challenges, Advances, and Opportunities 9.2 High-Level Synthesis 11.0 LUNCHTIME KEYNOTE SESSION IP4 Interactive Presentations IP5 Interactive Presentations Special & EU Session

Room 1 Room 1 Room 1 Track 1 Track Room 1 12.1 Special Day on “Model-Based Design of Intelli gent Systems” Session: MBD of Safe and Secure Systems 11.1 Special Day on “Model-Based Design of Intelli gent Systems” Session: MBD of Cyber- Physical Systems Exhibition and Coffee Break 1530–1600 Exhibition and Lunch Break, Lunch Area 1320 – 1350 Exhibition and Coffee Break 1000 – 1030 10.1 Special Day on “Model-Based Design of Intelli gent Systems” Session: Hot topic: Model- Based Machine Learning Registration | Speaker’s Breakfast, Lunch Area Breakfast, | Speaker’s Registration 9.1 Special Day on “Model-Based Design of Intelli gent Systems” Session: Experiences from the trenches, model-based design at work THU Keynote Special Day Session 26 1600 – 1730 1530 – 1600 1400 – 1530 1230 – 1400 1100 – 1230 1000 – 1100 0830– 1000 0730 THURSDAY, 28MARCH 2019 THURSDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI 1600 – 1730 1600 – 1600 1530 – 1530 1400 – 1400 1230 – 1230 1100 – 1100 1000 0830– 1000 0730 Secure Systems MBD ofSafeand Session: gent Systems” Design ofIntelli “Model-Based Special Dayon 12.1 1530–1600 Exhibition andCoffeeBreak Physical Systems MBD ofCyber- Session: gent Systems” Design ofIntelli “Model-Based Special Dayon 11.1 1320 –1350 Exhibition andLunchBreak,Area Learning Based Machine Hot topic:Model- Session: gent Systems” Design ofIntelli “Model-Based Special Dayon 10.1 1000 –1030 Exhibition andCoffeeBreak design atwork model-based the trenches, Experiences from Session: gent Systems” Design ofIntelli “Model-Based Special Dayon 9.1 Registration |Speaker’s Breakfast,LunchArea Room 1 Room 1 Room 1 Room 1 Track 1

IP5 InteractivePresentations 11.0 LUNCHTIMEKEYNOTESESSION IP4 InteractivePresentations Logic Synthesizing The Artof 12.2 circuits mixed-signal modeling of and high-level in optimization Novel techniques 11.2 Opportunities Advances, and Challenges, Scales: Design at Extreme Analytics Enabling Graph Special Session: 10.2 Synthesis High-Level 9.2 Room 2 Room 2 Room 2 Room 2 Track 2 Room 3 Room 3 Room 3 Room 3 Track 3 circuits andyield Aging, calibration 12.3 Models Computing Rebooting our Special Session: 11.3 Systems and Real-time for Multicore Dependability System-level 10.3 Hardware Secure Open RISK-V? Towards RISC-V or Special Session: 9.3 Poster Area Poster Area Room 1 Applications for Low-Power Optimization Design and 12.4 Smarter Learning Gets 11.4 Ain’t FakeNews! Technologies Disruptive 10.4 Learning meet? and Machine Where doNoC 9.4 Room 4 Room 4 Room 4 Room 4 Track 4 www.date-conference.com THURSDAY, 2019 MARCH 28 D-Track Simulation for Analysisand System Modelling 12.5 Room 5 1530–1600 Exhibition andCoffeeBreak Fault-Tolerance Multicore, and Virtualization, alla Fiorentina: Mozzarella Vitello e 11.5 Room 5 1320 –1350 Exhibition andLunchBreak,Area placement SSD anddata 10.5 Room 5 1000 –1030 Exhibition andCoffeeBreak Bottlenecks Memory andI/O Attacking 9.5 Room 5 Track 5 Registration |Speaker’s Breakfast,LunchArea IP5 InteractivePresentations 11.0 LUNCHTIMEKEYNOTESESSION IP4 InteractivePresentations challenges implementation public key Trojans and 12.6 Room 6 Tasks Platforms and Microfluidic Solutions for Automation Design 11.6 Room 6 management resource Self-adaptive 10.6 Room 6 perspective an industrial architectures: highly-parallel Reliability of 9.6 Room 6 Track 6 A-Track Hardware Network Deep Neural Strategies for Emerging 12.7 Room 7 Schemes Scheduling Extending 11.7 Room 7 techniques machine learning for emerging Architectures 10.7 Room 7 Predictability Runtime 9.7 Room 7 Track 7 Poster Area Poster Area T-Track Room 1 (part 2) and Verification Development System FPGA /ARM Approach to An Industry 12.8 Exhibition Theatre (part 1) and Verification Development ARM System to FPGA/ Approach An Industry 11.8 Exhibition Theatre stories calls andsuccess FED4SAE, open Initiative & Everywhere Smart Anything digitization: Europe 10.8 Exhibition Theatre Computers Real Quantum and Working with Developing for Tool Chain: IBM’s Qiskit Special Session: 9.8 Exhibition Theatre Track 8 E-Track 1530 – 1600 1530 – 1400 1230 – 1100 1000 1600 – 1730 1600 – 1530 1400 – 1230 1100 0830– 1000 0730 27

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19

See Page 169 " See Page 0830 – 1700 Room 5 W05 AxC: 4th on Workshop Approximate Computing 0845 – 1730 Room 4 W10 Workshop on Open- Source Design Automation for FPGAs – OSDA www.date-conference.com 0830 – 1730 Room 9 W04 6th Workshop on Design Automation for Understanding Hardware Designs (DUHDE6) 0830 – 1730 Room 8 W09 Quo vadis, Logic Synthesis? CONFERENCE & CONFERENCE EXHIBITION 09 March – 13 2020 France Grenoble, Alpexpo, 0830 – 1730 Room 1 W03 Workshop DATE on Autonomous Systems Design (ASD2019) 0830 – 1730 Room 10 W08 Grand Challenges and Research Tools for Quantum Computing 0830 – 1730 Room 2 W02 Recent Trends in Memristor Science & Technology 0830 – 1730 Room 7 W07 Workshop on Machine Learning for CAD Workshop Registration and Welcome Refreshments and Welcome Registration Workshop Coffee Break Lunch Break Coffee Break Organisers: IT Emilia, of Modena and Reggio University Burgio, Paolo IT Emilia, Bertogna, Modena and Reggio Marko 29 March 2019, 1000 – 1500, between Rooms 1 and 4 1 and between Rooms 1000 – 1500, 2019, 29 March International F1/10 Autonomous Racing F1/10 Autonomous International by IEEEDemo supported CEDA 0830 – 1730 Room 3 1000 – 1030 1200 – 1300 1430 – 1500 0730 – 0830 W01 The 5th International on Workshop Optical/Photonic Interconnects for Computing Systems (OPTICS) 0845 – 1615 Room 6 W06 2nd International on Workshop Embedded Software for the Industrial IoT (ESIIT 2019) 28 FM03 F RIDAY E V EN TS FRIDAY, 29 MARCH 2019 FRIDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com M07 M05 M04 M03 M02 M01 1800–2100 1600-1800 1530-1600 1400-1530 1300 2019 MARCH 25 TUTORIALS,

Tutorials Qiskit Quantum Computing, Qand intro toIBM Safety andSecurity inAutomotive 2.0Era Internet ofThings Hardware-based Security Solutions forthe Application-Level Computing Techniques: FromComponent- to A Comprehensive Analysis ofApproximate differences design patterns andvendor-specific FPGAs –commonoptimization strategies, OpenCL designflows forIntel andXilinx Semiconductor Manufacturing andTest Applications ofMachineLearningin Tutorials Coffee Break Room 71400 Room 81400 Room 61400 Room 51400 Room 91400 Room 41400 Tutorial andConferenceRegistration hosted byEDAA, ACM SIGDA, CEDA andIEEE Marco Platzner, Paderborn University, DE Monday TutorialsChair: Welcome Reception &PhDForum – – – – – – 1800 1800 1800 1800 1800 1800 " SeePage 164 29

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com 1800 – Coffee Break for Tutorials Practitioners for Recommendations Speaker: FR LIP6, CNRS, Sorbonne Université, Stratigopoulos, Haralampos-G. PartIII machine applying when issues practical main the illustrate will based on recommendations learning several Ittechniques. will provide in the applications several in developing own experience the presenters' past. issues Practical that will be discussed include: types of learning and validation training selection, feature extraction, feature machines, non- limited and unbalanced datasets, dataset preparation, processes, mitigating the gen- error, generalization metrics for datasets, stationary artificial explainable intelligence. error, eralization Speaker: US at Dallas, Texas of The University Makris, Yiorgos of applica- overview and comprehensive Part a concise II will provide and manufacturing test.tions of machine learning in semiconductor how explain we will definewill we problem, the application, each For and we will show a case study to machine learning can come the rescue, analog/ test alternate include: for Applications industrial datasets. on yield learning, diagnosis, fault test compaction, ICs, mixed-signal/RF wafer-level test, adaptive outlier detection, tuning, post-manufacturing analog test modeling, correlation spatiotemporal & lot-level spatial hotspot detection, on-chip neuromorphic testers, estimation, metrics verification pre-silicon inking, die trimming, diagnosis, fault board-level yield migration, fab-to-fab in estimation yield validation, post-silicon and to the next. one design generation from when transitioning estimation Overview of Machine Learning Applications in of Machine Learning Applications Overview and Test Manufacturing Semiconductor Introduction and Motivation Introduction Speakers: FR LIP6, CNRS, Sorbonne Université, Stratigopoulos, Haralampos-G. US at Dallas, Texas of The University Makris, Yiorgos and the benefits of using the challenges, the need, Part I will motivate on actualutility discuss its and will learning machine yield- and test- of an abstract representation will give We problems. industrial related will also illus- We problems that can be tackled using machine learning. - manufac semiconductor the link between machine learning and trate turing and test. Room 4 1400 Room Organisers: FR LIP6, CNRS, Sorbonne Université, Stratigopoulos, Haralampos-G. US at Dallas, Texas of University The Makris, Yiorgos is data a wealth of circuit, of an integrated Throughout the lifetime from Ranging operation. its robust ensuring and reliable for collected and from monitors, characterization to process design-time simulations on custom- specification tests to diagnostic measurements high-volume Mining this is invaluable. in inherent this data the information er returns, interest has seen intense using machine learning methods information This elu- to seeks tutorial years. recent in breakthroughs numerous and manufacturing in semiconductor the utility of machine learning cidate machine learning will be introduced, from concepts and test. Relevant using industrial and showcased practice, with current agglomerated will also be given. practitioners for Recommendations data. Applications of Machine Learning in in Learning of Machine Applications and Test Manufacturing Semiconductor 1530 – 1600 1420 – 1530 1400 – 1420 30 1600 – 1645 M01 MONDAY, 25 MARCH 2019 MONDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1645 –1745 MONDAY, 2019 MARCH 25 1800 –2100 1745 –1800 hosted byEDAA, ACM SIGDA, CEDA andIEEE Welcome Reception &PhDForum systems. integration ofmachinelearninghardware inautonomous vehicles and the to tolerancethanks gain interestwill alsodiscussfaultthat methods hardware isany different from testing any regular integrated circuit. We In particular,testing machinelearning extentto what wewilldiscuss the "inverse"discuss problemtesting machinelearninghardware. of andsemiconductor manufacturing problems. test ficiently We willalso forwhether deeplearningmethodsopennewopportunities solvingef Part V willdiscussemerging applications. Inparticular, wewilldiscuss Haralampos-G. Stratigopoulos, SorbonneUniversité, CNRS, LIP6, FR Speaker: Emerging Applications vide several industrialdata. casesstudiesonactual choice oflearningmodels,trainingthe procedures, etc., and wewillpro- Fortraining eachapplicationthe collection of data, wewilldiscuss the mixed-signal/RF ICs, adaptivetest, yieldlearning, detection. andhotspot the following four mainstream applications: fortest alternate analog/ learning insemiconductortest. manufacturing and We willdelve into IVwilldescribeinmore applicationsPart detailselected ofmachine Yiorgos Makris, The University of Texas Dallas, at US Haralampos-G. Stratigopoulos, SorbonneUniversité, CNRS, LIP6, FR Speakers: Selected Applications inDepth 31 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com 1800 – Welcome Reception & PhD Forum Reception Welcome and IEEE CEDA SIGDA, ACM hosted by EDAA, Paderborn Center for Parallel Computing, DE Computing, Parallel for Center Paderborn Kenter, Tobias Chair: SDAccel with Xilinx Design example OpenCL SDK for FPGA with Intel Design example what do we want the compile Discussion of levels: the used abstraction explicitly? what do we want to express to infer, design complex OpenCL FPGA success stories, libraries examples, DE Computing, Parallel for Center Paderborn Kenter, Tobias Speaker: Key differences between Intel FPGA and Xilinx tools: and Xilinx tools: FPGA Intel differences between Key memory ports local pipelining, loop outer and replication DE Computing, Parallel for Center Paderborn Kenter, Tobias Speaker: Coffee Break for Tutorials multiplication matrix efficient yet Simple, OpenCL designs with OpenCL and FPGA design: OpenCL and FPGA design: common constructs and patterns DE Computing, Parallel for Center Paderborn Kenter, Tobias Speaker: - reports and comple generated models based on analysis of formance design We will present data. and profiling with measurements mented both tools and portabilitypatterns that for work well thus can promote Based butlight shed also on differences. designs, of OpenCLFPGA based of in pipelining difference the central we will illustrate on examples, replication on local memory ports, which has implications nested loops, of design space exploration. and predictability Room 9 1400 Room DE University, Paderborn Kenter, Tobias Organiser: computing in the reconfigurable new results of fraction An increasing synthesis tools. Among obtained with the help of high level domain are and Intel popular OpenCLthe tools are SDAccel the more based Xilinx - OpenCL.upon building for program SDK the same Since are they FPGA portability be- would hope for one language, ming model and source vast majority the designs. However, OpenCL based FPGA tween different tool and FPGA one vendor for is only optimized of published research focus both vendors activities, and In training their dissemination family. respective with tools and patterns design their effective on promoting hardware. their respective for for training and provide we want to broaden that scope In this tutorial, the workshop research, both of PostDoc tool chains. During two years into these and insights tools. experience has gained extensive organizer with per examples by step optimization step This tutorial will contain OpenCL design flows for Intel and Xilinx Xilinx and for Intel flows design OpenCL strategies, optimization FPGAs – common vendor-specific and design patterns differences • • • 1800 – 2100 1710 – 1800 1530 – 1600 1440 – 1530 1400 – 1440 32 1600 – 1710 M02 MONDAY, 25 MARCH 2019 MONDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI 1800 –2100 www.date-conference.com M03 MONDAY, 2019 MARCH 25 • • • • Application-Level Computing Techniques: FromComponent- to A Comprehensive Analysis ofApproximate Approximate Computing for Safety-Critical Applications Methods and tools forMethods and approximate computing hosted byEDAA, ACM SIGDA, CEDA andIEEE Welcome Reception &PhDForum Techniques for approximate computing General introduction Motivations tolerance mechanisms. particular, andlow-costtutorial willshowhowdesignefficient fault the the contextcan beexploited in ofsafety-critical applications. More in tutorial isdevotedthe to present of howAxC paradigm part The last works for designspaceexploration willbedetailed. fixed-point andfloating-point is considered. Finally, thedifferent frame- described. the complexThen problem ofword-length optimization for to analyzeproaches approximation effects onapplication qualitywillbe efficientlyexploit approximate ofall, First computing. thedifferent ap to tools tutorial isdedicatedto methodsand the of The second part memoïzation, andcomputation approximation willbedetailed. the processing. of The concepts ofloop perforation,termination, early tions areto reduce used complexity byskippingorapproximating parts the different paradigms. computationAt level, transforma algorithmic - point) andalso,to derive someconclusionstry bycomparing wewill computations when using customized arithmetic (fixed-point, floating- terms ofenergy-efficiency,sults in area, performance versusaccuracy of data.data or less-up-to-date We will present some compile-time re- arithmetic, byusingefficient can becarried-out precision scaling, less and voltage over-scaling willbedetailed.At data level, approximation At hardware level, approximation functional through operators inexact threetechniques accordingto levels: hardware, data andcomputation. More indetail, present wewillfirst existing approximate computing follow a bottom-up approach: from component,to application-level. up tutorial introducesThis basicandadvancedtopics onAxC. Weto intend plementing algorithms, inexact showinganinherent resiliencyto errors. imprecise computation for bothsoftware andhardware components im- efficiency.It has been demonstrated the literature in the effectiveness of to selectivelyAxC relaxthe specifications, aims trading accuracy off for computation and, consequently, requiring ofresources, ahighamount cient, faster, and less complex. Intuitively, instead of exact performing to investigatelished howcomputing systemscanbemore effi- energy A newdesignparadigm, Approximate Computing (AxC), hasbeenestab Olivier Sentieys, FR INRIA, Bosio,Alberto INL, FR RennesDaniel Menard,INSA Organisers: Room 51400 THE OUTLINE OF OUTLINE THE PRESENTATIONTHE IS AS FOLLOWS • • • • • • • • • Results toleranttechniques exploiting fault lowcost Implement AxC Approximate Computing VS Reliability Design spaceexplorationGeneral introduction Motivations Word-length optimization for fixed-point andfloating-point Analysis ofapproximation on application effect quality Computation level approximation Hardware level approximation Data level approximation – 1800 / IETR, FR 33 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com 1800 – THE TUTORIAL HAS THE FOLLOWING OBJECTIVES: THE FOLLOWING HAS TUTORIAL THE proaches are promising alternatives for - the classical crypto-based authenti for alternatives promising are proaches in the embedded and IoT devices the smart for protocols world. cation University of Southampton, GB of Southampton, Basel Halak, University Chair: for IoT Authentication Lightweight based Hardware Application US Park, College of Maryland, Gang Qu, University Speaker: - re Things (IoT) applications, embedded systems and In many the Internet of limited that power are cannot battery and they memory, CPU, like sources the security solutions. Meanwhile, security the classic cryptographic afford is not as high as securethe on traditional these systems/devices requirement demonstrate to example an as authentication use we In systems. this talk, can help characteristics to build lightweight physical and how hardware we specifically, More protocols. such as authentication security primitives the emerging will report work our recent CMOS, that utilizes the traditional and user for technique scaling (VoS) over and voltage RRAM technologies, ap practical These detection. spoofing GPS as well as authentication device Chair Introduction Chair Room 6 1400 Room GB of Southampton, Basel Halak, University Organiser and Chair: GB Belfast, O'Neill, Queen's University Maire Co-Chair: The security of the internet of - is one of things challenges fac the major This technology has led to bil- alike. and researcher ing both engineers Reports in our lives. entrenched lions of low power devices to become and de- deployed, currently are IoT devices 15 billion thatstate currently This massive ployment 2020. 50 billion by is expected the year reach to Various has led concerns. deployment of devices to significant security of with a swarm shown weaknesses in IoT infrastructure, have attacks attacking devices rogue darkness, a city in leaving light bulbs potentially in critical infrastructure. attacks to infrastructure - universi international four leading effort a combined of This tutorial, aims to disseminate the IoT security, ties in hardware-based the field of DATE techniques in and state-of-the-art this field results latest research community. researchers experienced both for The beneficial highly be will tutorial delving into this considering topic.and students describe the security challenges of internet of things devices To IoT devices techniques for the basics of attestation explain To techniques authentications lightweight the principles of explain To Unclonable Functions of Physically the design principles explain To of designing hardware- in the area problems Describe open research To IoT applications. security schemes for Hardware-based Security Solutions for the for Solutions Security Hardware-based of Things Internet • • • • • 1405 – 1445 1400 – 1405 34 M04 MONDAY, 25 MARCH 2019 MONDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1600 –1645 1445 –1530 MONDAY, 2019 MARCH 25 1800 –2100 1645 –1730 1530 –1600 hosted byEDAA, ACM SIGDA, CEDA andIEEE Welcome Reception &PhDForum their vulnerabilityto machine-learningattacks.cluding circuitschallenges indesigningchallenge-response onFPGAs, PUF in- designs,pact highuniquenessandgoodreliability.the willalsodiscuss It identification generator (ID) circuits specifically forFPGAs that offer com- talk willfocusto designefficient, onhow PUF lightweight andscalable on FPGAs,their vulnerabilityto machine-learningattacks. including This circuitsthe challengesindesigningchallenge-response also discuss PUF offerthat designs, compact high uniqueness and good reliability. will It identificationscalable PUF generator (ID) circuits specifically for FPGAs sources. talk willfocusto designefficient,This onhow lightweight and uniquenessandinsufficient reliability, and consume excessive FPGA re- FPGAs haveto date. beenproposed However, on FPGAthey often offer the manufacturing process. implementations Many PUF for ASICsand the inherent siliconon variation betweendevices whichoccursduring the extractionbles ofadigital identifier from electronic devices, based isasecurityprimitive whichena- A Physical(PUF) unclonablefunction Speaker: Maire O'Neill,Queen'sUniversity Belfast, GB Practical usingFPGA DesignGuidelinesPUF lessons anddirections forthe future. ical cloningattacks. tutorial concludes oflearned The withasummary tacks usingmachine-learningalgorithms, sidechannelattacks andphys- their potential countermeasures, including mathematical modelling at and technology the outstandingsecuritychallengesfacing outlines PUF protocols, tutorial secure andlowcost this sensors. of The finalpart includes; secure cryptographic keys generation/storage, authentication facingtechnologies, IoT this context, in wegive specific that examples defenseto build robust threats emerging security mechanisms against it to use andhow technology explainsthe PUF whysecond weneed part their mainevaluationphysically and unclonablefunctions metrics. The tutorial provides acomprehensive overviewthe designprinciplesof on tive suitablefor resource-constrained this of IoTdevices. part The first allows buildinglightweighttechnology cryptographicthis chip; primi- ing process variationsto generate auniquesignature for eachsilicon Physicallythe intrinsic UnclonableFunctions manufactur (PUFs) exploit Speaker: BaselHalak,University ofSouthampton, GB Unclonable Functions IoTDevicesSecuring usingPhysically Coffee BreakforTutorials current andpropose mechanismsexhibit newresearch directions. worked devices. Lastly,the limitations wediscuss andpotential issues and reliabilitytheir functionality guaranteeson they provide to net present ofattestation asummary them based approaches byclassifying tutorial,this In the basicsofdevice wesummarize attestation. Wethen andCyber-Physical(IoT) System (CPS). of embeddeddevices, of those widelyusedinInternet especially Things Device attestationthe operational is a promisingto solution demands devices hasalsorisen. a consequence,to ensure aneed secure andreliable operationthese of In recent years we have seen a rise in popularity of networked devices. As Speaker:Jin, Yier The University ofCentral Florida, US Systems Device Attestation forIoTandResources-Constrained 35 - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com 1800 – hosted by EDAA, ACM SIGDA, and IEEE CEDA SIGDA, ACM hosted by EDAA, ple with. & PhD Forum Reception Welcome Automotive Security: Security: Automotive from Ad-hoc to Standards Moving Ad-hoc to Standards is a from Moving Security: Automotive D: PART evolving a rapidly the latestto share knowhow from module crafted The module startsdomain – with a detailed look security. automotive - “opportuni threat of an automobile and surface atthe various attack mechanisms necessary HW/SW the foundational we survey Then, ties”. for standards emerging and also review electronics automotive to secure the we examine Finally, development. semiconductor automotive secure that designers need of security and safety to grap curious relationship Coffee Break for Tutorials Safety II Functional Automotive II Functional of a is Safety two partthe second Automotive mod - C: PART This developer. a semiconductor for functional safety ule on automotive various techniques used in- that the the quanti are module firstcovers We analysis. safety qualitative analysis phase that follows safety tative from the eyes today ecosystem EDA of safety the readiness then survey functional with emerging conclude We developer. of a semiconductor changes in the 2nd edition the key and review topics of interest safety of ISO26262. Automotive Functional Safety I Functional Automotive I is the first Functional Safety of a Automotive two part module B: PART Using developer. a semiconductor for functional safety on automotive chip compliant in leading functional safety experience the presenters' various aspects examines the module and certification, development its parent ISO 26262 and standard functionalof safety the automotive start of with We the foundations IEC61508. standard industrial safety - com safety terminologyand metrics, key including functionalsafety and system level component HW/SW, for process pliant development analysis. safety qualitative and mechanisms, safety Introduction Introduction starts inof the trends with a brief overview top level A: PART design industries driving various and semiconductor that are automotive and security. of safety including concerns the emerging requirements, Room 8 1400 Room IN Instruments, Texas Ravi, Srivaths Organiser: Speakers: IN Instruments, Texas Pillai, Viswanathan Prasanth IN Instruments, Texas Ravi, Srivaths - revolu by a has been spurred consumption semiconductor The increasing of electronics The integration industry. tion witnessed in the automotive and by infotainment automobile driven conventional and networking into autono- of EV/HEV, by megatrends back is accelerated years a few ADAS - “Au sometimes as termed These trends, mobility. mous driving and shared being into the semiconductors requirements various drive 2.0”, tomotive - para becoming are and security requirements safety Of sourced. these, the authors' This tutorial leverages mount due to their impact and liability. and security as a part- in driving safety devel of semiconductor experiences - foun into system requirements down complex By breaking opment cycles. an the is intended tutorial provide to at level, ones semiconductor dational of developer. accessible semiconductor the subject any treatment for Safety and Security in Automotive 2.0 Era Automotive in and Security Safety 1800 – 2100 1650 – 1800 1530 – 1600 1420 – 1530 1400 – 1420 36 1600 – 1650 M05 MONDAY, 25 MARCH 2019 MONDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com M07 MONDAY, 2019 MARCH 25 1800 –2100 to IBM QandQiskit to IBM Quantum Computing, intro hosted byEDAA, ACM SIGDA, CEDA andIEEE Welcome Reception &PhDForum Feel freeto lookat: https://qiskit.org for more information. several quantum programs Qandsimulator systems. onIBM Weto run andshowhow willgive anhands-onintroductionto Qiskit withquantumment computing. morethan 90,000peoplehave offerings tolearnand usedIBM's experi- We’ll QExperience continue IBM wherethe no-charge bydescribing algorithms. demonstrable advantage andsignificant over classical computers and ing quantum advantage: wherethe point quantum computing shows toward andshowwheretimeline we aretechnology the reachthe in - of beapplied. might types ofproblemsto whichit We'llthe basics describe the motivationtalk we'lldiscuss this forIn quantum computingthe and are nowandperhaps always willbeintractable for "classical" computers. of computingthe possibility of solving some problemsthat holds open on real hardware Q.throughthe cloud IBM via This radically newkind Though earlyinitsdevelopment, quantum computing isnowavailable Perricone,Robert IBM, US SheshaShayee Raghunathan, IBM, IN Leon Stok,IBM, US Speakers: Organiser: Leon Stok,IBM, US Room 71400 – 1800 37

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com 38

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI MAIN CONFERENCE www.date-conference.com 2019 MARCH –28 26 39

FRI THU WED TUE MON March 25 – 29 2019, Florence, Italy DATE19 See Page 6 " See Page 7 " See Page www.date-conference.com 1030 – in the Exhibition Area Coffee Break in the Exhibition IEEE Fellow Award IEEE Fellow Service Award IEEE CEDA Award Contribution IEEE Outstanding CS TTTC Addresses Keynote EDAA Outstanding Dissertations Award 2018 Award Dissertations Outstanding EDAA Award Fellow DATE Welcome Addresses Welcome of awards Presentation Award Achievement 2019 EDAA Assisted and Automated Driving Assisted and Automated DE Porsche, Bortolazzi, Jürgen lower floor Spadolini, Padiglione da Basso, at Fortezza (Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE) Erlangen-Nürnberg, Friedrich-Alexander-Universität Teich, (Jürgen and Secure Deterministic Safe, with Working to Edge from Cloud Intelligence DE Labs Europe, Astrid Elbe, Intel (Jan Madsen, Technical University of Denmark, DK of Denmark, University Technical (Jan Madsen, DE) Frankfurt, Goethe-University Jano Gebelein, US Synopsys, Domic, (Antun IT) of Pisa, University Luca Fanucci, DK) of Denmark, University Technical (Jan Madsen, (Jacob Abraham, University of Texas at Austin, US) at Austin, Texas of University Abraham, (Jacob Jürgen Teich Jürgen Chair 2019 General DATE Fummi Franco Chair 2019 Programme DATE Auditorium 0830 Auditorium DE Erlangen-Nürnberg, Friedrich-Alexander-Universität Teich, Jürgen Chair: IT Verona, di Università Fummi, Franco Co-Chair: Opening Session: Plenary, Awards Ceremony Ceremony Awards Plenary, Session: Opening Addresses & Keynote 40 1030

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0845 0830 1.1 TECHNICAL PROGRAMME

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 2.2 1300 2.1 TUESDAY, 2019 MARCH 26

Physical Attacks Executive Panel: LifeAfterCMOS channel attackstemperature andspying onIoTdevices' viaDRAM. the reconfigurabilitysession include ofFPGAs to defend side- against together withitscorresponding countermeasure.this topics in Other In addition, apractical attack isdescribed onavery popularplatform faultpersistent analysis, electromagnetic fault injection, andglitching. techniques suchas This sessioncovers fault analysis statethe art of Co-Chair: ElifKavun, University ofSheffield, GB Chair: LejlaBatina, Radboud University, NL Room 21130 Buvna Ayyagari-Sangamalli, AMAT, US Mark Heiligman,IARPA, US Synopsys,Antun Domic, US Alessandro Curioni,IBM, CH future,of ourindustry's to gobeyond and the CMOS box. thinkers greatestto industry's explore these questions, to color an image This panel, moderated byDanHutcheson,the together someof brings They alreadytoday'sthe promise ofsolving bring intractable problems. tum computers (QC) —may dramaticallythe landscapeofHPC. change classes ofcomputersthe laws basedon ofquantum physics —orquan- ing 100-1,000Xlesspower.term,the long In today's foundations for new anorderby delivering ofmagnitudemore least at whileus- performance term, to reinvigorate promise SCE short Josephsonjunction-based HPC where researchers have advances madesignificant in the recent years. In andarchitectureselectronics (SCE) basedonquantum computing (QC), Many are already doing so with circuits based on super-conducting the CMOS box. thinking outside them means Meeting tectures alone. devices, channelandinterconnect materials, orintegrated archi circuit - electronics andare byevolutionary unlikelyto bemet improvements in ogy, andphysics applications greatly exceedthe capabilitiesofcurrent intelligencements (AI), ofartificial biochemistry, medicine, pharmacol- Moore'sthe same cost." law: Yet, "at the computing require and memory - —wehavelessly bygoingvertical alreadythe second infringed clauseof tors involume? Andeventhe progress if inMoore's lawcontinues relent transisto design and manufacturethose sible - trillions of an IC made of vacancy resultingtotal available in ahandful bepos- carriers — willit silicon atom source/drain separated byachannelofsinglesilicon atom ofasingle that to be taxy —wheretakethe cross ofaFET we section mately 0.3nanometers.Eventhe useofatomic ifweenvision layer epi- continue forever:the silicon atom diameteris2.92Ångstroms, approxi - under development, markinganother100Ximprovement. This cannot IC. Today, 7-nanometerisinearlymanufacturing, and5-nanometer is the IC brokethe 1-micron barrier — a100X improvement over Noyce's the monolithicintegrated of years Roughlythe birth later, circuit. thirty Sixty years ago, Noyce Robert filed U.S. Patent 2,981,877, whichmarked Chair: G. DanHutcheson, VLSI Research, US Jamil Kawa, Synopsys, US Marco Casale-Rossi, Synopsys, IT Organisers: Room 11130 Lunch BreakinArea Panelists: – – 1300 1300 41 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - 1 , André André , 2 3 Temasek Lab Temasek 2 and Saibal Muk 1 Zhejiang University, CN University, Zhejiang and Kui Ren and Kui 1 3 3 www.date-conference.com and Krishnendu Chakrabarty , Nikhil Chawla , 2 2 Intel Corporation, US Corporation, Intel , Fan Zhang Fan , 2 2 and Jakub Szefer and Jakub 2 , Ramesh Karri Ramesh , 1 , Nikolaos Athanasios Anagnostopoulos Athanasios Nikolaos , , Monodeep Kar , 1 NYU, US 1 2 Technische Universität Darmstadt, DE Darmstadt, Universität Technische , Shivam Bhasin Shivam , 2 1 1300 – 1 , Stefan Katzenbeisser Stefan , 2 Yale University, US; US; University, Yale US; Technology, Institute of Georgia Duke University, US; US; University, Duke Nanyang Technological University, Zhejiang University, CN; Zhejiang University, University, Technological Nanyang Dual-gate self-aligned a-InGaZnO transistor model for self-aligned a-InGaZnO transistor Dual-gate applications flexible circuit Spying on Temperature using DRAM Temperature on Spying Attacks based Fault Glitch Supply Power Mitigating Circuit Modulation Clock All-Digital Fast with IP1-4 IP1-3, IP1-2, IP1-1, Lunch Break in Lunch Area Multi-Tenant FPGA-based Reconfigurable Systems: Systems: Reconfigurable FPGA-based Multi-Tenant and Defenses Attacks One Fault is All it Needs: Breaking Higher-Order Higher-Order Breaking Needs: it is All One Fault Analysis Fault Persistent Masking with hopadhyay oratories, Nanyang Technological University, SG; SG; University, Technological Nanyang oratories, 1 1 1 Speaker: Kris Myny, imec, BE imec, Kris Myny, Speaker: Wim Dehaene and Jan Genoe, Hikmet Çeliker, Florian De Roose, Authors: BE imec, Kris Myny, Room 3 1130 Room Organisers: US Labs, Jim Huang, Hewlett Packard DE (KIT), Technology Institute of Karlsruhe Mehdi Tahoori, US Synopsys, Jamil Kawa, Chair: field which can be growing and fast is an emerging electronics Flexible domains such as application demanding and emerging used in many several are There Things (IoT). and Internet of smart sensors, wearables, which can be used to design and and paradigms processes technologies, computing and electronics traditional Unlike circuits. flexible fabricate flexible by performance characteristics, domain which is mostly driven are they (as costs with low fabrication mainly associated are electronics they (as and low energy consumption market) in consumer used even While the main advances systems). be used in energy-harvested could the de- aspects, and process fabrication focused on in this field is mainly The exposure. had limited sign and in particular flow, design automation purpose of this special session is to bring of design au- to the attention in flexible of field the advances of some on key the community tomation which aspects, as well as some of electronics the design (automation) - com automation by design some furthercan hopefully inspire attention field. munity to this fast-growing Speaker: Nikhil Chawla, Georgia Institute of Technology, US Technology, of Institute Georgia Nikhil Chawla, Speaker: Arvind Singh Authors: Speaker: Krishnendu Chakrabarty, Duke University, US University, Duke Krishnendu Chakrabarty, Speaker: Elnaggar Rana Authors: DE Darmstadt, TU Anagnostopoulos, Athanasios Nikolaos Speaker: Wenjie Xiong Authors: Speaker: Shivam Bhasin, Nanyang Technological University, SG University, Technological Nanyang Bhasin, Shivam Speaker: Jingyu Pan Authors: 1 Schaller Special Session: Circuit design and design Circuit Special Session: electronics for flexible automation

42 1130 2.3 IPs 1245 1300 1230 1200 1130 TUESDAY, 26 MARCH 2019 TUESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1230 1200 1130 2.4 1300 1236 1214 1152 TUESDAY, 2019 MARCH 26 Modeling andRuntime Management Temperature andVariability Driven Technology), DE Karlsruhe at Applied Sciences/InstituteofNanotechnology Instituteof 1 University, US Authors: Reid, Scott Antonio Montoya andKwabena Boahen, Stanford Speaker: Reid, Scott Stanford University, US Pan, University of Texas, Austin, US Authors: Wei Ye, MohamedBaker Alawieh, MengLi, Yibo LinandDavid Z. Speaker: David Z.Pan, University of Texas, Austin, US Authors: SheriffSadiqbatcha Speaker: Sheldon Tan, University ofCalifornia, Riverside, US system design, run-timeadaptivityarethese papers. discussedin tational models. Considerations suchaslithographic variations, cooling ranging from manufacturing andhardware,the way all to compu up - addressthese challengesusingnovelthat techniques papers two IP and swered duringsystemdesign. This sessionconsists offour regular papers temperatureing variability duringrun-timeare keyto bean- questions prediction andoptimization,Thermal modelling, spot hot andmanag - Co-Chair: Ronald Dreslinski Jr, University ofMichigan, US Chair: Marco Domenico Santambrogio, Polytechnic University ofMilan, IT Room 41130 Authors: M.Fattori Speaker: EugenioCantatore, Eindhoven University of Technology, NL Authors: Tsung-Ching JimHuang Speaker: Tsung-Ching JimHuang, Hewlett-Packard Labs, US Authors: Farhan Rasheed nology, DE Karlsruhe at Sciences /InstituteofNanotechnology Instituteof Tech Speaker: JasminAghassi-Hagmann, Offenburg University ofApplied 1 Stanford University, US; celli Kwang-Ting Cheng 1 1 Engineering, Georgia Instituteof Technology, US; LITEN, FR neering, University ofCalifornia, US; Joerg Henkel Sivapurapu Beigl Michael Neuromorphic Architecture PinT: Polynomial inTemperature Decode Weights ina Lithography HotspotDetection Litho-GPA: Gaussian Process Assurance for Infrared Thermal Imaging Thermal ModelingforMulti-Core ProcessorsThrough Hot SpotIdentification and System Parameterized Lunch BreakinArea Electronics Circuit DesignandAutomation forPrinted Flexible Hybrid Electronics Process DesignKit andDesignAutomation for Inorganic Printed Electronics Predictive ModelingandDesignAutomation of University ofCalifornia, Riverside, US; Hewlett-Packard Labs, US; Karlsruhe Instituteof Technology (KIT), DE; Eindhoven University of Technology, NL; 2 andMicaelCharbonneau 4 , Madhavan Swaminathan 2 1 andSheldon Tan , JasminAghassi-Hagmann – 1300 3 1 andRaymond Beausoleil , J.A. Fijn 3 Department of Electrical and Computer ofElectrical Engi- Department 1 , MichaelHefenbrock 2 1 Department ofChemicalEngineering, Department , Hu L. 1 , Hengyang Zhao 3 1 1 ,Lei Ting 1 , EugenioCantatore 4 2 School of Electrical andComputerSchool ofElectrical Karlsruhe Instituteof Tech 4 , SichengLi 2 2 University ofBrescia, IT; andMehdiB. Tahoori 2 , Leilai Shao 2 Offenburg University of 1 1 1 , HussamAmrouch , Rajendra Bishnoi 1 , ZhenanBao 3 1 , Sridhar ,Fabrizion Torri- nology, DE 1 2 , 1 3 2 , CEA- , 43

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 , 1 1 Seam- 3 , Hassan , 1 , Mohammed , , Javier Martin- Javier , 3 1 , Fabio Passos Fabio , 1 and Francisco Vidal Vidal and Francisco 2 , Turk Shadi , Universitat Autonoma de Autonoma Universitat 2 2 www.date-conference.com , Elisenda Roca , 1 , Roselyne Chotin-Avot Roselyne , New York University, US; US; University, York New 1 2 and Haralampos-G. Stratigopoulos and Haralampos-G. 4 , Montserrat Nafria Montserrat , 2 , Pablo Saraza-Canflanca Pablo , 1 , Yasin Muhammad , 1 , Rafael Castro-Lopez Rafael , 1 1300 New York University Abu Dhabi, AE Abu Dhabi, University York New 4 – , Marie-Minerve Louërat Marie-Minerve , 4 , Ozgur Sinanoglu , 1 1 , Rosana Rodriguez Rosana , 2 Instituto de Microelectrónica de Sevilla, ES; ES; Sevilla, de Instituto de Microelectrónica FR; LIP6, CNRS, Sorbonne Université, Generation of Lifetime-Aware Pareto-Optimal Fronts Fronts Pareto-Optimal of Lifetime-Aware Generation Simulator Reliability Using a Stochastic via Logic Circuits Securing Mixed-Signal MixLock: Locking IP1-7 Lunch Break in Lunch Area IR-aware Power Net Routing for Multi-Voltage Mixed- for Multi-Voltage Net Routing Power IR-aware Design Signal Enhancing Two-Phase Cooling Efficiency through Cooling Enhancing Two-Phase for Power-Hungry Mapping Workload Thermal-Aware Servers IP1-6 IP1-5, in Lunch Area Lunch Break Aboushady less Waves, FR; less Waves, 1 Speaker: Julian Leonhard, Sorbonne Université, CNRS, LIP6, FR LIP6, CNRS, Sorbonne Université, Julian Leonhard, Speaker: Julian Leonhard Authors: Speaker: Mark Po-Hung Lin, National Chung Cheng University, TG Chung Cheng University, National Lin, Mark Po-Hung Speaker: Guan-Hong Liou and Mark Po-Hung Su, Yen-Yu Wang, Shuo-Hui Authors: TW Chung Cheng University, National Lin, Authors: Toro-Frias Antonio Room 5 1130 Room BE Leuven, Gielen, KU Georges Chair: FR TIMA, Manuel Barragan, Co-Chair: techniques analog/mixed- The session presents to analyse and optimize IR-aware addressing security, and reliability high circuits signal towards as well as securing mixed-signal optimization lifetime-aware routing, via logic locking.circuits Speaker: Arman Iranfar, EPFL, CH EPFL, Arman Iranfar, Speaker: Atienza, and David Marina Zapater Ali Pahlevan, Arman Iranfar, Authors: CH EPFL, 1 Barcelona, ES Barcelona, Fernandez Thari Nabeel Solutions for reliability and security of security and for reliability Solutions circuits mixed-signal Martinez Pablo Martin-Lloret Pablo

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 2.7 1300 IPs 1245 1230 1200 1130 2.6 TUESDAY, 2019 MARCH 26

neural networks Analysis andoptimization techniquesfor quantum andapproximate computing Computational in andresource-efficiency performance and energy consumption according to the target application.target consumption andenergy performance the accordingto the neural network behavior onedge devicestheir to optimize in order This session presentsthree papers with new approachesto characterize Co-Chair: MohamedSabry, NTU, SG Chair: SaiPudukot, Georg MasonUniversity, US Room 71130 versity, CN Huang, HaiZhao, Xiaoyao LiangandLiJiang, ShanghaiJiao Tong Uni- Authors: Zhuoran Song, Ru Wang, Ru, Dongyu ZhenghaoPeng, Hongru Speaker: LiJiang, ShanghaiJiao Tong University, CN Twan BastenandHailongJiao, Eindhoven University of Technology, NL Authors: Paul Detterer, CumhurErdin, MajidNabi, JosePineda deGyvez, Speaker: Paul Detterer, Eindhoven University of Technology, NL versity of Technology, CZ Authors: Zdenek Vasicek, Vojtech Mrazek andLukas Sekanina, BrnoUni- Speaker: Lukas Sekanina, BrnoUniversity of Technology, CZ Linz, AT Authors: AlwinZulehner andRobert Wille, JohannesKepler University Speaker: AlwinZulehner, JohannesKepler University Linz, AT the fourth paper. training acceleration ofneural networks runningonGPUisproposed in works. Finally, approximate anefficient technique random for dropout application for approximatethe area circuits in ofwireless sensornet application.target observablethe in third paperpresentsThe anew approximationcircuit methodcapable of exploiting data distributions ing systems. The secondthis sessiondealswithanautomated paperof cated asanapproachto buildmore enabling resource-efficient comput nificantly accelerate thisprocess. Approximate computing isoften advo- utilization papershows of decision diagrams how asmart first cansig- tion ofquantum computations isvery computationally expensive. The the contextciency in ofquantum andapproximate Simula- computing. technologies. emerging This sessionaddresses various ofeffi- aspects Achieving computational and resource-efficiency is often promised by Co-Chair: Lukas Sekanina, BrnoUniversity of Technology, CZ Trefzer,Chair:Martin University of York, GB Room 61130 IP1-8, IP1-9, IP1-10 Lunch BreakinArea acceleration inGPGPU Approximate training RandomDropout forDNN Computation ofaSensorNetwork Transceiver Trading Digital Accuracy forPower inanRSSI Data Distribution Automated Circuit Approximation Method Driven by Computations Potential inDD-basedSimulation ofQuantum Matrix-Vector vs. Matrix-Matrix Multiplication: – – 1300 1300 45 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - See Page 8 " See Page and Tajana and Tajana 3 , Wang Pi Wang , 2 www.date-conference.com , Wu Fan , University of California River of California University 1 2 1300 – , John Messerly , 1 1420 – Peking University, CN University, Peking 3 1 University of California San Diego, US; US; San Diego, of California University Lunch Break in Lunch Area and Engineering Humanism da Vinci, Leonardo and Milan Florence between Machine Learning at the Edge for embedded and low the Edge for embedded and low Machine Learning at Neural Movidius Intel the exploiting platforms: power Stick Computing of the Semiconductor The ESD Alliance - At the Center Universe Machine Learning is Changing the Game for the Game for Machine Learning is Changing and will soon help and Characterization Variability Verification and Digital Analog A Binary Learning Framework for Hyperdimensional for Hyperdimensional Learning Framework A Binary Computing IP1-13 IP1-12, IP1-11, Lunch Break in Lunch Area Data Locality Optimization of Depthwise Separable Separable of Depthwise Optimization Locality Data for CNN Accelerators Inference Convolutions Low-Complexity Dynamic Channel Scaling of Noise- Scaling Channel Dynamic Low-Complexity Edge Devices CNNResilient for Intelligent Rosing Room 1 1350 Room IT Synopsys, Casale-Rossi, Marco Chair: CH De Micheli, EPFL, Giovanni Co-Chair: - Tec e della Museo Nazionale della Scienza Claudio Giorgione, Speaker: IT Vinci, da nologia Leonardo Speaker: Gionata Benelli, IngeniArs, IT IngeniArs, Benelli, Gionata Speaker: US ESDA, Cohen, Paul Speaker: edacentrum, DE Haase, edacentrum, Jürgen Organiser: Alliance will present Design In their this session System the Electronic a Siemens Business will discuss Mentor, and results. newest initiatives - designing and pro for of Machine Learning application for approaches scenarios for IngeniArs will analyze products. ducing microelectronics Machine executing for smartrealizing by using accelerators edge devices algorithms. and Deep Learning Learning US a Siemens Business, Mentor, Amit Gupta, Speaker: 1130 Theatre Exhibition Speaker: Hao-Ning Wu, National Tsing Hua University, TW Hua University, Tsing National Wu, Hao-Ning Speaker: Hua Uni- Tsing National Huang, and Chih-Tsun Wu Hao-Ning Authors: TW versity, US San Diego, of California, University Mohsen Imani, Speaker: Mohsen Imani Authors: Speaker: Younghoon Byun, Pohang University of Science and Technology Technology of Science and University Pohang Byun, Younghoon Speaker: KR (POSTECH), and Sunggu Lee Kim, Jeonghun Minho Ha, Byun, Younghoon Authors: KR (POSTECH), Technology and of Science University Pohang Lee, Youngjoo side, US; US; side, 1 LUNCHTIME KEYNOTE SESSION KEYNOTE LUNCHTIME How Electronic Systems can benefit from can benefit Systems Electronic How Machine Learning and from ESD Alliance

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1600 3.1 TUESDAY, 2019 MARCH 26 the NextBigWave Executive Panel: Semiconductor IP, Surfing Greg Yeric, ARM, US Andrei Vladimirescu, Berkeley, US Joachim Kunkel, Synopsys, US K. Arteris, CharlesJanac, US Alessandro Cremonesi, STMicroelectronics, IT for decade. the next ofsemiconductor IP opportunities veteranindustry Raul Camposano, willexplorethe the challengesand design andmanufacturing of VLSI systems. This panel, moderated byEDA of collaborationto rapidly achievethe maturity levels required forthe electronics andsilicon photonics, whichrequire anunprecedented level technologies are new emerging suchassuper-conductingand NAND; formance; newmemoriesare maythat emerging complement 3DDRAM areUnits (TPU) havethat emerging demonstrated unprecedented per disrupting computing architectures: massively parallel Tensor Processing decades ofdominancebygeneral andGPU, purposeCPU innovation is transmission preventsthat cal lines breakthrough improvements. After sors, memory, and storage stacks,- the signal lossesinelectri aswell processorsthe lagging frequency, is it but the latencythe proces across - the 7/5nanometernodes: powerremainsto is nowmoving aconcern, become Ourindustry acritical enabler ofmodernsystems-on-a-chip. sors, interconnect, interface, FPGA, and complete sub-systems, and has synthesizable-IP, has dramatically it expanded, and now spans proces- years,thirty the last transitionthe fromthanksto to "soft", "hard" and to eachandeverycomplex different porting process technology. Over then,cern. Back was "hard", semiconductor IP physical-IP, whichrequired the 1-micron barrier, andpowerwas con becoming- designers'biggest corporated in1990, years ago,thirty almost the ICwas while breaking has made agreat dealofprogressSemiconductor IP since ARMwas in- Chair: RaulCamposano, SageDesignAutomation, US Jamil Kawa, Synopsys, US Giovanni DeMicheli,EPFL, CH Organisers: Room 11430 Coffee BreakinExhibition Area Panelists: – 1600 47 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - and 1 1 www.date-conference.com , Janardhan Rao Doppa Rao Janardhan , and Umit Ogras 2 2 Colorado State University, US University, State Colorado 2 , Ryan Kim Ryan , 1 Mathworks, US Mathworks, 2 , Suat Gumussoy , 1 1 1600 – Arizona State University, US; US; University, State Arizona Washington State University, US; US; University, State Washington Power and Thermal Analysis of Commercial Mobile Analysis and Thermal Power and Case Studies Experiments Platforms: Area Coffee Break in Exhibition Design and Optimization of Heterogeneous Design and Optimization Interconnect by Emerging enabled Systems Manycore Promises and Challenges Technologies: Smart Thermal Management for Heterogeneous Management Thermal Smart Multicores 1 1 Speaker: Partha Pande, Washington State University, US University, State Washington Pande, Partha Speaker: Joardar Kumar Biresh Authors: US University, State Arizona Umit Ogras, Speaker: Bhat Ganapati Authors: Speaker: Joerg Henkel, Chair for Embedded Systems (CES), Karlsruhe Karlsruhe (CES), Embedded Systems Chair for Henkel, Joerg Speaker: DE (KIT), Technology Institute of Institute Karlsruhe Heba Khdr and Martin Rapp, Henkel, Joerg Authors: DE of Technology, Room 2 1430 Room Organisers: US University, State Washington Partha Pande, DE Technology, Institute of Karlsruhe Jörg Henkel, SE University, Linköping Eles, Petru Chair: US University, State Colorado Sudeep Pasricha, Co-Chair: appli- yet demanding, a phenomenal growth in exciting, experience We com- and scientific analytics, graph such as deep learning, areas cation new devices a demand for driven have areas These application puting. smaller form-factors into high-performance computing that package deep scenarios (e.g., application constrained in heavily that operate new presents this Naturally, systems). in embedded inference learning and energy cost, performance, design challenges increasing to meet ever consider a holistic ap will This special session requirements. efficiency proach to the broad topic of heterogeneous architectures. Towards this Towards architectures. to proach topic of heterogeneous broad the the funda- addressing talks it forward-looking of three consists end, designfor and new approaches proposals, existing challenges, mental The first focus on talk will systems. heterogeneous ing and exploring learning techniques in a efficiency thermal to achieve various utilizing talk will shift The second the discussion toward system. heterogeneous of designing systems the problems these heterogeneous to accelerate machine learning techniques innovative will present We applications. design hardware efficientthat application-specific can be used to make application the corresponding as developing as easy and inexpensive under stringent performance requirements achieving Finally, software. stability analysis due a systematic to require tight thermal constraints The power and temperature. between leakage feedback the positive analysis stability and safety a power-temperature third talk will present conditions under whichthe sufficient the power- technique that reveals following The point. to a stable fixed converges trajectory temperature in this special briefly outline each topiccovered that will be paragraphs session. Special Session: Smart Resource Resource Smart Special Session: Space Exploration and Design Management Processors for Heterogenous Partha Pratim Pande Pratim Partha 48 1600 1530 1500 1430 3.2 TUESDAY, 26 MARCH 2019 TUESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1500 1430 3.4 1600 IPs 1530 1500 1430 3.3 TUESDAY, 2019 MARCH 26

Analysis Physical Design, Extraction andTiming Reliability Methods andCharacterisation techniquesfor Barcelona UAB, ES 1 1 Lopez Hong Kong, HK ChenandEvangelineAuthors: Gengjie Young, The Chinese University of Speaker: Chen, Gengjie The ChineseUniversity ofHong Kong, HK Tong, University ofCalifornia SanDiego, US Authors: Andrew Kahng, Uday Mallappa, Lawrence Sauland Shangyuan Speaker: Uday Mallappa, University ofCalifornia SanDiego, US dom walk basedcapacitanceextraction. addresses issuesonreusability andreproducibility inparallelized ran- routability driven convolutional neural networkpredictor. paper The last algorithms: oneadoptingadataflow driven approach, theotherusinga length performance. The followingtwo papers present macro placement approach for zero skewtree clock construction yieldingsuperiorwire- ciency ofcornertiming analysis. based The second paperproposes an paperusesmultivariateThe first linear regression toincrease the effi- Co-Chair: Po-Hung Lin Mark,National ChungChengUniversity, TW Chair: Patrick Groeneveld, Cadence DesignSystems, US Room 41430 Authors: DanielKraak Speaker: DanielKraak, Delft University of Technology, NL Shobha Vasudevan, University at Urbana-Champaign, ofIllinoisat ECE US Authors: Keven Feng, Sandeep Vora, Rui Jiang, ElyseRosenbaum and Speaker: Keven Feng, University UrbanaChampaign, ofIllinoisat US Authors: Pablo Saraza-Canflanca Speaker: Pablo Sarazá Canflanca, Universidad deSevilla, ES the agingofSRAMsto analyse methodology the characterisation andESDaswella discusses ofBIT This sections Co-Chair:Arnaud Virazel, LIRMM, FR Chair: SaidHamdioui, TU Delft, NL Room 31430 Montserrat Nafria dioui IP1-14, IP1-15, IP1-16, IP1-17, IP1-18 Dim Sum: Light Clock TreebySmall DiameterSum Advanced-Node Design Analysis forFaster Effort DesignConvergence in “Unobserved Corner” Prediction: Reducing Timing Coffee BreakinExhibition Area Analysis ofMemoryTiming Methodology forApplication-Dependent Degradation Posed ByElectrostatic Discharge-induced SoftErrors Guilty AsCharged: Computational Reliability Threats CMOS transistors characterization ofBias Temperature Instability in New methodfortheautomated massive Instituto deMicroelectrónica deSevilla, ES; Delft University of Technology, NL; 1 1 ,Pieter Weckx , ElisendaRoca – – 1600 1600 2 andFrancisco Vidal Fernandez 2 , Stefan Cosemans 1 , Javier Martin-Martinez 1 , Agbo Innocent 1 , Javier Diaz-Fortuny 2 imec vzw., BE 1 2 ,Mottaqiallah Taouil andFrancky Catthoor 2 Universitat Autonoma de 2 , Rosana Rodriguez 1 2 , Rafael Castro- 1 , SaidHam- 2 2 , 49

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - , 1 Duke Duke 3 , Marc Marc , 1 2 Duke Uni- Duke 2 4 , Yong Rafael Rafael Yong , 2 , Tao-Chun Yu Tao-Chun , 1 4 , Jordi Petit Jordi , and Lei Yin and Lei 1 1 www.date-conference.com and Jiang Hu 2 , Guan-Qi Fang Guan-Qi , Texas A&M University, US University, A&M Texas 2 4 , Wenjian Yu Wenjian , 2 1 , Jordi Cortadella Jordi , and Ramesh Karri and Ramesh 1 3 , Sukanta Bhattacharjee Sukanta , , Yiran Chen Yiran , 1 1 New York University Abu Dhabi, AE; AE; Abu Dhabi, University York New ANSYS Inc., US Inc., ANSYS , Zhiyao Xie Zhiyao , 2 2 1 , Zhezhao Xu , 1 1600 NYU, US and Ferran Martorell and Ferran 4 – 2 , Shao-Yun Fang Shao-Yun , 3 NVIDIA Corporation, US; US; NVIDIA Corporation, 3 eSilicon EMEA, Barcelona, ES Barcelona, EMEA, eSilicon 2 , Krishnendu Chakrabarty , 2 New York University, US; US; University, York New Tsinghua University, CN; University, Tsinghua National Taiwan University of Science and Technology, TW; TW; Technology, of Science and University Taiwan National ES; UPC, Desieve the Attacker: Thwarting IP Theft in Sieve- Thwarting the Attacker: Desieve Biochips Valve-based Area Coffee Break in Exhibition PUFs Deep Attacks: Enhanced modeling attacks using modeling attacks Enhanced PUFs Deep Attacks: of techniques to break the security deep learning PUFs arbiter double Optically Interrogated Unique Object with Simulation Simulation Unique Object with Interrogated Optically Attack Prevention RTL-Aware Dataflow-Driven Macro Placement Dataflow-Driven RTL-Aware Floating Parallel and Reusable Realizing Reproducible Usage for Practical Solvers Random Walk IP1-20 IP1-19, Area Coffee Break in Exhibition Routability-Driven Macro Placement with Embedded Embedded with Macro Placement Routability-Driven CNN-Based Model Prediction Galceran-Oms Haoxing Ren Haoxing 1 Speaker: Mahmoud Khalafalla, University Of Waterloo, CA Waterloo, Of University Khalafalla, Mahmoud Speaker: of University Gebotys, and Catherine Mahmoud Khalafalla Authors: CA Waterloo, US University, York New Mohammed, Shayan Speaker: Mohammed Shayan Authors: Speaker: Povilas Marcinkevicius, Lancaster University, GB Lancaster University, Marcinkevicius, Povilas Speaker: Nema M. Abdela- Bagci, Ethem Ibrahim Marcinkevicius, Povilas Authors: Lancas- and Utz Roedig, Young Robert J. Woodhead, Christopher S. zim, GB ter University, Room 5 1430 Room DE TUM, Johanna Sepulveda, Chair: DE of Stuttgart, University Ilia Polian, Co-Chair: which turns the investment, considerable industryElectronics involves The develop of protection Propertytheir Intellectual a main concern. Speaker: Mingye Song, Tsinghua University, CN University, Tsinghua Mingye Song, Speaker: Mingye Song Authors: ment of new solutions technologies will depend on it. In this session, Dots Quantum biochips and PUF-like microfluidic based on obfuscated and attack that challenges PUF-based shown. Moreover, are devices (QD) identifier techniques using machine learning is presented. Speaker: Alexandre Vidal Obiols, Polytechnic University of Catalonia, ES of Catalonia, University Polytechnic Obiols, Vidal Alexandre Speaker: Obiols Vidal Alexandre Authors: Speaker: Yu-Hung Huang, National Taiwan University of Science and University Taiwan National Huang, Yu-Hung Speaker: TW Technology, Huang Yu-Hung Authors: Song versity, US; US; versity, 1 1 1 Hardware authentication and attack and attack authentication Hardware prevention University, US; US; University,

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1500 1430 3.7 1600 IPs 1530 1500 1430 3.6 TUESDAY, 2019 MARCH 26

Systems Design Automation ofCyber-Physical Software Solutions forReliable Memories Annaswamy 1 and Twan Basten, Eindhoven University of Technology, NL Authors: Róbinson MedinaSánchez, Alberto SanderStuijk, DipGoswami Powertrains, NL Speaker: Robinson Medina, Eindhoven University of Technology & TNO Authors: Leslie Maldonado Speaker: Wanli Chang, University of York, GB least,not assume-guarantee contract optimization. to systemdynamics,ing designofvariable-delay controllers and, but last tems, e.g.,the computation/communication designof platform accord- The sessionaddressestechniques for design moderncyber-physical sys- Co-Chair: Stefano Centomo, University of Verona, IT Chair: LeiBu,NanjingUniversity, CN Room 71430 Authors:Li Wei Speaker: QinganLi, Wuhan University, CN Delaware, US Authors: Fateme HosseiniandChengmo Sadat Yang, University of Speaker: Chengmo Yang, University ofDelaware, US Authors: JingChen Speaker: Yi Wang, ShenzhenUniversity, CN VLIW cores. advantage the DynamicBinary during ofit Translation process byusing entationtaketo dependencyspeculation dealswithmemory andhow a wearleveling aware allocator memory for PCMmemories. pres - The IP gate read disturbanceerrors inSTT-RAM. Finally,third paperproposesthe second paperpresents anarchitecture-independent frameworkto miti- SSDwith3Dcharge-trapscheme for open-channel flashmemory. The paperintroducesThe first aprocess-variation-resilient spaceallocation This sessionexplores solutionsfor reliable different memoriesat levels. Co-Chair: Borzoo Bonakdarpour, Iowa State University, US Chair: ValentinGherman, CEA-Leti, FR Room 61430 1 1 Technology, NL IP1-21 with on-linemeasurable variable-delay Implementation-aware designofimage-based control Automotive CPSDesign Exploiting System Dynamics forResource-Efficient Coffee BreakinExhibition Area Memory Systems Stack andHeap Management inPCM-basedMain A Wear Leveling Aware MemoryAllocator forBoth Mitigation ofReadDisturbanceErrorsinSTT-RAM Compiler-Directed andArchitecture-Independent for Open-Channel SSDwith 3DFlash PATCH: Process-Variation-Resilient SpaceAllocation Shenzhen University, CN; Wuhan University, CN; MIT, US; 2 University of York, GB; 1 , DipGoswami – – 1 , Ziqi Shuai 1600 1600 1 ,Yi Wang 2 City University ofHongKong, HK 2 1 1 University ofFlorida, US , ChunXue , WanliChang 4 and Samarjit Chakraborty andSamarjit 1 , AmelieChiZhou 3 TUM, DE; 2 ,Mengting Yuan 2 , Debayan Roy 4 Eindhoven University of 1 , Rui Mao 3 1 3 andQinganLi , Anuradha 1 and Tao Li 2 51 1

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 and Pierluigi and Pierluigi 2 www.date-conference.com Toyota InfoTechnology Center, US Center, InfoTechnology Toyota , Shinichi Shiraishi Shinichi , 2 2 1600 – , Eunsuk Kang Eunsuk , 1 1 University of Southern California, US; US; California, of Southern University in Exhibition Area Coffee Break in Exhibition Collaborative Research Centre: SFB 876 Providing SFB 876 Providing Research Centre: Collaborative Analysis Data by Resource-Constrained Information TR89 Invasive Research Centre: Transregional Computing SFB 912 Highly Research Centre: Collaborative Computing Energy Efficient Adaptive Conquering MPSoC Research Project: Bi-National of a Self-Aware Principles with Complexity Information Collaborative Research Centre: SFB 901 On-the-fly Research Centre: Collaborative Computing DFG Collaborative Funding Instruments - An Funding Instruments Collaborative DFG Overview for Exascale SPP1648 Software Program: Priority Computing Management Data SPP2037 Scalable Program: Priority Hardware for Future Concurrent FOR1800 Controlling Research Unit: and space automotive self-aware - towards Change vehicles in Exhibition Area in Exhibition Coffee Break Optimizing Assume-Guarantee Contracts for the Contracts Assume-Guarantee Optimizing Systems Design of Cyber-Physical Nuzzo 1 Speaker: Gerhard Fettweis, Technische Universität Dresden, DE Dresden, Universität Technische Fettweis, Gerhard Speaker: DE TUM, Herkersdorf, Andreas Speaker: DE IDA, Braunschweig, TU Ernst, Rolf Author: Speaker: Marco Platzner, Paderborn University, DE University, Paderborn Platzner, Marco Speaker: DE Dortmund, TU Chen, Jian-Jia Speaker: Erlangen- Friedrich-Alexander-Universität Teich, Jürgen Speaker: DE Nürnberg, Speaker: Kai-Uwe Sattler, TU Ilmenau, DE Ilmenau, TU Sattler, Kai-Uwe Speaker: DE IDA, Braunschweig, TU Ernst, Rolf Speaker: Speaker: Andreas Raabe, DFG, DE DFG, Raabe, Andreas Speaker: DE TUM, Bungartz, Hans-Joachim Speaker: Friedrich-Alexander-Universität Erlangen- Friedrich-Alexander-Universität Teich, Jürgen Organiser: DE Nürnberg, DE Raabe, DFG, Andreas Moderator: im- of paramount is considered research interdisciplinary Collaborative and jumps in tech- of breakthroughs portancethe achievement for today in- Raabe Andreas Dr. director program In this session, nical innovation. by offered are instruments funding which types of collaborative troduces but also fund- in Germany, (DFG) the Deutsche Forschungsgemeinschaft an introduction After cooperations. international ing opportunities for col- medium and longfor short, term funding instruments different into of in topics ofthe scope initiatives example concrete research, laborative with by representatives and summarized will be shortly introduced DATE week. during the conference exhibiting also a majority of these initiatives Exhibition Theatre 1430 Theatre Exhibition Speaker: Chanwook Oh, University of Southern California, US of Southern California, University Oh, Chanwook Speaker: Oh Chanwook Authors: DFG Collaborative Funding Instruments Collaborative DFG 52 1600 1537 1530 1515 1522 1507 1500 1445 1452 1430 1600 3.8 1530 TUESDAY, 26 MARCH 2019 TUESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com IP1-7 IP1-6 IP1-5 IP1-4 IP1-3 IP1-2 IP1-1 IP1 1615 3ps.8 TUESDAY, 2019 MARCH 26

Larroze Interactive Presentations Research Work Publisher’s Session: How toPublishYour Leti, FR 1 1 sity ofAppliedSciences, DE; Authors: ManuelBarragán Speaker: ManuelBarragán, TIMA laboraory, FR Technology, Delhi, IN Authors: Lokesh SiddhuandPreeti Ranjan Panda, IndianInstituteof Speaker: Lokesh Siddhu, Delhi, IIT IN sity ofManchester, GB Authors: ChaoZhang, MilanMihajlovic and Vasilis Pavlidis, The Univer Speaker: MilanMihajlovic, University ofManchester, GB Authors: BenPerach andShaharKvatinsky, Technion, IL Institute of Technology, IL Speaker: BenPerach, Faculty Engineering,Technion ofElectrical -Israel Authors: BenjaminHettwer Speaker: BenjaminHettwer, BoschGmbH, Robert DE Authors: HaohaoLiaoandCatherine Gebotys, University of Waterloo, CA Speaker: HaohaoLiao, University of Waterloo, CA Authors: JohanLaurent Speaker: JohanLaurent, Univ. Grenoble Alpes, Grenoble INP, LCIS, FR Poster Area 1600 Exhibition Theatre 1615 tation inacorresponding regular session. Additionally, paper is briefly introduced each IP in a one-minute presen- Interactive Presentations runsimultaneouslyduringa30-minuteslot. byCadence AcademicNetwork supported CNM, (CSIC –Universidad de Sevilla), ES; 1 Florian Pebay-Peyroula University Bochum, DE Neumann entire exhibition,the publicationto discuss ofyour book. next search dissemination. Hewillbeavailablethis session, in the aswell rial Director for Springer, willpresent hisadvicefor collaboration inre- their researchpublish workwithSpringerNature. CharlesGlaser, Edito- This publisher’s sessioninvitesto allattendeesto discusshowandwhy Speaker: CharlesGlaser, Springer, US machine-learning indirect test On theuseofcausal feature selection inthecontext of Management of3DMemories FastCool: LeakageAware Dynamic Thermal for Thermal Analysis of3-DICs Adaptive Transient Leakage-Aware Model Linearised Generator UsingSTT-MTJ STT-ANGIE: AsynchronousTrueRandomNumber on FPGAs Implementation Diversity and Partial Reconfiguration CryptographicSecuring Circuits byExploiting Fault Model Methodology forEMFault Injection: Charge-based processor andSoftware Countermeasures Fault Injection onHiddenRegisters in aRISC-VRocket Robert BoschGmbH,Robert Corporate Research, Sector DE; LCIS -Grenoble Instituteof Technology - Univ. Grenoble Alpes, FR; TIMA Laboratory, FR; 3 , Sylvain Bourdel 2 and Tim Güneysu – 1630 2 Instituto deMicroelectronica deSevilla, IMSE- 2 1 ,Beroulle Vincent 3 andSalvador Mir – 1 1645 , GildasLeger 1 3 , JohannesPetersen 3 Horst Görtz Institutefor Görtz ITSecurity,Horst Ruhr- 2 3 , Florent Cilici RFICLab, FR 1 , ChristopheDeleuze 1 2 , Stefan Gehrer 2 Hamburg Univer 1 , Estelle Lauga- 1 and 1 , Heike 2 CEA- 53 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 2 , 2 DENSO and Gerd and Gerd 2 1 2 and Robert 3 , Nikolaj Nikolaj , 2 , Zhonghai Lu , 1 KTH Royal Insti- Royal KTH 2 , Kalpana Senthamarai Senthamarai Kalpana , 2 and Hirotoshi Yasuoka and Hirotoshi 1 , Andre Guntoro Andre , www.date-conference.com 1 , Yifei Wang Yifei , , Rolf Drechsler Rolf , 1 2 and Rolf Drechsler and Rolf 2 University of Bremen, DE of Bremen, University , Martin Roetteler , 2 1 Cyber-Physical Systems, DFKI Systems, Cyber-Physical 2 1 1 , Meng Zhang , 1 3 , Georg Nührenberg Georg , , Elena Ioana Vatajelu Elena Ioana , 1 RWTH Aachen University, DE Aachen University, RWTH 1 2 , Christoph Schorn , , Daniel Grosse , , Philipp Niemann Philipp , 1 1 1 Beijing Memblaze Technology Co., Ltd., CN Ltd., Co., Technology Beijing Memblaze Grenoble-Alpes University, FR University, Grenoble-Alpes 3 3 , Mathias Soeken Mathias , 1 , Wu Fei , 1 and Changsheng Xie 3 TIMA, FR; FR; TIMA, 2 University of Bremen, DE of Bremen, University 3 Microsoft, US Microsoft, 2 and Lorena Anghel and Lorena and Giovanni De Micheli and Giovanni 2 2 2 1 LIRMM, FR; FR; LIRMM, Huazhong University of Science and Technology, CN; Technology, of Science and Huazhong University Robert Bosch GmbH, DE; DE; Robert Bosch GmbH, DE; Bayern, des Freistaats - Landesforschungsinstitut fortiss EPFL, CH; EPFL, Johannes Kepler University Linz, AT; AT; Linz, University Johannes Kepler DE; GmbH, of Bremen/DFKI University Characterizing the Reliability and Threshold Voltage Voltage and Threshold the Reliability Characterizing NAND Flash Trap Shifting of 3D Charge Runtime Monitoring Neuron Activation Patterns Neuron Activation Monitoring Runtime Delay In-Situ Using Dynamic Tracking Health Chip Monitoring for Injection Guided Fault Counter Program PCFI: Assessment GPU Reliability Accelerating Guaranteed Compression Rate for Activations in CNNs for Activations Rate Compression Guaranteed Approach using a Frequency Pruning One Method - All Error-Metrics: A Three-Stage A Three-Stage - All Error-Metrics: One Method in Approximate Error-MetricApproach for Evaluation Memory Pebbling Game for Quantum Reversible Management With Framework CNNTypeCNN: Development Types Data Flexible Accuracy and Compactness in Decision Diagrams for for Diagrams in Decision Compactness and Accuracy Computation Quantum Hidden Delay Fault Sensor for Test, Reliability and Reliability Sensor for Test, Fault Hidden Delay Security Neural Binary on mapping Variation Effect of Device to Memristor Crossbar Array Network Ascheid Bjorner Wille 1 1 1 1 Speaker: Weihua Liu, Huazhong University of Science and Technology, Technology, of Science and Huazhong University Liu, Weihua Speaker: CN Weihua Liu Authors: Speaker: Hadi Ahmadi Balef, Eindhoven University of Technology, NL Technology, of University Eindhoven Balef, Hadi Ahmadi Speaker: de Gyvez, and José Pineda Goossens Kees Hadi Ahmadi Balef, Authors: NL Technology, of University Eindhoven US Northeastern University, Previlon, Fritz Speaker: Kaeli, and David Tiwari Devesh Charu Kalra, Previlon, Fritz Authors: US Northeastern University, Speaker: Sebatian Vogel, Robert Bosch GmbH, DE Robert Bosch GmbH, Vogel, Sebatian Speaker: Authors: Sebastian Vogel DE fortiss, Cheng, Chih-Hong Speaker: Chih-Hong Cheng Authors: Speaker: Giulia Meuli, EPFL, CH EPFL, Giulia Meuli, Speaker: Giulia Meuli Authors: CZ Technology, of Brno University Sekanina, Lukas Speaker: CZ Technology, of Brno University Sekanina, and Lukas Rek Petr Authors: Speaker: Saman Fröhlich, University of Bremen/DFKI GmbH, DE GmbH, of Bremen/DFKI University Saman Fröhlich, Speaker: Saman Fröhlich Authors: Speaker: Alwin Zulehner, Johannes Kepler University Linz, AT Linz, University Kepler Johannes Alwin Zulehner, Speaker: Alwin Zulehner Authors: Speaker: Giorgio Di Natale, CNRS - TIMA, FR TIMA, CNRS - Di Natale, Giorgio Speaker: Di Natale Giorgio Authors: KR POSTECH, Yi, Wooseok Speaker: University Pohang Kim, Kim and Jae-Joon Yulhwa Yi, Wooseok Authors: KR Technology, of Science and GmbH, DE; DE; GmbH, Kannan 1 1 Corporation, JP Corporation, SE; Technology, tute of 1 Xiangfeng Lu Xiangfeng 54 IP1-16 IP1-15 IP1-14 IP1-13 IP1-12 IP1-11 IP1-10 IP1-9 IP1-8 TUESDAY, 26 MARCH 2019 TUESDAY, IP1-18 IP1-17

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 4.2 1830 1800 1730 1700 4.1 IP1-21 IP1-20 IP1-19 TUESDAY, 2019 MARCH 26 Wang Reconfigurable Architecture and Tools Executive Session: TheFuture ofTest arithmetic components. hardware accelerator andapproximateto multi-core interfaces CPUs able CPUs,two interactive alongwith presentations introducethat novel mapping for FPGAs, andhardware securitycoprocessor for reconfigur onto coarse-grained reconfigurable arrays, thermalaware application This sessionpresents improvedthreethat papers application mapping Co-Chair: LarsBauer, Karlsruhe Instituteof Technology, DE Chair: SmailNiar, Université Polytechnique Hauts-de-France, FR Room 21700 byDestination Florencesupported Convention and Visitors Bureau Speaker andAuthor: Leon Stok, IBM, US Speaker andAuthor: Jeff Rearick, AMD, US PDF Solutions, US Speaker andAuthor: Andrzej Strojwas, Carnegie MellonUniversity and (e.g., insystemvalidation andsecurity)willalsobeexplored. ofquantum computers.test The roletesting beyond of manufacturing reliability nodes, advanced at technology the waythe designand all to fromtraditional test, manufacturingto its role in addressing yield and titled "TheFutureThis session of Test" explores varioustest: of aspects Chair: SubhasishMitra, Stanford University, US Room 11700 Authors: SimonRokicki, Erven Rohou andSteven Derrien, IRISA, Rennes, FR Speaker: SimonRokicki, FR INRIA, Authors:Zhao Yi-Cheng Speaker: Yi-Cheng Zhao, National Tsing HuaUniversity, TW Authors: DaijoonHyun, Yuepeng Fan and Youngsoo Shin, KAIST, KR Speaker: DaijoonHyun, KAIST, KR 1 Exhibition Reception inExhibition Area Computers? What about theDesignandTest ofQuantum Three possible alternate realities forthefuture oftest and Below Yield andReliability Challenges andSolutions at 7nm Designed Machines Aggressive MemorySpeculation inHW/SW Co- Digital Circuit Blocks A Mixed-Height Standard CellPlacement Flow for Synthesis throughMachineLearning Accurate Wirelength Prediction forPlacement-Aware National TsingUniversity,Hua TW; 2 ,Yun-Ru Wu – – 1830 1830 2 , Hsin-ChangLin 1 , Yu-ChiehLin 2 2 andShu-Yi Kao Realtek Semiconductor Corp., TW 1 ,Ting-Chi Wang 2 1 , Ting-Hsiung 55 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com 1830 1830 – – Data Flow Testing for SystemC-AMS Timed Data Flow Flow Timed Data for SystemC-AMS Testing Flow Data Models IP2-5 IP2-4, IP2-3, Area in Exhibition Reception Exhibition Automated Activation of Multiple Targets in RTL in RTL Targets of Multiple Activation Automated Testing Models using Concolic using Coverage- Set Simulators Instruction Verifying guided Fuzzing FIXER: Flow Integrity Extensions for Embedded RISC-V for Embedded Extensions Integrity Flow FIXER: IP2-2 IP2-1, Area in Exhibition Reception Exhibition Thermal-Aware Design and Flow for FPGA Design and Flow Thermal-Aware Improvement Performance Context-memory Aware Mapping for Energy Efficient Efficient for Energy Mapping Aware Context-memory CGRAs with Acceleration Room 4 1700 Room IL Technion, Shahar Kvatinsky, Chair: FR TIMA, Elena-Ioana Vataleju, Co-Chair: the memory at emerging how improve technologies looks session This processing-in-memory, like applications in digital systems for processing processors. and nonvolatile Networks Binary Neural processing, graph Speaker: Muhammad Hassan, DFKI GmbH, DE DFKI GmbH, Hassan, Muhammad Speaker: and Rolf Hoang M. Le Daniel Grosse, Muhammad Hassan, Authors: DE of Bremen, University Drechsler, Bureau Visitors and Convention supported Florence by Destination Speaker: Prabhat Mishra, University of Florida, US of Florida, University Mishra, Prabhat Speaker: of University Mishra, Alif Ahmed and Prabhat Lyu, Yangdi Authors: US Florida, DE of Bremen, University Vladimir Herdt, Speaker: Drechsler, and Rolf Hoang M. Le Daniel Grosse, Vladimir Herdt, Authors: DE of Bremen, University supported by Destination Florence Convention and Visitors Bureau Visitors and Convention supported Florence by Destination 3 1700 Room EE Technology, of University Tallinn Jaan Raik, Chair: IT Turin, of Polytechnic Vinco, Sara Co-Chair: to perspectives, different from coverage This session improving targets functional to improve testing, multiple with concolic targets activate cov path and to achieve instruction set metrics for simulators, coverage optimi- IPsthe session covering complete Three in SystemC-AMS. erage and design. system verification for zations Speaker: Tajana Rosing, University of California, San Diego, US San Diego, of California, University Rosing, Tajana Speaker: of California, University Rosing, Tajana Behnam Khaleghi and Authors: US San Diego, US University, State The Pennsylvania Ghosh, Swaroop Speaker: - Penn Jaeger, Trent Ghosh and Swaroop Basu, Aditya Asmit De, Authors: US University, State sylvania Speaker: Satyajit Das, Univ. Bretagne-Sud, CNRS UMR 6285, Lab-STICC, FR Lab-STICC, CNRS 6285, UMR Bretagne-Sud, Univ. Das, Satyajit Speaker: de Université Martin Coussy, and Philippe Kevin Das, Satyajit Authors: FR Bretagne-Sud, Digital processing with emerging memory processing with Digital technologies Improving test generation and coverage test generation Improving

56 4.4 IPs 1800 1830 1730 1700 4.3 IPs 1830 1800 1730 1700 TUESDAY, 26 MARCH 2019 TUESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1830 IPs 1815 1800 1730 1700 4.5 1830 1815 1800 1730 1700 TUESDAY, 2019 MARCH 26

Hardware TrojansandSplit Manufacturing 1 1 jee 1 1 supported byDestination Florencesupported Convention and Visitors Bureau Authors: Abhrajit Sengupta Speaker: Abhrajit Sengupta, New York University, US Authors: Yangdi Lyu andPrabhat Mishra, University ofFlorida, US Speaker: Prabhat Mishra, University ofFlorida, US Authors: Nicole Fern Speaker: Nicole Fern, University ofCalifornia Santa Barbara, US Swaroop Ghosh, Pennsylvania State University, US Authors: MohammadNasimImtiaz Khan, Karthikeyan Nagarajan and Speaker: Swaroop Ghosh, The Pennsylvania State University, US semiconductor supplychains. to strengthenthe securityof technique manufacturing asa cusses split the securityofhardware-softwareto threat systems.Furthermore, dis- it This session elaborates on Hardware Trojans, which are an emerging Co-Chair: GiorgioDiNatale, TIMA,FR Chair: NeleMentens, KU Leuven, BE Room 51700 byDestination Florencesupported Convention and Visitors Bureau Authors: Perricone Robert Speaker: Perricone, Robert University ofNotre Dame, US Authors: LiangChang Speaker: LiangChang, BeihangUniversity, CN sity ofCentral Florida, US Authors: ShaahinAngizi, JiaoSun, Wei ZhangandDeliangFan, Univer Speaker: DeliangFan, University ofCentral Florida, US Authors:Valerio Tenace Speaker: Roberto Giorgio Rizzo, Politecnico di Torino, IT Weisheng Zhao 1 and OzgurSinanoglu University AbuDhabi, DE; Niemier IP2-6 Exhibition Reception inExhibition Area FEOL, Unlock at theBEOL A New Paradigm in Split Manufacturing: Lockthe Side Channel Analysis Efficient Test Generation for TrojanDetection using Hardware TrojansandVerification Blindspots Evaluating Assertion SetCompleteness toExpose Hardware TrojaninEmergingNon-Volatile Memories Exhibition Reception inExhibition Area CoMET Technology An EnergyEfficient Non-Volatile Flip-Flop basedon Network CORN: In-BufferComputing forBinary Neural SOT-MRAM GraphS: AGraph ProcessingAccelerator Leveraging Memristive Crossbars SAID: ASupergate-Aided LogicSynthesis Flow for University ofNotre Dame, US; Beihang University, CN; Politecnico di Torino, IT; University ofCalifornia Santa Barbara, US; New York University, US; 2 , AnupamChattopadhyay 1 , SachinS. Sapatnekar – 1 1830 and Yuan Xie 1 and Tim Cheng 4 1 , XinMa 1 , Roberto Giorgio Rizzo 2 2 Nanyang Technological University, SG University ofCalifornia, Santa Barbara, US 2 1 4 New York University AbuDhabi, IN; , Zhaoxin Liang New York University AbuDhabi, AE 1 , MohammedNabeel 2 2 andAndrea Calimera 2 2 ,Zhaohao Wang 2 ,Jian-Ping Wang University ofMinnesota, US 2 2 , MeghnaMankalale 2 HKUST, HK 1 1 , Debjyoti Bhattachar 2 , YouguangZhang andX, Sharon Hu 2 , JohannKnetchel 1 3 2 New York , Michael 1 1 , 3

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FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 and 1 , Tobias Massier Tobias , 2 1 www.date-conference.com and Kang Shin and Kang 2 , Martin Baumann , 1 General Motors Research & Development, US & Development, Motors Research General 2 2 , Soheil Samii , 1 TUM, DE TUM, 2 1830 1830 – – TUM CREATE, SG; SG; CREATE, TUM University of Michigan, US; US; of Michigan, University TEEM: Online Thermal- and Energy-Efficiency Online Thermal- TEEM: MPSoCs on CPU-GPU Management GPGPU in Near-Threshold Warps Predicting Critical Analysis Point Choke using a Dynamic Applications Decentralized Non-Neighbor Active Charge Balancing Charge Non-Neighbor Active Decentralized Packs in Large Battery IP2-8 IP2-7, Area in Exhibition Reception Exhibition Design Optimization of Frame Preemption in Real- Preemption of Frame Design Optimization Ethernet Time Switched for Agreement Byzantine Unanimous Chained CUBA: Management Platoon Decentralized 1 1 Speaker: Amit Kumar Singh, University of Essex, GB of Essex, University Singh, Amit Kumar Speaker: Singh and Klaus Amit Kumar Somdip Dey, Samuel Isuwa, Authors: GB of Essex, University McDonald-Maier, US University, Utah State Sanyal, Sourav Speaker: and Roy Sanghamitra Bal, Aatreyi Basu, Prabal Sanyal, Sourav Authors: US University, Utah State Chakraborty, Koushik Room 7 1700 Room AT Wien, Muhammad Shafique, TU Chair: IT di Milano, William Politecnico Fornaciari, Co-Chair: for GPU- two on energy efficiency papers, three This session presents based systems and one about performance and accuracy exploring for SNN The firstpresents paper when using GPUs modeling. tradeoffs online an CPU-GPU and energythermal management for mechanism respective and efficient mapping, by enabled system partitioning, thread and boost in GPUs points the choke paper identifies The second models. high energy efficiency. achieving for point induced critical warps choke SNN- simulator that intro a GPU-accelerated The paper presents third and capability of performing low-precision duces stochasticity in STDP simulation. Speaker: Alexander Lamprecht, TUM CREATE, SG CREATE, TUM Lamprecht, Alexander Speaker: Lamprecht Alexander Authors: Bureau Visitors and Convention supported Florence by Destination Speaker: Taeju Park, University of Michigan, US of Michigan, University Park, Taeju Speaker: Park Taeju Authors: DE TUM, Emanuel Regnath, Speaker: DE TUM, and Sebastian Steinhorst, Emanuel Regnath Authors: Room 6 1700 Room DE Robert GmbH, Bosch Ziegenbein, Dirk Chair: DE Technology, of University Saidi, Hamburg Selma Co-Chair: to smart approaches automo- in three communication In session, this The first end-to-end paper optimizes presented. systems design are tive The sec- preemption. with frame networks time-sensitive for latencies - maneu platoon vehicle scheme for a consensus ond paper introduces to non-neighbor approach a decentralized The paper presents third vers. packs. balancing in battery charge Energy and power efficiency in GPU-based Energy and power systems Smart Communication Solutions for Solutions Communication Smart Systems Automotive Sebastian Steinhorst

58 1730 1700 4.7 IPs 1800 1830 1730 1700 4.6 TUESDAY, 26 MARCH 2019 TUESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1830 1800 1730 1700 4.8 1830 1800 TUESDAY, 2019 MARCH 26 Electronics Large Scale Integration ofSuperconductive Embedded Tutorial: Paving theWay forVery supported byDestination Florencesupported Convention and Visitors Bureau Author: Nobuyuki Yoshikawa, Yokohama National University, JP Author: MassoudPedram, USC, US Author: Pooya Jannaty, Synopsys, US Exhibition Theatre 1700 byDestination Florencesupported Convention and Visitors Bureau Institute of Technology, US Authors: Xueyuan She, Yun Long andSaibalMukhopadhyay, Georgia Speaker: Xueyuan She, Georgia Instituteof Technology, US tree synthesis, biasdistribution, andplace&route engines. superconductivetransmission lines,to specialized logicsynthesis, clock modelingoflogiccellsand device modelingandsimulationto compact from JJ starting technology SFQ introducingtutorial aimsat the SCE This typically 2or3,count of useofbiasingcurrentsthe powersource, as etc. nature logiccellsandneedfor ofmost path balancing, limitedfanout based signaling, prevalence askey ofinductors passive element, clocked voltage-current (current-phase) behavior, cryogenic operation, pulse- withcomplextheir reliancetwo-terminal Josephson junctions of on fundamentally different from CMOS logic families, for example, terms in biased SFQlogicfamilies (such asRSFQ, ERSFQ, andAQFP) are, however, mated designofSCE VLSI circuits andprocessors onchip. The ac-anddc- tools are designmethodologiesand developedthat to enablefullyauto- state-of-the-art. To logic thepotential ofSCE fulfill families, isessential it adders, simplefiltersandADCs, andbit-serial processors the defining logic isfar ofCMOS,that behind SFQ withsemi-manualdesign of16-bit and analysis, modeling, compact synthesis, physical designofSFQ-based processor.a SCE The state-of-the-artterms oflibraries, in simulation CMOS processors, delivering a 30GHzsingle-threaded for performance of4orsoGHz canbreakthe currentthat limit performance nologies forthe adiabatic family), promising post-CMOSthe most tech- isoneof it dissipationenergy transition approaching 10^(-19)Joulesper (and lower technology.CMOS" With proven switching speeds in 100's of GHz and family oflogiccellshasappeared andwithin-reach asapotent "beyond- Superconductive based on single flux quantum electronics (SCE) (SFQ) Chair: JamilKawa, Synopsys, US Massoud Pedram, USC, US Jamil Kawa, Synopsys, US Organisers: Exhibition Reception inExhibition Area SFQ logic) quantum-flux-parametroncircuits (AC-biasedlogic Library designand tools foradiabatic engine forDC-biasedSFQlogic circuits Architectures, synthesis flow, andplace&route Josephson Junctions Physics-based modelinganddevice simulation of Exhibition Reception inExhibition Area Spiking Neural Network Fast andLow-Precision LearninginGPU-Accelerated – 1830 59

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 2 and Kuldeep S Meel and Kuldeep 1 www.date-conference.com , Kian Ming A. Chai , National University of Singapore, SG of Singapore, University National 2 2 , Mate Soos Mate , 1 1000 1000 – – DSO National Laboratories, SG; SG; Laboratories, DSO National fbPDR: In-depth combination of forward and of forward In-depth combination fbPDR: in Property Directed Reachability analysis backward Checking Equivalence Concolic High Coverage Bridging ANF CNF and Bosphorus: Solvers for Machine-validating A Framework Coq: au CUDA Programs GPU Assembly in Exhibition Area Coffee Break in Exhibition Heterogeneous Compute Architectures for Deep Architectures Heterogeneous Compute Learning in the Cloud Silicon Heterogeneity in the Cloud Silicon Heterogeneity in HPC and in the data computing GPU accelerated center 1 Speaker: Mate Soos, National University of Singapore, SG of Singapore, University National Soos, Mate Speaker: Choo Davin Authors: US at Dallas, Texas University Benjamin Ferrell, Speaker: of University Hamlen, Jun Duan and Kevin Benjamin Ferrell, Authors: US at Dallas, Texas Speaker: Tobias Seufert, University of Freiburg, DE of Freiburg, University Seufert, Tobias Speaker: DE Freiburg, University Seufert and Christoph Scholl, Tobias Authors: US Mentor, Sagar Chaki, Speaker: US Mentor, Chauhan, Sagar Chaki and Pankaj Pritam Roy, Authors: Room 2 0830 Room IT Bruno Kessler, Fondazione Cimatti, Alessandro Chair: IT Torino, di Politecnico Cabodi, Gianpiero Co-Chair: The papers. The session includes application technical and three three model advanced and evaluating technical papers aim at improving The appli- and SAT. reasoning algebraic and combining checking engines, of correctness for the is used verification papers show how formal cation synthesis, high-level checking for equivalence GPU assembly programs, of CMOS. rates and assessing failure Speaker and Author: Ken O'Brien, Xilinx Research, IE Research, Xilinx O'Brien, Ken and Author: Speaker Speaker and Author: Babak Falsafi, EPFL, CH EPFL, Babak Falsafi, and Author: Speaker US NVidia, Messmer, Peter and Author: Speaker Room 1 0830 Room DE University, Plessl, Paderborn Christian Chair: CH IBM Research, Hagleitner, Christoph Co-Chair: claiming the are systems with accelerators computing Heterogeneous list of the largest HPC and systems TOP500 computing in the top ranks Accelerators datacenters. hyperscale cloud adoption in find increasing performance returns despite and efficiency gains the diminishing offer The in technologyfrom traditional session will setthis talks scaling. the - of accelera proposition and analyze the value this special day stage for of this vibrant An overview workloads. and emerging traditional tors for on systems detailed presentations by more will be followed environment using GPUs and FPGAs Improving Formal Verification and Verification Formal Improving to GPUs and High-Level Applications Synthesis Special Day on “Embedded Meets Hyperscale Meets Hyperscale “Embedded on Special Day Computing Heterogeneous Session: HPC” and and in HPC in the Datacenter 60 0945 0900 0930 0830 5.2 1000 0900 0830 0830 5.1 WEDNESDAY, 27MARCH 2019WEDNESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1000 IPs 0945 0930 0915 0900 0830 5.3 1000 IPs WEDNESDAY, 2019 MARCH 27

Karunaratne Schaafsma EU Projects 1 Authors: Serzat Safaltin Speaker: Mustafa Altun, Istanbul Technical University, TR 4 Authors: Andrey Sadovykh Speaker: Gunnar Widforss, Mälardalen University, SE danengo, IstitutoSuperiore MarioBoella, IT Authors: Scionti, Alberto SimoneCiccia, Olivier Terzo andGiorgio Gior Speaker: SimoneCiccia, IstitutoSuperiore MarioBoella(ISMB), IT 5 Authors: SaidHamdioui Speaker: SaidHamdioui, Delft University of Technology, NL of Siena, IT Authors: Roberto Giorgi, Marco Procaccini andFarnam Khalili, University Speaker: Roberto Giorgi, University ofSiena, IT Chair: Schoeberl, Martin Technical University ofDenmark, DK Room 30830 herst, US 1 1 oppement des Méthodes et Processus Industriels, desMéthodeset oppement FR; Luca Benini Bagnato Technology, CZ; Widforss soy IP2-11, IP2-12 IP2-9, IP2-10 Coffee BreakinExhibition Area Technology Development andCircuit Modeling Realization ofFour-Terminal Switching Lattices: of theMegaM@Rt2 EUProject- Large Collaborative Projects-APreliminary CaseStudy On theUseofHackathons toEnhance Collaboration in Platform forSmart Vision Applications Chip-to-Cloud: anAutonomous andEnergyEfficient Architectures basedonMemristive Devices Applications ofComputation-In-Memory Embedded Platform AXIOM: AScalable, Efficient andReconfigurable Coffee BreakinExhibition Area Delft University of Technology, NL; Istanbul TechnicalUniversity, TR; Maelardalens Hoegskola, SE; SOFTEAM; InnopolisUniversity, FR; IMEC, NL; 1 , Sebahattin Gurmen 7 4 , WasifAfzal , AdnanAshraf 6 5 IMEC, BE 4 , AbbasRahimi , SandeepPande 4 , HoangAnhDuNguyen – 7 1000 SOFTEAM, FR 4 andAlexandra Espinosa Hortelano 1 1 2 , OguzGencer , AbuSebastian 1 , HugoBruneliere , CsabaAndras Moritz 1 4 ,Dragos Truscan ,Mottaqiallah Taouil 5 andFernando G.Redondo 5 Association pourlaRecherche leDével et - 2 University ofMassachusetts, Am- 2 2 IBM, CH; Abo Akademi, FI; 1 , ManuelLe Gallo 1 , M.Ceylan Morgul 2 , Das Shidhartha 5 , Pavel Smrz 2 , Pierluigi Pierini 3 ARM Ltd., GB; 2 1 andMustafa Altun , Francky Catthoor 6 3 Brno University of Intecs S.p.A., IT; 6 2 , Alessandra 3 , Siebren 4 3 1 , Geethan , Ak Levent 4 3 ETHZ, CH; , Gunnar 6 , 1 - - 61

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - , Partha Partha , 2 1 , César Fuguet Fuguet César , 2 and Yier Jin Yier and 2 , Hai (Helen) Li , 1 www.date-conference.com 2 , Vivet Pascal , 2 1 Duke University, US University, Duke 2 , David Z. Pan David , 2 , Jana Doppa , 2 University of Texas, Austin, US Austin, Texas, of University 2 , Yvain Thonnart Yvain , 1 , Bing Li , Univ. Grenoble Alpes, CEA-LETI, FR CEA-LETI, Alpes, Grenoble Univ. , Meng Li , 1 2 1 1000 1000 – – and Krishnendu Chakrabarty 1 and Ayse Kivilcim Coskun and Ayse 2 University of Florida, US; US; of Florida, University Boston University, US; US; Boston University, US; University, State Washington Design Obfuscation through Selective Post-Fabrication Post-Fabrication Selective through Obfuscation Design Programming Transistor-Level Sequential Crunching for Fast Key-Condition KC2: Deobfuscation Circuit through Redundancy Piercing Logic Locking Keys Identification REGENT: A Heterogeneous ReRAM/GPU-based REGENT: CNNs by NoC for Training Enabled Architecture IP2-14 IP2-13, Area Coffee Break in Exhibition SiPterposer: A Fault-Tolerant Substrate for Flexible for Flexible Substrate A Fault-Tolerant SiPterposer: Design System-in-Package for Power-Efficient Selection Wavelength WAVES: NoCs Photonic 2.5D-Integrated Pratim Pande Pratim 1 gos Makris, The University of Texas at Dallas, US at Dallas, Texas of The University gos Makris, US of Florida, University Jin, Yier Speaker: Shamsi Kaveh Authors: US San Diego, of California, University Orailoglu, Alex Speaker: US UC San Diego, Orailoglu, Li and Alex Leon Authors: Speaker: Yiorgos Makris, The University of Texas at Dallas, US at Dallas, Texas of The University Makris, Yiorgos Speaker: Bo Reddy, Rajavendra Gaurav Tian, Jingxiang Shihab, Mustafa Authors: Yior Sechen and Carl Schaefer, Benjamin Carrion Jr., Swartz William Hu, Room 5 0830 Room CH ALARI-USI, Regazzoni, Francesco Chair: DE of Bremen, University Daniel Grosse, Co-Chair: a popular technique is becoming to protectObfuscation IPs and designs. This session reports based on obfuscation protection in the last advances them. attacking and on methodology for Speaker: Biresh Joardar, Washington State University, US University, State Washington Joardar, Biresh Speaker: Joardar Biresh Authors: Speaker: Pete Ehrett, University of Michigan, US of Michigan, University Ehrett, Pete Speaker: of University Bertacco, Valeria and Austin Todd Ehrett, Pete Authors: US Michigan, US University, Boston Narayan, Aditya Speaker: Narayan Aditya Authors: Room 4 0830 Room IT Bertozzi, di Ferrara, Davide Università Chair: FR LIRMMSassatelli, Gilles CNRS of Montpellier, / University Co-Chair: This section discusses emerging Photonics and technologies such as applied NoCs to functional enhance to non-functionaland ReRam sys- communication a flexible The first paper presents tems parameters. The second chip assembly yield. near-100% chiplets ensuring for fabric NoCs by in photonic problem the energypaper addresses minimization for the ther on and off switching lasers still accounting the adaptively mal sensitivity of optical devices. The third paper proposes a NoC-based a The proposes paper third devices. optical of sensitivity mal in-memory computing for CNNs training for using ReRAMs architecture energy efficiency. to maximize 1 1 Tortolero Hardware Obfuscation Hardware Emerging technologies for better NoCs for better technologies Emerging

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 5.7 1000 IPs 0930 0900 0830 5.6 1000 IPs WEDNESDAY, 2019 MARCH 27

Huang Data-driven Acceleration inIoT–EdgetoCloud Energy efficiency Complutense deMadrid, ES; 1 1 cision floating-point operations andGPU-basedpredictable execution. computing platforms. extensionsthe RISC5 for dealwith low-preThe IPs - introducestrafficto reduce data subsetting memory forapproximate kernel to reducetilling approachto L2cache. access third paper The (PIM) architectures.ing-in-memory The second paper proposes a novel plication-data criticality. paper presentsThe first a compiler for process- This sessionpresents accelerated computing paradigms guidedbyap Co-Chair: Borzoo Bonakdarpour, Iowa State University, US Chair: AncaMolnos, CEA-Leti, FR Room 70830 Authors: LuisCostero Speaker: LuisCostero, Universidad Complutense deMadrid, ES Authors: FlorianGlaser Speaker: FlorianGlaser, ETH Zurich, CH rangi, Delhi, IIT IN Authors: Priyanka Singla, Shubhankar SumanSinghandSmrutiR.Sa- Speaker: Priyanka Singla, Delhi, IIT IN baseband processor forthe IoTapplications. paper,an IP proposesthat asoftware/hardware co-design ofadigital video efficient transcoding forcloudservers. Thesessionalso features nism for ultra-low-power devices. third paper implementsThe energy- builds anenergy-efficient, hardware-supported synchronization mecha- mechanism for devices harvesting. capableofenergy The second paper device hierarchy. papershows an energy-awareThe first checkpointing theIoT three efficiencyin This sessionincludes papersdiscussingenergy Co-Chair: BarisAksanli, SanDiegoState University, US Chair: SemeenRehman,TU Wien,AT Room 60830 Katzalin Olcoz Federal Instituteof Technology Lausanne(EPFL), CH IP2-17 IP2-15, IP2-16 Coffee BreakinExhibition Area Efficient Real-TimeMulti-User VideoTranscoding MAMUT: Multi-Agent Reinforcement Learningfor Power Tightly Coupled Clusters Synchronization andCommunication forUltra-Low- Hardware-Accelerated Energy-Efficient for EnergyHarvesting Devices FlexiCheck: AnAdaptive Checkpointing Architecture Coffee BreakinExhibition Area Dpto. deArquitectura decomputadores yAutomática. Universidad ETH Zürich, CH; 1 andLucaBenini 1 – – andDavid Atienza 1000 1000 2 Università diBologna, IT 1 , ArmanIranfar 1 , GermainHaugou 1 2 Embedded Systems Laboratory (ESL), Swiss 2 2 , MarinaZapater 1 , Davide Rossi 2 , Francisco D. Igual 2 , Qiuting 63 1 , -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 , Rafael Rafael , 2 and 1 Indian 3 - UFRGS – Universi - Nitin Chandra , 2 , Petru Eles Petru , 2 2 , Joao Paulo Lima Joao Paulo , 2 www.date-conference.com , Antonio Carlos Schneider Carlos Antonio , 2 1 , Paulo Cesar Santos Cesar Paulo , 1000 , Sudipta Chattopadhyay , 1 Singapore University of Technology and De- Technology of University Singapore , Swagath Venkataramani Swagath , 1 2 – 1 IBM T. J. Watson Research Center, US; US; Center, Research Watson J. T. IBM 2 2 , Marco Antonio Zanata Alves Zanata Antonio Marco , 2 1 and Anand Raghunathan 3 and Luigi Carro 2 Purdue University, US; US; University, Purdue NED University of Engineering and Technology, PK; PK; Technology, NED and of Engineering University SE; University, Linköping Automotive powertrain demonstrator powertrain Automotive Area Coffee Break in Exhibition ARAMiS II project overview process for model-based ARAMiS II development development software multicore development multicore supporting Methods and tools Cache-Aware Kernel Tiling: An Approach for System- An Approach Tiling: Kernel Cache-Aware of GPU-Based Optimization Performance Level Applications Approach to A Data-Centric Subsetting: Data Computing Approximate IP2-20 IP2-19, IP2-18, Area Coffee Break in Exhibition A compiler for Automatic Selection of Suitable Suitable of Selection for Automatic A compiler Instructions Processing-in-Memory Institute of Technology Madras, IN Madras, Technology Institute of F. de Moura F. sign (SUTD), SG sign (SUTD), Beck Author: Rolf Ernst, TU Braunschweig, DE Braunschweig, TU Ernst, Rolf Author: US AG, Continental Stefan, Kuntz Author: DE of Augsburg, University Bauer, Bernhard Author: DE Deutschland GmbH, Denso Automotive Sebastian Kehr, Author: Organisers: DE Technology, Institute of Sandmann, Karlsruhe Timo DE Technology, Institute of Karlsruhe Becker, Jurgen DE Technology, Timo Institute of Sandmann, Karlsruhe Chair: wellas avionics and in automotive domains the applications Safety-critical demandas Industrytopic the future still increasing and clear a show 4.0 power is needed, processing This demand for power. digital processing for machines with realtime driving and connected e.g. highly automated for - by an increas this demand is substantiated Furthermore, requirements. This justi- with other systems and services. and integration ing interaction technologyfies the usage of multicore in embedded systems in the near domains successfully applied in other application which is already future, in applications safety-critical smartphones.and tablets However, PCs, like - require additional complex domains show many the above-mentioned only be fulfilled partly with an unjus- if at all, can, which at present ments, presentproposed special session shall The effort. tified high development - a summary of topics re the most and research results important achieved applications. systems in safetycritical an efficient use of multicore garding 0830 Theatre Exhibition Speaker: Younghoon Kim, Purdue University, KR University, Purdue Kim, Younghoon Speaker: Kim Younghoon Authors: Speaker: Arian Maghazeh, Linköping University, SE University, Linköping Arian Maghazeh, Speaker: Arian Maghazeh Authors: Speaker: Luigi Carro, UFRGS - Federal University of Rio Grande do Sul, BR do Sul, Rio Grande of University UFRGS - Federal Luigi Carro, Speaker: Ahmed Hameeza Authors: choodan 1 1 dade Federal do Rio Grande do Sul, BR do Sul, Grande do Rio dade Federal 1 Special Session: The ARAMiS II Project - Special Session: for safety-critical Use of Multicore Efficient Applications Zebo Peng Zebo

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com IP2-10 IP2-9 IP2-8 IP2-7 IP2-6 IP2-5 IP2-4 IP2-3 IP2-2 IP2-1 IP2 WEDNESDAY, 2019 MARCH 27 Interactive Presentations 1 Yinlong Xu sity of Technology (TU Wien), AT 1 Authors: AmanGoelandKarem Sakallah, University of Michigan, US Speaker: AmanGoel, University ofMichigan, US Speaker andAuthor: JosefStrnadel, BrnoUniversity of Technology, CZ Authors: Ta-WeiHuang Speaker:Yun-Yun Tsai,National TsingUniversity, Hua TW Jian-Jia Chen, Technical University ofDortmund, DE Authors: Lea Schönberger, Georg von derBrüggen, Schirmeierand Horst Speaker: Lea Schönberger, University,TU Dortmund DE University ofBremen, DE Authors: HoangM.Le, DanielGrosse, NiklasBrunsandRolf Drechsler, Speaker: NiklasBruns, Cyber-Physical Systems, DFKIGmbH, DE Authors: JunchenZhaoandIanHarris, University ofCalifornia Irvine, US Speaker: IanHarris, University ofCalifornia, Irvine, US Authors: HaitaoZhang Lanzhou University, CN Speaker: HaitaoZhang, SchoolofInformation ScienceandEngineering, Authors: HaoChen Speaker: HaoChen, University ofScienceand Technology ofChina, CN ing, University ofCalifornia SanDiego, US Authors: MohsenImani, Ricardo Garcia, Andrew Huangand Tajana Ros- Speaker: MohsenImani, University ofCalifornia, SanDiego, US Authors: Marcelo Brandalero (UFRGS), BR Speaker: Marcelo Brandalero, Universidade Federal doRioGrande doSul Poster Area 1000 tation inacorresponding regular session. Additionally, paper is briefly introduced each IP in a one-minute presen- Interactive Presentations runsimultaneouslyduringa30-minuteslot. byCadence AcademicNetwork supported 1 1 Antonio Carlos SchneiderBeck Techniques onVerilog RTL Designs Empirical Evaluation ofIC3-basedModelChecking for Bathtub-Shaped Failure Rates Using Statistical ModelCheckingtoAssessReliability Adaptive CruiseControl Vehicle SequenceReordering with Cooperative Filters inBroadcastBuses Design Optimization forHardware-Based Message Designs viaCoverage-guided Fuzzing Detection ofHardware TrojansinSystemC HLS Language Specifications UsingSubtreeAnalysis Automatic Assertion Generation fromNatural Vehicle Distributed Application Systems Model CheckingisPossible to Verify Large-scale Layer HCFTL: ALocality-Aware Page-Level FlashTranslation Efficiency CADE: Configurable Approximate Divider forEnergy Reconfigurable Acceleration Heterogeneous Systems with Transparent and TransRec: Improving Adaptability inSingle-ISA University ofScienceand Technology ofChina, CN; UFRGS -UniversidadeUFRGS Federal doRioGrande doSul, BR; Lanzhou University, CN; National TsingUniversity,Hua TW; 1 – 1 , ChengLi 1030 1 1 ,Ayang Tuo ,Yun-Yun Tsai 2 Shanghai Jiao Tong University, CN 1 1 , MuhammadShafique , YubiaoPan 1 1 andGuoqiangLi 2 National TaiwanUniversity, TW 1 , Chung-Wei Lin 2 , MinLyu 2 Huaqiao University, CN 1 , YongkunLi 2 2 , LuigiCarro 2 and Tsung-Yi Ho 2 Vienna Univer 1 and 1 and 65 1 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - , Ioanna Ioanna , 1 2 , Georgios Georgios , 1 , Andrea Andrea , 1 , Amit Kumar Amit Kumar , 2 , Sotirios Xydis Sotirios , 2 Aristotle University of Aristotle University 2 www.date-conference.com University of Catania, IT; IT; of Catania, University , Davide Rossi Davide , 2 2 , Maurizio Palesi , 1 and Andrea Marongiu and Andrea 2 3 , Konstantina Koliogeorgi Konstantina , 1 , Stefan Mach Stefan , , Achilleas Chytas Achilleas , 1 2 1 ETH Zurich, CH Zurich, ETH 2 University of Southampton, GB of Southampton, University 4 4 , Luca Benini , 1 , Xiaohang Wang , 1 Democritus University of Thrace, GR Thrace, of Democritus University Università di Bologna, IT di Bologna, Università 3 2 and Dimitrios Soudris 2 and Luca Benini 1 , Alexandra Kosvyra Alexandra , 1 and Terrence Mak Terrence and 3 ETH Zürich, CH; Zürich, ETH IT; di Bologna, Università South China University of Technology, CN; Technology, of South China University GB; of Essex, University National Technical University of Athens, GR; GR; of Athens, University Technical National Design and Evaluation of SmallFloat SIMD extensions SIMD extensions of SmallFloat Design and Evaluation to the RISC-V ISA for Resource Management Adaptive Dynamic vDARM: Systems Virtualized Multiprocessor Taming Data Caches for Predictable Execution on Execution Caches for Predictable Data Taming GPU-based SoCs Partial Encryption of Behavioral IPs to Selectively IPs to Selectively Partial of Behavioral Encryption Synthesis in High-Level the Design Space Control Multi-Standard Co-Design of Software-Hardware Processor for IoT Baseband Digital Deep Learning-Based Circuit Recognition Using Sparse Recognition Deep Learning-Based Circuit Circuit Sum Decaying and Level-Dependent Mapping Representation Modular FPGA Acceleration of Data Analytics in Analytics of Data Acceleration FPGA Modular Heterogenous Computing Dynamic and Congestion-aware An Accuracy- ACDC: for Networks-on-Chip Method Control Traffic NoC Design for CPU- Optimal and Performance Power Models Using Formal GPU Architecture Co-design Implications of On-Demand-Acceleration of On-Demand-Acceleration Implications Co-design The AEGLE approach Analytics: Healthcare for Cloud 1 1 Chouvarda Speaker: Jianmin Qian, Shanghai Jiao Tong University, CN University, Tong Shanghai Jiao Jianmin Qian, Speaker: Shanghai Ma and Haibing Guan, Ruhui Jian Li, Jianmin Qian, Authors: CN University, Tong Jiao Speaker: Björn Forsberg, ETH Zürich, CH Zürich, ETH Forsberg, Björn Speaker: Forsberg Björn Authors: IT di Bologna, Università Tagliavini, Giuseppe Speaker: Authors: Giuseppe Tagliavini Speaker: Zi Wang, The University of Texas at Dallas, US at Dallas, Texas of The University Wang, Zi Speaker: of The University Schaefer, and Benjamin Carrion Wang Zi Authors: US at Dallas, Texas FR CEA-Leti, Bernier, Carolynn Speaker: FR LETI, CEA, Bernier, Hela Belhadj Amor and Carolynn Authors: Speaker: Massoud Pedram, University of Southern California, US of Southern California, University Pedram, Massoud Speaker: Shahin Nazarian Nuzzo, Pierluigi Soheil Shababi, Fayyazi, Arash Authors: US of Southern California, University and Massoud Pedram, Speaker: Siyuan Xiao, South China University of Technology, CN Technology, of South China University Siyuan Xiao, Speaker: Siyuan Xiao Authors: 3 US Irvine, of California University Nader Bagherzadeh, Speaker: of Califor University Nader Bagherzadeh, Alhubail and Lulwah Authors: US nia - Irvine, Speaker: Christoforos Kachris, ICCS-NTUA, GR ICCS-NTUA, Kachris, Christoforos Speaker: Dimitrios Soudris and Elias Koromilas, Kachris, Christoforos Authors: GR Thrace, of Democritus University Speaker: Konstantina Koliogeorgi, National Technical University of University Technical National Koliogeorgi, Konstantina Speaker: GR Athens, Dimosthenis Masouros Authors: 1 Thessaloniki, GR; GR; Thessaloniki, 1 Zervakis Marongiu Singh 66 IP2-20 IP2-19 IP2-18 IP2-17 IP2-16 IP2-15 IP2-14 IP2-13 IP2-12 IP2-11 WEDNESDAY, 27MARCH 2019WEDNESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 6.2 1230 1200 1130 1100 6.1 WEDNESDAY, 2019 MARCH 27 Application Session:Special 3DSensor -Hardware to and HPC” Session: Near-memorycomputing DaySpecial on “Embedded MeetsHyperscale cuss design ofinnovative biosensors usingfine-grain 3Dintegration. stacking for ultra-low-power applications. Finally,talk willdis- the fourth through 3Ddie ofmm-scalesensors the concept talk willpresentthird controlto create withina3Dimagesensor highlyintelligent cameras. The the feasibilitywill discuss ofembeddingmachinelearningbased feedback of recent advancements in 3D image sensor design, the secondtalk while imaging. willpresent adetailed The first overview andsmart performance talks will two ing. focus onapplicationThe first of3Dintegration tohigh- to ultra-low-power imaging high-performance IoT platformsto bio-sens - platform for designing innovative sensorsfor applications ranging from session willpresent fourtalks illustrating how3Dintegration creates a intelligence.to innovations systemswithin-built This indesigningsmart forms. Moreover, close proximity of processing and sensinghasalso lead tween sensing and processing has fueled new generation of senor plat in asmallvolume coupled withpotential for highlyparallel accessbe - sensors.energy-efficient tostackheterogeneous Theability components and/ortential thedesignofhigh-throughput for is tremendous benefit ofMoore'sgrowth law. Anapplication where 3Dhasalready shownpo- The 3D integration hasemerged asakeyto continue enabler performance Co-Chair:Pascal Vivet, CEA-Leti, FR Chair: Fabien Clermidy, CEA-Leti, FR Saibal Mukhopadhyay, Georgia Instituteof Technology, US Pascal Vivet, CEA-Leti, FR Organisers: Room 21100 Corda andGagandeepSingh, Research IBM Zurich, CH Florian Auernhammer, ChristophHagleitner, Lorenzo Chelini, Stefano Authors: Janvan Lunteren, Ronald Luijten, Dionysios Diamantopoulos, Speaker: Janvan Lunteren, Research IBM Zurich, CH Speaker andAuthor: BorisGrot, University ofEdinburgh, GB Z Authors: Fabian Schuiki, MichaelSchaffnerand LucaBenini,IIS, ETH Speaker: LucaBenini, IIS, ETH Z these bottlenecks andbuildmore balanced computing systems. tions ranging fromto address micro-architecturethe runtime system to computingtakes systemandproposes the memory afresh innova lookat - bandwidthacrossmemory abroad range ofapplications. Near-memory complex hierarchy, memory often but failthe availableto optimallyutilize improve the samepace. at Today's microprocessors behinda this fact hide by Moore's law, system did not the latencythe memory and bandwidth of of processors inavailable byexploitingthegrowth transistors delivered to increasethe peakcomputationalto beeasy used capabilities While it Co-Chair: ChristianPlessl,Paderborn University, DE Chair: ChristophHagleitner, Research, IBM CH Room 11100 Lunch BreakinArea Processing Acceleration Platform andits application toStencil Coherently AttachedProgrammable Near-Memory Software, Silly! Near-Memory Processing: It'stheHardware AND 22nm FD-SOI floating-point generalized reduction workloads in NTX: Anenergy-efficient streamingaccelerator for urich, CH – – 1230 1230 urich, CH 67 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - - , Olivier Olivier , 2 , Perrine Perrine , 1 , Maxence Maxence , 1 verine , Stephane Chevob Stephane , 1 , Thomas Thomas Dombek , 2 www.date-conference.com , Cheramy Se Cheramy , 1 , Laurent Millet Laurent , 1 , Maria Lepecq Maria , 1 1 , Didier Lattard Didier , 1 , Luis Angel Cubero MonteAlegre Cubero Luis Angel , 2 , Gilles Sicard , 1 1230 – CEA-LIST, FR CEA-LIST, 2 , Alexandre Valentian Alexandre , and Fabien Clermidy and Fabien 1 , Sebastien Thuriès , 1 2 , Karim Ben Chehida Karim , 2 CEA-Leti, FR; FR; CEA-Leti, Low-Power Variation-Aware Cores based on Dynamic Cores based on Dynamic Variation-Aware Low-Power Truncation Bitwidth Data-Dependent Image Scheme for Reliable Detection Fault A Smart Processing Applications IP3-1 Lunch Break in Lunch Area Sensor-Based Approximate Adder Design for Sensor-Based Approximate and Deep-Learning Error-Tolerant Accelerating Applications Lunch Break in Lunch Area 3D Interconnects and Integration technologies for technologies and Integration 3D Interconnects Systems Biosensor A Camera with Brain - Embedding Machine Learning - Embedding Machine Brain with A Camera in 3D Realizing mm-scale Things: of Tiny IoT2 - the Internet stacking sensors through 3D die Advanced 3D Technologies and Architectures for 3D and Architectures 3D Technologies Advanced Sensors Image Smart be Bouvier Bichler 1 Batude Speaker: Luca Cassano, Politecnico di Milano, IT di Milano, Politecnico Luca Cassano, Speaker: and Antonio Cassano Luca Cristiana Bolchini, Biasielli, Matteo Authors: IT di Milano, Politecnico Miele, Speaker: Ning-Chi Huang, National Chiao Tung University, TW University, Tung Chiao National Ning-Chi Huang, Speaker: Depart Wu, Chen and Kai-Chiang Szu-Ying Ning-Chi Huang, Authors: GB Belfast, Queen's University Tsiokanos, Ioannis Speaker: Karakonstantis, and Georgios Mukhanov Lev Tsiokanos, Ioannis Authors: GB Belfast, Queen's University ment of Computer Science, National Chiao Tung University, TW University, Tung Chiao National Science, ment of Computer Room 3 1100 Room GB London, Imperial College Constantinides, George Chair: GB Rishad Shafik, Newcastle University, Co-Chair: requirements. design conflicting and dependability are Approximation ap require power trade-offs dependability and/or meet performance, To Speaker: David Blaauw, University of Michigan, US of Michigan, University Blaauw, David Speaker: Li-Xuan Kim, Yejoong Wu, Xiao Cho, Minchang Sechang Oh, Authors: Hun- Yang, Kaiyuan Bang, Suyoung Pannuto, Pat Lim, Wootaek Chuo, of Michigan, University Blaauw, and David Dennis Sylvester Seok Kim, US US Technology, Institute of Georgia Muhannad Bakir, and Author: Speaker This session analysis and design methodologies. with insightful proaches in designing arithmetic units paradigms driven approximation presents detection fault using machine learning. schemes and developing Speaker: Saibal Mukhopadhyay, Georgia Institute of Technology, US Technology, Institute of Georgia Saibal Mukhopadhyay, Speaker: - Muham Long, Yun Saha, Priyabrata Mudassar, Burhan Ahmad Authors: Wolf Marilyn Ko, Hwan Jong Na, Taesik Gebhardt, Evan Amir, mad Faisal US Technology, Institute of Georgia and Saibal Mukhopadhyay, Speaker: Pascal Vivet, CEA-Leti, FR CEA-Leti, Vivet, Pascal Speaker: Vivet Authors: Pascal When Approximation Meets Dependability When Approximation

68 IPs 1200 1230 1130 1100 1230 6.3 1206 1144 1122 1100 WEDNESDAY, 27MARCH 2019WEDNESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1130 1100 6.5 1230 IPs 1200 1130 1100 6.4 WEDNESDAY, 2019 MARCH 27

Cazorla Black-Schaffer System Level Security performance Hardware support formicroarchitecture fatirad lunya, ES; 1 1 Pudukotai Dinakarrao rick Schaumont, Virginia Tech, US Authors: Archanaa S. Krishnan, CharlesSuslowicz, Daniel Dinu andPat Speaker: Archanaa S. Krishnan, Virginia Tech, US Authors: HosseinSayadi Speaker: Houman Homayoun, George MasonUniversity, US tation,the kernelto self-attest. and to protect malware, security:to detect port to provide secure intermittent compu- This sessionincludesfour papersonhardwareto sup techniques based Co-Chair: Pascal University Benoit, ofMontpellier, FR Chair:Lionel Torres, University ofMontpellier, FR Room 51100 Rutzig, UFSM, BR Authors: MichaelJordan, Tiago Knorst, Julio Vicenzi andMateus Beck Speaker: Mateus Rutzig, UFSM, BR Authors: MehdiAlipour Speaker: MehdiAlipour, UppsalaUniversity, SE Authors: Jordi Cardona Supercomputing Center, ES Speaker: Jordi Cardona, Univ. Politècnica deBarcelona andBarcelona torized code runtime. at flowandgenerating dynamicanalysisofinstruction paper isabout vec- schedulingoperationsstruction inaggressive OoOprocessors. third The checking multicore contentions. The second paper reducesthe costly in- proposes low-overheadto enhancesysteminterrupts hardware support formance beyondto achieve ispossible what bysoftware. paper The first embedded real-time processorsto improve their per their efficiency or This sessiondealswithhardware mechanismsfor or high-performance Co-Chair: Sylvain FR Collange, INRIA/IRISA, Chair: CristinaSilvano, Politecnico diMilano, IT Room 41100 ogy, NO 1 IP3-2, IP3-3, IP3-4 State Power Across Loss Secure Intermittent Computing Protocol: Protecting Assisted Malware Detection Hardware-Approach forRun-TimeSpecialized 2SMaRT: ATwo-Stage MachineLearning-Based Lunch BreakinArea Energy Efficient DLP Detection Boosting SIMDBenefitsthroughaRun-timeand Scheduling forOoOProcessors MicroArchitecture:FIFOrder Ready-Aware Instruction Access Count andContention TimeEnforcement Maximum-Contention Control Unit (MCCU): Resource George MasonUniversity, US; Barcelona Supercomputing Center andUniversitat Politecnica deCata- Uppsala University, SE; 1 andHoumanHomayoun 2 2 Barcelona Supercomputing Center, ES 1 – – 1230 1230 1 ,Mohsenin Tinoosh 1 1 , Carles Hernandez 2 1 , Rakesh Kumar Norwegian UniversityNorwegian ofScienceand Technol- , HoseinMohammadiMakrani 2 University Baltimore of Maryland County, US 1 2 , Stefanos Kaxiras 2 2 , Avesta Sasan , JaumeAbella 1 , SaiManoj 1 2 , Setareh Ra - 1 andFrancisco andDavid 69 - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - 1 , Luca , 2 and Nele 2 www.date-conference.com , Mauro Conti Mauro , 2 and David Atienza and David , Kaspar Schindler Kaspar , 2 1 , Amir Aminifar , 1 , Lukas Cavigelli Lukas , 1 1 , Md Masoom Rabbani Md Masoom , 1 Sleep-Wake-Epilepsy-Center, Department of Neurology, Department of Neurology, Sleep-Wake-Epilepsy-Center, University of Padua, IT of Padua, University 1230 2 2 – Swiss Federal Institute of Technology Lausanne (EPFL), CH Lausanne (EPFL), Technology Institute of Federal Swiss 2 1 and Abbas Rahimi 1 EPFL, CH; EPFL, Department of Information Technology and Electrical Engineering, and Electrical Engineering, Technology Department of Information KU Leuven, BE; Leuven, KU A Self-Learning Methodology for Epileptic Seizure for Epileptic A Self-Learning Methodology Edge Labeling Minimally-Supervised with Detection IP3-10 IP3-9, IP3-8, IP3-7, Lunch Break in Lunch Area Laelaps: An Energy-Efficient Seizure Detection Seizure Detection An Energy-Efficient Laelaps: iEEG Recordings Long-term Human from Algorithm Alarms False without of MRPs for Analysis Time-Frequency Automatic Devices Mechatronic Mind-controlled SACHa: Self-Attestation of Configurable Hardware of Configurable Self-Attestation SACHa: IP3-6 IP3-5, Lunch Break in Lunch Area RiskiM: Toward Complete Kernel Protection with with Protection Kernel Complete Toward RiskiM: Support Hardware Benini 1 Speaker: Damián Pascual, EPFL, CH EPFL, Damián Pascual, Speaker: Damián Pascual Authors: Speaker: Giovanni Mezzina, Politecnico di Bari, IT di Bari, Politecnico Mezzina, Giovanni Speaker: IT di Bari, Politecnico Mezzina, and Giovanni Venuto Daniela De Authors: Speaker: Alessio Burrello, Department of Information Technology and Technology Department of Information Alessio Burrello, Speaker: CH Zurich, ETH Electrical Engineering, Alessio Burrello Authors: Room 6 1100 Room IT di Bari, Politecnico Venuto, Daniela De Chair: CY of Cyprus, University Theocharis Theocharides, Co-Chair: This session brings together a settechnologies novel that of exploit arti- and implant analytics wearable and data on low-power ficial intelligence healthcare. living and assistive augmented real-time for able sensors, Speaker: Jo Vliegen, imec-COSIC/ESAT, KU Leuven, BE Leuven, KU imec-COSIC/ESAT, Vliegen, Jo Speaker: Authors: Jo Vliegen Speaker: Dongil Hwang, Seoul National University, KR University, Seoul National Dongil Hwang, Speaker: Lee, Younghan Seongil Jeon, Yang, Myonghoon Dongil Hwang, Authors: Dept. of Electrical and Computer Paek, Yunheung and Kwon Donghyun (ISRC), Center Research Semiconductor Inter-University Engineering and KR University, Seoul National 1 1 ETH Zurich, CH; Zurich, ETH Mentens and Implantable Wearable Intelligent Living Sensors for Augmented Inselspital, Bern University Hospital, University Bern., CH Bern., University Hospital, Bern University Inselspital,

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1230 1215 1200 1130 1100 6.7 WEDNESDAY, 2019 MARCH 27 Physical System? How SecureandVerified is your Cyber- and Xuandong Li 1 California, Irvine, US Authors: Korosh Vatanparvar andMohammadAlFaruque, University of Speaker: Korosh Vatanparvar, University ofCalifornia, Irvine, US Authors: Lei Bu Speaker: Lei Bu, NanjingUniversity, CN Houman Homayoun, George MasonUniversity, US Mohammadi Makrani, Cameron Nowzari, Setareh Rafatirad and Authors: SaiManojPudukotai Dinakarrao, HosseinSayadi, Hosein Speaker: SaiManojPudukotai Dinakarrao, George MasonUniversity, US Mohammad AlFaruque, University ofCalifornia, Irvine, US Authors: Rokka Sujit Chhetri, Anthony BahadirLopez, Jiang Wan and Speaker: MohammadAlFaruque, University ofCalifornia, Irvine, US the cyber-physicalof system. model checkingwithlinearprogramming isusedfor on-lineverification tive control malware thenetwork.Bounded to limit diffusionin isused malware networknodelevel.to detect at used Stochasticmodelpredic - Networks areto increase used security. Lightweight machinelearningis of moderncyber-physical systems.Conditional Generative Adversarial The session addresses security and verification the design aspects for Co-Chair: ChinaNormalUniversity, MingsongChen,East CN Chair: University Wanli of Chang, York, GB Room 71100 nic Univ., HK Lunch BreakinArea Recovery inAutomotive Cyber-Physical Systems Self-Secured Control with Anomaly Detection and Physical Systems Incremental OnlineVerification ofDynamic Cyber- Network-level Malware Confinement inIoTNetworks Lightweight Node-level Malware Detection and Systems for theSecurity Analysis ofCyber-Physical Production GAN-Sec: Generative Adversarial Network Modeling Nanjing University, CN; – 1 , ShaopengXing 1230 1 2 Dept. ofComputing,Dept. The HongKong Polytech- 1 , Xinyue Ren 1 , Yang Yang 1 ,Qixin Wang 71 2

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com 1230 – EuroLab4HPC - Joining forces towards European EuroLab4HPC - Joining forces towards systems computing in Exascale leadership on efficient based business Open innovation networking Lunch Break in Lunch Area Carrots TETRaWIN Presentation of TETRAMAX Presentation EVERMORE Speaker: Neven Rusković, Spica Sustativi d.o.o., HR d.o.o., Spica Sustativi Rusković, Neven Speaker: SE Technology, of Chalmers University Stenström, Per Speaker: DE ZENIT GmbH, Bernd Janson, Speaker: Speaker: Rainer Leupers, RWTH Aachen, DE Aachen, RWTH Leupers, Rainer Speaker: IT di Bologna, Università Rossi, Davide Speaker: IT Lifely, Solinas, Antonio Speaker: Exhibition Theatre 1100 Theatre Exhibition Organisers: IT of Pisa, University Luca Fanucci, DE Bernd Janson, ZENIT GmbH, IT of Pisa, University Luca Fanucci, Moderator: Industry is of One Europe's to imple- the mostfor challenge demanding during Besides technologies. the problems technical mentinformation - touch digitalization of analogue processes, and replacement installation - in and outside compa and exchange es of interaction the whole process system blackouts misuse of personal data, with hacks like Threats nies. many and prevent discussed experts heavily or lack of qualified IT are But so far. digitalization fostering from smaller SMEs, especially players, the question about will be solved if all - those problems even the contribu is and lower energy reduction consumption to CO2 tion of digitalization technologies blockchain like innovations still remaining. New promising at least point of view. from the energy fail seem saving to completely on Cyber with focus all aspects of digitalization solutions for receive To Hubs and via the instrument (CPS) of Digital Innovation Systems Physical started (DIH)Smartits Commission European the Anything Everywhere Horizon The to business. research from transfer to foster Initiative (SAE) smart is one of them offering and in- TETRAMAX Action 2020 Innovation cooperation. university-industry European dividual funding schemes for - Tech - on direct cooperation conceptThe focuses technology transfer sup (TTX) and SMEs - between universities Experiments Transfer nology - inves like and other stakeholders networks ported by open innovation and by way in a pragmatic will demonstrate The session speakers tors. and can be initiated how technology examples transfer use of concrete and use pitfalls the associated and in practice to overcome implemented the goal is to motivate opportunities. Amongst others, the innovation and technologyto engage in international stakeholders transfer more TETRAMAX. partbecome of - their experi share will representatives TETRAMAX During the session, - or con investor entrepreneur, founder, as researcher, ences and insights sultant. TETRAMAX: Smart funding for digitalization digitalization for funding Smart TETRAMAX: Industry of Europe’s 72 1230 1200 1215 1130 1145 1100 1115 6.8 WEDNESDAY, 27MARCH 2019WEDNESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 7.2 1600 1530 1500 1430 7.1 1350 1345 7.0 WEDNESDAY, 2019 MARCH 27

technologies Accelerators usingnovel memory LUNCHTIME KEYNOTE SESSION Systems and HPC” Session: Tools and Runtime DaySpecial on “Embedded MeetsHyperscale consisting ofProcessing Elements andmultiple DRAM layers. on Inference proposes a3D-stacked neuromorphic (DCNN) architecture a 3D-stacked Cube). (HybridMemory memory third paperfocusesThe consumption andenergy performance usingnear-data processing on second andimproves onefocuses (HE) the onHomomorphicEncryption use resistive-RAMto accelerate (RRAM) an Automata Processor (AP). The this goal. paper The first focuses onpattern matching andproposes to use novel combination andcomputing ofmemory to achieve elements The sessionfocuses onacceleratingthree complex applications. They all Co-Chair: Andrea Marongiu, Università di Bologna, IT Chair: MladenBerekovic, TU Braunschweig, DE Room 21430 Speaker andAuthor: JoãoM.P. Cardoso, University ofPorto/FEUP, PT Speaker andAuthor: JesusLabarta, Barcelona Supercomputing Center, ES Speaker andAuthor: Jeffrey S Vetter, OakRidgeNational Laboratory, US tasks byraisingthe level ofabstraction for application specification the developer these with support that tools andruntime systems discuss the overallmodeling andoptimizing andefficiency. thissession, In wewill the strength ofeachresourceto exploit applicationtype, partitioning or programmer, handlingdifferent e.g. programming and execution models, use multiplecomputing the resourcesto posesadditionalchallenges Programming andoperating heterogeneous computingthat systems Co-Chair: ChristophHagleitner, Research, IBM CH Chair: ChristianPlessl,Paderborn University, DE Room 11430 Speaker: David Pellerin, Amazon, US Speaker: David Atienza, EPFL, CH Co-Chair: ChristianPlessl,Paderborn University, DE Chair: ChristophHagleitner, Research, IBM CH CEDA byIEEE supported Room 11345 Coffee BreakinExhibition Area status, trendsandopenissues Automatic forFPGAs: coderestructuring current Homogenizing Heterogeneity: theOmpSs approach Computing Extreme Heterogeneity inHighPerformance Intelligent, Cloud-Connected Devices Heterogeneous, HighScale Computing intheEra of CEDAIEEE LuncheonAnnouncement – – – 1600 1600 1420 " SeePage 9 73

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2 and 2 - and Fran , Zili Shao Zili , 2 1 , Alexandros Alexandros , 1 - Dimitris Kon , 3 , Rui Mao Rui , 1 , Jaume Abella , 2 www.date-conference.com , Carles Hernandez Carles , 2 , Arkady Bramnik Arkady , 3 2 , Karyofyllis Patsidis Karyofyllis , 2 Democritus University of Thrace, GR Thrace, of Democritus University 3 , Amelie Chi Zhou , 1 The Chinese University of Hong Kong, HK; of Hong Kong, The Chinese University 2 , Carles Hernandez Carles , 1 , Leonidas Kosmidis Leonidas , , Yi Wang Yi , 1 1 , Yiannakis Yiannakis Sazeides , 1 Barcelona Supercomputing Center, ES Center, Supercomputing Barcelona 2 1600 – 2 2 Barcelona Supercomputing Center, ES Center, Supercomputing Barcelona and Giorgos Dimitrakopoulos and Giorgos 2 3 3 University of Cyprus, CY; CY; of Cyprus, University , Chrysostomos Nicopoulos , 2 2 - ècnica de Cata Polit and Universitat Center Supercomputing Barcelona Supercomputing - Barcelona ècnica de Catalunya Polit Universitat Intel, IL; Intel, University of Florida, US of Florida, University Shenzhen University, CN; Shenzhen University, High-Integrity GPU Designs for Critical Real-Time GPU Designs for Critical High-Integrity Systems Automotive IP3-15 IP3-14, Area Coffee Break in Exhibition Error-Shielded Register Renaming Subsystem for a Subsystem Error-Shielded Register Renaming Core Out-of-Order Scheduled Dynamically in Embedded Codes Error Correction Look-Ahead LAEC: Cache Processors L1 Data Towards Cross-Platform Inference on Edge Devices Inference on Edge Devices Cross-Platform Towards Emerging Neuromorphic Architecture with IP3-13 IP3-12, IP3-11, Area Coffee Break in Exhibition Near-Data Acceleration of Privacy-Preserving of Privacy-Preserving Acceleration Near-Data Memory 3D-Stacked Search with Biomarker Time-division Multiplexing Automata Processor Automata Multiplexing Time-division stantinou cisco Cazorla cisco Jaume Abella 1 1 celona Supercomputing Center, ES Center, celona Supercomputing Alcaide Sergi Authors: cnica de Catalunya - Bar ècnica de Catalunya Polit Universitat Alcaide Portet, Sergi Speaker: Authors: Ron Gabor Ron Authors: Benedicte Pedro Authors: Room 3 1430 Room UA Abu Dhabi, NYU Michail Maniatakos, Chair: GB of Manchester, University Foutris, Nikolaos Co-Chair: processors focuses onThis session first the dependability of out-of-order renaming sub-systemregister andand specifically in the L1 cache. the - to enable ISO26262 ASIL-D com it analyzes the main requirements Then, GPUs. (COTS) Off-The-Shelf Commercial pliance for 3 Speaker: Alvin Oliver Glova, University of California, Santa Barbara, US Barbara, Santa of California, University Glova, Alvin Oliver Speaker: Yuan Xing Hu and Li, Shuangchen Itir Akgun, Glova, Alvin Oliver Authors: US Barbara, Santa of California, University Xie, CN Shenzhen University, Wang, Yi Speaker: Authors: Shangyu Wu Speaker: Jintao Yu, Delft University of Technology, NL Technology, of University Delft Yu, Jintao Speaker: Motta- Abu Lebdeh, Muath Hoang Anh Du Nguyen, Yu, Jintao Authors: NL Technology, of University Delft and Said Hamdioui, Taouil qiallah 1 1 and Tao Li and Tao lunya, ES; ES; lunya, ES; (BSC), Center CPU and GPU microarchitecture dependability Andreou

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 7.5 1600 IPs 1545 1530 1500 1430 7.4 WEDNESDAY, 2019 MARCH 27

system Reliable andPersistent: FromCachetoFile Accelerators Power Delivery Networks toCNN Low Power Design: FromHighly-Optimized comm Technologies, Inc., US 1 1 tems, whilemaintaining crash consistency memory. usingpersistent amplification causedbyfrequently-updated inodesinjournaling filesys- changes andhot/cold pattern varies. to reducethird paperaims write The tive pagemigration decisionsbetweenDRAM andNVRAM asworkload compromisingout cacheperformance. The second paper makes adap the accumulationeliminate ofread disturbancesinSTT-MRAM with- memory. paper proposes anovelThe first to cachedesign completely enhancingreliabilityat ofnon-volatile andperformance cachesandmain This sessionintegrates bothhardware andsoftware optimizations aiming Co-Chair: Alexandre Levisse, EPFL-ESL, CH Chair:Chengmo Yang, University of Delaware, US Room 51430 di Torino,IT Authors: LucaMocerino, Valerio Tenace andAndrea Calimera, Politecnico Speaker: LucaMocerino, Politecnico di Torino, IT 3 Authors: Andrew B. Kahng nology, KR Speaker: SeungwonKim, National Ulsan InstituteofScienceand Tech- Lu WangAuthors: Speaker: Lu Wang, ShanghaiTech University, CN US; Authors: SunikHeo Speaker: MinsooKim, UCSanDiego, US acceleratorer efficient basedonassociativeCNN inference. CAMs for work for 3D integrated systems. Finally,the fourth paperpresents a pow cores. third paper presentsthe While an optimized power delivery net switch capefficiency convertersfrom on-chip for heterogeneous many presents a new formulation and optimizationthe best strategyto get optimization mesh IR node. in an advancedtechnology The second paper the wholedesignstack. paperpresentsThe first aninnovative power The sessionpresents four paperscovering poweroptimizationthrough Co-Chair: Università Andrea diBologna, Bartolini, IT Chair:Pascal Vivet, CEA-Leti, FR Room 41430 1 Chutong Yang qiang Zhou Samadi IP3-16 Coffee BreakinExhibition Area Recurrent Data Reuse Energy-Efficient Convolutional Neural Networks via Wafer Integration Technology Power Delivery Pathfinding forEmergingDie-to- Switched-Capacitor Converters in HeterogeneousMulticore Chips with Integrated ofPowerOptimizing theEnergyEfficiency Supply Staple Insertion inSub-10nmVLSI Detailed DropMitigation Placement forIR byPower Samsung Electronics Co., Ltd., KR; Ulsan NationalUlsan InstituteofScienceand Technology (UNIST), KR; UC SanDiego, US; ShanghaiTech University, CN; 3 UC SanDiego, US 4 andBangqiXu 1 3 – – 1600 1600 1 ,Leilei Wang 2 1 Pohang University ofScienceand Technology, KR; , Andrew Kahng 1 1 , Seokhyeong Kang 2 1 Zhejiang University, CN , DejiaShang 2 University ofCalifornia SanDiego, 2 , MinsooKim 1 , ChengZhuo 2 , SeungwonKim 3 ,Lutong Wang 2 andPing- 3 , Kambiz 4 3 Qual- and 75 - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 1 , Xian- , 1 , Qiuwei Deng , 2 and Hossein Asadi 2 www.date-conference.com - Technol of University Amirkabir , Zhichao Yan , 2 1 , Hamed Farbeh Hamed , 1 University of Texas Arlington, CN Arlington, Texas of University 2 1 , Baiping Wang , 1 1600 – and Duo Liu 1 Chongqing University, CN; Chongqing University, Sharif University of Technology, IR; Technology, of Sharif University Irradiance-Driven Partial Reconfiguration of PV Partial Reconfiguration Irradiance-Driven Panels IP3-17 Area Coffee Break in Exhibition Cost/Privacy Co-optimization in Smart Energy Grids in Smart Co-optimization Cost/Privacy Energy for Distributed Framework A Low-Complexity Smart-Grid Targeting Market Reducing Write Amplification for Inodes of Journaling Journaling of Inodes for Amplification Write Reducing Memory using Persistent Systems File Area Coffee Break in Exhibition UIMigrate: Adaptive Data Migration for Hybrid Non- for Hybrid Migration Data Adaptive UIMigrate: Memory Systems Volatile Enhancing Reliability of STT-MRAM Caches by Caches by STT-MRAM of Enhancing Reliability Accumulation Read Disturbance Eliminating 1 zhang Chen Speaker: Enrico Macii, Politecnico di Torino, IT Torino, di Politecnico Macii, Enrico Speaker: Macii and Massimo Enrico Vinco, Sara Daniele Jahier Pagliari, Authors: IT Torino, di Politecnico Poncino, Speaker: Kostas Siozios, Dept. of Physics, Aristotle University of Thes- of Aristotle University Dept. of Physics, Siozios, Kostas Speaker: GR saloniki, Department of Physics, Siozios and Stylianos Siskos, Kostas Authors: GR Thessaloniki, of Aristotle University Room 6 1430 Room IT Verona, of Quaglia, University Davide Chair: IT Torino, di Politecnico Massimo Poncino, Co-Chair: to optimizing smart approaches - three grid and photovol In this session, and privacy. efficiency, cost, targeting presented, taic systems are DE TUM, Alma Proebstl, Speaker: Sebastian Steinhorst and Sa- Sangyoung Park, Alma Proebstl, Authors: DE TUM, marjit Chakraborty, Speaker: Xianzhang Chen, Chongqing University, CN University, Chongqing Xianzhang Chen, Speaker: Wenbin Zhang, Runyu Xianzhang Chen, Duo Liu, Yang, Chaoshu Authors: CN Chongqing University, Tan, Yujuan Moming Duan and Wang, Speaker: Duo Liu, College of Computer Science, Chongqing University, CN Chongqing University, Science, of Computer College Duo Liu, Speaker: Tan Yujuan Authors: Speaker: Hossein Asadi, Sharif University of Technology, IR Technology, of Sharif University Hossein Asadi, Speaker: Elham Cheshmikhani Authors: ogy, IR 1 Optimization of Smart Energy Systems Energy of Smart Optimization

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Systems Toward CorrectandSecureEmbedded 1 1 University, Lahore, PK 1 Jian-Jia Chen, Technical University ofDortmund, DE Authors: Kuan-Hsun Chen, NiklasUeter, Georg von and derBrüggen Speaker: Kuan-Hsun Chen, TU Dortmund, DE Authors: Imran Abbasi Speaker: Imran Abbasi, NUST, PK Authors: Hyunyoung Oh Speaker: Hyunyoung Oh, SeoulNational University, KR Authors: Faiq Khalid Speaker: Faiq Khalid, ofcomputer engineering, Department TU Wien, AT Authors: Ring Martin hardware Trojanattacks. chine learningalgorithmsfrom adversarial attacks, andzero-footprint behavioralefficient analysisofmalware, improved ofma- protection ness enforcementthe field. in to be topics explored The security include topics explored includeverification of execution deadlinesand correct tems withstrong assurances ofcorrectness andsecurity. The correctness This sessionwillexplore noveltechniques for developing embeddedsys- Co-Chair:Falcone, Ylies University Grenoble Alpes, FR Chair: ToddAustin, University ofMichigan, US Room 71430 Sungroh Yoon Axel Jantsch 1 Junaid Qadir Wille of Waterloo,CA IP3-18 Coffee BreakinExhibition Area Area Footprint Undetectable Hardware Trojanswith ZeroPower and TrojanZero: Switching Activity-Aware Designof Models with aGPU-inspiredEngineforMachineLearning Real-Time Anomalous Branch Behavior Inference Noise Filtering onAdversarial MachineLearning FAdeML: UnderstandingtheImpact ofPre-Processing and Potential Pitfalls Efficient Computation ofDeadline-MissProbability Systems AfterDeployment Better Late Than Never Verification ofEmbedded University ofBremen, DE; NUST, PK; Seoul National University, KR; Vienna University of Technology (TU Wien), AT; 2 andRolf Drechsler 2 Vienna University of Technology (TU Wien), AT; 2 2 , Garg Siddharth andMuhammadShafique 1 – and Yunheung Paek 1600 1 , MuhammadAbdullahHanif 1 , Fritjof Bornebusch 1 , Faiq Khalid 1 1 ,Hayoon Yi 2 Johannes Kepler University Linz, AT 3 andMuhammadShafique 2 Soongsil University, KR 1 2 , SemeenRehman 1 , Hyeokjun Choe 1 1 , ChristophLüth 2 Information Technology 1 , SemeenRehman 1 , YeongpilCho 2 , Awais Kamboh 2 1 3 , Robert University 2 , 1 77 , 1 , -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - , Ser , 1 , Davide Davide , 1 , Ernesto Sanchez , 1 www.date-conference.com , Andrea Floridia Andrea , 1 2 , Annachiara Ruospo Annachiara , 1 1600 – STMicroelectronics, IT STMicroelectronics, , Riccardo Cantoro Riccardo , 2 1 1630 – and Alessandro Sansonetti and Alessandro 2 , Cozmin Pogonea Cozmin , 1 Politecnico di Torino, IT; IT; Torino, di Politecnico Non-Intrusive Self-Test Library for Automotive Critical Critical Automotive for Library Self-Test Non-Intrusive and Solutions Constraints Applications: Pipeline Intra-Unit Dependency-Resolving Multipliers High-Throughput for Architecture with Multiplier Logarithmic A Hardware-Efficient Accuracy Improved Inspiring Futures @ Infineon Technologies @ Infineon Inspiring Futures @ Cadence Inspiring Futures @ eSilicon Inspiring Futures Area Coffee Break in Exhibition Academia or Industry? - or everything! Career and everything! - or Academia or Industry? by HiPEAC powered opportunities internship career in an ever-changing to kick start your How world gio De Luca Speaker: Dae Hyun Kim, Washington State University, US University, State Washington Dae Hyun Kim, Speaker: US University, State Washington Jihee Seo and Dae Hyun Kim, Authors: Univer and Jie Han, Bruce Cockburn Mohammad Saeed Ansari, Authors: Speaker: Ernesto Sanchez, Politecnico di Torino, IT Torino, di Politecnico Ernesto Sanchez, Speaker: Bernardi Paolo Authors: Speaker: Fernando De Bernardinis, eSilicon, IT eSilicon, De Bernardinis, Fernando Speaker: 1600 Area Poster supported Academic Network by Cadence 30-minute slot. run simultaneously during a Presentations Interactive - presen one-minute a in IPeach introduced briefly is paper Additionally, session. regular in a corresponding tation CA sity of Alberta, Speaker: Antonella Magliocchi, University of Pisa, IT of Pisa, University Magliocchi, Antonella Speaker: AT Technologies, Infineon Simone Fontanesi, Speaker: DE Design Systems, Cadence Klotz, Anton Speaker: Speaker: Xavier Salazar, Barcelona Supercomputing Center, ES Center, Supercomputing Barcelona Salazar, Xavier Speaker: Exhibition Theatre 1430 Theatre Exhibition Organisers: IT of Pisa, University Luca Fanucci, IT of Pisa, Massai, University Rossano ES Center, Supercomputing Barcelona Salazar, Xavier IT of Pisa, University Luca Fanucci, Moderator: aims session This bring to recruiters –together large companies mostly centres – and research as well as universities with potential and small, and HiPEAC. by DATE in the jobseekers technology covered areas will be to The progamme tailored - the needs of and re the students Itsearchers. will include: recruitment for officer by and mentoring the HiPEAC insights career university a local advisor from activities and a careers pitches company networking informal time for 1 Interactive Presentations Interactive Inspiring futures! Careers Session @ DATE @ DATE Session Careers Inspiring futures! (part 1) Piumatti • • • 78 IP3-3 IP3-2 IP3-1 1600 IP3 1545 1515 1530 1430 1445 7.8 WEDNESDAY, 27MARCH 2019WEDNESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com IP3-13 IP3-12 IP3-11 IP3-10 IP3-9 IP3-8 IP3-7 IP3-6 IP3-5 IP3-4 WEDNESDAY, 2019 MARCH 27 far Kuttanna ment ofInformationment Engineering, University ofPadua, IT 1 1 Authors: Lorenzo Ferretti Speaker: Lorenzo Ferretti, Università dellaSvizzera italiana, CH Authors: PhilippMayer, Raphael Strebel andMicheleMagno, ETH Zurich, CH Speaker: MicheleMagno, ETH Zurich, CH University, KR Authors: Jung-Woo Chang, Keon-Woo Kang andSuk-Ju Kang, Sogang Speaker: Suk-Ju Kang, SogangUniversity, KR mad Shafique, Vienna University of (TU Technology Wien), AT Authors: Marchisio, Alberto MuhammadAbdullahHanifand Muham- Speaker: Marchisio, Alberto Vienna University of Technology (TU Wien), AT Authors: DipanKumar Mandal Speaker: DipanKumar Mandal, Intel Corporation, IN Universität Dresden, DE Authors: Fischbach, Robert Tilman andJensLienig, Horst Technische Speaker: Tilman Horst, Technische Universität Dresden, DE Authors: Florenc Demrozi rona, IT Speaker: Graziano Pravadelli, ofComputer Science, Dept. Univ. of Ve- Authors: YuanqiShen Speaker: HaiZhou, University, Northwestern US Technology Kanpur, IN Authors: DeepakSirone andPramod Subramanyan, IndianInstituteof Speaker: Pramod Subramanyan, IndianInstitute of Technology Kanpur, IN versity ofNaplesFederico II, IT Authors: Alessandro Cilardo, Mirko Gagliardi and Vincenzo Scotti, Uni- Speaker: Alessandro Cilardo, CeRICT, IT Sreenivas Subramoney 1 1 Graziano Pravadelli preet SKalsipreet network accelerator onFPGA SDCNN: Anefficient sparse deconvolutional neural CapsuleNets with Data Reuse CapsAcc: AnEfficient Hardware Accelerator for and Power Software Co-designApproachforUltra-low Latency OdometryAttheEdge-AHardware-Visual Inertial Transfer Printing Heterogeneous Systems Manufactured byMicro- Assembly-Related Chip/Package Co-Designof the freezingofgait inParkinsonians An indoorlocalization system todetectareascausing Based Epilepsy Monitors Tailoring SVM InferenceforResource-Efficient ECG- and Wearable Applications Communication andSensingforInternet ofThing ZeroPowerTouch: Zero-Power Smart Receiver forTouch Encryptions SigAttack: New High-level SAT-based AttackonLogic Functional Analysis Attacks onLogicLocking in heterogeneousmanycore accelerators Lightweight hardware support forselective coherence Northwestern University,Northwestern US; Intel Corporation, IN; ofComputer Science,Department University of Verona, IT; USI Lugano, CH; 2 , David Atienza 2 1 , BijiGeorge 2 EPFL, CH; 2 , Leila Cammoun 1 1 2 , YouLi 1 Intel Corporation, US ,Hong Wong 1 1 1 , Giovanni Ansaloni , GopiNeela ,Bragoi Vladislav 3 Centre HospitalierUniversitaire Vaudois, CH 1 , ShuyuKong 2 1 northwestern university,northwestern CN , Srivatsava Jandhyala 3 2 andPhilippeRyvlin , LanceHacking 1 , Santhosh Kumar Rethinagiri 2 1 , AminRezaei ,Federico Tramarin 1 , Laura Pozzi 2 1 andBelliappa , OmJOmer 3 1 andHaiZhou 1 , AmirAmini- 2 Depart 2 and 1 , Gur - 1 , 79 - 1

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - 1 3 2 and Vasilis and Vasilis 2 and Ben Gu 3 and Joerg Henkel and Joerg - Design Sys Cadence 2 - of Man The University 3 3 www.date-conference.com and Olivier Sentieys 1 , Zhiyu Zeng , 2 Vienna University of Technology Technology of University Vienna 2 , Xin Li , 1 Qualcomm, IE; Qualcomm, INRIA, FR 2 2 , Przemyslaw Mroszczyk Przemyslaw , 1 Duke University, US; US; University, Duke 2 , Muhammad Shafique Muhammad , 1 , Angeliki Kritikakou , 1 , Wenjian Yu Wenjian , 1 1830 – 3 University of Manchester, GB; GB; of Manchester, University CN; University, Tsinghua Univ Rennes/IRISA/INRIA, FR; Karlsruhe Institute of Technology, DE; DE; Technology, Institute of Karlsruhe Panelists: Assertion-Based Verification through Binary through Binary Verification Assertion-Based Instrumentation Adaptive Word Reordering for Low-Power Inter-Chip Inter-Chip for Low-Power Reordering Word Adaptive Communication for Power Ordering Matrix Machine-Learning-Driven Grid Analysis Fine-Grained Hardware Mitigation for Multiple Long- for Multiple Mitigation Hardware Fine-Grained Units on VLIW Function Transients Duration A Fine-Grained Soft Error Resilient Architecture under under Architecture Error Resilient Soft A Fine-Grained Considerations Power 1 1 1 ample, embedded systems have used heterogeneous architectures with architectures used heterogeneous systems have embedded ample, long a very time due to strict for or ef realtime co-processors specialized studied extensively community has the EDA Hence, constraints. ficiency and optimization analysis, application algorithms and tools for models, designed to are applications HPC and datacenters In contrast, operation. but homoge- parallel massively harvest the performance of networked, with our experts will debate In this panel, resources. neous computing can and embedded communities what the datacenter the audience, each other. learn from NVidia, US NVidia, Messmer, Peter IT di Bologna, Luca Benini, Università GB of Edinburgh, Boris Grot, University CH Zurich, IBM Lunteren, Research Jan van US Laboratory, Oak Ridge National Vetter, S Jeffrey ES Center, Jesus Labarta, Supercomputing Barcelona PT of Porto/FEUP, University Cardoso, P. João M. CH EPFL, Babak Falsafi, Room 1 1700 Room Co-Chairs: CH Zurich, IBM Research Christoph Hagleitner, DE University, Christian Plessl, Paderborn technologies and HPC/datacenter origins, Despite different very their ex challenges similar computing.embedded than For face applications Speaker: Laurence Pierre, Univ. Grenoble Alpes, FR Alpes, Grenoble Univ. Pierre, Laurence Speaker: Grenoble Lab (Univ. TIMA Pierre, Brignon and Laurence Enzo Authors: FR INP), Grenoble CNRS, Alpes, Speaker: Wenjian Yu, Tsinghua University, CN University, Tsinghua Yu, Wenjian Speaker: Ganqu Cui Authors: Speaker: Angeliki Kritikakou, University of Rennes 1 - IRISA/INRIA, of Rennes University FR Angeliki Kritikakou, Speaker: Psiakis Rafail Authors: GB of Manchester, University Eleni Maragkoudaki, Speaker: Eleni Maragkoudaki Authors: Speaker: Sajjad Hussain, Chair for Embedded Systems, KIT, Karlsruhe, DE Karlsruhe, KIT, Embedded Systems, Chair for Sajjad Hussain, Speaker: Sajjad Hussain Authors: Pavlidis (TU Wien), AT (TU Wien), 1 Special Day on “Embedded Meets Hyperscale “Embedded Meets Hyperscale on Special Day can HPC and What Panel: and HPC” from embedded computing learn hyperscale chester, GB chester, tems, Inc., US Inc., tems, 80

8.1 IP3-18 IP3-17 IP3-16 IP3-15 IP3-14 WEDNESDAY, 27MARCH 2019WEDNESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1815 1800 1730 1700 8.2 WEDNESDAY, 2019 MARCH 27 sish Mitra signal, security andsoftware verifying Systems-on-Chip: digital, mixed- Session:Special Innovative methodsfor Universita 1 mon 1 Authors: Georges Gielen Speaker: Georges Gielen, KU Leuven, BE Authors: Eshan Singh Speaker: SubhasishMitra, Stanford University, US Authors: MohammadRahmani Fadiheh Speaker: Wolfgang Kunz, University ofKaiserslautern, DE Authors: Cox Henry Chen, and Harry MediaTek, US Speaker: Cox, Henry MediaTek, US DATE research community. above) design verificationthat address –major directions must the for the newchallenges(stated also onlydesignbugsbut will discussnot importantly,insurmountable outstandingchallenges.Most this session approachesto overcome from andacademia industry these seemingly ofcomplexnent Systems-on-Chip). This specialsessionfocuses onnovel software complexity (firmware andsoftware form asignificant compo- hardware designs), for systemsafety automotive (e.g. applications), and the recent Spectre/Meltdown security (e.g. attacks stemming from problems are exacerbated byeven challenges: more hardware difficult computationtimes andmay failto capturethe system. allbugsin These true nightmare.tion is a Traditionaltechniques require extremely long blocks, etc. While designingsuchchipsisahugeeffort, their verifica- tors, multiplecores andmemories, several analog andmixed-signal Modern-day integrated circuits cancontain severaltransis billionsof - Co-Chair: Giovanni DeMicheli,EPFL, CH Chair: Schlichtmann,TUM, Ulf DE Georges Gielen,KU Leuven, BE Subhasish Mitra, Stanford University, US Organisers: Room 21700 Universita Stoffel Mitra 1 Universita Subhasish Mitra Analog Verification inMixed-Signal SOCs Review ofMethodologies forPre-andPost-Silicon Microcontroller Cores: Industrial CaseStudy Symbolic QEDPre-siliconVerification forAutomotive Detection byUniqueProgram Execution Checking Processor Hardware Security Vulnerabilities andtheir an algorithm-to-firmware development methodology Hardware andfirmware verification and validation: KU Leuven, BE; Stanford University, US; University ofKaiserslautern, DE; 3 , Ralf Schnieder 1 4 , WolfgangKunz 2 t Kaiserslautern,t DE; t Kaiserslautern,t DE; t Munchen,t DE – 2 1830 2 Stanford University, US and Wolfgang Kunz 3 1 , Karthik Ganesan , Keerthikumara Devarajegowda 4 , ClarkBarrett 1 2 , NektarXama Infineon AG/TechnischeTechnologies 5 3 Infineon AG/TechnischeTechnologies Infineon Technologies, DE; 2 Stanford University, US 1 1 , WolfgangEcker 1 1 1 , MohammadFadiheh , Karthik Ganesan , DominikStoffel 2 , SebastianSi- 5 andSubhasish 1 , ClarkBarrett 2 4 andSubha- Technische 4 , Dominik 81 2 ,

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 -

3 - 2 and 1 University University 3 , Ahmed , 2 , Arani Sinha Arani , 2 and Xuan and Xuan 1 and Smail Niar 1 , Bernd Becker , 3 Intel, US Intel, 3 , Jan Burchard , , Dian Zhou , www.date-conference.com 1 2 , Sudhakar Reddy Sudhakar , 1 , Hai Zhou , 1 University of Valenciennes and Hainaut- Valenciennes of University , Morteza Biglari-Abhari , 2 Mentor, a Siemens Business, DE; DE; a Siemens Business, Mentor, 3 1 2 , Irith Pomeranz , University of Iowa, US; US; of Iowa, University Northwestern University, US Northwestern University, 1 2 , Benjamin Thiemann , 2 , Wunderlich Hans-Joachim , 1 3 , Changhao Yan , 1 1830 1830 1 – – , Natalia Lylina Natalia , 3 1 University of Auckland, NZ; NZ; of Auckland, University CN; University, Fudan University of Freiburg, DE; DE; of Freiburg, University US; University, Purdue Adaptive Vehicle Detection for Real-time Autonomous for Real-time Autonomous Detection Vehicle Adaptive System Driving Walk Solver Random FPGA-based Floating An Efficient using SDAccel Extraction for Capacitance Resynthesis for Avoiding Undetectable Faults Based Faults Undetectable for Avoiding Resynthesis Guidelines on Design-for-Manufacturability Circuits for Approximate Generation Pattern Test Satisfiability Based on Boolean On Functional Test Generation for Deep Neural for Deep Neural Generation Test On Functional IPs Network Scan Networks in Reconfigurable Flow On Secure Data Atteya of Stuttgart, DE of Stuttgart, 1 1 Zeng and Venkataraman Srikanth Matthias Sauer Matthias Cambresis, FR Cambresis, 1 ping deep neural networks to multi-FPGA platforms. to multi-FPGA networks ping deep neural NZ of Auckland, The University Hemmati, Maryam Speaker: Hemmati Maryam Authors: CN University, Fudan Wei, Xin Speaker: Authors: Xin Wei Speaker: Anteneh Gebregiorgis, Karlsruhe Institute of Technology, DE Technology, Institute of Karlsruhe Gebregiorgis, Anteneh Speaker: Institute Karlsruhe Tahoori, and Mehdi B. Gebregiorgis Anteneh Authors: DE of Technology, 4 1700 Room GB Warwick, of University Suhaib Fahmy, Chair: DE University, Paderborn Platzner, Marco Co-Chair: of papers the state the artthatthree advance This session presents in and circuit analysis, driving, autonomous for applications FPGA-based on map presentation and one interactive processing, time-series data Speaker: Naixing Wang, Purdue University, US University, Purdue Wang, Naixing Speaker: Authors: Naixing Wang Speaker: Bo Luo, The Chinese University of Hong Kong, HK of Hong Kong, University The Chinese Bo Luo, Speaker: The Chinese Univer and Qiang Xu, Wei Lingxiao Li, Yu Bo Luo, Authors: HK sity of Hong Kong, DE of Freiburg, University Raiola, Pascal Speaker: Raiola Pascal Authors: Room 3 1700 Room IT Torino, di Politecnico Sonza Reorda, Matteo Chair: PL Business, A Siemens Mrugalski, Mentor, Grzegorz Co-Chair: im- of increasing are Circuits and Approximate Networks Deep Neural new challenges pose completely They portance applications. in many these chal- with respectto face approaches Promising to test generation. Scan Networks 1 and 4. Reconfigurable by papers presented lenges are vali- test, for post-silicon access allow flexible to embedded instruments security and debug or diagnosis. On the other hand dation this creates an approach 2 provides account. Paper into issues to be thattaken have testability is improving for Resynthesis flow. data secure to guarantee the of paper 3. topic 1 Applications of Reconfigurable Computing of Reconfigurable Applications Test Preparation and Generation and Preparation Test 82 1730 1700 8.4 1815 1800 1730 1700 8.3 WEDNESDAY, 27MARCH 2019WEDNESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 8.6 IPs 1800 1730 1700 8.5 IPs 1800 WEDNESDAY, 2019 MARCH 27

Robotics andIndustry 4.0 Don’t ForgettheMemory Hong Kong, HK cal University, CN; 1 sults aswellevaluation ofrelevant use-cases. 4.0. to Industry cal systemsapplied theoreticalThe sessionincludes re- This sessionpresents newresultsthe fieldof robotics andcyberphysi in - Co-Chair: ArminSchoenlieb, Infineon Technologies, AT Chair: Federica Ferraguti, University of Modena-Reggio, IT Room 61700 Zhao, Wuhan National Labfor Optoelectronics, CN Authors: HongweiQin, DanFeng, Wei Tong, JingningLiuand Yutong versity, CN of China, SchoolofComputer Scienceand Technology, HuazhongUni- Center ofdata storage systemsand Technology, ofEducation Ministry Key Laboratory ofInformation Storage System, EngineeringResearch Speaker: HongweiQin, Wuhan National Laboratory for Optoelectronics, Wang, National University ofDefense Technology, CN Authors: ShengMa, Yang Guo, Chen, Shenggang LiboHuangandZhiying Speaker: ShengMa, National University ofDefense Technology, CN Authors: Lei Han Speaker: Zhaoyan Shen, ShandongUniversity, CN read caches. the session with a new cache replacementpletes algorithm for NVM disk lookup structures. indeepdirectory Aninteractive presentation com - third presentation proposesto improve anewmethod entry directory multicore locality.the mainmemory requeststo maintain memory The mentation. The second presentation proposesto orchestrate a method tation improvesthe parallelismthe Open-Channel SSD Linux imple- of different proposals covering memory, storage, andOS. presen- Thefirst traditionalthe system. memory suitable placein This sessionshowcases to finda technologies stillneed gapandemergingmemory memory to overcomeMulti-core systemsdemandnewsolutions the increasing Co-Chair: OlivierSentieys, FR INRIA, Chair: ChristianPilato, Politecnico diMilano, IT Room 51700 Authors: MaelGueguen Speaker: MaelGueguen, UnivRennes, Inria, CNRS, IRISA, FR 1 IP4-2, IP4-3 IP4-1 Open-Channel SSDs QBLK: Towards Fully Exploiting theParallelism of Multiplication onMulticore Accelerators Improving forMatrix theDRAMAccessEfficiency with Prefix-Awareness forMobile Devices DS-Cache: ARefinedDirectoryEntry Lookup Cache constraints onFPGA Accelerating Itemsetsampling usingsatisfiability Univ Rennes, CNRS, IRISA, FR; The HongKong Polytechnic University, HK; – – 1830 1830 1 , BinXiao 3 Shandong University, CN; 1 , OlivierSentieys 1 , Xuwei Dong 2 INRIA, FR INRIA, 2 2 , Zhaoyan Shen andAlexandre Termier 2 Northwestern Polytechni- Northwestern 4 The ChineseUniversity of 3 andZili Shao 1 83 4

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - , Cesare Cesare , , Gerald Gerald , 1 2 and Gerd and Gerd 1 and Nobuhiko and Nobuhiko 3 The University of The University 3 University of Ferrara, IT of Ferrara, University , Cristian Secchi Cristian , 2 www.date-conference.com 1 , Shinpei Kato , , Christian Steger , , Andre Guntoro Andre , 2 1 1 2 Saitama University, JP; Saitama University, 1 è , Takuya Azumi Takuya , , Andrea Pertosa Andrea , 2 Graz University of Technology, AT Technology, of University Graz , Hannes Plank , 1 1 2 1 RWTH Aachen University, DE Aachen University, RWTH 2 , Jannik Springer , 1 , University of Ferrara, IT of Ferrara, University , è 1830 – and Marcello Bonf and Marcello and Norbert Druml 1 2 1 1 Robert Bosch GmbH, DE; DE; Robert Bosch GmbH, Ritsumeikan University, JP; University, Ritsumeikan University of Modena and Reggio Emilia, IT; IT; Emilia, and Reggio of Modena University AT; Technologies, Infineon Multi-objective Precision Optimization of Deep Neural Neural Deep of Optimization Precision Multi-objective for Edge Devices Networks and Optimization Design Space Exploration Towards Networks Neural for Convolutional Algorithms of Fast (CNNs) on FPGAs with Networks Pattern Local Binary Accelerating FPGAs Programmable Software IP4-9 IP4-8, IP4-7, Self-Supervised Quantization of Pre-Trained Neural Neural of Pre-Trained Quantization Self-Supervised Acceleration for Multiplierless Networks Communication-Computation co-Design of co-Design Communication-Computation in CPS Applications Chain Task Decentralized in ROS Performance Scalable for Resource Manager Environments Distributed IP4-6 IP4-5, IP4-4, Hybrid Sensing Approach For Coded Modulation For Coded Modulation Sensing Approach Hybrid Cameras Time-of-Flight A methodology for comparative analysis of analysis for comparative A methodology 4.0 Industry robots for collaborative Tokyo, JP Fantuzzi Holweg 1 Speaker: Muhammad Adeel Pasha, LUMS, PK LUMS, Adeel Pasha, Muhammad Speaker: Department of Ahmad and Muhammad Adeel Pasha, Afzal Authors: PK LUMS, SBASSE, Electrical Engineering, US UC San Diego, Jeng-Hau Lin, Speaker: Tu and Zhuowen Vahideh Akhlaghi, Lotfi, Atieh Jeng-Hau Lin, Authors: US UC San Diego, Gupta, Rajesh Speaker: Nhut-Minh Ho, National University of Singapore, SG of Singapore, University National Ho, Nhut-Minh Speaker: National Wong, Weng-Fai and Vaddi Ramesh Ho, Nhut-Minh Authors: SG of Singapore, University Speaker: Sebastian Vogel, Robert Bosch GmbH, DE Robert Bosch GmbH, Vogel, Sebastian Speaker: Authors: Sebastian Vogel Room 7 1700 Room NL IMEC-NL, Sandeep Pande, Chair: Technology Institute of Science and Lee, Ulsan National Kyuho Co-Chair: KR (UNIST), challenges research papers various that address This session presents multi- devices, edge for networks neural deep of optimization including of CNNs design space exploration network acceleration, plierless neural on FPGAs. networks local binary pattern and accelerating on FPGAs Speaker: Eli Bozorgzadeh, University of California, Irvine, US Irvine, of California, University Eli Bozorgzadeh, Speaker: Univer Solmaz Kia, and Eli Bozorgzadeh Ahmad Razavi, Seyyed Authors: JP University, Ritsumeikan Fukutomi, Daisuke Speaker: Fukutomi Daisuke Authors: Speaker: Armin Schoenlieb, Infineon Technologies, AT Technologies, Infineon Armin Schoenlieb, Speaker: Armin Schoenlieb Authors: Speaker: Marcello Bonf Marcello Speaker: US Irvine, sity of California, Authors: Federica Ferraguti Federica Authors: 1 1 1 Embedded hardware architectures for deep architectures Embedded hardware networks neural Nishio Ascheid

84 IPs 1815 1800 1730 1700 8.7 IPs 1815 1800 1730 1700 WEDNESDAY, 27MARCH 2019WEDNESDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com Party 1745 1730 1715 1700 8.8 WEDNESDAY, 2019 MARCH 27 • • • DATE |Networking Party Event 2) (part futures!Inspiring CareersSession @DATE 1930 –2300 Speaker: NeslihanKose Cihangir, Intel, DE Speaker: Camila Giunti, IngeniArs, IT Speaker: JanAndersson, Cobham Gaisler, SE Speaker: EluisaGhilardi, Microtest, IT Exhibition Theatre 1700 time for informal networking company pitches andacareersactivities advisorfrom alocal university career insightsthe HiPEAC andmentoring by officer for recruitment willinclude: searchers. It the students andrethe needsof - tailoredThe progammeto willbe areas coveredtechnology jobseekersthe in byDATE andHiPEAC. and small, withpotential aswelluniversities andresearch centres – mostly companies largetogether recruiters – to bring This session aims Moderator: LucaFanucci, University ofPisa, IT Xavier Salazar, Barcelona Supercomputing Center, ES Rossano Massai,University ofPisa, IT Luca Fanucci, University ofPisa, IT Organisers: Inspiring FuturesInspiring @Intel FuturesInspiring @IngeniArs FuturesInspiring @Cobham Gaisler FuturesInspiring @Microtest – 1830 " SeePage 13 85

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - -

In- 1 2 3 Uni- 3 , Francesco Francesco , 2 HKUST, CN; HKUST, 2 and Wei Zhang Wei and 3 , Philippe Coussy , 1 www.date-conference.com , Mohammed Shayan , 2 , Sharad Sinha Sharad , 2 ALaRI, CH ALaRI, 3 2 NYU, US; US; NYU, 2 , Kanad Basu Kanad , , Jean-Christophe Le Lann Jean-Christophe Le , 1 1 Universite de Bretagne-Sud / Lab-STICC, FR; FR; / Lab-STICC, de Bretagne-Sud Universite 2 , Tingyuan Tingyuan Liang , 1 3 1000 1000 – – and Ramesh Karri and Ramesh 3 Hong Kong University of Science and Technology, HK; Technology, of Science and University Hong Kong ENSTA Bretagne, FR; FR; Bretagne, ENSTA IT; di Milano, Politecnico High-Level Synthesis of Benevolent Trojans of Benevolent Synthesis High-Level Congestion Machine Learning Based Routing Synthesis in FPGA High-Level Prediction IP4-13 IP4-12, IP4-11, IP4-10, Area Coffee Break in Exhibition Transient Key-based Obfuscation for HLS in an Obfuscation Key-based Transient Environment Cloud Untrusted in Exhibition Area Coffee Break in Exhibition Model Based Design at THALES: The current status status The current THALES: Model Based Design at challenges and new and AI, Controls, Model-Based Design for Systems in Intelligent Communications software, TWINSCAN of Development Model Driven from scratch not but versité Bretagne Sud, FR Sud, Bretagne versité and Guy Gogniat dian Institute of Technology Goa, IN Goa, Technology dian Institute of 1 1 Speaker: Jieru Zhao, HKUST, CN HKUST, Jieru Zhao, Speaker: Jieru Zhao Authors: Speaker: Hannah Badier, ENSTA Bretagne, Lab-STICC, Brest, FR Brest, Lab-STICC, Bretagne, ENSTA Hannah Badier, Speaker: Hannah Badier Authors: IT di Milano, Politecnico Pilato, Christian Speaker: Christian Pilato Authors: Room 2 0830 Room JP Technology, Institute of Tokyo Hara-Azumi, Yuko Chair: ES UPC, Jordi Cortadella, Co-Chair: (HLS) used be can synthesis to high-level how show we In session, this to predict IPsprotected information the out and exploitto high-level Speaker and Author: Pieter Mosterman, Mathworks, US Mathworks, Mosterman, Pieter and Author: Speaker NL ASML, Schiffelers, Ramon and Author: Speaker IP model of a high-level the protection of design. First, the physical come is discussed by using functional lock context in a cloud-based synthesis Trojans of hardware how the concepts talk investigates The second ing. is approach to IPs.can be used during HLS A novel to add watermarks dur level at physical congestion then proposed to estimate the routing how discusses to estimate the presentation The interactive ing HLS. the hardware/software performance for cost and the software hardware interface. Room 1 0830 Room SE KTH, Sander, Ingo Chair: NL Technology, of University Stuijk, Eindhoven Sander Co-Chair: FR Thales, Rioux, Laurent and Author: Speaker 1 High-Level Synthesis High-Level Special Day on “Model-Based Design of Design “Model-Based on Special Day Experiences Session: Systems” Intelligent design at model-based from the trenches, work Regazzoni

86 IPs 0930 1000 0900 0830 1000 9.2 0930 0900 0830 9.1 THURSDAY, 28MARCH 2019 THURSDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 0900 0830 9.3 THURSDAY, 2019 MARCH 28 Secure OpenHardware Session:Special RISC-VorRISK-V? Towards 1 Authors: IliaLebedev Speaker: Ilia Lebedev, MIT, US Stefan Mangard, Graz University of Technology, AT Authors: Thomas Unterluggauer, Schilling, Robert Mario Werner and Speaker: Stefan Mangard, Graz University of Technology, AT RISC-V andanapplication example usingaRISC-V basedSOC. andfault attack resistantof side-channel accelerators ofcrypto basedon ments withsecure (TEE) hardware enclavesthe RISC-V, basedon design on RISC-V, open-source projects fortrusted execution building environ- entations ranging from isolated on-oroff-chip secure elements based ditional asahardware securitymodule. The sessionconsists offour pres- fora SOC both,the data processing asamulticore systemandonead- an application example where RISC-V based processors are integrated in system willbecoveredtalk. third the presentation by The last willgive tographic operations.to integrate How securitycoprocessors inaRISC-V tation. Securitymodulesusuallyneedaccelerators for standardized cryp security by newconcepts. This area will be coveredthe second by presen- open source hardware offers toimprove project newchances enclave's the knownapproachesthis areaWhile all in havethe knownweaknesses standardtrusted execution processors suchas environments orenclaves. hardware attacks. RISC-V currently lacks securityfeatures provided in talkwill give an tosecureRISC-Vfirst example how processors against into SOCs, offering transparent anchor a trust opensource for SOCs. The an idealopensource secure element, whichcanbeeasilyintegrated attacks. RISC-V processors hardware hardened against attacks could be dedicated whichishardened against securitymodulewithitsownCPU hardware basedonRISC-V.trendthe integration A inmodernSoCsis ofa This specialsessionfocuses onchancesandrisks offered byopensource both architectural andmicroarchitectural securitysolutionsisrequired. RISC-V becomes asecurityRISK-V, more research anddevelopment in plementationsthreatto avoid onoursystems.Inorder poseamajor that the other hand unsecuresecure solutions. On RISC-V and performant im- nity inbothhardware andsoftwaretogether, to muchmore yielding the development ofcountermeasuresto awideresearch open commu- software,their originisinhardware. while Opensource hardware allows michroarchitecture security problems in closed source hardware with Currentlysuch asMeltdownorSpectre. researchers the to fix often try tations. Suchimplementations microarchitectural resist must attacks driverto createcould beafurther opensource secure RISC-V implemen- coprocessorsto bechecked able the source bymany level. usersat This of open source hardware with hardware security extensions and secure still amainconcernthis architecture. RISC-V in allowsthe development attention ofresearch andindustrial communities; however securityis which enablesanewera of processor innovation. RISC-V hascaptured ized RISC-V SOCs. architecture isafree (ISA), set andopeninstruction towardsa path anultra-fast designcycle for complex andhighlycustom- softwarethat developers aretoday. doing Opensource hardware opens verified,could select opensource hardware blocks thesamemanner in complex, highlycustomized SoCs, willbedesirable SoCdesigners that it ponents from different providers. tobuilding comes Especially whenit variety ofcomplex integratethat SoCs hardware heterogeneous IP com - intelligence are thedevelopmentThings andartificial pushing ofawide quirements oflargely diverse applications. Cloudcomputing, Internet-of- computingthe re andSystem-on-Chip - to meet (SoC)designapproaches The end of Moore'sthe renewed law is pushing interest on entirely new Chair: GeorgSigl,TUM,DE Room 30830 Dayeol Lee enclaves Sanctorum: Alightweight security monitor forsecure Channel Attacks Protecting RISC-VProcessorsagainst Physical Side MIT, US; 2 UC Berkeley, US 2 , KrsteAsanovic – 1000 1 , Kyle Hogan 2 , DawnSong 1 , JulesDrean 2 andSrinivas Devadas 1 , David Kohlbrenner 1 2 , 87 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - , 1 1 and Johanna and Razvan Bu- and Razvan 1 2 www.date-conference.com 2 and Matthias Hiller and Matthias 2 , Daniel Mueller-Gritschneder Daniel , 1 Ohio University, US Ohio University, 2 , Avinash Karanth Avinash , , Ulf Schlichtmann , 1 2 , Uzair Sharif Uzair , 1 Fraunhofer IIS / EAS, DE IIS / EAS, Fraunhofer and Zhonghai Lu 2 1 , Christian Skubich Christian , 1 , Ahmed Louri , 1 1000 – KTH Royal Institute of Technology, CN Technology, Institute of Royal KTH 2 UFRGS, BR UFRGS, 1 2 2 - Tech of Defense University National Technology, Institute of Royal KTH George Washington University, US; US; University, Washington George TUM, DE; DE; TUM, DE; AISEC, Fraunhofer Learn-to-Scale: Parallelizing Deep Learning Inference Parallelizing Learn-to-Scale: Architecture Multiprocessor on Chip Reservation Virtual Channel Advance High-performance, Energy-efficient, Fault-tolerant Fault-tolerant Energy-efficient, High-performance, Design Using Reinforcement Network-on-Chip Learning Real-time Detection and Localization of DoS Attacks of DoS Attacks and Localization Real-time Detection in NoC based SoCs A Security Architecture for RISC-V based IoT Devices for Architecture A Security Area Coffee Break in Exhibition Towards Reliable and Secure Post-Quantum Co- Post-Quantum and Secure Reliable Towards on RISC-V Processor based Cezar Rodolfo Wedig Reinbrecht Wedig Rodolfo Cezar 1 1 Speaker: Kaiwei Zou, Institute of Computing Technology, Chinese Acad- Technology, Institute of Computing Zou, Kaiwei Speaker: CN of Sciences, emy Institute of Li and Xiaowei Li, Huawei Wang, Ying Zou, Kaiwei Authors: CN of Sciences, Chinese Academy Technology, Computing SE Technology, Institute of Royal KTH Wang, Boqian Speaker: Authors: Boqian Wang Speaker: Ke Wang, George Washington University, US University, Washington George Wang, Ke Speaker: Wang Authors: Ke Speaker: Subodha Charles, University of Florida, US of Florida, University Subodha Charles, Speaker: University Mishra, and Prabhat Lyu Yangdi Subodha Charles, Authors: US of Florida, Room 4 0830 Room SE University, Mälardalen Masoud Daneshtalab, Chair: FR Institute of Nanotechnology, Sébastien Le Beux, Lyon Co-Chair: using machine intelligence The NoC design is being enhanced - tech attack, is one Denial-of-Service efficiently. system more nologies to drive flooding the network, propertycaused by a malicious intellectual core thatreal-time DoS can affect a NoC. In and this session a lightweight detec- with attack timely detectionbe presented will mechanism attack among error a trade-offs Find and power overhead. tion and minor area challeng- energy and a very is performance, retransmission, packet rate, mechanism to opti- ing topic. fault-tolerant In this session a proactive learning reinforcement energy efficiency and performance with mize (RL) Method to exploit will be proposed. and noise-toler the elasticity bottleneck the algorithms learning deep of circumvent to features ance will be their execution and accelerate moving data of on-chip inter-core en- a better interconnects This method shows discussed in this session. factinto account the Taking predict that we can the des- ergy efficiency. at ahead estab we can interface the network packets of some tination from the source to builtthe destination up by reserving lishes a highway the This mechanism can reduce transfer target packets' virtual channel. in this session. and will be presented latency Speaker: Matthias Hiller, Fraunhofer AISEC, DE AISEC, Fraunhofer Hiller, Matthias Speaker: Auer Lukas Authors: Speaker: Johanna Sepulveda, TUM, DE TUM, Johanna Sepulveda, Speaker: Tim Fritzmann Authors: 1 Sepulveda 1 nology, CN; nology, nescu Where do NoC and Machine Learning meet? Where do NoC and 88 0945 0930 0900 0830 1000 9.4 0945 0930 THURSDAY, 28MARCH 2019 THURSDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 0930 0900 0830 9.6 1000 IPs 0930 0900 0830 9.5 1000 THURSDAY, 2019 MARCH 28

an industrial perspective Reliability ofhighly-parallel architectures: Attacking MemoryandI/OBottlenecks Houston, US cisco Cazorla, Barcelona Supercomputing Center, ES Authors: Mikel Fernandez, Gabriel Fernandez, JaumeAbellaandFran- Speaker: Mikel Fernandez, Barcelona Supercomputing Center, ES SungGil Lee, ByunghoonLee andJong-BaeLee, Samsung, KR Authors: Kyungsu Kang, SanghoPark, Byeongwook Bae, Choi, Jungyun Speaker: Kyungsu Kang, SamsungElectronics, KR Authors: Enrico Mezzetti Speaker: JaumeAbella, Barcelona Supercomputing Center (BSC), ES from Solid-State-Driveto 5G highly-parallel designsonfour different application domains ranging This session addressesthe issues of proving, verifying and enhancing Co-Chair: Fabien Clermidy, CEA, FR Chair: DorisKeitel-Schulz, Infineon Technologies, DE Room 60830 University of Technology, IR Authors: SabaAhmadian, Reza Salkhordeh andHossein Asadi, Sharif Speaker: SabaAhmadian, SharifUniversity of Technology, IR Jingweijia TanAuthors: Speaker: Jingweijia Tan, JilinUniversity, CN Berlin, DE Authors: SohanLal, JanLucasandBenJuurlink, Technical University of Speaker: SohanLal, Technical University ofBerlin, DE for showcasenewopportunities alternativethis section cachesolutions. SSD-based I/Oby proposing cachingsystem. anew smart The papers in GPU cacheutilization byexploiting non-frequently accessedblocks, and by using new adaptiveory compressiontechniques, the by enhancing the GPUcachemem- to betterexploit session presentstechniques new Focusing hierarchythe memory on and I/O and memory bottlenecks,this Co-Chair: CristinaSilvano, Politecnico diMilano, IT Chair: LeonidasKosmidis, Barcelona Supercomputing Center, ES Room 50830 and Francisco Cazorla 1 versity, CN; 1 IP4-14, IP4-15 Estimates fortheSpaceDomain Multicore Early Design Stage Guaranteed Performance Industrial CaseStudy Seamless SoCVerification Platforms: UsingVirtual An for Automotive Applications AURIX TC277 Multicore Contention ModelIntegration Coffee BreakinExhibition Area LBICA: ALoadBalancerforI/OCacheArchitectures Energy-Efficient GPUL2Cache LoSCache: Leveraging Locality Similarity toBuild Compression forGPUs SLC: MemoryAccessGranularity Aware Selective Lossy Coffee BreakinExhibition Area Jilin University, CN; Barcelona Supercomputing Center, ES; 3 Pacific National Laboratory, Northwest US; – – 1000 1000 2 College ofCommunication Engineering, JilinUni- 1 1 ,Kaige Yan 1 , LucaBarbina 2 , ShuaiwenLeon Song 2 2 , JaumeAbella Magneti Marelli S.p.A., IT 1 , Stefania Botta 4 University of 3 andXinFu 4 89 2

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - 1 - - 1 2 and Nor 2 and Lui Sha 3 and Rolf Ernst and Rolf 2 , Bo Liu , 1 Northeastern Univer MPI-SWS, DE MPI-SWS, 2 2 , Claus Kestel , 1 www.date-conference.com ONERA, FR ONERA, 2 and Björn Brandenburg and Björn , Marc Boyer Marc , 1 1 , Jen-Yang Wen Jen-Yang , 2 , Matthias Alles Matthias , 1 , Mitra Nasri Mitra , 1 1000 – , Borislav Nikolic Borislav , 1 , Zhiwei Feng , 1 University of Kaiserslautern, DE of Kaiserslautern, University 2 1000 – 2 NVIDIA, US NVIDIA, 3 Max Planck Institute for Software Systems, DE; DE; Systems, Software Max Planck Institute for University of Illinois at Urbana-Champaign, US; US; of Illinois at Urbana-Champaign, University Technische Universität Braunschweig, DE; DE; Braunschweig, Universität Technische Creonic GmbH, DE; DE; GmbH, Creonic A Container-based DoS Attack-Resilient Control Control DoS Attack-Resilient A Container-based Systems for Real-Time UAV Framework Self- for Non-Preemptive Test An Exact Schedulability Suspending Real-Time Tasks Area Coffee Break in Exhibition Scratchpad Memories with Ownership Memories with Scratchpad Increasing Accuracy of Timing Models: From CPA to CPA+ From CPA of Timing Models: Increasing Accuracy in Exhibition Area in Exhibition Coffee Break Polar Code Decoder Framework Code Decoder Polar bert Wehn 1 1 Johannes Kepler University Linz, AT Linz, University Robert Johannes Kepler Wille, Organiser: AT Linz, University Robert Johannes Kepler Wille, Chair: conventional speedups over substantial promise computers Quantum such as quantum applications relevant practical many for computers sim- quantum cryptography, machine learning, optimization, chemistry, While considered more. and many systems of linear equations, ulation, - shown impres have years recent a long time, for of the future" "dreams - leading computers to accomplishments the firstreal quantum sive within this develop A leading force by everyone. which can be utilized which launched ment - the IBM is IBMthe first Q Experience Research in- them and make computers quantum to build universal dustrial initiative In a cloud access. audience accessible the meantime, through to a broad academic institutions, 500 companies, a worldwide network of Fortune advance to collaborate startupsand and within work initiative this This special session aims this potential to foster computing. quantum suc- showcasing as well as Qiskit community introducing by to EDA the 0830 Theatre Exhibition Speaker: Mitra Nasri, Delft University of Technology, NL Technology, of University Delft Nasri, Mitra Speaker: Yalcinkaya Authors: Beyazit Speaker: Martin Schoeberl, Technical Uniersity of Denmark, DK Uniersity of Denmark, Technical Martin Schoeberl, Speaker: Baris and Jens Oktay Strøm, Biskopstø Tórur Martin Schoeberl, Authors: DK of Denmark, University Technical Sparsø, US of Illinois at Urbana Champaign, University Chen, Jiyang Speaker: Chen Jiyang Authors: Speaker: Leonie Köhler, TU Braunschweig, DE Braunschweig, TU Köhler, Leonie Speaker: Köhler Leonie Authors: Room 7 0830 Room DE Braunschweig, TU Ernst, Rolf Chair: DE of Kaiserslautern, University Gerhard Fohler, Co-Chair: This session includes papers at predictability thatthe runtime address of autonomous in the area are applications Potential of HW and SW. level systems. Speaker: Timo Lehnigk-Emden, Creonic GmbH, DE GmbH, Creonic Lehnigk-Emden, Timo Speaker: Timo Lehnigk-Emden Authors: 1 sity, CN; sity, 1 Special Session: IBM’s Qiskit Tool Chain: Chain: Tool Qiskit IBM’s Special Session: Real with for and Working Developing Computers Quantum Runtime Predictability Runtime 90 9.8 1000 0945 0930 0900 0830 9.7 1000 0945 THURSDAY, 28MARCH 2019 THURSDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com IP4-6 IP4-5 IP4-4 IP4-3 IP4-2 IP4-1 IP4 1000 0930 0900 0830 THURSDAY, 2019 MARCH 28 Interactive Presentations 1 1 Speaker: Federico Vesentini, University of Verona, IT Authors: ManuelPencelli Speaker: Manuel Pencelli, Yanmar R&DEurope S.r.l., IT sity of Verona, IT Authors: Stefano Centomo, Enrico Fraccaroli andMarco Panato, Univer Speaker: Stefano Centomo, University of Verona, IT Authors: Alexandra Listl Speaker: Alexandra Listl, TUM, DE Authors: NingBao Speaker: NingBao, Renmin University ofChina, CN Authors: WentaiZhang Speaker: JiaxiZhang, Peking University, CN Poster Area 1000 Author: Rod Van Meter, Keio University, JP Author: Robert Wille, JohannesKepler University Linz, AT Author: Yehuda Naveh, Research, IBM US workwithquantumactually computers. the user-viewwell as anditsextensionsto canbeutilized onhowQiskit ownsolutionsusingEDA IBM's (sometimes outperforming expertise), as rience,the developerto develop viewonhow newmethodsfor Qiskit QExpecoversthe IBM - and ownperspective onQiskit allsides: IBM's algorithms onareal quantum computer. Tothis end, the specialsession tool -eventuallythe with allowingfor efficiently and robustly executing to developcess storiesonhow newmethodsforto work aswellhow tation inacorresponding regular session. Additionally, paper is briefly introduced each IP in a one-minute presen- Interactive Presentations runsimultaneouslyduringa30-minuteslot. byCadence AcademicNetwork supported Nong Xiao 1 Zanchettin 1 Ulf SchlichtmannUlf versity, CN retti Cooperating Agents underRigidBody Constraint Planning with Real-TimeCollision Avoidance for Servomechanisms Accurate Dynamic ModellingofHydraulic Production Line From Multi-Level toAbstract-based Simulation ofa Application-Aware AgingAnalysis SRAM DesignExploration with Integrated TrendforNVM-based ReadCache Macroscopic A Write-Efficient Cache Algorithm basedon on Multi-FPGA Architectures An Efficient Mapping ApproachtoLarge-Scale DNNs Coffee BreakinExhibition Area Using Qiskit: Compilation NISQ-era forQiskit the Toolkit Developing forQiskit: Introducing EDA Methodsinto for Quantum Computing Qiskit: AnOverview oftheOpen-SourceFramework Chair ofElectronic DesignAutomation, DE; Renmin University ofChina, CN; Peking University, CN; YANMAR S.R.L, R&DEUROPE IT; 2 , Niccolini Marta 3 2 2 1 – , YunpengChai 1030 1 , Matteo Ragaglia 2 1 Sun Yat-sen University, CN; 1 , JiaxiZhang , DanielMueller-Gritschneder 1 ,Renzo Villa 2 Politecnico diMilano, IT 2 1 Auburn University, US andXiaoQin 1 , MinghuaShen 2 , Alfredo Argiolas 1 , Paolo Rocco 2 TUM, DE; 2 3 Sun Yat-SenUni- 2 2 , GuojieLuo andAndrea Maria 2 3 , SaniNassif Radyalis, US 1 , GianniFer 1 and 3 - and 91 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 1 1 and 1 2 , Wu Haitao , 3 Northeastern Uni- 3 and Tajana Rosing Tajana and 2 and Chun Jason Xue and Chun Jason 2 and Robert Wille and Robert www.date-conference.com 1 - Devaraje Keerthikumara , 1 Intel, US Intel, 2 , Weiying Weiying Zhang , 2 Vidyasirimedhi Institute of Science Vidyasirimedhi , Emily Shriver , 2 2 Temple University, US; US; University, Temple , Wolfgang Ecker Wolfgang , 2 , Sarana Nutanong Sarana , 1 , Elena Zennaro , 1 1 , Ping Huang Ping , 1 , Ankit More , 1 , Qiao Li , Johannes Kepler University Linz, AT Linz, University Johannes Kepler 1 2 Jinan University, CN Jinan University, 4 4 , Martin Manzinger , 1 Huanghuai University, CN; Huanghuai University, University of California San Diego, US; US; San Diego, of California University Infineon AG, DE; DE; AG, Infineon City University of Hong Kong, HK; Kong, of Hong City University Queue Based Memory Management Unit for Unit Queue Based Memory Management Heterogeneous MPSoCs Application Performance Prediction and Optimization and Optimization Prediction Performance Application Technology Under Cache Allocation for Techniques Factorization Matrix Generalized Logic Synthesis Approximate Request Scheduler Conflict-Aware A Multi-layer CARS: SSDs for NVMe Practical Causality Handling for Synchronous Handling for Synchronous Causality Practical Languages RAGra: Leveraging Monolithic 3D ReRAM for Monolithic Leveraging RAGra: Processing Graph Massively-Parallel Inspired of Memory Systems Estimation Cost Accurate Vision Computer by Machine Learning for The Case for Exploiting Underutilized Resources in Resources Underutilized Exploiting The Case for Architectures Mobile Heterogeneous Edge Computing for Detection Category Online Rare 1 1 Longxin Lin Longxin Speaker: Steven Smyth, Kiel University, DE Kiel University, Smyth, Steven Speaker: and Reinhard Schulz-Rosengarten Alexander Smyth, Steven Authors: DE Kiel University, Dept. Science, of Computer Hanxleden, von US UCSD, Kim, Yeseong Speaker: Kim Yeseong Authors: Speaker: Lorenzo Servadei, Infineon Technologies, DE Technologies, Infineon Servadei, Lorenzo Speaker: Servadei Lorenzo Authors: Speaker: Yufei Cui, City University of Hong Kong, HK of Hong Kong, City University Cui, Yufei Speaker: Cui Yufei Authors: CN Technology, of Science and University Huazhong Huang, Yu Speaker: and Yao Pengcheng Hai Jin, Liao, Xiaofei Zheng, Long Huang, Yu Authors: CN Technology, of Science and Huazhong University Chuangyi Gui, Authors: Nicola Piccinelli, Federico Vesentini and Riccardo Muradore, Muradore, and Riccardo Vesentini Federico Piccinelli, Nicola Authors: IT Verona, of University US Irvine, of California, University Nikil Dutt, Speaker: US UC Irvine, Nikil Dutt Amiri Sani, and Ardalan Hsieh, Chenying Authors: Speaker: Robert Wittig, Technische Universität Dresden, DE Dresden, Universität Technische Wittig, Robert Speaker: Fettweis, and Gerhard Emil Matus Hasler, Mattis Wittig, Robert Authors: DE Dresden, Universität Technische gowda US University, Brown Sherief Reda, Speaker: US University, Brown Soheil Hashemi and Sherief Reda, Authors: CN Huanghuai University, Yang, Tianming Speaker: Yang Tianming Authors: 1 and Technology, TH and Technology, 1 versity, CN; versity, 92 IP4-15 IP4-14 IP4-13 IP4-12 IP4-11 IP4-10 IP4-9 IP4-7 IP4-8 THURSDAY, 28MARCH 2019 THURSDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1130 1100 10.2 1230 1200 1130 1100 10.1 THURSDAY, 2019 MARCH 28 and Opportunities Extreme Scales: DesignChallenges, Advances, Session:Special Enabling Graph Analytics at Model-Based MachineLearning Intelligent Systems” Session: Hottopic: DaySpecial on “Model-Based Designof TU Kaiserslautern, DE; Werner National Laboratory, US Suetterlein, Antonino Tumeo andMarcin Zalewski, Pacific Northwest Lumsdaine, JosephManzano, Andres Marquez, Marco Minutoli, Joshua Authors: Vito Giovanni Castellana, MaurizioDrocco, JohnFeo, Andrew Speaker: John Feo, Pacific National Laboratory, Northwest US State University, US Authors: Ananth Kalyanaraman andPartha Pratim Pande, Washington Speaker: Ananth Kalyanaraman, Washington State University, US andexchangetwo groups.ment the ofideasbetween architecture, byfostering anenvironment conduciveto active engage- new vibrant andHPC the intersectionofgraph community at analytics another andspawningnewresearch directions. to builda The goalis andcomputer architectureanalytics are capableofbenefitingfrom one for discussionofrecent graphthat advancesto show have that started this emerging research area. The specialsessionwillserve asanavenue es, and exciting for opportunities research in anddevelopment exist that the sessionwillcover ofuniquechallenges,the spectrum advanc latest - computing. andhighperformance graphtalks, analytics these Through threetalks byspeakersthe intersectionof session willhost whoworkat ing innovations inalgorithmsandarchitectures isproposed. The special topic specialsessiononenablingextreme us- scalegraphA hot analytics Chair: ParthaPande, Washington State University, US Organiser: Ananth Kalyanaraman, Washington State University, US Room 21100 Speaker andAuthor: de Vries, Bert GNReSound, NL Speaker andAuthor: OrlandoMoreira, GrAIMatter Labs, NL Authors: WolfgangEcker Speaker: Wolfgang Ecker, Infineon Technologies, DE Co-Chair: Patricia Derler, National Instruments, US Chair: Andreas Gerstlauer, University of Texas, Austin, US Room 11100 1 versity Linz, DE Data Analytic Workflows An Enhanced Parallel Graph Platform forReal-world Challenges toward Extreme-scale Graph Analytics SurveyA Brief ofAlgorithms, Architectures, and Lunch BreakinArea Bayesian Model-basedMachineLearning Automated Signal ProcessingDesignthrough computing: challenges andopportunities Formal computation modelsinneuromorphic Model Driven Architecture Vision Embedded Systems’ Automation following OMG's Infineon Technologies AG / TU Munich, DE; 1 , ZhaoHan – – 1230 1230 1 andLorenzo Servadei 3 Infineon Technologies AG/Johannes Kepler Uni- 1 , Keerthikumara Devarajegowda 3 2 Infineon AG/ Technologies 2 , Michael 93

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 1 and 1 1 and Jianhui Jiang 2 , Mingsong Chen , 2 and Terrence Mak Terrence and 2 www.date-conference.com , Zebo Peng Zebo , 1 Nanjing University of Science and Nanjing University 2 , Junlong Zhou , ARM Ltd., GB ARM Ltd., 1 2 , Shidhartha Das , , Ying Ying Zhang , 1 1 Linköping University, SE University, Linköping 2 , Tongquan Wei Tongquan , 1 University of Notre Dame, US Dame, of Notre University 3 1230 1230 – – 3 University of Southampton, GB; GB; of Southampton, University Tongji University, CN; University, Tongji East China Normal University, CN; East China Normal University, CoDAPT: A Concurrent Data And Power Transceiver for Transceiver And Power Data A Concurrent CoDAPT: 3D-ICs Wireless Fully QPUs for superconducting permutations Compiling A Deterministic-Path Routing Algorithm for Algorithm Routing A Deterministic-Path NoC on Wafer-Level Faults Many Tolerating IP5-3 IP5-2, IP5-1, Lunch Break in Lunch Area CE-Based Optimization for Real-time System for Real-time System CE-Based Optimization under Learned Soft Error Rate Availability Identifying the Most Reliable Collaborative Workload Workload Collaborative the Most Reliable Identifying in Heterogeneous Devices Distribution in Lunch Area Lunch Break Scaling up Network Centrality Computations Centrality Network up Scaling 1 X, Sharon Hu Sharon X, Speaker: Benjamin Fletcher, University of Southampton, GB of Southampton, University Fletcher, Benjamin Speaker: Benjamin Fletcher Authors: CH EPFL, Soeken, Mathias Speaker: Bruno Schmitt and Gio- Mozafari, Fereshte Soeken, Mathias Authors: CH EPFL, De Micheli, vanni Room 4 1100 Room IT di Bologna, Elena Gnani, Università Chair: CNRS-LIRMM, FR Aida Todri-Sanial, Co-Chair: a wide This is the right session that covers see something real? Wanna to pho- 3D integration wireless from technologies: of disruptive variety computing. to quantum way all the tonics and thin film electronics, Speaker: Ying Zhang, Tongji University, CN University, Tongji Zhang, Ying Speaker: Zhongsheng Chen Authors: Speaker: Liying Li, East China Normal University, CN East China Normal University, Liying Li, Speaker: Liying Li Authors: CN; Technology, Speaker: Paolo Rech, UFRGS, BR UFRGS, Rech, Paolo Speaker: and Navaux Philippe Daniel Oliveira, Dávila, Gabriel Piscoya Authors: BR UFRGS, Rech, Paolo Room 3 1100 Room IT Torino, di Politecnico Di Carlo, Stefano Chair: IT di Milano, Politecnico Luca Cassano, Co-Chair: - in hetero assessments reliability from topics ranging This session covers systems in real-time of the availability optimization geneous systems, as well as fault tech- tolerant under permanent faults, and transient systems. core niques in many Speaker: Henning Meyerhenke, Humboldt-University Berlin, DE Berlin, Humboldt-University Henning Meyerhenke, Speaker: Hum- der Grinten, van and Alexander Henning Meyerhenke Authors: DE Berlin, boldt-University 1 1 Disruptive Technologies Ain't Fake News! Ain't Fake Technologies Disruptive System-level Dependability for Multicore for Multicore Dependability System-level and Real-time Systems

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Self-adaptive resourcemanagement SSD anddata placement Maine, US 1 ogy, Offenburg University ofAppliedScience, DE 1 Hagmann esco Cerizzi andAntonio Miele, Politecnico diMilano, IT Authors: DanieleAngioletti, Francesco Bertani, CristianaBolchini, Franc- Speaker: Antonio Miele, Politecnico diMilano, IT niques are basedoneithermachinelearningorheuristics. ticores, edgecomputing devices andstorage systems. Proposedtech - This session covers run-time resourcetechniques for management mul- Co-Chair: AndyPimantel,University of Amsterdam, NL Chair: University Merret, Geoff of Southampton, GB Room 61100 Authors: ShiqingLi, Yixun Wei andLei Ju, ShandongUniversity, CN Speaker: ShiqingLi, ShandongUniversity, CN Chenlei TangAuthors: Speaker: Chenlei Tang, HuazhongUniversity ofScienceand Technology, CN Suzhen WuAuthors: Speaker: HongJiang, The University of Texas Arlington, at US in CPU-FPGA multicore systems. based storagethe latter covers while data andmanagement placement andlatency.throughput twopaperspropose solutions The first for SSD- to improveThis sessiondealswithsomesolutions andstorage memory Co-Chair:Hamid Tabani, Barcelona Supercomputing Center, BSC, ES Chair: OlivierSentieys, FR INRIA, Room 51100 Authors: Ahmet Turan Erozan Speaker: Ahmet Turan Erozan, Karlsruhe Instituteof Technology, DE Authors: HassnaaEl-Derhalli Speaker: SébastienLe Beux, Ecole Centrale deLyon, FR Xu 1 1 IP5-5 IP5-4 Workloads onHeterogeneousMulticores A Runtime ResourceManagement Policy forOpenCL Lunch BreakinArea heterogeneous multiprocessor system-on-chips Automatic data placement forCPU-FPGA Update Overhead forSSD RAID RAFS: ARAID-Aware File System toReduce theParity Read Data Replication forFlashStorage HotR: Alleviating Read/Write Interference with Hot Lunch BreakinArea on Additive ResistorTuning Inkjet-Printed TrueRandomNumberGenerator based Stochastic Computing with Integrated Optics Karlsruhe Instituteof Technology, DE; Concordia University, CA; Huazhong University ofScienceand Technology, CN; Xiamen University, CN; 1 ,Fei Wu 2 andMehdi Tahoori 1 andChangshengXie – – 1230 1230 1 ,Zhang Weiwei 1 ,Jiguang Wan 2 The University of Texas Arlington, at US 2 Lyon InstituteofNanotechnology, FR 1 , SébastienLe Beux 1 1 , Rajendra Bishnoi 1 1 1 , BoMao , YifengZhu 2 Karlsruhe Instituteof Technol- 1 andHongJiang 1 2 , JasminAghassi- 2 andSofiene Tahar , ZhiyuanLiu 2 University of 1 2 , Peng 1 95

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - 3 , , 3 1 - , Yu Ji Yu , 1 1 - Lilje Pasi , 2 , Vasileios Tsout Vasileios , 1 1 , Lei Deng Lei , Temple Univer Temple 2 2 , Char Khazanov , 1 1 and Dimitrios Soudris UC Irvine, US UC Irvine, 2 4 , Jing Ye , Karlsruhe Institute of Karlsruhe 1 2 State Key Laboratory of Laboratory Key State www.date-conference.com 2 and Luca Benini National University of Singa- University National 2 2 , Amir M. Rahmani , and Ke Zhou and Ke 1 2 1 , Joerg Henkel Joerg , 4 2 , Hamed F. Langroudi Hamed F. , and Dhireesha Kudithipudi and Dhireesha , Dimosthenis Masouros Dimosthenis , 1 2 1 , Shuangchen Li , 1 Tsinghua University, University of California, of California, University University, Tsinghua , Nuria Pazos , 3 1 , Ping Huang Ping , , Anil Kanduri , 1 University of California Irvine & TU Wien, US; US; Wien, TU Irvine & of California University 1 2 , Lars Bauer , 2 and Yuan Xie Yuan and 3 , Xing Hu , Tsinghua University, CN University, Tsinghua Haute Ecole Arc Ingénierie, HES-SO, CH HES-SO, Ingénierie, Arc Haute Ecole 1 and Nikil Dutt 4 2 3 Democritus University of Thrace, GR Thrace, of Democritus University 1230 3 – , John L. Gustafson , 1 , Wu Dong , 4 , Farzad Samie Farzad , 1 , Axel Jantsch Axel , 1 Rochester Institute of Technology, US; US; Technology, Institute of Rochester Integrated Systems Laboratory, ETH Zurich & Haute Ecole Arc Ingé- Arc & Haute Ecole Zurich ETH Laboratory, Systems Integrated US; Barbara, Santa of California, University Huazhong University of Science and Technology, CN; Technology, of Science and Huazhong University National Technical University of Athens, GR; GR; of Athens, University Technical National FI; Turku, of University AT; Wien), (TU Technology of University Vienna Memory Trojan Attack on Neural Network Network Memory Trojan Attack on Neural Accelerators Using the Posit Network A Deep Neural Deep Positron: Number System Learning to infer: RL-based search for DNN primitive RL-based search for DNN primitive Learning to infer: on Heterogeneous Embedded Systems selection Goal-Driven Autonomy for Efficient On-chip Resource On-chip Efficient for Autonomy Goal-Driven to Goals Objectives Translating Management: at Reliability High Data Achieving Scrub Unleveling: Scrubbing Cost Low IP5-7 IP5-6, Lunch Break in Lunch Area DMRM: Distributed Market-Based Resource Resource Market-Based Distributed DMRM: Systems Edge Computing of Management Santa Barbara, CN; Barbara, Santa Jeffrey Lillie Jeffrey Jianyu Xu Jianyu 1 1 1 1 Speaker: Xing Hu, University of California, Santa Barbara, CN Barbara, Santa of California, University Xing Hu, Speaker: Zhao Yang Authors: Speaker: Miguel de Prado, HES-SO/ETHZ, CH HES-SO/ETHZ, Prado, Miguel de Speaker: Miguel de Prado Authors: Room 7 1100 Room NL Technology, of University Sander Stuijk, Eindhoven Chair: CH EPFL, Marina Zapater, Co-Chair: optimize to approach learning reinforcement a firstThe presents paper how a memory paper showcases The second parameters. the accelerator network. neural a of lower and accuracy the used be can attack, to Trojan the en- to improve accelerators The lasthardware two papers introduce of ergy network. the consumption - Technol of Science and Huazhong University Jiang, Tianming Speaker: ogy, CN Tianming Jiang Authors: Speaker: Anil Kanduri, University of Turku, FI Turku, of University Anil Kanduri, Speaker: Elham Shamsa Authors: 3 - of Ath University Technical National Dimosthenis Masouros, Speaker: GR ens, Manolis Katsaragakis Authors: Speaker: Zachariah Carmichael, Rochester Institute of Technology, US Technology, Institute of Rochester Carmichael, Zachariah Speaker: Carmichael Zachariah Authors: Computer Architecture, Institute of Computing Technology, Chinese Technology, Institute of Computing Architecture, Computer CN; of Sciences, Academy pore, SG pore, Technology, DE; DE; Technology, souras 1 sity, US sity, 1 nierie, HES-SO, CH; HES-SO, nierie, Architectures for emerging machine machine for emerging Architectures techniques learning berg

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and successstories Everywhere Initiative &FED4SAE, opencalls Europe digitization: Smart Anything Giovanni Gherardi, Energica Motor Company, IT Rosanna Zaza, AlitecSrl, IT Michael Setton, DigitalCatapult, GB Marcello Coppola, STMicroelectronics, FR gies alternatives, FR Speaker: IsabelleDor, Commissariat àl’énergie auxéner atomique et Exhibition Theatre 1100 versity, CA Authors: Arash Ardakani, Jiand Zhengyun Warren Gross, McGillUni- Speaker: Ji, Zhengyun McGillUniversity, CA targeted objectives andimpact. will confront oflargethe viewpoint industrial, RTOstheir andSMEs and users andsuppliersacross value Europe.throughout chains This session companiesto further plusaccess VC funding,to potential v)andAccess toinnovativeto €60kinfinancialsupport support, iv)Up Management R&D centers, ii) Technical coaching from domain experts, iii) Innovation platforms, Advanced Technologies, and Testbeds from Industrialsand accelerate developments CPS CPS combiningto leading-edge i)Access presentation of awarded projects illustrateto FED4SAE one-stop-shop to businesses fromtechnologies any and any sectors companies. The bringinginnovative aimsat FED4SAE project Cyber-Physical System through SAE opencalls, alsoI4MSfocusing but onmanufacturing. Cascade fundingisavailable andnetworkingopportunities. support competences,trainingto develop technical skills, businessmanagement tailored isnowavailableSME service to provideto R&Danddigital access technologies. A competitive digital the latest throughthe adoptionof to helpcompaniesto becomeprojects provide more onestop-shops throughthe inclusionofinnovative technologies. SAE H2020 digital SMEs, their products andservices to enhance andmid-caps start-ups Everywhere Anything (SAE)The goalofSmart initiativeto support is Chair: MarcelloCoppola, STMicroelectronics, FR énergies alternatives, FR Organiser: Isabelle Dor, Commissariat àl’énergie aux atomique et IP5-8, IP5-9, IP5-10 Lunch BreakinArea collaboration SME, RTO, industrial: how SAEsupport the digitization SAE, anexample ofECinitiative tosupport Europe Lunch BreakinArea in LSTMs Learning toSkip IneffectualRecurrent Computations – 1230 - 97

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 , 2 See Page 10 " See Page , Shravan Narayan Shravan , 1 www.date-conference.com 2 , Jean-Joseph Marty Jean-Joseph , 1 1530 1530 1350 – – – and Rajesh Gupta and Rajesh 2 University of California at San Diego, US at San Diego, of California University 2 INRIA, FR; INRIA, FR; Behavioral Modeling of Transistor-Level Circuits Circuits Modeling of Transistor-Level Behavioral Automata to Hybrid Abstraction using Automatic in Exhibition Area Coffee Break in Exhibition Modeling Cross-Layer Interactions for Designing for Designing Interactions Modeling Cross-Layer Systems Cyber-Physical Certifiable of embedded programming verified Steps toward devices computing Specifying and Evaluating Quality Metrics for Vision- Quality Specifying and Evaluating Systems based Perception A Fundamental Look at Models and Intelligence at Look A Fundamental Speaker: Ahmad Tarraf, Goethe University Frankfurt, DE Frankfurt, Goethe University Tarraf, Ahmad Speaker: DE Frankfurt, Goethe University and Lars Hedrich, Tarraf Ahmad Authors: Room 2 1400 Room ES IMSE, Fernandez, V. Francisco Chair: TW Chung Cheng University, Lin, National Mark Po-Hung Co-Chair: model gen- behavioral the automated for presented New techniques are analog/mixed- of efficientand simulation numerical-symbolic eration efficient analog for approach optimization Bayesian a Also circuits. signal is presented. circuit synthesis Speaker: Jean-Pierre Talpin, INRIA, FR Talpin, Jean-Pierre Speaker: Talpin Authors: Jean-Pierre Speaker: Samarjit Chakraborty, TUM, DE TUM, Samarjit Chakraborty, Speaker: Martin Becker, James H. Anderson, Samarjit Chakraborty, Authors: Stavros Thiele, Lothar Metta, Ravindra Halder, Samiran Helmut Graeb, DE TUM, Yeolekar, and Anand Tripakis Room 1 1400 Room ES de Cantabria, Universidad Villar, Eugenio Chair: NL Technology, of University Marc Geilen, Eindhoven Co-Chair: US University, State Arizona Deshmukh, Jyotirmoy Speaker: Anand Bal- Xin Qin, Puranic, Aniruddh Adel Dokhanchi, Authors: Desh- V. and Jyotirmoy Fainekos Georgios Heni Ben Amor, akrishnan, US of Southern California, Univ. mukh, Speaker: Edward Lee, UC Berkeley, US UC Berkeley, Lee, Edward Speaker: Room 1 1320 Room NL Technology, of University Geilen, Eindhoven Marc Chair: NL Technology, of University Stuijk, Eindhoven Sander Co-Chair: 1 Novel techniques in optimization and high- techniques in optimization Novel circuits modeling of mixed-signal level Special Day on “Model-Based Design of “Model-Based on Special Day of Cyber- MBD Session: Systems” Intelligent Systems Physical LUNCHTIME KEYNOTE SESSION KEYNOTE LUNCHTIME Deian Stefan 98 1400 1530 11.2 1500 1430 1400 11.1 1320 11.0 THURSDAY, 28MARCH 2019 THURSDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1530 1500 1430 1400 11.3 1530 IPs 1500 1430 THURSDAY, 2019 MARCH 28

Models Session:Special RebootingourComputing Author: MassimilianoDi Ventra, UCSD, US Author: NagadastagiriReddy, Penn State, US Authors: Koen andCarmen G.Almudever, Bertels TU Delft, NL to developtheir activities. We believethe EDA willstimulate it researchersto lookinto newgrounds puting Initiative -https://rebootingcomputing.ieee.org endorsesit. that - Rebootingthe IEEE the missionandroles large Community at of with - the link between tighteningDATE the purpose of serve the EDA and com- tures, such as neuromorphic computing, or in-memory this proposal also the DATEto spective community beyondthe currently novel hot architec- computing problems very efficiently. to In addition provide a clear per ing where self-organizing logicgates canbeemployedto solve complex from The University ofCalifornia SanDiego, willfocus onmemcomput computing usingintrinsic oscillators. talk,third The from researchers of Notre Dame, Georgia Tech andPenn State, willpresent new ways of ming language). The secondtalk, from researchers fromthe University making a useful computer, including micro architecture and program- the practicalitiesquantum of to basicphysics computing the most from be provided: talk,The first from researchers from TU Delft, will cover far beyond ourcurrent Von Neumanncomputing model. Threetalks will topic session,to elaborate weintend ondisruptive computing models the requires disrupt Vonthat solutions Neumannparadigm.this hot In towards scaling. the energy morea limiterof The quest energy-efficiency neck,the system performance, only limits nowadays not also acts but as off-chip data memory rates. trend, This knownas Von Neumannbottle- the ever-increasingkeepsto worsening due and gap between on-chip niques are successfully employed incontemporary designs,trendthe the use of optimized accelerators or advancedtech- power management crease of computing needs. While alternative design approaches, suchas computing architectures arethe in- morethan ever struggling to sustain Withthe current slowingdownofMoore's Law, standard Von Neumann Co-Chair: IanO'Connor, Ecole Centrale ofLyon, FR Chair: Pierre-Emmanuel Gaillardon,University ofUtah, US Organiser: Pierre-Emmanuel Gaillardon,University ofUtah, US Room 31400 Zhou andXuan Zeng, Fudan University, CN Authors: ShuhanZhang, Wenlong Lv, Fan Yang, Changhao Yan, Dian Speaker: ShuhanZhang, Fudan University, CN slautern, DE Authors: Carna Zivkovic andChristophGrimm, University ofKaiser Speaker: Carna Zivkovic, University ofKaiserslautern, DE IP5-11 Coffee BreakinExhibition Area The Memcomputing Paradigm Intrinsic Computing usingweakly coupled oscillators From Qubit toComputer Coffee BreakinExhibition Area Synthesis UsingNeural Network Bayesian Optimization ApproachforAnalog Circuit Eventand Discrete Models Nubolic Simulation ofAMSSystems with Data Flow – 1530 - 99 - -

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3 , Yiyuan Yiyuan Xie , 4 , Qian Lou , and Arijit Raychowdhury 3 2 www.date-conference.com College of Computer Science, Science, of Computer College 2 Samsung, US Samsung, 2 Indiana University Bloomington, US Bloomington, Indiana University , Yichen Ye Yichen , 5 Department of Intelligent Systems Department Systems of Intelligent 2 4 , Titash Titash Rakshit , 1 College of Electronics and Information Engi- and Information of Electronics College 3 , Wenyang Liu Wenyang , 1 , Aqeel Anwar Aqeel , 1 1530 1530 – – 5 Georgia Institute of Technology, US; US; Technology, Institute of Georgia Nanyang Technological University, SG; SG; University, Technological Nanyang AIX: A high performance and energy efficient and energy efficient A high performance AIX: on FPGA for a DNN-based inference accelerator commercial speech recognition Area Coffee Break in Exhibition Transfer and Online Reinforcement Learning in STT- and Online Reinforcement Transfer for Autonomous MRAM Based Embedded Systems Drones NeuADC: Neural Network-Inspired RRAM-Based Network-Inspired Neural NeuADC: with Conversion Analog-to-Digital Synthesizable Support Quantization Reconfigurable for Deep Accelerator A Nanophotonic Holylight: Centers Learning in Data neering, Southwest University, CN; Southwest University, neering, Engineering, Indiana University, US; US; University, Indiana Engineering, 1 1 Speaker: Insik Yoon, Georgia Institute of Technology, US Technology, Institute of Georgia Yoon, Insik Speaker: Authors: Insik Yoon Speaker: Weichen Liu, School of Computer Science and Engineering, Science and Engineering, School of Computer Liu, Weichen Speaker: CN Singapore, University, Technological Nanyang Weichen Liu Authors: Speaker: Xuan Zhang, Washington University St. Louis, US St. University Louis, Washington Zhang, Xuan Speaker: Zhang, and Xuan Chakrabarti Ayan Xin He, Cao, Weidong Authors: US University, Washington Room 4 1400 Room CN Cheng, Beihang University, Yuanqing Chair: IT Torino, di Politecnico Graziano, Mariagrazia Co-Chair: and learning emerging deep how enable learn technologies and Come - industryrecogni speech from applications: of a wide range for beyond at to drones cloud computing tion in industrial the edge. Room 5 1400 Room FR / Lab-STICC, de Bretagne-Sud Universite Philippe Coussy, Chair: DE Ulm University, Michael Glass, Co-Chair: optimizing the perfor solutions for This session showcases innovation Chongqing University, CN; Chongqing University, KR Telecom, SK Ahn, Minwook Speaker: Seungrok Kim, Wonsub Seok Joong Hwang, Ahn, Minwook Authors: Youngjoon Lim and Woohyung Chung, Mookyoung Lee, Yeonbok Jung, KR Telecom, SK Kim, as well as fault-tolerant and virtualmance of multiprocessors machines, an approach to The first paper presents (DNNs). networks deep neural multiple where scenarios performancein virtual-machine (VM) improve paper applies for The second device. storage a single physical share VMs and heuristic mal (ILP-based) techniques to of scheduling the problem containing multiprocessors asymmetric in tasks computing approximate The paper in- third trade-offs. performance/power with different cores of DNNs robustness the errors, troduces techniques to bit-flip to improve in space and military applica- such as those due to single-event-upsets with firstthe out round session, the presentations interactive Two tions. and the in virtualized multiprocessors, being on migration task and data on how to optimize second the performance of machine learning tasks clusters. in compute and Lei Jiang and Lei Vitello e Mozzarella alla Fiorentina: alla Fiorentina: e Mozzarella Vitello and Fault- Multicore, Virtualization, Tolerance Learning Gets Smarter Gets Learning 100 11.5 1530 1515 1500 1430 1400 11.4 THURSDAY, 28MARCH 2019 THURSDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1530 IPs 1500 1430 1400 11.6 1530 IPs 1500 1430 1400 THURSDAY, 2019 MARCH 28

Microfluidic PlatformsMicrofluidic and Tasks Design Automation Solutions for 1 Chakrabarty 1 1 Authors: Yu-HueiLin Speaker: Bing Li, TUM, DE Authors: ZhishengChen Speaker: XingHuang, National Tsing HuaUniversity, TW Authors: MohamedIbrahim Speaker: MohamedIbrahim, Intel Corporation, US acloserinsight. to get this domainandwant curios about the area alsoresearchers resultsthe latest in andinterest but in whoare This variety makesthis sessionidealfor both, already experts working include parameter spaceexploration, physical synthesis, andwashing. chips, andProgrammable Microfluidic Devices (PMDs). The covered tasks arraysbased onmicro-electrode-dot (MEDA biochips), flow-based bio- precisely,the presentations are covering platforms suchasbiochips which covers both, awiderange ofdifferent platforms tasks. More and The sessionprovidestalks ondesignautomation for microfluidic devices Co-Chair:Andy Tyrrell, University of York, GB Chair: Wille, JohannesKeplerRobert University Linz, AT Room 61400 Authors: Lei Mo Speaker: Lei Mo, FR INRIA, Authors: ChristophSchorn Speaker: ChristophSchorn, BoschGmbH, Robert DE University, KR Authors: Taehyung Lee, MinhoLee and Young IkEom, Sungkyunkwan Speaker: Taehyung Lee, Sungkyunkwan University, KR 1 Yi Ho 1 IP5-14, IP5-15, IP5-16 IP5-12, IP5-13 Coffee BreakinExhibition Area Programmable Devices Microfluidic Block-Flushing: ABlock-based Washing Algorithm for Biochips Distributed Considering Channel Storage Physical Synthesis ofFlow-Based Microfluidic Biocircuits UsingMEDA Biochips BioScan: Parameter-Space Exploration ofSynthetic Coffee BreakinExhibition Area MulticoreAsymmetric Processors Approximation-aware Task Deployment on for DeepNeural Networks An Efficient Bit-Flip ResilienceOptimization Method I/O Interference VM-aware Flush Mechanism forMitigating Inter-VM INRIA, FR;INRIA, BoschGmbH,Robert DE; Fuzhou University, CN; Duke University, US; National TsingUniversity,Hua TW; 2 and Ulf Schlichtmann andUlf 2 IRISA/INRIA, Univ.IRISA/INRIA, Rennes, FR 1 – 1 1530 , AngelikiKritikakou 1 , Tsung-YiHo 2 Indian Statistical Institute, Kolkata, IN 2 1 National TsingUniversity,Hua TW; , XingHuang 2 RWTH AachenUniversity, DE 1 , Andre Guntoro 1 3 , Bhargab Bhattacharya 1 , BingLi 2 2 TUM, DE andOlivierSentieys 2 ,Guo Wenzhong 2 and Ulf Schlichtmann andUlf 1 andGerd Ascheid 2 andKrishnendu 1 , BingLi 1 3 TUM, DE 2 3 , Tsung- 2 101

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - 3 Yunnan University, CN; University, Yunnan www.date-conference.com 2 and Weichen Liu Weichen and 2 , Di Liu , 1 1530 – , Nan Guan , 1 1530 – The Hong Kong Polytechnic University, HK; University, Polytechnic The Hong Kong SG University, Technological Nanyang in Exhibition Area Coffee Break in Exhibition in Exhibition Area Coffee Break in Exhibition Analyzing GEDF Scheduling for Parallel Real-Time Real-Time for Parallel GEDF Scheduling Analyzing Deadlines Arbitrary with Tasks for Fixed-Priority Methods and General Simple Problems in Optimization Schedulability of Streaming Applications Scheduling Real-Time Hard CSDF Graphs as Cyclic Modeled 1 age and test-case generation while reducing the while reducing time and resources age and test-case generation required. will learn you In this set of tutorial sessions, using lat system architectures and software hardware How to evaluate in Simulink est feature and ARM FPGA the How to implementthat an application leverages SOC of a Zynq core examples that of through the approach and diversity The flexibility algorithm and a video-processing a motor control include prototyping algorithm. design and workflowcombines system level co-design that A HW/SW generation code with automatic simulation MathWorks, US MathWorks, John Zhao, Organiser and Speaker: embedded-system for a rich environment and Simulink provide MATLAB to algorithms ready specialized of proven, with libraries development, enables a model-based The environment specific applications. use for of the algo- fast and implementation prototyping for design workflow A system- such as MPSoC. embedded rithms on heterogeneous targets, and partitioning, exploration enables architectural design approach level workflows. and HW development between SW as well as coordination cover throughout improves verification design process the Functional 1400 Theatre Exhibition Speaker: Paolo Pazzaglia, Scuola Superiore Sant Anna, Pisa, IT Pisa, Sant Anna, Scuola Superiore Pazzaglia, Paolo Speaker: Scuola Di Natale, Marco Biondi and Alessandro Pazzaglia, Paolo Authors: IT Sant'Anna, Superiore NL University, Leiden Sobhan Niknam, Speaker: Uni- Leiden Stefanov, Todor and Wang Peng Sobhan Niknam, Authors: NL versity, Speaker: Xu Jiang, The Hong Kong Polytechnic University, HK University, Polytechnic The Hong Kong Jiang, Xu Speaker: Jiang Xu Authors: 3 Room 7 1400 Room IT of Pisa, Sant’Anna Scuola Superiore Di Natale, Marco Chair: NL Delft, TU Nasri, Mitra Co-Chair: global of fixed-priority, with generalization papers This session presents flows. data to synchronous and applications EDF, An Industry Approach to FPGA/ARM System Approach to FPGA/ARM System An Industry (part 1) Verification and Development Extending Scheduling Schemes Scheduling Extending • • • • 102 1530 1530 11.8 1500 1430 1400 11.7 THURSDAY, 28MARCH 2019 THURSDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com IP5-9 IP5-8 IP5-7 IP5-6 IP5-5 IP5-4 IP5-3 IP5-2 IP5-1 IP5 THURSDAY, 2019 MARCH 28 Interactive Presentations 1 1 1 (TU Wien),AT Seoul National University, KR Authors: SeongsikPark, JaeheeJang, SeijoonKimandSungroh Yoon, Speaker: SeongsikPark, SeoulNational University, KR University ofNotre Dame, US Authors: AnnFranchesca Laguna, MichaelNiemierandX, Sharon Hu, Speaker: Ann Franchesca Laguna, University ofNotre Dame, US Authors: Rapp Martin Speaker: Rapp, Martin Karlsruhe Institute of Technology, DE Montreal, Quebec, CA andComputer ofElectrical ment Engineering, Concordia University, Authors: MahmoudMasadeh, OsmanHasanandSofiene Tahar, Depart Speaker: MahmoudMasadeh, Concordia University, CA 3 Authors: Dimitra Papagiannopoulou Lowell, US Speaker: Dimitra Papagiannopoulou, University ofMassachusetts Authors: ZhengZhao Speaker: David Z.Pan, University of Texas, Austin, US University, HK Authors: Farah Naz Taher Speaker: Farah Naz Taher, University of Texas Dallas, at US Authors: MoslemDidehban Speaker: HwisooSo, Yonsei University, KR Authors: Hussain Sajjad Speaker: Hussain, Sajjad Chairfor EmbeddedSystems, KIT, DE Poster Area 1530 tation inacorresponding regular session. Additionally, paper is briefly introduced each IP in a one-minute presen- Interactive Presentations runsimultaneouslyduringa30-minuteslot. byCadence AcademicNetwork supported 1 hao Feng 1 1 and IrisBahar Zhu oungwoo Lee Augmented Neural Networks onanFPGA Energy-Efficient InferenceAccelerator forMemory- Neural Networks Design ofHardware-Friendly MemoryEnhanced Cores Prediction-Based Task Migration onS-NUCA Many- Approximate Computing Using MachineLearningforQuality Configurable Violations forEnergySavings usingHTM IgnoreTM: Opportunistically Timing Ignoring Optical LogicSynthesis Exploiting Wavelength Division Multiplexing for Diversity throughHigh-Level Synthesis Common-Mode Failure Mitigation: Increasing Hard ErrorDetection andRecovery A software-level Redundant MultiThreading forSoft/ Architecture Thermal-Awareness inaSoftErrorTolerant Karlsruhe Instituteof Technology, DE; Arizona State University, US; Karlsruhe Instituteof Technology, DE; Boston University, US; University ofMassachusettsLowell, US; University of Texas, Austin, US; The University of Texas Dallas, at US; 1 andBenjaminCarrion Schaefer 1 , Ray T. Chen 2 4 – 1600 1 1 , Derong Liu 1 , AnujPathania andDavid Z.Pan 4 1 Brown University, US , MuhammadShafique 1 , Matthew Joslin 1 , HwiSooSo 2 Yonsei University, KR 2 Cadence DesignSystems, US 2 ,Zhoufeng Ying 1 1 2 ,Sungseob Whang National University ofSingapore, SG 1 2 , TulikaMitra The HongKong Polytechnic 2 Vienna University of Technology 1 2 , Aviral Shrivastava 2 CloudHealth Technologies,US; 1 , AnjanaBalachandran 2 andJoerg Henkel 1 , BiyingXu 2 andJoerg Henkel 2 , TaliMoreshet 1 andKy 1 , Cheng- 2 1 , Zhiqi - 103 1 - 3

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - Uni- , 3 2 and Jonathan and Jonathan 1 , Chunhua Xiao , 3 Hong Kong Polytechnic Polytechnic Hong Kong 5 www.date-conference.com 2 Chongqing University, CN; Chongqing University, , Yakovlev Alex , 2 1 , Wanli Chang Wanli , 6 2 University of Westminster, GB Westminster, of University 2 and IzzetKale 1 Temporal Computing, GB Computing, Temporal 2 , Rishad Shafik , 1 and Lei Jiang and Lei 5 , Mengquan Li , 1 Southwest University, CN; Southwest University, 4 1730 Indiana University Bloomington, US Bloomington, Indiana University 6 – , Nan Guan , 4 2 Nanyang Technological University, SG; SG; University, Technological Nanyang Newcastle University, GB; GB; Newcastle University, university of Westminster, GB; GB; Westminster, of university Semantic Integration Platform for Cyber-Physical for Cyber-Physical Platform Integration Semantic Design System in Systems Latency Reaction Cause-Effect Worst-Case Communication Non-Blocking with Fault Localization in Programmable Microfluidic in Programmable Localization Fault Devices in Sensing Using Micro-ringThermal Resonators Optical Network-on-Chip GENIE: QoS-guided Dynamic Scheduling for CNN- Scheduling GENIE: QoS-guided Dynamic SME Clusters on based Tasks Encoding of Manchester Implementation Adiabatic NFC System for Passive and Power-elastic based Modulation A Pulse Width Perceptron Design Mixed-signal Robust Finding All DC Operating Points Using Interval- Using Points DC Operating Finding All Algorithms Verification Based Arithmetic HDCluster: An Accurate Clustering Using Brain- Clustering Accurate An HDCluster: Computing Inspired High-Dimensional versity of York, GB; GB; York, of versity 1 Yiyuan Xie Yiyuan 1 sity, SE sity, - Van Systems Integrated Software Institute for Qishen Zhang, Speaker: US derbilt University, and Janos Sztipano- Kecskes Tamas Bapty, Ted Qishen Zhang, Authors: US University, Vanderbilt vits, SE Uppsala University, Wang, Yi Speaker: Uppsala Univer Wang, Yi Dai and Gaoyang Abdullah, Jakaria Authors: Room 1 1600 Room FR Nice Sophia Antipolis, Mallet, Frédéric Université Chair: NL Technology, of University Marc Geilen, Eindhoven Co-Chair: Speaker: Mengquan Li, Chongqing University, CN Chongqing University, Li, Mengquan Speaker: Weichen Liu Authors: Speaker: Ulf Schlichtmann, TUM, DE TUM, Ulf Schlichtmann, Speaker: Bing Li and Ulf Schlicht Liu, Chunfeng Bernardini, Alessandro Authors: Speaker: Sachin Maheshwari, University of Westminster, GB Westminster, of University Sachin Maheshwari, Speaker: Sachin Maheshwari Authors: GB MR, Mileiko, Sergey Speaker: Mileiko Sergey Authors: DE TUM, mann, Speaker: Itrat A. Akhter, University of British Columbia, CA Columbia, of British University A. Akhter, Itrat Speaker: of University Mark Greenstreet, and Reiher Justin Akhter, Itrat Authors: CA British Columbia, CN Technology, of Defense University National Zhaoyun Chen, Speaker: - and Chu Wen Mei Yu, Jie Yang, Haoduo Luo, Lei Zhaoyun Chen, Authors: CN Technology, of Defense University National Zhang, nyuan Speaker: Mohsen Imani, University of California, San Diego, US San Diego, of California, University Mohsen Imani, Speaker: Gupta Saransh Worley, Thomas Kim, Yeseong Mohsen Imani, Authors: US San Diego, of California University Rosing, Tajana and 1 University, HK; University, Special Day on "Model-Based Design of Special Day MBD of Safe Session: Systems" Intelligent and Secure Systems Edwards 104 1630 1600 12.1 IP5-16 IP5-15 IP5-14 IP5-13 IP5-12 IP5-11 IP5-10 THURSDAY, 28MARCH 2019 THURSDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 12.3 1715 1700 1630 1600 12.2 1700 THURSDAY, 2019 MARCH 28 Aging, calibration andyield circuits ko ofSynthesizingThe Art Logic 1 1 1 reliability. to mitigateThis sessiondiscussesmethods defects, faults, variability and Co-Chair: NaghmehKarimi, University Baltimore of Maryland county, US US Chair:Hank Walker, TAMU, Room 31600 Authors: AnnaBernasconi Speaker: AnnaBernasconi, Universita, IT Authors: HeinzRiener Speaker: HeinzRiener, EPFL, CH EleonoraAuthors: Testa Speaker: Eleonora Testa, EPFL, CH Authors: Levent Aksoy andMustafa Altun, Istanbul Technical University, TR Speaker: Levent Aksoy, Istabul Technical University, TR a Booleanfunction. time algorithmfor symmetricapproximation computingthe closest for neric logic rewriting algorithm. The fourth paper proposes a polynomial- techniques andintegrates logicsynthesisexact them into ascalablege- resubstitution, AIGoptimization andkerneling. third paperimprovesThe Boolean optimization todifference-based flowincludingenhancements lattice usingBooleansatisfiability. Thesecond paperpresents ascalable an approximate synthesis algorithmfor realizing ona alogicfunction current computing limitsoflogic synthesis. paperintroducesThe first targetssearch new emerging applications of synthesis and extendsthe The recent progress inlogicsynthesis ispresentedthis session. in The re- Co-Chair:Villa, University Tiziano of Verona, IT Chair: Cortadella Jordi,UPC, ES Room 21600 Authors: Ludovic Apvrille andLetitia Li, Télécom ParisTech, FR Speaker: Ludovic Apvrille, LTCI, Télécom ParisTech, Université Paris-Saclay, FR Gaillardon d'Informatica, Università di Verona, IT De Micheli Approximate LogicSynthesis bySymmetrization Networks with ExactSynthesis On-the-fly and DAG-aware: Rewriting Boolean Scalable Boolean MethodsinaModernSynthesis Flow Logic Synthesis UsingSwitching Lattices A Satisfiability-Based Approximate Algorithm for Requirements inEmbeddedSystems Harmonizing Safety, Security andPerformance Università diPisa, IT; EPFL, CH; EPFL, CH; 3 ,Patrick Vuillod 2 2 4 1 UC Berkeley, US Synopsys Inc., US; andGiovanni DeMicheli andMathias Soeken – – 1730 1730 2 , JiongLuo 2 1 Università degliStudidiMilano, IT; , WinstonHaaswijk 1 , LucaAmaru 1 , ValentinaCiriani 3 2 UC Berkeley, US; , ChristopherCasares 1 1 2 , Mathias Soeken 1 , AlanMishchenko 2 and TizianoVilla 4 University ofUtah, US 2 , Pierre-Emmanuel 1 , AlanMishchen- 3 Dipartimento Dipartimento 2 , Giovanni 3 105

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 , - 2 , Mat 1 2 , 1 , Karuna Nidhi Karuna , 1 1 , Andrea Calimera Andrea , 1 2 www.date-conference.com and Xiaoqing Wen and Xiaoqing 1 Texas Instruments Inc., US Inc., Instruments Texas , Deepika Neethirajan Deepika , 2 - Semicon International Vanguard 1 2 , Chung-Chih Hung Chung-Chih , 1 and Yiorgos Makris Yiorgos and 2 2 , Jie Song , 1 , Antonio Cipolletta Antonio , 1 Università di Bologna, IT di Bologna, Università 2 Kyushu Institute of Technology, JP Technology, Institute of Kyushu 2 and Stefano Mattoccia and Stefano , Chauchin Su Chauchin , , Amit Nahar , 2 1 2 , Yuanjie Hu Yuanjie , 1 1730 – , Fabio Tosi Fabio , 2 and Shao-Chang Huang and Shao-Chang 2 Politecnico di Torino, IT; IT; Torino, di Politecnico Anhui University, CN; Anhui University, The University of Texas at Dallas, US; US; at Dallas, Texas of The University National Chiao Tung University, TW; TW; University, National Tung Chiao Exploration and Design of Low-Energy Logic Cells for 1 and Design of Low-Energy Exploration Systems kHz Always-on Monocular Unsupervised Energy-Efficient Enabling on ARMv7-Based Platforms Depth Estimation Dynamic Scheduling on Heterogeneous Multicores Scheduling Dynamic in Near-Threshold Energy Point Optimal the Selecting Computing Bayesian Optimized Importance Sampling for High Sampling Optimized Importance Bayesian Estimation Rate Failure Sigma Seed Calibration Vmin Adaptive Wafer-Level Forecasting and single- self-recoverable double-upset Single-event low design for latch pulse filterable transient event applications power Package and Chip Accelerated Aging Tests for Power for Power Aging Tests Accelerated and Chip Package Evaluation MOSFET Reliability teo Poggi 1 1 1 Speaker: Antonio Cipolletta, Politecnico di Torino, IT Torino, di Politecnico Cipolletta, Antonio Speaker: Peluso Valentino Authors: Speaker: Sami Salamin, Karlsruhe Institute of Technology (KIT), DE (KIT), Technology Institute of Karlsruhe Sami Salamin, Speaker: Karlsruhe Henkel, and Joerg Hussam Amrouch Sami Salamin, Authors: DE Technology, Institute of BE Leuven, KU ESAT-MICAS, Maxime Feyerick, Speaker: KU Verhelst, and Marian De Roose Jaro Maxime Feyerick, Authors: BE Leuven, Speaker: Ann Gordon-Ross, University of Florida, US of Florida, University Ann Gordon-Ross, Speaker: and Greg Ann Gordon-Ross Vazquez, Ruben Edun, Ayobami Authors: US of Florida, University Stitt, Room 4 1600 Room IT di Bologna, Università Tagliavini, Giuseppe Chair: DK of Denmark, University Technical Jan Madsen, Co-Chair: point of views, different design from low-power This session explores - and image process based scheduling of multicores network neural from and continuous computing near-threshold for low-power to ultra ing, monitoring IoT sensors. Speaker: Yiorgos Makris, The University of Texas at Dallas, US at Dallas, Texas of The University Makris, Yiorgos Speaker: Xanthopoulos Constantinos Authors: CN Anhui University, Yan, Aibin Speaker: Authors: Yan Aibin Speaker: Dennis Weller, Karlsruhe Institute of Technology, DE Technology, Institute of Karlsruhe Weller, Dennis Speaker: Saber Golan- Mohammad Michael Hefenbrock, Weller, Dennis Authors: Technology, Institute of Karlsruhe Tahoori, Michael Beigl and Mehdi bari, DE - Interna Vanguard Technology, Department of LAD Lin, Tingyou Speaker: TW tional Semiconductor, Tingyou Lin Authors: Chily Tu TW ductor Corporation, Sirish Boddikurapati 1 Design and Optimization for Low-Power for Low-Power Design and Optimization Applications 106 1715 1700 1600 1630 12.4 1715 1700 1630 1600 THURSDAY, 28MARCH 2019 THURSDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1715 1700 1630 1600 12.6 1700 1630 1600 12.5 THURSDAY, 2019 MARCH 28 Nicollin challenges Trojans andpublickey implementation Kuhn Simulation System ModellingforAnalysis and 1 1 versity, JP Authors: SongBian, Masayuki Hiromoto and Takashi Sato, Kyoto Uni- Speaker: Song Bian, Kyoto University, JP Authors: Hiromitsu Awano andMakoto Ikeda, The University of Tokyo, JP Speaker: Hiromitsu Awano, The University of Tokyo, JP Authors: XiaolongGuo Speaker: Yier Jin, University ofFlorida, US tation challengesofpublickey inASICandFPGA. context FPGAs. ofmulti-tenant two papersdiscussimplemen- The other the otherofpracticalto designanddetect, attacks and methods the in This sessioncontains 2pagerson Trojans, ofwhichoneisonformal Co-Chair: NeleMentens, KU Leuven, BE Chair: PatrickVirginia Schaumont, Tech,US Room 61600 Authors: Matthias Jung Speaker: Matthias Jung, Fraunhofer IESE, DE Authors: Ralf Stemmer Speaker: Ralf Stemmer, Carl von Ossietzky Universität Oldenburg, DE Authors: Pascal Fradet Speaker: Xavier Nicollin, Univ. Grenoble Alpes, FR prototypes usingspeculativetemporal decoupling. Finally, paperaddressesthe simulation ofSystemC-based the last virtual model of computation with aprobabilistic method for real-time analysis. namic systems. The second papercombinesthe synchronous dataflow dataflow modelof computationreconfigurability supporting fordy analysis performance and optimisation. paper proposes a novelThe first ofsystemmodellingforthe importance design,The sessionhighlights Co-Chair: GianlucaPalermo, Politecnico diMilano, IT Chair: Ingo Sander, KTH Royal Instituteof Technology, SE Room 51600 1 1 Grüttner FPGAs Timing Violation Induced Faults in Multi-Tenant Secure Inference DArL: Dynamic Parameter Adjustment forLWE-based Curve Scalar Multiplication FourQ onASIC: BreakingSpeedRecords forElliptic Design andDetection ofCharge-Domain Trojans When Capacitors Attack: Formal MethodDriven Speculative Temporal Decoupling Usingfork() MPSoCs with Shared MemoryCommunication Probabilistic State-Based RT-Analysis ofSDFGs on RDF: Reconfigurable Dataflow INRIA, FR;INRIA, University ofFlorida, US; Fraunhofer IESE, DE; University ofOldenburg, DE; 1 and Norbert andNorbert Wehn 3 andArash Shafiei 2 and Wolfgang Nebel 2 Orange, FR; – – 1730 1730 2 University ofKaiserslautern, DE 1 1 1 , AlainGirault 3 1 , Huifeng Zhu , HenningSchlender G-INP, FR , Frank Schnicke 2 2 2 Washington Louis, University inSt. US 2 OFFIS e.V., DE 1 1 2 , Ruby Krishnaswamy ,Jin Yier 1 , Markus Damm 1 , MaherFakih 1 andXuan Zhang 1 , Thomas 2 , Kim 2 , Xavier 2 107 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - 2 and 2 , Kia , 1 , Bingzhe Li , 2 , Hai (Helen) Li , 1 and Hai (Helen) Li 2 www.date-conference.com , Bing Li , University of Louisiana at of Louisiana University 1 2 , Yiran Chen Yiran , 2 , M. Hassan Najafi , 1 , Bing Li , 1 1730 Duke University, US University, Duke , Grace Li Zhang Grace , 2 – 1 1 , Ziru Li Ziru , 1 1 1730 University of Minnesota, US of Minnesota, University – 3 Duke University, US University, Duke 2 and David Lilja and David 3 Tsinghua University, CN; University, Tsinghua TUM, DE; DE; TUM, US; Cities, Twin of Minnesota, University RED: A ReRAM-based Deconvolution Accelerator A ReRAM-based Deconvolution RED: Un-reliable with DNNDesign of Reliable Accelerator ReRAM Energy-Efficient Convolutional Neural Networks with with Networks Neural Convolutional Energy-Efficient Processing Deterministic Bit-Stream Aging-aware Lifetime Enhancement for Memristor- Lifetime Enhancement Aging-aware based Neuromorphic Computing Bazargan 1 1 Ulf Schlichtmann MathWorks, US MathWorks, John Zhao, Organiser and Speaker: description). Part 2 of tutorial (see Session 11.8 for 1600 Theatre Exhibition Speaker: Saibal Mukhopadhyay, GEORGIA TECH, US TECH, GEORGIA Saibal Mukhopadhyay, Speaker: Institute of Georgia and Saibal Mukhopadhyay, Long Yun Authors: US Technology, Speaker: M. Hassan Najafi, University of Louisiana at Lafayette, US atLouisiana Lafayette, of University Najafi, M. Hassan Speaker: Faraji Abdolrasoul Sayed Authors: US University, Duke Li, Hai (Helen) Speaker: Fan Zichen Authors: stream processing. stream DE TUM, Shuhang Zhang, Speaker: Shuhang Zhang Authors: Room 7 1600 Room GB of Ulster, Harkin, University Jim Chair: CN University, Tong Li Jiang, Jiao Shanghai Institute: Co-Chair: of deep neural to new approaches the acceleration This session presents with papers focusing architectures on ReRAM-based focused networks and devices with unreliable operation challenges of reliable on the key proposed are ReRAM 3D In addition, effects. counter-aging for strategies of processing. In graphics the evolution of general in the acceleration low-coston work energy and efficientemerging computing, stochastic bit with deterministic is also explored networks neural convolutional Speaker: Mirjana Stojilovic, EPFL, CH EPFL, Stojilovic, Mirjana Speaker: CH EPFL, Mirjana Stojilovic, Mahmoud and Dina Authors: Lafayette, US; US; Lafayette, 1 An Industry Approach to FPGA/ARM System Approach to FPGA/ARM System An Industry (part 2) Verification and Development Emerging Strategies for Deep Neural Neural for Deep Strategies Emerging Hardware Network 108 12.8 1715 1700 1630 1600 12.7 THURSDAY, 28MARCH 2019 THURSDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI –1730 1500 1300 1030 W04 W03 W02 –1500 1430 1200 1000 0830 0730 W10 W09 W08 W07 W06 W05 www.date-conference.com WORKSHOPS, FRIDAY, 29 MARCH W01 – – – –

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Workshops Workshops Understanding Hardware Designs(DUHDE6) 6th Workshop onDesignAutomation for Design (ASD2019) DATE Workshop onAutonomous Systems device towards 100trillion synapses ofbrain Technology: thejourneyfromsingle memristor & Recent Science TrendsinMemristor for FPGAs–OSDA Workshop on Open-Source DesignAutomation Quo vadis, LogicSynthesis? Quantum Computing Grand Challenges andResearchTools for Workshop onMachineLearningforCAD Software fortheIndustrial 2019) IoT(ESIIT 2nd International Workshop onEmbedded AxC: 4thWorkshop onApproximate Computing International Demo F1/10Autonomous Racing Coffee Break Workshop Registration Workshops supported by IEEE CEDA – Session 3 –Session CEDA IEEE by supported 2 –Session CEDA IEEE by supported 1 –Session CEDA IEEE by supported University,Michael Glaß,Ulm DE Francisco Cazorla, Barcelona Supercomputing Center andIIIA-CSIC, ES Friday WorkshopsCo-Chairs: Room 4 0845 Room 80830 Room 100830 Room 70830 Room 60845 Room 50830 Room 90830 Room 10830 Room 20830 Room 30830 International Demo F1/10Autonomous Racing Lunch Break (OPTICS) Photonic Interconnects forComputing Systems The 5thInternational Workshop onOptical Workshops International Demo F1/10Autonomous Racing Coffee Break – – – – – – – – – – 1730 1730 1730 1615 1700 1730 1730 1730 1730 1730 109 /

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - - / www.date-conference.com 1730 – WORKSHOP FOCUS: WORKSHOP TOPICS TO BE DISCUSSED INCLUDE BUT ARE NOT LIMITED TO: LIMITED INCLUDE NOT ARE BE DISCUSSED BUT TO TOPICS CMP, FR CMP, Jean Christophe Crebier, Speaker: Invited From system level simulations to silicon photonic to silicon simulations From system level circuit fabrication to From co-simulation for EPSoC design: EPDA Keynote: photonic circuit generators US UC Berkeley, Vladimir Stojanovic, MPW services for Photonics & ICs prototyping Introduction to OPTICS Introduction Room 3 0830 Room Co-Chairs: General HK Technology, of Science and University Hong Kong Jiang Xu, US University, State Colorado Mahdi Nikdast, CA de Montréal, Polytechnique Ecole Gabriela Nicolescu, Chair: Committee Programme Institute of Nanotechnology FR Sébastien Le Beux, Lyon Members: Committee Programme US Boulder, of Colorado University Alan Mickelson, US Boston University, Coskun, Ayse SP de Murcia, Católica Abellán,Universidad José L. US Northwestern University, Hardavellas, Nikos INRIA, FR Olivier Sentieys, JP University, Kyoto Ishihara, Tohru CN University, Tong Shanghai Jiao Ye, Yaoyao FR CNRS – FOTON, Léger, Yoan technolo- of alternative an exploration Law is slowing down, As Moore’s at architectures CMOS-based traditional replace to developed are gies constraints stringent application the heart processing. Moreover, of data artificial systems, intelligence centers, in data data transfers on massive - new com requires (eHPC), and embedded high-performance computing interconnect Sili- technologies. systems with novel munication-centric this compat its achieve to to thanks candidate prime a is photonics con etc. mal devices, ibility with CMOS fabrication process, scalability, and growing maturity. maturity. and growing scalability, process, fabrication ibility with CMOS photon- in silicon aims at discussing the most advances OPTICS recent fabrication the device topics from covering systems, computing ics for circuit design up optimization through to all system-level the way the of is The workshop (EPDA). Automation Design with Electronic-Photonic high-performance photonics, working on silicon interest to researchers of It of invited talks the is comprised systems and EDA/EPDA. computing mosthighest out industry and academia addressing recent caliber from opportunitiesa new and and panel Ideas a during discussed comes. are progress. works-in session highlights poster presentations refereed non-uniformity/thermal Design Automation): (Electronic-Photonic EPDA modeling interconnects crosstalk-aware floor-planning, design, aware etc. and simulation, optical-electronic hybrid interconnects, Interconnects: Inter/Intra-chip - proto communication optical switched networks, passive/active-based design etc. I/O cols, - res center, data embedded high-performance computing, Applications: etc. all-optical logic gates, computing, ervoir on-chip circuit demonstrator, and Circuits: Photonics Devices Silicon ather optical switches, modulators, electro-optic photodetectors, lasers, Photonic Interconnects for Computing for Computing Interconnects Photonic (OPTICS) Systems on Optical Workshop International The 5th • • • • 0940 – 1000 0830 – 0840 110 0840 – 0940 0840 – 1000 W01 FRIDAY, 29 MARCH 2019 FRIDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1030 –1050 1030 –1150 1000 –1030 FRIDAY, 2019 MARCH 29 1150 –1200 1130 –1150 1110 –1130 1050 –1110 1200 –1300 Invited Speaker: JunShiomi,Kyoto University, JP Speed Approximate Parallel Multipliers Integrated OpticalNeural Networks Exploiting Light Invited Speaker: Zurich, IBM Offrein, Bert CH computing paradigms Advancing siliconphotonics fortraditional andnovel Invited Speaker: Fabio Pavanello, IMEC, BE a transceiver application in65nmbulk CMOS advanced CMOSplatforms usingaphotonicsmodule: Electronics-photonics integration in Invited Speaker: Timo Aalto, VTT,FI and I/Ocoupling 3 µmand12SOIplatforms foropticalinterconnects IO andcomputing Silicon Photonicsforon-chip interconnects, Coffee Break Lunch Break versity, CA Hassnaa El-Derhalli, SébastienLe BeuxandSofiene Tahar, Concordia Uni- Stochastic Computing with Integrated Optics Xuanqi Chen, Zhifei Wang and Yi-Shing Chang, al., et HKUST, andIntel, CN US Photonic Networks BOSIM: Holistic OpticalSwitch ModelsforSilicon Lucien DelBosque, IanO'ConnoR andSébastienLe Beux, ECL, FR Hardware Emulation Platform ofOpticalNetwork-on-Chip Peng Yang, Zhifei Wang, Zhehui Wang andJiangXu, HKUST, CN Rack-Scale Computing Systems RSON: anInter/Intra-Chip SiliconPhotonicNetwork for Thales andResearch Technology, FR, andC2N, FR Maxime Delmulle, Sylvain Combrié, Fabrice Raineri and Alfredo De Rossi, Zhifei Wang, JiangXu, Peng Yang, al., et HKUST, CN Fabric forData Center High-Radix Nonblocking Integrated OpticalSwitching Tsun-Ming Tseng, Schlichtmann, Ulf TUM, DE Design Automation forWavelength-Routed OpticalNoCs Poster Presentation (session 1) Integrated spikingnanolaser 111

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com Quantitative Analysis of Optical/Electrical of Optical/Electrical Analysis Quantitative Interfaces and Optical-Electrical Interconnects MOCA: an Inter/Intra-Chip Optical Network for Optical Network Inter/Intra-Chip an MOCA: Memory Coffee Break Zhehui Wang, Jiang Xu and Zhifei Wang, et al., HKUST, CN HKUST, et al., Wang, and Zhifei Jiang Xu Wang, Zhehui Core Many Up your Light FR ECL, Beux and Ian O'Connor, Sébastien Le Clément Zrounba, Power through Adaptive Crosstalk Noise Reduction Optical Networks in Inter/Intra-Chip Control CN HKUST, et al., Wang, and Zhifei Yang Peng Luan Huu Kinh Duong, Zhehui Wang, Jiang Xu and Zhifei Wang, et al., HKUST, CN HKUST, et al., Wang, and Zhifei Jiang Xu Wang, Zhehui Optical Networks Design with System-Level Enabling and Integration Architecture Through On-Chip Synthesis Topology of University et al., Schrape, and Oliver Maddalena Nonato Tala, Mahdi DE IT and IHP Microelectronics, Ferrara, FODON: Ultra-High-Radix Low-Loss Optical Switching Switching Optical Low-Loss Ultra-High-Radix FODON: Fabric CN HKUST, et al., and Jiang Xu, Wang Zhehui Wang, Zhifei III-V on Silicon nano- hybrid with All-optical sampling for photonic computing resonators De Rossi, and Alfredo Raineri Fabrice Combrié, Sylvain Constans, Léa FR FR and C2N, Technology, Thales and Research Hardware-software Co-design of Optical Neural Co-design of Optical Neural Hardware-software Networks Z. Chen and David T. Ray Ying, Zhoufeng Zheng Zhao, Speaker: Invited US at Austin, Texas of The University Pan, (session 2) presentation Poster C2N, FR C2N, Vivien, Laurent Speaker: Invited on for optical networks multiplexing Mode division and limitations potential – chip FR Foton, Christophe Peucheret, Speaker: Invited for high III-V on silicon nanodevices semiconductor computing performance FR University, Raineri, Paris-Sud Fabrice Speaker: Invited New Devices for New Architectures for New Devices New in silicon photonics advances Recent 1430 – 1500

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1500 –1520 1500 –1620 FRIDAY, 2019 MARCH 29 1720 –1730 1620 –1720 1600 –1620 1540 –1600 1520 –1540 Concluding Remarks andClosing Session Vladimir Stojanovic, UCBerkeley, US Vivien, C2N,Laurent FR Yvain CEA-Leti, Thonnart, FR Ian O’Connor, ECL, FR Chair: University Davide ofFerrara, Bertozzi, IT into therealworld Panel: on-chip Bringing opticalinterconnects Invited Speaker: FR Cédric Killian,IRISA/INRIA, adaptability ONoCs: fromofflineoptimization toruntime Invited Speaker: Aditya Narayan, BostonUniversity, US Network-on-Chips A System-Level Perspective onSiliconPhotonic Invited Speaker: Schlichtmann,TUM, Ulf DE and BreakingDown Barriers EDA forWRONoCs: FromTopology toPhysical Design, Invited Speaker: UmarKhan,IMEC, BE Designing large-scale photonicintegrated circuits Toward largescale on-chip opticalinterconnects Panelists:

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FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - - - 2009), 2009), – www.date-conference.com Politecnico Milano, Italy. He received the Laurea (cum Laurea the received He Italy. Milano, Politecnico 1730 – 2011, and the EU Marie Curie Fellow award, 2013. Prof. Chua is Chua Prof. 2013. award, and Fellow Curie Marie EU the 2011, – 2017) and DATE (2017). He is a Senior Member of the IEEE. He was 2017) and DATE – AIM ANDAIM FOCUS AND SPEAKERS INVITED KEYNOTE ents. He was elected as a foreign member of the European Academy of Academy member of the European elected as a foreign He was ents. member of the Hungar a foreign in 1997, Sciences (Academia Europea) of the Institute fellow and an honorary of Sciences in 2007, ian Academy in Germany, of Munich, University Technical Study at the of Advanced including the Frederick major prizes, with many honored 2012. He was in Award Pioneer the IEEE Networks Neural in 1974, Emmons Award Fel- the Guggenheim in 2005, Award the first Kirchhoff IEEE Gustav 2000, dur Kingdom) (United Award Professor Leverhulme 2010, in award low 2010 ing of all fields the in 2002 from a Recipient top 15 most cited authors Award from period 1991 of engineering published during to 2001, the 10-year (ISI) database. Contents the Current Ielmini, Daniele 1995in Milano di Politecnico from Engineering Nuclear in Ph.D. and laude) at the Dipartimento di Elettronica, Professor He is a Full respectively. e 2000, as appointments after di Milano, Politecnico e Bioingegneria, Informazione in 2010. He held visit Professor in 2002 and Associate Assistant Professor (2006) and the University Stanford (2006), Corporation ing positions at Intel interests of Illinois at Urbana-Champaign (2010). His research University such memories, of non-volatile include and characterization the modeling memory phase change (PCM), memory, charge trap as nanocrystal memory, magnetic torque and spin-transfer switching memory(RRAM), resistive switching - the book 'Resistive he coedited In 2016, memory (STT-MRAM). Wiley-VCH. for applications' device to redox-processes fundamental from than 250 papers published more 8 book chapters, He authored/coauthored and conferences, atinternational presented and journals international in with an H-index than 5300 citations, more received His works 6 patents. - Subcom Technical October in several 2016). He has served of 41 (Scopus, such as IEEE-IEDM (2008 conferences, mittees of international IEEE-IRPS (2006 – 2008), IEEE-SISC – 2010), (2008 INFOS (2011 – 2017), ISCAS (2016 - in 2015. He re Thomson Reuters by a Highly Cited Researcher recognized - Consolida the ERC in 2013, Award Outstanding Researcher the Intel ceived and in 2015. Rappaportthe IEEE-EDS Award Paul in 2014, tor Grant Room 2 0830 Room Organisers: KR University, Min, Kookmin Kyeong-Sik DE Dresden, Universität Technische Tetzlaff, Ronald IT Torino, di Politecnico Corinto, Fernando - Tech Science & in Memristor Trends on Recent focuses This workshop 100 trillion single memristor device towards from the journey nology: in 1971 and predicted theoretically Memristors were synapses of brain. have a lot of researches in 2008. Since then, experimentally demonstrated - memristor uses of non-vol possible been done technologyto develop for systems, neuromorphic logics, computing analog circuits, memories, atile we etc. of memristor science and In workshop technology, this special about some invited oftechniques talks state-of-the-art the recent have also discuss We etc. fabrication, integration, & systems, memristor circuits mimic human brain's systems can neuromorphic how memristor-based - real ~1014 synapses for and with ~1011 neurons architecture neuronal hope that can be this workshop We systems. neuromorphic izing future challenges of memristor the recent we review where forum, a premier - technology possibility of artificial-intelligence hard and discuss future be based on memristor science and which can technology. ware of the invention his He is widely known for USA. Berkeley, Chua, Leon O. in- memristor and has been recognized Chua's Circuit.the His research 16 honorary including major awards, numerous through ternationally pat and 7 U.S. and Japan, in Europe major universities from doctorates Recent Trends in Memristor Trends ScienceRecent & the journey from single Technology: 100 trillion towards memristor device of brain synapses 114 W02 FRIDAY, 29 MARCH 2019 FRIDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com FRIDAY, 2019 MARCH 29 committee of the IEDM fromcommitteethe IEDM 2015 of chatronicstechnologies the memory fromtill 2015 and served on 2008 tor grant. Dr.the journal,the editorialboard Sebastianserved of on Me- In 2015hewas awardedthe European Research Council (ERC) consolida- the field ofmico-/nanoscalehis contributionsto mechatronic systems. he receivedthe IFAC Mechatronic Systems Young Researcher Award for tions onControl Systems Technology OutstandingPaper Award. In2013 Control2009 IEEE Systems Technology Awardthe 2009IEEE and Transac- Zurich. computingmemory IBM Dr. at Sebastian isaco-recipientthe of technologies andcurrentlythe research memory on in- leads effort He was acontributorto several keythe spaceofstorage projects in and Mathematics) from Iowa State University in1999and2004, respectively. in 1998andM.S. andPh.D. degrees Engineering(minorin inElectrical degree andElectronics Engineering from inElectrical BITS Pilani, India, Master Inventor Research IBM at - Zurich. He received a B. E. (Hons.) Abu Sebastian, the IEEE. of Design Automation Association (EDAA) Award for 2001.Heisamember ment,the European engineering, Hewasthe recipient of product etc. for semiconductor memories, designfortestability, BIST, yieldenhance- test,and systematic generation fault modeling,test andoptimization ests include and reliability,VLSItest CMOS deep-submicron ICdesign (e.g.,with industrialpartners Intel, ST, Infineon, etc).His research inter the areatesting; ofcooperationthem arethe result manypapers in of of 40conferencethe authorofabookandabout Hamdioui is andjournal time inyieldimprovement for advanced semiconductor memories.Dr. yield ramp andfor activities developing systematic ways ofreducingthe lands, where hewas responsible for drivingadvanced debugand product and halfyears withPhilipsSemiconductors inFrance and The Nether new generations ofmicroprocessors. Inaddition, morethan one hespent the embeddedcachedesignsin advanced andmultiport Intel single-port responsible for solutions developing test for and efficient new low-cost Intel Corporation inSanta Clara andFolsom, California, where hewas eraltesting inparticular. andmemory acouple Hespent ofyears with a consultant and/or asresearcher issuesingen- anddevelopertest on yearsHe hasmorethan eight ofexperience andacademiaas inindustry The Netherlands. He iscurrentlythe Delft University with of Technology. grees (bothwithhonors) fromtheDelft University of Technology, Delft, Said Hamdioui, TU Delft, Netherlands. He receivedthe MSEEandPhDde- memories. over $100M VCto dateto develop funding generation next non-volatile ofCrossbarScientist Inc, aSilicon Valley semiconductor company with ing 11Ph.D. students and3Postdocs. Heisalsoco-founder andChief tions withanh-factor of61(GoogleScholar).Prof. Lu iscurrently advis- published over havethat 100journalpapers received over 20,000cita- 2016 in 2012, 2014-15Rexford E.HallInnovation Excellence Award,the and AwardNSF CAREER in2009, EECSOutstandingAchievement Award Fellow,He isanIEEE Associate Editor for Nanoscale,the arecipient of currently aProfessorthe LurieNanofabrication andDirector of Facility. the facultyMA.the University Hejoined of ofMichiganin2005andis he was apostdoctoral research fellow Harvard at University, Cambridge, China, and Rice University, Houston, TX respectively. Fromto 2005, 2003 B.S. (1996)andPh.D(2003)inphysics from Tsinghua University, Beijing, nowiretransistors, andotheremerging devices. Hereceived electrical his and memristive systems, neuromorphic circuits, aggressively scaledna- two-terminal resistive based on ty memory devices (RRAM), memristors Wei Lu, University ofMichigan.Hisresearch- interest includeshigh-densi devices. lector current research interests includeneuromorphic device, ReRAM andse- papers.His technology morethan 360journalpapersand32IEDM/VLSI of Scienceand Technology (POSTECH), SouthKorea. Hehaspublished Korea in1997. Since 2012, hehasbeenaProfessor Pohang at University InstituteofScienceand Gwangju gineering at Technology (GIST), South a seniorresearcher, hebecameaProfessor ofMaterials ScienceandEn- versity of Texas Austin, at USA in 1992. After five years at LG Semicon as Hyunsang Hwang received his Ph.D. in Materials Science fromthe Uni- – 2017 David E.Liddle Research Excellent Award. To date hehas IBM Zurich.IBM He is a Principal Research Staff Member and – 2016. 115 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - www.date-conference.com - He re USA. Barbara, Santa Inc., Technologies Mentium Prezioso, Mirko and physics the matter condensed in theoretical degree the M.S. ceived science and materials technology from the in advanced degree Ph.D. Since respectively. in 2004 and 2008, Italy, Parma, of Parma, University of with University the Assistant Professor Research a been has he 2013, he has been where USA, CA, Barbara, Santa Barbara, at Santa California hardware. and neuromorphic working on memristors Xia Qiangfei Dr. USA. Amherst, of Massachusetts, University Xia, Qiangfei Amherst Engineering at UMass of Electrical & Computer is a professor Lab . He received Systems and head of and Integrated the Nanodevices Princeton University, in Electrical in 2007 from Engineering his Ph.D. in Engineering of a recipient Guggenheimthe Fellowship he was where Princeton). He as a from then spent years three fellowship graduate (a - Cali Alto, in Palo Laboratories in the Hewlett associate Packard research Amherst of UMass as an he joined the faculty In October 2010, fornia. - started clock pro (tenure in January 2011). He was assistantprofessor in January with 2016 and tenure then moted professor to an associate include interests Xia's research in September 2018. Dr. a full professor and enabling systems technologies, integrated devices, beyond-CMOS RF systems reconfigurable in machine intelligence, with applications Award Faculty Young a DARPA He has received security. and hardware and Joseph I. Goldstein H. and the Barbara an NSF CAREERAward, (YFA), Xia to graduate teaches freshman Dr. Award. Outstanding Junior Faculty Engi- to Electrical including Introduction and Computer courses, level Microelectronic (ECE Devices Semiconductor 344), neering (ENGIN 112), (ECE571) Engineering (ECE and Nanostructure 597/697NS). Fabrication a cam- (DTA), Award Teaching the Distinguished for nominated He was atteaching UMass. exemplary highestpus-wide honor recognize to International the for member a as serves Xia committee technical Dr. and Nano- Technology Beam and Photon Ion, on Electron, Conference and Symposium the IEEE International (EIPBN) conference, fabrication the co-program He was to name a few. (ISCAS), and Systems on Circuits on Nanoimprint & Nanoprint Conference the 14th International chair for and international (NNT). U.S. panelist He is also an active for Technology archival tens of international for and a peer reviewer funding agencies, his most service notable is the UMass, Within journals and conferences. in Hall. He is a the Marcus facility new clean room building of a brand senior member of IEEE and SPIE. the B.S. He received Korea. Seoul, University, Kookmin Min, Kyeong-Sik University, Korea engineering from and computer in electronics degree in electri- degrees and Ph. D. and the M.S.E.E. in 1991, South Korea, Seoul, - Technol and Science of Institute Advanced Korea from engineering cal he In 1997, respectively. in 1993 and 1997, South Korea, Daejeon, ogy, engaged in the develop he was where Inc., joined Hynix Semiconductor, ment of low-power and high-speed DRAM circuits. From 2001 to 2002, 2001 to 2002, From circuits. and high-speed DRAM ment of low-power Japan, Tokyo, Tokyo, of with the University Associate a Research he was logic circuits. memories and low-leakage he designed low-leakage where Seoul, University, of Kookmin he joined the Faculty In September 2002, in of Electricalthe School a Professor he is currently where South Korea, of California, with the University Professor Visiting Engineering. a He was August 2008 from to July 2009. His research USA, CA, Merced, Merced, and power IC design. memory design, VLSI, low-power include interests and He is a member of Engineers of Korea, the Institute of Electronics Engineers Communication and Information, Electronics, of Institute the Asian as such committees, program technical various on was He Japan. in SoC Design Conference, International Conference, Circuits Solid-State were He and his students on Semiconductors. Conference and Korean IDEC of the recipient IDECthe (2011), & Design Methodology CAD Award and IDEC Award Chip Design Contest (2011), Award Chip Design Contest (2012). de- the Laurea He received Italy. Torino, di Politecnico Corinto, Fernando - and communica in electronics degree and electronics in the Ph.D. gree Doc- and the European respectively, tions engineering in 2001 and 2005, he In 2004, Italy. Torino, Torino, di all from the Politecnico in 2005, torate (within Curie Actions'the 'Marie under the Fellowship Marie Curie won a of an Assistant Professor He is currently Programme). Sixth Framework Torino. di Politecnico Theory with the Dipartimento di Elettronica, Circuit dynamical cir of nonlinear mainly in activitiesthe areas are His research He networks. nonlinear/nanoscale cuits and systems and locally coupled papers. journal and conference than 90 international of more is coauthor journals and international papers for of several He has been reviewer 116 FRIDAY, 29 MARCH 2019 FRIDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com FRIDAY, 2019 MARCH 29 Devices, andSystems (MEMRISYS) 2019. gram Chairforthe International Conference onMemristive Materials, the in2016.Heis Networkstheir Applications and (CNNA) Technical Pro- Session Chairforthe 15thInternational Workshop onCellular Nanoscale cuits, Systems, andApplications". HehasbeenProgram ChairandSpecial the COSTin "Memristors-Devices, IC1401MemoCIS Action Models, Cir Committeeden. Since2014heisManagement Substitutefor Germany conferred aPerformance BonusAward from Technische Universität Dres- ofEducation.the ItalianMinistry fromTheory InNovember 2017hewas conferredtitle asAssociatethe habilitation Professor Circuit inElectrical ing Technical Committee sinceMay (CNNAC) 2017.InApril2017hewas asSecretary foracts the Cellular NanoscaleNetworks andArray Comput of Circuit anditsApplicationsTheory (IJCTA) Paper 2007 Best Award. He and memristors. Dr. Ascoli was honoredthe International with Journal cuits and systems, networks of oscillators, Cellular Nonlinear Networks Hisresearchtrical Engineering. intereststhe area liein ofnonlinearcir where heiscurrently pursuingaHabilitation inFundamentals ofElec- andComputerElectrical Engineering, Technische Universität Dresden, Czech Republic. Since2012heisScientific Collaborator the in Faculty of ofMicroelectronics,Department BrnoUniversity of Technology, Brno, Politecnico di Torino. Since2018heisScientific Collaborator the with ofElectronics and the Department in Assistant Telecommunications at CSRSwedenanalog engineerat AB. Fromto 2012hewas 2009 Research versity College Dublinin2006.Fromto 2009heworked 2006 asRFIC Alon Ascoli received aPh.D. Degree inElectronic Engineeringfrom Uni - Engineers,of Electrical Committee. the GermanURSI andof Society (2001 PAPERS.LAR Prof. TetzlaffIEEE CAS was "Distinguished the Lecturer" of forthe IEEE TRANSACTIONS SYSTEMS—PART AND ONCIRCUITS - I: REGU networks, andmemristors.Fromto 2003hewas 1999 Associate Editor system modellingandidentification, Volterra systems, cellularnonlinear Germany. Hisscientific ofsignalsandsystems, theory interests the liein mentals Engineeringat ofElectrical Technische Universität Dresden, Ronald Tetzlaff, sium onMemristor. on Cellular NanoscaleNetworkstheir Applications and and 3rd Sympo- 2007. Dr. Corinto wasthe Technical Program Chairforthe 13th Workshop andSystems.cuit Heisalso Visiting Professor PPCUofBudapest, at since on Cellular NanoscaleNetworks andArray Computing andNonlinearCir CASthe IEEE, ior Memberof the IEEE Memberof Technical Committees principal investigator of several research projects. Since 2010, he is Sen- conferences andchairofsessionsininternational conferences.the Heis – 2002). He is a member of the ITG,2002). Heisamemberof the GermanSociety of TU Dresden, Germany. HeisaFull Professor ofFunda- 117 - - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com Retrieve Gene Design and Analysis Gene Design and Analysis Retrieve / Politecnico di Torino, IT Torino, di Politecnico Corinto, Fernando Speaker: Invited Network-inspired Neural Memristor Cellular Processing for Signal Paradigms DE Dresden, TU Tetzlaff, Ronald Speaker: Invited Store Memristor CNNfor Bistable-like DE Dresden, TU Alon Ascoli, Speaker: Invited University of Massachusetts, Amherst, US Amherst, of Massachusetts, Xia, University Qiangfei Speaker: Invited Memristor-crossbar-based networks: neural from ideal to reality KR University, Min, Kookmin Kyeong-Sik Speaker: Invited Memristor Networks Oscillatory with Computing Mentium Technologies Inc., US Inc., Technologies Mentium Prezioso, Mirko Speaker: Invited memory computational using imprecise Computing CH Sebastian, IBM Abu Zurich, Speaker: Invited Coffee Break for Brain-Inspired Crossbar Arrays Memristive Computing Lunch Break Devices: Memristive on Based Computation-in-Memory is still missing? and what is all about What NL Delft, TU Hamdioui, Said Speaker: Invited a and beyond: circuits for neurocomputing Memristive progress update Resistive switching based Synapse and based Synapse switching Resistive Devices based Neuron switching Threshold for neuromorphic system KR Hyunsang Hwang, POSTECH, Speaker: Invited for neuromorphic and RRAM foundations systems in-memory computing US of Michigan, University Lu, Wei Speaker: Invited UC Berkeley, US Chua, UC Berkeley, Leon O. Coffee Break and circuits for analogue Emerging devices in-memory computing IT Milano, Daniele Ielmini, Politecnico Speaker: Invited Opening session Opening of all the foundation Rules No Backtracking Keynote: memristors non-volatile 1620 – 1645 1645 – 1710 1530 – 1555 1555 – 1620 1400 – 1430 1430 – 1500 1330 – 1400 1130 – 1200 1200 – 1300 1000 – 1030 1100 – 1130 118 1500 – 1530 1300 – 1330 1030 – 1100 0845 – 1000 0830 – 0845 FRIDAY, 29 MARCH 2019 FRIDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com W03 FRIDAY, 2019 MARCH 29 0830 –0950 • • • Design (ASD2019) DATE Workshop onAutonomous Systems Electronic development. In 2009hewasthe "Elec- appointed asheadof development,the in management module- and project VW Electric/ BAN Challenge2007.Fromto 2009he was 2007 responsible for concept the CAROLO-Team with and participated the the finalsof in DARPAUR Controlthe Engineering at Technical University Braunschweig in2005 became aprofessor for "Electronic Vehicle Systems"the Instituteof in head of Telephone-/Telematics andAntenna systemsdevelopment. He Compatibility of Volkswagen AG. In2002Dr. Form wasthe appointed as to 2002heworkedthe Centre asaseniorengineerin for Electromagnetic Engineering asresearch fellow in1987andreceived hisPh.D. in1992.Up sity ofBraunschweig, Germany,the Institutefor joined Communication Born in1959, Thomas Formthe Univer Engineeringat studiedElectrical be solved incooperation with allstakeholders conceivable, can only that task this is an automotive wide that industry to approveauthorities the release is ofautomated It drivingfunctions? which scenarioshavetested andhow,to be to enableregulatory inorder verification and validation concepts, current discussionsare focused on to provideable secondthird path? anindependent function or Regarding the systemisabsolutenecessary.of Is, for example, Intelligence Artificial be evaluated.to economic Inaddition aspects,the redundancy ensuring tem costs. Advantages anddisadvantages ofexisting solutionshaveto sensors,the mainobjectives are miniaturization andreduction ofsys- dundancies aswellverification and validation questions. Regarding there are several unresolved issues regardingtechnologies, sensor re- fromthe Volkswagen AG. However, fortechnologies areleasethese of driving. isacurrent exampleThe vehicle- SEDRIC andmobility-concept companies havethe improvements shown ofautomatedthe sector in In recent years, various publications andpresentations of from alot AG, DE Thomas Form, HeadofElectronics and Vehicle Research, Volkswagen Challenges ofAutomated andConnectedDriving Keynote 1 Keynotes Session two following distinguishedkeynotes: with postersandlive demos.Inaddition,the workshop willfeature the open callfor papers, complementedtalks, byinvited andanexhibition The workshop consists ofregular from sessionswithpapersselected an security. learning, safe andsecure changesandupdates, autonomoussystems systems design, safety functional for applications withmachine to, limited including, not but safety functional concepts, fail-operational ofdependablesystemsdesignforAll aspects autonomoussystems optimization, verification, validation, test. and The designfor autonomoussystemsincludingprocesses, modelling, hardware, software andcommunication. their architectures,execute including the autonomoussystemfunctions Embedded andcyber-physical systemsplatforms and implement that areas: and methodologiesinautonomoussystemsdesign. This includesseveral to exploreThe goalofASDis recent industrialandacademicmethods internationalthe 1st workshopASD is onAutonomous Systems Design. Dirk Ziegenbein, BoschGmbH, Robert DE Selma Saidi,Hamburg University of Technology, DE Rolf Ernst, TU Braunschweig, DE Organisers: Room 10830 HIGHLIGHTS – 1730 119 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com

Keynote 2: Keynote the Impossible – Challenging Adaptive AUTOSAR ing services. Graduated from the State University of New York, Masaki York, of New University the State from ing services.Graduated and in the field of OS architecture of experience than 20 years has more of embedded system appli- use in wide range technologies for related He appliances. and electronic industrial, including automotive, cations - multiple popular Japanese books/interna has authored/co-authored technical given and talks articlestional systems, embedded and OS on directing the technol- servingWhile as a CTO worldwide. in conferences he acts as one of in the architects at eSOL, and architecture ogy strategy years in recent His interest Platform. of Adaptive Architecture Force Task - process parallel architectures, OS/platform next-generation spans from - scrum/kan as well as learning, machine including systems adaptive ing, ban based development. Software CTO at eSOL Co., Ltd., JP Ltd., at eSOL Co., CTO Software Masaki Gondo, - to autonomous driving seem steadily pro related researches The vast vehicle some research to just news - it have gressing no longer makes bringing this technology to market, the However, autonomously. drive with responsibilities, ethical and societal, legal, all with associated the and impossible at its worst.hard at its best, is costjustifiable efficiency, in elec- challenges drastic industry is facing the automotive Furthermore, impact which also heavily - the whole ve services, connected tric vehicles, is ARchitecture) Open System (AUTomotive hicle architecture.AUTOSAR parties. partnership interested of automotive a worldwide development specifica- platform One of its latest challenges is the software to develop named AUTOSAR and autonomous driving, automated the highly tion for of the challenges of such an overview This talk gives Platform. Adaptive reflecting the by of AUTOSAR the solution approach followed a platform, It Adaptive. of AUTOSAR architecture and the overall industrial needs, OS technology a new multi-kernel the author develops, also introduces with chal- the coping for essential is OS architecture such why describing lenge in the long run. POSIX/AUTOSAR/ that provides company the at eSOL, CTO is Masaki engineer and various tools, development software various RTOS, TRON tronics and Vehicle Research" within Volkswagen Group research. Major research. Group Volkswagen within Research" Vehicle and tronics L3 driving in vehicle "Jack" AUDI of presentation the were achievements CESto 2015 in Las San Francisco Journalists from mode with automatic of "SEDRIC"pod driving autonomous the in and presentation the Vegas of funded the German national he is 2017. Since 2016 coordinator the to answer the question "L3 Highway which wants project PEGASUS He got it". enough and how the to prove is safe – how safe Chauffeur significant influence ondevelopment the for Award ADAS e.V. Uni-DAS assistance systems in 2017. of driver and introduction 120

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1300 1300 –1430 1030 1030 –1200 0950 –1000 FRIDAY, 2019 MARCH 29 1140 1120 1000 –1030 1200 –1300 1100 Coffee Break Lab-STICC, FR Sara Zermani andCatherine Dezan UAV CaseStudy Decision MakingEnginebasedonDecision Networks: GenerationIP3: ofaReconfigurable Probabilistic Université Polytechnique Hauts-de-France, FR Mohamed Ouslim Mohamed Yazid Lachachi, Abdelmalik Taleb-Ahmed, SmailNiarand Vehicle ALIDARIP2: Only Perception System forAutonomous Arizona State University, USA and Aviral Shrivastava Rachel Dedinsky, MohammadKhayatian, Mohammadreza Mehrabian Vehicles Intersection Management ofConnectedAutonomous IP1: ADependable Detection Mechanism for Martina Maggio,Martina University ofLund, SE Predictable Cloud Computing Autonomous Data Center –FeedbackControl for Dependable Autonomous Systems Lunch Break University ofBraunschweig, DE Marcus Nolte, MischaMöstl, JohannesSchlatow andRolf ErnstTechnical Automation Systems A Multiview ApproachToward Updatable Vehicle 2 Soroa Inaki Martin for Vehicle Platoons Feasibility Study andBenchmarking ofEmbeddedMPC 3 2 Shota Tokunaga Simulink for ROS-based Self-driving Systems UsingMATLAB/ IDF-Autoware: Integrated Development Framework Ralph Lange, BoschGmbH, Robert DE on Deeply EmbeddedAutonomous Platforms theNextGenerationBringing RobotOperating System Development ApproachesforAutonomous Systems Interactive Presentations 1 1 NXP Semiconductor, NL Eindhoven University of Technology Graduate SchoolofScienceandEngineering, SaitamaUniversity, JP Hitachi Automotive Systems, Ltd Graduate SchoolofEngineeringScience, Osaka University 1 , YukiHorita 1 , AmrIbrahim 2 , YasuhiroOda 1 , DipGoswami 2 and Takuya Azumi 1 andHongLi 2 3 121

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 and 2 and Sebastian 3 www.date-conference.com , Markus Grabowski Markus , , Jeff Stafford , 1 2 Assystem Germany GmbH Assystem Germany 2 , Verena Klös Verena , , Chris Hobbs , 1 1 , Adan Flores , 1 1 1 University of Waterloo, CA Waterloo, of University Limited,CA Systems QNX Software Inc. America Electronics Renesas Technische Universität Berlin, DE, DE, Berlin, Universität Technische Fischmeister 1 Closing & Exhibition Closing Stefan Kowalewski, RWTH Aachen, DE Aachen, RWTH Kowalewski, Stefan Design Automation Change- Concurrent Controlling Integration Systems for Critical DE Braunschweig, TU Ernst, Rolf Panel Discussion Axel Jantsch, TU Wien, AT Wien, TU Jantsch, Axel Coffee Break Systems on Autonomous Research Clusters software service-oriented to automotive An approach research project in a multi-partner architectures Safety and Security Analysis of AEB for L4 Autonomous for L4 Autonomous of AEB Analysis Safety and Security using STPA Vehicle Sharma Shefali 2 3 Self-Reflection Model of Recursive a Formal Towards Fault-Tolerance by Graceful Degradation Degradation Graceful by Fault-Tolerance for Car Platoons E. Zarrouki Mohammed Baha 1 Sabine Glesner 1530 1600 1430 – 1500 1350 1410 122 1630 – 1730 1500 1500 – 1630 1330 FRIDAY, 29 MARCH 2019 FRIDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com W04 FRIDAY, 2019 MARCH 29 0830 –0845 • • • • • • • • • • • • Understanding Hardware Designs(DUHDE6) 6th Workshop onDesignAutomation for Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE Moderators: Workshop opening Future applications ofdesignunderstanding Machine learningfor designunderstanding Formal methodsfor designunderstanding Metrics for cores (open-source) (IP) intellectual property Analysis ofinteraction betweenhardware andsoftware Innovative for GUIs designandverification Reverse engineering Data/Control path extraction functionality Feature localization: Localization ofcode implementing specialized Knowledge extraction from design structures any at level ofabstraction Extraction ofhigh-level properties tronic systemlevel(ESL)to registertransfer down level (RTL) Design descriptionsfromthe formal specification level toelec- (FSL) design understanding: the followingtopics in to The workshop limited focus is not includes but fully understandadesignpre- andpost-synthesis. verify for properties paths security-critical ofadesign,to whichincludes Inhardware unitsfor use. functional aparticular security,to isvital it units, optimizationsto reducethe required area,tailored andspecially standing ofhardware requires into deepinsight concurrently operating to similarproblems.teams leads Under ing size ofdesignsanddesign the hardwaretools. In tackled by area,the re-use ofIP-blocks,the grow gineering arethe research well established in community andpartially topics like software maintenance, software understandingorreverse en- a designismajorobstaclefor productivity. Insoftware engineering, when documenting anewdesign,the detailsof alackinunderstanding team asanewmember,ing alarge whenextending alegacydesign, or Understanding ahardwaretough process. designcanbea When enter Cunxi Yu, EPFL, CH Clifford Wolf, Symbiotic EDA, AT Georg Weissenbacher, Vienna University of Technology, AT Pramod Subramanyan, IndianInstituteof Technology Kanpur, IN Jannis Germany Stoppe,DFKIGmbH, DE Heinz Riener, EPFL, CH GermanAerospace Center,Jan Malburg, DE Ian Harris, University ofCaliforna Irvine, US Tara Ghasempouri, Tallinn University of Technology, EE Görschwin Fey, Technische Universität Hamburg, DE Azadeh Davoodi, University of Wisconsin-Madison, US Maciej Ciesielski,University ofMassachusetts, US Programme Committee Members: Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE Christian Krieg, Vienna University of Technology, AT Organisers andModerators: Room 90830 TOPICS TU Wien,Krieg, AT Christian – 1730 123 - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - - www.date-conference.com ing techniques, Hardware Trojan detection algorithms and side-channel Trojan Hardware ing techniques, malicious analysis algorithms – all of which aim discover to algorithmically in led has to concern progress the latter The up. bottom the from behavior top-down techniques based on model checking and security verification progress I will some recent try In to review synthesis. this talk, syntax-guided in both top-down analysis. I will argue and bottom-up that both top-down and bottom-up benefittechniques can synergistically each other. in the Department- is an Assistant Professor of Com Subramanyan Pramod Kanpur. Technology, puter Science and Engineering at the Indian Institute of and subsequent Princeton University to his Ph.D., from He obtained his Ph.D. - re His Berkeley. California, of atscholar postdoctoral a University the was he meth- lie at the intersection of systems security and formal interests search on system-building techniques focused is thatcan research His current ods. has won several research Pramod's of security. guarantees verifiable provide - and Commu at Computer the ACM Award including the Bestawards Paper Dissertation Outstanding Ph.D. SIGDA ACM the Security conference, nication at Award the Best Student Paper Award, Design Automation in Electronic Trust. Security and on Hardware-Oriented IEEE Symposium Complete Specification Mining Mining Specification Complete Lunch Break Views Engineering for Security: Reverse talk: Invited the Bottom. and From the Top IN Kaipur, Technology Indian Institute of Subramanyan, Pramod Speaker: seen much hand-wringing about posed security concerns have years Recent designs. Seemingly at the other end of the spectrumby malicious hardware The that design flaws lead to security breaches. inadvertent hardware are engineer of algorithmic reverse has led to development concern former Coffee Break 2 block presentation Paper Based on Source- Code Verification Binary Deductive Specifications ACSL Code-Level for Conflicts in Assertions HDL Descriptions Extracting Paper presentation block 1 block presentation Paper Circuits Design of QCA Gate-Level Towards Invited talk: Addressing Integrated Circuit Integrity Integrity Circuit Integrated Addressing talk: Invited Learning and Machine Analysis Using Statistical Techniques US Princeton University, Burcin Cakir, Speaker: Electrical Engineering Depart from degree her B.S. received Cakir Burcin ment of Bilkent University, and her Ph.D. degree from Princeton Univer Princeton from degree Ph.D. and her University, mentBilkent of models thatrepresent can formulating is motivation research Her sity. bases/frameworks mathematical and express systems accurately real algorithms and further in developing She had experience analysis. for of She is a recipient systems. hardware analyses secure to help design Her Princeton University. from award Upton Fellowship Robbins Francis at DATE Award Best Paper detection received Trojan work on Hardware journals on various as a referee (2015). She also has served Conference Besides her work and seminar talks. workshop and gave and conferences with two in- in industry research she also had experience at Princeton, Labs. and Cambridge (MSR) in Redmond Research ternships at Microsoft 0930 – 1000 124 1200 – 1300 1300 – 1400 1100 1130 1030 – 1200 1030 1000 – 1030 0930 0845 – 0930 FRIDAY, 29 MARCH 2019 FRIDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1715 1700 1630 1600 1500 –1600 1430 –1500 1400 1400 –1430 FRIDAY, 2019 MARCH 29 1600 –1730 development ofanewopensource FPGA place-and-routetool, nextpnr. FPGAs. Aswelldeveloping Project Trellis, hehasbeeninvolvedthe in bitstream documentation UltraPlusthe neweriCE40 project, to include world of open source FPGAs by Icestorm,extending Project the iCE40 mation ImperialCollege at Engineeringstudent London. Heenteredthe David Shah to FPGAsapplicable from othervendors. development andverification discussedequally everything -withalmost bitstreamthat documentationthe possibilities scribe someof bringfor tion,the interestingthe way, detailsomeof along lessonslearnt andde- this opendocumenta- the processesto build talk willdescribe used This this. to paritywith theFPGAbitstream tobringing ecosystem documentation step isafirst the softwareaccepted in development community; anddeveloping open Open source compilers suchasGCC andLLVM are nowwidelyusedand the constraintsmentation possiblewithin not the vendor of FPGAtools. and nextpnr for place-and-route,to low-levelthe door andopens experi- source Verilogto bitstream using flow theseparts for Yosys for synthesis their internals. the development open to ofanend-to-end This hasled documentation forthem;to openupabetterunderstanding of inorder Project Trellis hascreated opensource bitstream, architecturetiming and The Latticeisafamily ECP5 of mid-rangeto 85klogiccells) (up FPGAs. Speaker: David Shah,Symbiotic EDA, GB documentation for theLattice ECP5FPGAs Invited talk: ProjectTrellis: openbitstream Coffee Break Language Scenario Description Generating aUML SequenceDiagram fromaNatural for theHWVerification Process The Verification Cockpit -HarnessingData Analytics Processors Using AIforthePerformance Verification ofHigh-End Floorplans Design Mapper: Dataflow Analysis forBetter Verification Platform ofanEffectiveEngineering Automatic Assertion-based Paper presentation block 4 Paper presentation block 3 is a engineer at Symbioticis aengineerat EDA andaElectronic andInfor 125 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 3 and Gerd Ascheid and Gerd 1 www.date-conference.com , Andre Guntoro Andre , 2 Esslingen University of Applied Sciences, DE, DE, of Applied Sciences, University Esslingen 2 , Matthias Roth Roth Matthias , 1 1700 – Robert Bosch GmbH, DE, DE, Robert Bosch GmbH, DE Aachen University, RWTH AIM AIM THE WORKSHOP: OF KEYNOTES: Reliability Evaluation of Mixed-Precision Architectures of Mixed-Precision Evaluation Reliability Paolo Rech, Fernando Fernandes dos Santos and Daniel Oliveira, UFRGS, BR UFRGS, and Daniel Oliveira, dos Santos Fernandes Fernando Rech, Paolo Functions of Transcendental Computing Approximate Applied to Artificial Networks Neural RWTH IDS, Tobias Gemmeke, Hoffler and Cecilia Arthur Ruder, Xin Fan, DE Aachen Univ, Christoph Schorn 3 Word-Length Noise Budgeting in Multiple-Kernel Optimization FR of Rennes 1, University and Olivier Sentieys, Yuki Tomofumi Ha, Van-Phu Coffee Break 1 Session Technical Network of Deep Neural Resilience-based Mapping Units Computing to Approximate Operations Opening Session Neuro- with Re-Engineering Computing 1: Keynote and Systems. Circuits, Devices, Inspired Learning: Approximations Engineering of Purdue School of Electrical and Computer Roy, Kaushik US University, Room 5 0830 Room FR INL, Alberto Bosio, Chair: Programme Co-Chairs: General IT II, of Naples Federico University Mario Barbareschi, DE of Stuttgart, University Claus Braun, - and the verifi paradigm between AxC of connections The investigation the of testtwo points from of digital circuits and the reliability cation, view: impacts paradigm the design and computing how the approximate circuits; of integrated flow manufacturing exploited reliability disciplines can be testing and how the verification, paradigms. computing in the approximate with Neuro-Inspired Computing Re-Engineering title: Roy, Kaushik Prof. and Approximations Systems. Circuits, Devices, Learning: Energy- for Computing Transprecision title: Cristiano Malossi, Dr. Efficiency 1 AxC: 4th Workshop on Approximate on Approximate Workshop 4th AxC: Computing • • • •

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1500 –1700 1300 –1330 1200 –1300 FRIDAY, 2019 MARCH 29 1430 –1500 1330 –1430

Leveugle 1 1 1 Alessandro Savino Quest forOptimization Metrics Targeting Approximation throughData Lifetime: A Technical Session 2 Coffee Break ResearchCristiano Malossi,IBM ofZurich, CH Efficiency Keynote 2: Transprecision Computing forEnergy- Alessandro Cilardo, Università degliStudidiNapoliFederico II, IT Stefano Marrone andCarlo Sansone, University ofNaplesFederico II, IT Approximate Computing forSizingHiddenLayer inCNN E. Sanchez Lifetime Exploiting Approximate Computing System toIncrease Technology, CZ Lukas Sekanina, Zdenek Vasicek and Vojtech Mrazek, BrnoUniversity of Approximate Circuits Towards OneMillion Component Library of TIMA, FR Ali Skaf, MonaEzzadeen, MounirBenabdenbiandLaurent Fesquet, Arithmetic Adjustable Precision Computing UsingRedundant Giuseppe Ascia NetworksEfficient onChip An Approximate Communication Technique forEnergy and Marco Platzner, Paderborn University, DE Linus Witschen, HassanGhasemzadeh Mohammadi, Matthias Artmann building fromgroundup Invited Talk: Approximate Computing inHPC: Lunch Break Maurizio Palesi Colombia, CO Approximate Circuits Jump Search: AFast Technique fortheSynthesis of Politecnico di Torino, IT, Politecnico di Torino, IT, University ofCatania, IT, 2 1 , P. Bernardi 1 1 andDavide Patti , VincenzoCatania 1 , MichelePortolan 1 and W. J. Perez-Holguin 2 2 University Grenoble Alpes, TIMA, FR Universidad Pedagógica y Tecnológica de 2 Indian Instituteof Technology Guwahati, IN 1 1 , JohnJose 2 , Stefano DiCarlo 2 , Salvatore Monteleone 2 1 andRegis 127 1 ,

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - www.date-conference.com 1615 – MOTIVATION AND OBJECTIVES MOTIVATION HIGHLIGHTS Room 6 0845 Room Organisers: DE / FZI, Tuebingen of Bringmann, University Oliver DE Technologies, Infineon Ecker, Wolfgang DE University, Paderborn Müller, Wolfgang DE München, Universität Technische Daniel Müller-Gritschneder, (IoT) industrial as is emerging the backbone for The Internet-of-things impact The tremendous is IoT of applications industrial to automation. in dramatically to grow and developments IoT research for reason a key importanceimpact and economic nextthe decade. for At of edge the the memory footprints software small extremely with devices ultra-thin IoT, of small amounts need to be cheap and capable to run with extremely IoT software At the same energy long lifetime. supporttime, a very over smartmust- capabili provide computing functions including real-time These mechanisms. update and remote safety, security, connectivity, ties, based on development on IoT software put a high pressure constraints the specific properties of IoT devices. The ESIIT 2019 joint academic/industry on software will focus workshop limited the very addressing of IoT devices and maintenance development of a of IoT edge nodes in and power dissipation context the resources issues like This covers IoT network. in an operational cycle long life very faultrecov upgrades, security, safety, configurability, synthesis, software ery, maintenance as well as constraints and opportunities and newly from as well as constraints maintenance ery, intends to provide The workshop platforms. IoT hardware emerging on new directions and communication exchange for an open platform plan especially give to We and industry. to academia and requirements to present experts a platform and leading research industrial speakers indus- and future in and mosttoday's results recent the requirements The main and maintenance. development software trial IoT-constrained are: objectives and needs industrial experts and future current to invite to present requirements re- different and ideas from technologies and discuss novel to present and domains areas search develop IoT platform needs for and future align and trends to explore and industry. of academia the perspective from ment and maintenance academic presentation with poster talks a range ESIIT 2019 will feature industrial presentations. invited as well as three AG) Technologies (Infineon Velten Michael Invited talk from Use Embedded Controller from Extensions IP-XACT for Proposals Title: Cases (Robert Bosch GmbH) Aljoscha Kirchner Invited talk from Smart for Sen- Development of Embedded Software Automation Title: sor ASICs IESE (Fraunhofer Thomas Kuhn Invited talk from the Industrial Internet of Middle for An Open Source 4.0: BaSys Title: Things 2nd International Workshop on Embedded on Embedded Workshop 2nd International IoT (ESIIT 2019) for the Industrial Software • • • • • • 128 W06 FRIDAY, 29 MARCH 2019 FRIDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI 1100 1000 –1030 1115 www.date-conference.com 1300 1300 –1430 1130 1030 1030 –1130 0900 0900 –1000 0845 –0900 FRIDAY, 2019 MARCH 29 1045 0930 1315 1200 –1300 1130 –1200

1 Harumi Watanabe Reconfiguration forIndustry IoT with Context-Oriented Programming andHardware An Experimental Platform forCooperative Work Session II: Applications fortheIOT Aljoscha Kirchner Smart SensorASICs Automation ofEmbedded Software Development for Michael Velten and Wolfgang Ecker, Infineon Technologies, DE Controller UseCases Proposals forIP-XACT Extensions fromEmbedded Gereon Führ Mappings onHeterogeneous MPSoCs forMultiA Heuristic Objective Software Application Rafael Stahl, Daniel Müller-Gritschneder Schlichtmann, andUlf TUM, DE Software Interface forIoTNodes Firmware-Driven Optimization ofthe Hardware/ Optimizations &Analysis fortheIoT Session IV: Safety, Security, Performance andPower Frank Schnicke, Markus Dammand Thomas Kuhn, Fraunhofer IESE, DE Industrial Internet ofThings BaSys 4.0: AnOpen-SourceMiddleware forthe Session Invited III: Industrial Presentations nomiya University, JP Kenta Arai, Takeshi Ohkawa, Kanemitsu Ootsuand Takashi Yokota, Utsu- Image ProcessingforIndustrial IoTDevices Component-based FPGADevelopment ofIntelligent Panagiotis Kalodimas An Open-Source, IoT-Tailored Face Detection Software Johann-Peter Wolff Human-Robot Interaction SensorBasedRobotGestureDetectionInertial forSafe 4 1 Session I: Invited Industrial Session Opening 1 1 1 Awaid-Ud-Din Shaheen Nobuhiko Ogura Lunch Break&PosterDiscussions Coffee Break&PosterDiscussions Grüttner Technical University ofCrete, GR; Robert BoschGmbH,Robert DE; University ofRostock, DE; Utsunomiya University, JP Tokai University, JP; RWTH Aachen, DE; 2 1 , AhmedHallawa 3 1 and Takeshi Ohkawa , Jan-HendrikOetjens 1 1 , Mikiko Sato 2 , ChristianHaubelt 2 Silexica GmbH, DE Kyushu University, JP; 1 , Antonis Nikitakis 2 2 Universität Tübingen,DE 2 OFFIS - Institut fürInformatik,OFFIS -Institut DE 1 , Rainer Leupers 1 ,Ikuta Tanigawa 2 Aristotle University of Thessaloniki, GR 4 1 1 , Rolf Schmedes andOliver Bringmann 1 andIoannisPapaefstathiou 3 Tokyo CityUniversity, JP; 1 , Gerd Ascheid 2 , Mariya Kawamura 2 andKim 1 and 2 129 1 2 ,

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1 , 1 2 , Christoph Scheytt , 1 , Sebastian Reiter , 1 www.date-conference.com University of Tübingen, DE Tübingen, of University 2 and Wolfgang Rosenstiel Wolfgang and 1 , Wolfgang Müller Wolfgang , 1 , Arthur Kühlwein , 1 Kasper & Oswald GmbH, DE GmbH, & Oswald Kasper 2 2 , Oliver Bringmann Oliver , 1 , Frederik Haxel Frederik , 1 , Bastian Koppelmann , 1 FZI Forschungszentrum Informatik, DE; DE; Informatik, Forschungszentrum FZI Heinz Nixdorf Institute, DE; DE; Heinz Nixdorf Institute, Coffee Break & Poster Discussions 1 Alexander Viehl Alexander and Benedikt Driessen 1 Plenary Discussions & Closing Discussions Plenary Towards Stateflow Model-Aware Debugging Using Debugging Model-Aware Stateflow Towards LLDB with Model-to-Source Tags OFFIS - Insti- Philipp Ittershagen and Kim Grüttner, Kebianyor, Bewoayia DE tut für Informatik, of Internet-of-Things- the Challenges Tackling Using Models Development AT Technology, Institute of Austrian Krenn, Willibald Rupert Schlick and A Syntax Oriented Code Generation Approach for SoC Approach for Code Generation Oriented A Syntax Design Automation Tech- Infineon Ecker, Wolfgang Neumeier and Andreas Werner, Michael DE nologies, RISC-V Design of Future-Proof Ecosystem for Agile Based IoT-Devices Hielscher Leon Peer Adelt Peer for IoT Software Frameworks Model Based V: Session Development Towards Distributed Runtime Monitoring with C++ with Monitoring Runtime Distributed Towards Contracts DE OFFIS - Institut für Informatik, Schmedes and Philipp Ittershagen, Rolf IoT Secure Applications for Tool Chain Security Austrian Shaaban, Magdy Christoph Schmittner and Abdelkader AT Technology, Institute of of Security Memory Analysis for Dynamic QEMU Software Sensitive Source-level Power Simulation of IoT Firmware for of IoT Firmware Simulation Power Source-level Energy Evaluation DE Tübingen, Universität Bringmann, and Oliver Michael Kuhn

1430 – 1500 1600 – 1615 1545 1530 1515 1400 1415 1345 130 1500 – 1600 1500 1330 FRIDAY, 29 MARCH 2019 FRIDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1030 –1100 1030 0830 –0900 W07 FRIDAY, 2019 MARCH 29 1100 –1130 1000 0930 –1000 0900 –0930 0830 Workshop onMachineLearningforCAD Siddharth Garg,Siddharth New York University, US Reliable ML Hardware ML4TPU: and MachineLearningfor Energy Efficient Rolf Drechsler, University ofBremen, DE Designs UsingMachineLearningTechniques Resilience Evaluation forApproximating SystemC Design forReliability usingMachineLearning Coffee Break Rajesh Gupta, UCSanDiego, US Machine LearningTechniques forVLSICAD Lilia Zaourar, CEA-LIST, FR Machine LearningforDesignSpaceExploration ofCPS Schlichtmann,Ulf TU Munich, DE Space Exploration ofApplication-specific NoCs Design Machine LearningApproachesforEfficient Design SpaceExploration usingMachineLearning0 Lilia Zaourar, CEA-LIST, FR Kai-Chiang Wu, National Chiao Tung University, TW Wehn,Norbert TU Kaiserslautern, DE Dimitrios Soudris, University ofAthens, GR Schlichtmann, Ulf TU Munich, DE Rajesh Gupta,UCSanDiego, US Georges Gielen,KU Leuven, BE New Garg, YorkSiddharth University, US Paul Franzon, Carolina North State University, US Rolf Drechsler, University ofBremen, DE Krishnendu Chakrabarty, Duke University,US Automation ofElectronic Systems (TODAES). ACMshop willbepublishedinaspecialissueat Transactions onDesign techniques. techniques aswellrun-time time The resultsthe work of the special needs for ML for CAD where CAD is broadly defined asdesign the workshopto discuss,purpose of is defineandprovide a roadmap for traditionalto MLapplications suchasimageclassification. Assuch, the requirethat challenges parallel advances inMLandCAD ascompared of MLfor avariety ofapplications. However, designprocesses present half-dozenoverthe past years have revolutionizedthe effectiveness CAD andelectronic system design. Advances inmachine learning (ML) This workshop focuses on machine learning methods for of all aspects Marilyn Wolf, Georgia Tech, US Jörg Henkel, Karlsruher für Institut Technologie (KIT), DE Hussam Amrouch, Karlsruhe Instituteof Technology (KIT), DE Organisers: Room 70830 Invited Speakers andPanelists: – 1730 131 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com Workshop Wrap-up Workshop plans (buy-your-own-meal) Joint dinner with discussion of future Buca Mario Ristorante Location: Huiyuan Song, PKU Advanced Institute of Information Technology, CN Technology, Institute of Information Advanced PKU Huiyuan Song, Go From Here? Where Do We Panel: Panelists: US University, State North Carolina Franzon, Paul US Rajesh Gupta, UC San Diego, FR CEA-LIST, Lilia Zaourar, DE Kaiserslautern, TU Norbert Wehn, US Tech, Georgia Marilyn Wolf, Moderator: Modeling of DRAM Behavior with with Modeling of DRAM Behavior Networks Neural Recurrent DE Kaiserslautern, TU Wehn, Norbert Machine Learning in Logic Synthesis Poster: CZ Technology, Brno Institute of Sekanina, Lukas using Graph Algorithm FPGA Routing Fast Poster: Network Neural Coffee Break Modeling Machine Learning for Circuit analog techniques in design and test of AI learning circuits integrated BE Leuven, KU Gielen, Georges Predictive Analytics for Run-Time Anomaly Detection Detection for Run-Time Anomaly Analytics Predictive Core Routers in Complex Prediction and Failure US University, Duke Krishnendu Chakrabarty, onto Implementation for Application A Methodology 3-D FPGAs GR of Athens, University Dimitrios Soudris, Lunch Break Learning and Run-Time Machine Design-Time for SoCs Techniques Robots with Circuits Designing Your US University, State North Carolina Franzon, Paul Learning-based methodologies for assessing chip chip for assessing methodologies Learning-based of aging and reliability in terms health TW University, Tung Chiao National Kai-Chiang, 1630 1730 1600 – 1615 1615 – 1630 1530 – 1600 1400 – 1430 1430 1330 – 1400 1200 132 1500 1500 – 1530 1300 1300 – 1330 1130 – 1200 FRIDAY, 29 MARCH 2019 FRIDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com W08 FRIDAY, 2019 MARCH 29 Quantum Computing Grand Challenges andResearchTools for Room 100830 computer architecture Xin-Chuan (Ryan) Wu (UChicago)third year – inquantum PhDstudent puter architecture Pranav Gokhale(UChicago) –second year inquantum PhDstudent com- prototype machines. to IBM's quantum computingtools andcloudaccess simulationtools for quantum computing andresearcher Qiskit for IBM's Ali Javadi-Abhari Research) (IBM – co-authorthe Scaffold of compiler and Scaffold compiler andsimulation tools for quantum computing. Diana Franklin (UChicago) –Education leadofEPiQC. Co-authorthe of quantum error correction. quantumcompiler machines, forto IBM cloud-access in andexpert ory,the Quantum Assembly(QASM) authorof the Qiskit languageand Research)Andrew Cross (IBM –Researcher inquantum computingthe- ultracold temperatures. quantum cold at computersthe studyofmolecularproperties and and technologies. Hiscurrent research areas arethe development ofrobust tems forthe natural both understanding world and developing new Ken Brown (Duke) – Leading researcherthe control in of quantum sys- computing for computer architects. tools fortion quantum computing and asynthesis lecture onquantum Fred Chong(UChicago) –co-authorthe Scaffold of compiler andsimula- IBM, allorganized notebooks, withinJupyter the afternoon. throughout and work with code examples running on real quantum hardware at This workshop will be highly interactive. Participantstools will install our tools andinterfaces. Language/Compiler Qiskit the IBM and tools willbeacombinationThese the Scaffold of Quantum Programming to runningexperiments quantum machines. guage oncloud-accessIBM ofsoftware set end-to-end tools from ahigh-level programming lan- Finally, wewillprovide anoverview andhands-onexperience withan algorithms ofnear-term significance. to delvethese challenges. to begin into We willalsointroduce quantum We willintroducethe basicconcepts andresourcesto enableresearchers require greater depth. proached withminimalquantum computing background andsomewill optimizations, andmanythese challengescanbeap more. Someof scheduling computations, reducing control complexity, machine-specific optimization, managingparallelism andcommunication, mappingand verification, definingandperforating abstraction boundaries, cross-layer gap, includingprogramming languagedesign, software andhardware This workshopthe grand willoutline researchthis challengesinclosing to hirethis area). in companiestrying this gap(thereto workonclosing areentists over 60publicandprivate this gap.close computerthe necessary sci- There of isaurgent shortage areto increasethe efficiencyofalgorithmsandmachines needed gorithms andnear-term machines.Software andarchitectures are what Yet asignificant resource gap remains betweenpractical quantum al- such asquantum chemistry, optimization, andquantum simulation. is computableof what and demonstrate practical applications in areas These machineshaveto fundamentallythe potential changeourconcept corner, machinesare andeven perhapsonlyafew 1000-qubit years away. bit) machineshave aroundthe machinesare beenbuilt, just 100-qubit Quantum computingpoint, aninflection isat (quantum where 72-qubit Organiser: Ali Javadi, IBM, US TEACHING ASSISTANTSTEACHING ORGANISERS WORKSHOP DETAILS: – 1730 133 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com Workshop Wrap-up Workshop Lunch Break (Hands-on for Compilation Tools Basic Algorithms, Demo) Coffee Break Chemistry Quantum for Algorithms Coffee Break Computing Basics of Quantum Intro to Grand Challenges in Quantum Computing in Quantum Challenges to Grand Intro Ken Brown (Duke) Brown Ken Diana Franklin (UChicago) Diana Franklin (IBM) Ali Javadi-Abhari Fred Chong (UChicago) Fred 134 1730 1300 1430 1500 1200 1000 1030 0830 FRIDAY, 29 MARCH 2019 FRIDAY,

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com W09 FRIDAY, 2019 MARCH 29 1000 –1015 0900 –1000 0840 –0900 0830 –0840 Quo vadis, LogicSynthesis? Coffee Break Anna Bernasconi, Università diPisa, IT relations Expressing flexibility in logic synthesis byBoolean Jordi Cortadella, Universitat Politecnica deCatalunya, ES Extracting functions fromBoolean relations Algorithmic foundations oflogic synthesis 1 -Part Tiziano Villa, d’Informatica, Dipartimento Università di Verona, IT retrospective onlogic synthesis Thirty-five years aftertheEspressobook: a Tiziano Villa, d’Informatica, Dipartimento Università di Verona, IT Luca Carloni, Columbia University, USand Introduction the field. tions of academia and industry,the state-of-art on and strategicto report direc - ofspeakerstogether aninclusivethis workshop brings list from both synthesis, machinelearningfor data analysis, etc.). To achievethis goal, in other domains (biological technology system design and an enabling the perspectives oflogicsynthesis, indigital bothasacoretechnology breakthroughs andindustrialsuccesses,time for is of anassessment it newborn Electronic DesignAutomation Industry. After many research the industrialdesignchainsofferedthe backboneof the became by tools likeof modernlogicdesign Espresso, MIS, SISand VIS,then which academic andindustrialresearch laboratories wavethe first triggered of modern logic synthesis. time by leading The work done aroundthat A. Sangiovanni-Vincentelli layer providedthe first the of foundations In 1984,the bookonEspresso byR.Brayton, G.Hachtel, C.McMullenand Tiziano Villa, d’Informatica, Dipartimento Università di Verona, IT Luca Carloni, Columbia University, US Gabriella Trucco, Università degliStudidiMilano, IT Andres Takach, Calypto DesignSystems, US Mathias Soeken, Integrated System Laboratory –EPFL, CH Tsutomu Sasao, MeijiUniversity, JP Marc Riedel,University ofMinnesota, US Sherief Reda, Brown University, US Weikang Qian,ShanghaiJiao Tong University, CN National Taiwan Jie-Hong Jiang, University, TW Masahiro Fujita, University of Tokyo, JP Jordi Cortadella, Universitat Politecnica deCatalunya, ES Valentina Ciriani,Università degliStudidiMilano, IT Anna Bernasconi, Università diPisa, IT Luca Amaru,Synopsys, US Speakers: Luca Carloni, Columbia University, US Tiziano Villa, d’Informatica, Dipartimento Università di Verona, IT Organisers: Room 80830 – 1730 135

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com On the minimization of variables to represent sparse to represent of variables On the minimization diagrams decision input multi-valued to DNA computing applied logic Stochastic How high-level synthesis enables design for reusability design for reusability enables synthesis high-level How accelerators of hardware Logic synthesis and biological models and biological Logic synthesis to synthesis of logic application biology: Synthetic models biological IT degli Studi di Milano, Università Trucco, Gabriella US of Minnesota, University Riedel, Marc Automated synthesis of distributed/parallel of distributed/parallel synthesis Automated reasoning and inductive through templates computing JP Tokyo, of University Fujita, Masahiro JP Meiji University, Sasao, Tsutomu Luca Carloni, Columbia University, US University, Columbia Luca Carloni, Coffee Break learning and machine Logic synthesis Weikang Qian, Shanghai Jiao Tong University, CN University, Tong Shanghai Jiao Qian, Weikang synthesis logic to approximate approaches Systematic US University, Brown Sherief Reda, synthesis High-level trends and future status synthesis: High-level US Design Systems, Calypto Takach, Andres Luca Amaru, Synopsys, US Synopsys, Luca Amaru, Lunch Break synthesis Approximate for area and delay synthesis logic Approximate optimization SAT in logic synthesis in logic SAT CH – EPFL, Laboratory System Integrated Soeken, Mathias technologies for emerging Synthesis in emerging technologies gates XOR IT degli Studi di Milano, Università Ciriani, Valentina Logic Synthesis Majority Algorithmic foundations of logic synthesis – Part 2 synthesis of logic foundations Algorithmic applications synthesis in logic interpolation Craig TW University, Taiwan National Jie-Hong Jiang, 1630 – 1730 1515 – 1530 1415 – 1515 1215 – 1315 1115 – 1215

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com W10 FRIDAY, 2019 MARCH 29 • • • • • Automation forFPGAs-OSDA Workshop onOpen-SourceDesign may bedifferent toopensoftware. commercialisetechnologies surrounding open-source hardware, which to license,Discussions andcasestudiesonhow acquire funding, and protection,time-to-market, datacenter/cloud infrastructure, etc. ofsafety,how open-source aspects canaffect security, verification, IP toolchain,the rent weaknessesin and/or perspectives from on industry Directions onwherethe open-source FPGA movement shouldgo, cur methods, andothers. main specificlanguages(DSL), highlevel synthesis (HLS), asynchronous hardware derived from descriptionlanguages(e.g. Python, Scala), do- Design methodologiesprovided asopen-source –suchasalternative lers, debuginfrastructure, etc. to and reducethe need “re-inventthe wheel”, andDDRcontrol PCIe - e.g. for ecosystemOpen-source FPGAs IP the IP –contributions enrich that synthesis, simulation, placeandroute, etc. toolflows lenges andsurveysthe target real silicon on required to parts: developments,Open-sourcethe latest FPGAtools – breakthroughs, chal- sions. manuscripts aswellany code for necessary reproducing itsconclu - mandate “open access” for publiclyfundedresearchto bothpublished the recent efforts theEuropean across to Union due (and beyond) that to entryriers andrisks for industry. poignant These aimsare particularly research anddevelopment, improving EDA quality,the bar andlowering forts for open design automation,to enabling unfettered with a view to explore, actors hobbyist disseminate, andnetworkover ongoingef together industrial,This one-day workshopto bring aims academic, and to drive reconfigurable silicon towards trend. thesame and GPU silicon, comesto CPU cess when it there and are already efforts cations and EDA innovations. Open-source is a proven and prevalent suc- the realisationcan hamper ofnovel anddeployment FPGA-based appli- – throughwhich them – proprietarytools and IP closed-sourceaccess devicesand lowcost contraststhe narrow with ways in whichonecan the handsofhobbyists.Howeverthe wideavailabilityas in these high of FPGAs are increasingly themselves finding in hugedata-centers as well website: osda.gitlab.io Davide Rossi, University ofBologna, IT Steffen Reith, RheinMainUniversity ofAppliedSciences, DE Nelson,Brigham Brent Young University, US Mieszko Lis, University ofBritishColumbia, CA Dirk Koch, University ofManchester, GB Steve Hoover, Redwood EDA, US Hipolito Guzman-Miranda, University ofSevilla, ES ImperialCollege London,Shane Fleming, GB University,Xin Fang, Northeastern US Andrea Borga,oliscience, NL Programme Committee Members: Clifford Wolf, Symbiotic EDA, AT Christian Krieg, Vienna University of Technology, AT University ofBritishColumbia,Eddie Hung, CA Organisers: Room 40845 TOPICS OF INTEREST AT OSDA INCLUDE, BUT ARE NOT LIMITED TO: – 1730 137 - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 ------www.date-conference.com PyGears: A Functional Approach to Hardware Design Approach to Hardware A Functional PyGears: Univer and Damjan Rakanović, Erdeljan Andrea Vukobratović, Bogdan RS Sad, sity of Novi and its Synthesis LegUp High-Level Commercialization CA Toronto, of Jason Anderson, University cir of a hardware (HLS) synthesis is synthesis the automated High-level Session 1: Full Papers 1: Session based on and library an open-source SoC builder LiteX: Migen Python DSL Lann Jean-Christophe Le Bourdeauducq, Sébastien Kermarrec, Florent FR Enjoy-Digital, and Hannah Badier, In An Open Source Context Verification On Hardware UK of Bristol, University Ben Marshall, nextpnr – a portable FPGA place and route tool FPGA place and route nextpnr – a portable AT SymbioticEDA, Hung, Shah and Eddie David for Open Source Framework a Complete OpenFPGA: FPGA Prototyping Tang Xifan Giacomin, Edouard Alacchi, Aurélien Baudouin Chauviere, US of Utah, University Gaillardon, and Pierre-Emmanuel Coffee Break & Demos citing applications of open-source electronics. In this talk, I will describe In electronics. of open-source this talk, citing applications (PULP) plat of Parallel-Ultra-Low-Power the open-source the evolution open next as well as opportunities generation and challenges for form systems. computing source of University the the PhD from received Rossi, Davide biography: Speaker in been a post in 2012. He has the Depart doc researcher Italy, Bologna, “Guglielmo Engineering Information and Electronic mentElectrical, of he currently where at of Bologna since 2015, the University Marconi” on focus interests position. His research holds an assistant professor inarchitectures energy efficient of heterogeneous the domain digital This includes systems on a chip. multi and many-core and reconfigurable support runtime and to strategies, implementation design architectures, high both of issues reliability and energy efficiency, performance, address tar platforms computing and ultra-low-power end embedded platforms than 80 he has published more geting the IoT domain. In these fields, and journals. conferences reviewed peer- paper in international Università di Bologna, IT di Bologna, Università Rossi, Davide objects envisions trillions of connected load- “internet of everything” The of local sig- amounts massive sensors requiring ed with high- bandwidth silicon While and classification. extraction pattern fusion, nal processing, due to decreasing the twilight law, of access cost is naturally the Moore's innovative for barrier a huge IPsrepresents still access the to hardware In this context, of IoT. the market approaching start-ups and companies a IPs represents growththe recent of high-quality hardware open source ex of number a for way the paving surpass to barrier, this way promising Welcome PULP Multi- RISC-V Based – An Open-Source Keynote: for In-Sensor Analytics Core Platform 1130 – 1200

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 1245 –1330 FRIDAY, 2019 MARCH 29 1330 –1400 1200 –1245 independent independent librarytool flow, and VHDL newFPGA hardware canalso take advantage of already available hardware. By also having a vendor platforms (UniBoard, UniBoard2, Perentie), new scienceapplications can both vendor andapplication independent. With generic, universal FPGA andavailabilitycost ofFPGA devices, ASTRON is that usesanapproach naturally have their hearts. FPGAs at To requirements, balanceproject streamingThe highperformance that datato do systemswebuild ASTRONsto make missionis discoveries inradio astronomy happen. Daniel van derSchuur, ASTRON, NL to OpenSource Reuse:VHDL fromVendor Independence Clifford Wolf, Symbiotic EDA, AT Hipolito Guzman,University ofSevilla, ES Drepper,Ulrich Red Hat, DE Andrea Borga,oliscience, NL to mandatethe EU the momentum within “open access” research. ware,their views onwhether openandclosed-source canco-exist, and open-source licenses(copyleft versus permissive)the context in ofhard- be panelist's experiencesthis, with doing the varioustheir opinions on you are building is ostensibly given away for free. Topics explored will business orresearch that groupthings aroundthe open-source –when The Paneliststo builda(stable!) ispossible willbediscussingwhetherit undertake researchonopen-sourceEDA/IP? Panel discussion: How doesonecommercialise/ Lunch Break and ChiefScientific Advisorof LegUp Computing Inc. FPGA 2017, andisGeneral Chairfor ACM FPGA 2018.HeisCo-Founder patents, andwas Program Co-Chair for FPL2016, Program Chairfor ACM 90 peer-reviewed research publications, 4bookchapters, holds29U.S. tools,of architectures, andcircuits for FPGAs. Hehasco-authored over the universityand joined in2008.Hisresearch interests are allaspects routing, and synthesis. He Xilinxbecame a Principal Engineer at in 2007 Inc., SanJose, CA, USA, in1997, where hewas involved inplacement, Endowed Chair.the FPGA Hejoined Implementation Tools Group, Xilinx, Computer Engineering, University of Toronto,the Jeffrey andholds Skoll Professor and Associate Chair, Research, and of Electrical the Dept. with Speaker Biography: JasonAnderson(http://janders.eecg.toronto.edu/) is sizedto anytargeted circuits FPGA. canbe key value proposition of LegUp is FPGA-vendor HLS agnosticism – synthe- founded in2015andreceived seedfundingfrom Intel Capital in2018.A LegUp Computing(https://www.legupcomputing.com/), Inc. whichwas isbeingcommercializedtechnology LegUp company, inastart-up HLS has beendownloadedbyover 5000groups from aroundtheworld. the University of Toronto --apubliclyavailable that research HLS tool community. at Iwilldescribeworkunderwaythe LegUp project HLS in maythat the challengesforthe digitaldesign hinderitsupdate HLS in current researchtalk willhighlight HLS directions andexpose someof use of, will only become HLS more pronouncedthe coming in years. The the recent drivetowardsbehind FPGAthe needfor, andwhy HLS and efficiency. andenergy throughput talk, this In Iwill the trends overview tandem withstandardto raise processors workin that computational to realize use HLS FPGA-based acceleratorsto applications customized ware expertise. the road, down that The hopeis software developers can to software accessible FPGAtechnology engineershaving limitedhard- rays (FPGAs)to improve designerproductivity andultimately,to make forthe upswingasadesignmethodology field-programmable gate ar inrecent years.tremendoustechnology ison been buzzaround HLS HLS the sidelinesofmainstreaming decadeson RTL digitaldesign,there has from asoftwarecuit program the1980s, proposed in first andspend- Panelists:

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FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com Bitvis, NO Bitvis, GHDL: Present and Future Present GHDL: Espen Tallaksen, Espen Tallaksen, - is spent on verifica an FPGA half time for the development On average reductions and major Ittion. reduce this is possible time, significantly to cost. For no extra and with only minor adjustments can be accomplished from the design we all know thatan FPGA – all the way the architecture quality and both the FPGA – is critical for top architecture to the micro time.the development Itthat be obvious should really this also applies Verification VHDL Universal (the open source to the testbench. UVVM - the verifica this and will reduce to solve Methodology) developed was attion while time significantly the same the product time improving simple and powerful a very that architecture provides UVVM quality. allow designers to build their own testthan ever much faster harness compo- a mix of - using verification their own and open source before methodology to and library an architecture, also provides UVVM nents. efficiently. extremely components to be made VHDL verification allow the best allows pos- – UVVM the mostAnd maybe important feature for sible commands testbench and test using high level case overview overview, The great and synchronization. control interface both DUT resulted in an reuse has modifiability and extensibility, maintainability, of this methodology spread to fast – and according the extraordinary Tristan Gingold, CERN, CH CERN, Gingold, Tristan CH CERN, Gingold, Tristan Coffee Break & Posters FPGA verification – The fastest growing UVVM world-wide! methodology OpenFPGA: a Complete Open Source Framework for Open Source Framework a Complete OpenFPGA: FPGA Prototyping Tang Xifan Giacomin, Alacchi and Edouard Aurélien Baudouin Chauviere, US of Utah, University Gaillardon, and Pierre-Emmanuel We Licence) v2: of CERN OHLDraft (Open Hardware feedback need your Session 2 – Lightning Talks 2 – Lightning Session Through FPGA Domain-specific Compilers Enabling Open Source US Labs, Research Xilinx and Chris Lavin, Kaviani Alireza for HDL tracer requirements A minimalist Minitracer: designs of University Guzmán-Miranda, and Hipólito López-Melendo Carlos ES Seville, be adopted/developed with minimal firmware rework needed. This talk rework needed. firmware with minimal be adopted/developed chose we how and independence to vendor of aboutis advantages the structures library IP, vendor VHDL code, source covering implement this, and synthesis importanttools. Another and simulation aspect is the au- as it on a library is updated testing of the firmware regression tomated scripted All basis. daily ASTRONs by structured and possible made is this Fi- on OpenCores.org. released as open source which is to be tool flow, its going is to release ASTRON how and why this talk will cover nally, and the in doing so. technical challanges on OpenCores, library firmware a digital designer at der Schuur is the Daniel van biography: Speaker de- As ASTRON (ASTRON). Astronomy Radio for Netherlands Institute GPU, (FPGA, high performance hybrid complex builds and operates signs, Daniel is passion- new discoveries, systems to make fiber networks) CPU, about ate system design the reducing time streaming to science - from to VHDL implementation. 1430 – 1500

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com FRIDAY, 2019 MARCH 29

1715 –1730 1645 –1715 1545 –1645 Ang LiandDavid Wentzlaff, PrincetonUniversity, US Using CustomFPGAs PRGA: AnOpen-sourceFramework forBuildingand Closing remarks OpenSource Siliconsist inacademia, andforthe industry hobbyistsalike. a vendor-independent organizationto promotethe mission andas- with the IP-XACT library. Python In2015, healsoco-founded FOSSiFoundation, core package manager; SERV,the award-winning RISC-V and ipyxact, CPU tools andcollaborations.interest in the FuseSoc Notableworkinclude IP then workedin 2011andhassince onmany FOSSiprojects withaspecial volved withfree project andopen source siliconthe OpenRISC through working for Qamcom Research & Technology. Hebecameactively in- Speaker biography: Olof Kindgren is a senior digital design engineer core business the cores,FuseSoCtime on canhelpspendingless the andmoretime on tools supported. lint This presentation willgive anoverview ofwhere of FuseSoC-compatible cores and14different simulation, synthesis and vendors. Having been around for seven yearsthere are now hundreds ing code,tools andmove change projects betweenFPGAs from different developers,a uniformto HDL build system to reuse easy exist makingit files. thisbybringingamodernpackageFuseSoC managerand rectifies filespowered developerstool-specific project bycustommakeHDL use - softwaretool with a flick of a switch,their build developers can select pend on, developers HDL rely oncopying around source code. Where Wherethe software developers which libraries simply specify they de- the software in terparts world.Onesucharea iscore management. In many ways, developers HDL have been many yearstheir coun behind - Kindgren,Olof Qamcom Research & Technology, SE FuseSoC –Coresnever beensomuch fun Benedikt Tutzer, ChristianKrieg, Clifford Wolf and Axel Jantsch, TU Wien, AT Application Development Python Wraps Yosys forRapid Open-SourceEDA Piraes, GR Aitzan Sari, Vasileios Vlagkoulis andMihalisPsarakis, University of Evaluation An Open-sourceFramework forXilinxFPGAReliability Session 3–Fullpapers keynotes onvarious ofFPGAtechnical aspects development. number ofcompanies Hehasgiven world-wide. many presentations and the UVVMis verification platform iscurrently that beingusedbyahuge pragmatic efficiencyandqualityimprovement. this interest of One result years Espen hashadaspecialinterest for cultivation methodology and Norway, includinghisearlierfounded companytwenty Digitas.During from PhilipsSemiconductors inSwitzerland andvarious companies in 1987 andhas30years’ experience withFPGA andASICdevelopment and FPGA. Hegraduatedthe University from ofGlasgow(Scotland) in founder ofBitvis, designcentre anindependent for embeddedsoftware Speaker Biography: Espen Tallaksenthe managing director and is featuresthe latest plannedextensions. andfurther fromthe ESA project to understand,youthis is howsimple buildandcontrol. willalsoshow It the UVVMther extension of functionality. This presentation willshow backed by ESA (the Europeanthrough Space Agency) a contract for fur standardisedtestbench architecture, VHDL recommended by Doulos and two verificationyears. UVVMover thelast methodology thenew is 2018 Wilson Research UVVM report wasthe byfar fastest growing FPGA 141 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 See Page 59 " See Page See Page 53 " See Page See Page 46 " See Page 52 " See Page www.date-conference.com 1830 1645 1600 1300 – – – – Tuesday 1700 Tuesday Tuesday 1615 Tuesday This publisher’s session invites all attendees to discuss how and why all attendees to session invites This publisher’s - Edito Glaser, Charles work with Springer Nature. publish research their - in re collaboration his advice for will present Springer, for rial Director as well as the in this session, He will be available dissemination. search next book. of your to discuss the publication exhibition, entire Tuesday 1430 Tuesday 1130 Tuesday Alliance will present Design In their this session System the Electronic discuss a Siemens Business will Mentor, and results. newest initatives - designing and pro for of Machine Learning application for approaches for scenarios IngeniArs will analyze products. ducing microelectronics Machine executing for smartrealizing by using accelerators devices edge algorithms. and Deep Learning Learning of paramount is considered research interdisciplinary Collaborative and jumps in of breakthroughs importancethe achievement for today Raabe Andreas Dr. director program In this session, technical innovation. offered are funding instruments which types of collaborative introduces but also (DFG) in Germany, by the Deutsche Forschungsgemeinschaft - an introduc After cooperations. international funding opportunities for medium and longfor short, term funding instruments different tion into of in topics the scope initiatives example concrete research, collaborative by representatives summarized and will be shortly introduced of DATE during the conference also exhibiting with a majority of these initiatives week. Embedded Tutorial: Paving the Way for Very for Very the Way Paving Embedded Tutorial: of Superconductive Integration Large Scale Electronics Publisher’s Session: How to Publish Your to Publish Your How Session: Publisher’s Research Work DFG Collaborative Funding Instruments Collaborative DFG How Electronic Systems can benefit from can benefit Systems Electronic How and from ESD Alliance Machine Learning 142 4.8 3ps.8 3.8 2.8 - will be nine Exhibi there programme, In addition to conference the will feature These workshops as part of the exhibition. Workshops tion - tutori our industry, in on state-of-the-art the technical presentations and as a special research opportunities on funding for information als, in is located the The theatre students. sessions for highlight career close to and of the booths the the rooms hall, of the exhibition centre technical conference. as delegates open to conference are sessions Theatre The Exhibition well as visitors. to exhibition edacentrum GmbH, DE GmbH, edacentrum Haase, Jürgen Chair: Theatre Exhibition EXHIBITION THEATRE SESSIONS THEATRE EXHIBITION

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com 10.8 9.8 8.8 7.8 6.8 5.8 EXHIBITION THEATRE SESSIONS and successstories Everywhere Initiative &FED4SAE, opencalls Europe digitization: Smart Anything Quantum Computers Developing for andWorking with Real Session:Special IBM’s Qiskit Tool Chain: 2 Part 1 Part futures!Inspiring CareersSession @DATE digitalization ofEurope'sIndustry TETRAMAX: Smart fundingfor Applications Efficient UseofMulticore forsafety-critical Session:Special Project- TheARAMiSII Wednesday 1100 targeted objectives andimpact. will confront oflargethe viewpoint industrial, RTOstheir and SMEs and users andsuppliersacross value Europe.throughout chains This session companiesto further plusaccess VC funding,to potential v)andAccess toinnovativeto €60kinfinancialsupport support, iv)Up Management R&D centers, ii) Technical coaching from domain experts, iii) Innovation platforms, Advanced Technologies, and Testbeds from Industrials and accelerate developments CPS CPS combiningto leading-edge i)Access presentation of awarded projects illustrateto FED4SAE one-stop-shop to businesses fromtechnologies any and any sectors companies. The bringinginnovative aimsat FED4SAE project Cyber-Physical System Thursday 1100 Thursday 0830 Wednesday 1700 Wednesday 1430 the innovationand use opportunities. ed and implementedto overcome in practice and the associated pitfalls and byuseofconcretetransfer examplestechnology how canbeinitiat to business. The session speakers will demonstrate in a pragmatic way transfer informationment to technologies and knowledgefrom research demanding challenge forthe most to imple- Europe'sOne of is Industry gamme will be tailored to the needs of the students andresearchers.the needsof tailoredto gamme willbe areas coveredtechnology jobseekersthe in byDATE andHiPEAC. The pro- and small, aswelluniversities andresearch centres –withpotential together recruitersto bring – mostly companiesThis session aims large Wednesday 0830 – – 1230 1000 – – – – 1230 1830 1600 1000 " SeePage 97 " SeePage 90 " SeePage 72 " SeePage 85 " SeePage 78 " SeePage 64 143 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - See Page 102 " See Page 108 " See Page www.date-conference.com 1530 1730 – – Thursday 1400 Thursday 1600 Thursday MATLAB and Simulink provide a rich environment for embedded-system for a rich environment Simulink provide and MATLAB to algorithms ready specialized of proven, with libraries development, model-based enables a The environment specific applications. use for of the algo- fast and implementation prototyping for design workflow A system- such as MPSoC. embedded rithms on heterogeneous targets, partitioning, and exploration enables architectural design approach level workflows. HW development and SW between as well as coordination cover throughout improves verification the design process Functional age and test-case generation while reducing the while reducing time and resources age and test-case generation required. Part 2 An Industry Approach to FPGA/ARM System System FPGA/ARM to Approach An Industry and Verification Development Part 1 144 12.8 11.8

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UB03.3 UB07.3 for platform a flexible provide (SOA) Service-Oriented Architectures a research present We applications. software automotive advanced and applications. software of platform prototyping fast for platform are and actuators sensors Several car. is built a RC around The hardware higher-level that can be accessed from microcontrollers over connected on 4 Linux- executed are User applications bus connections. ECUs over a multi-hop Ethernet network. All over based ECUs which communicate an automotive SOME-IP, over is realized of applications communication The development principle.that is based on the SOA layer middleware and all required user tasks, for skeletons code generates framework framework, code of the underlying SOA management and configuration model. Itbased on a user specified application is then automatically show usability the We ECUs. on the respective and compiled transferred scenario. by a remote-operation of the platform - Insti Royal KTH Chen, Zhonghai Lu and De-Jiu Becker, Matthias Authors: SE Technology, tute of Timeslots: UB02.3 The University Booth is organised during DATE and will be located in be located will and DATE during organised Booth is The University 26 Tuesday, from place will take All demonstrations area. the exhibition and public Universities during DATE. 2019, 28 March Thursday, to March, or software been invited to submit hardware institutes have research demonstrators. of 32 demonstrations is composed Booth programme The University solu- and hardware software presenting countries, ten different from in nine sessions of 2 or 2.5 h duration is organised programme The tions. the topics: and will cover • • • • to find out about you 2019 invites more the at Booth DATE The University research the international from and hardware latest in software trends community. giving visitors more than once, will be shown more Most demonstrators come to to flexibility the booth and find out aboutlatest the innovations. supplement to an attractive will give that sure are the demonstrators We to would like thank all We exhibition. and program conference DATE the programme. to this contributors online at https://www.date-conference. available is information More is included in Booth programme The University com/exhibition/u-booth. online at https://www.date-confer booklet and available the conference ence.com/exhibition/ub-programme. The following demonstrators will demonstrators The following ence.com/exhibition/ub-programme. at Booth. the University be presented A FAST PROTOTYPING FRAMEWORK FRAMEWORK PROTOTYPING A FAST AUTOMOTIVE FOR SERVICE-ORIENTED APPLICATIONS University Booth at DATE 2019 DATE at Booth University 146

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com UNIVERSITY BOOTH RADAR AN INTEGRATED HARDWARE-IN-THE-LOOP A RISC-VBASED VIRTUAL PROTOTYPE WITH PLATFORMMICROFLUIDICS DIGITAL RECONFIGURABLE A MODULAR the platform. LOC. The prototype showninFigureto demonstratethe purpose 2serves capable ofevolvingto matchthe instrumentation needsofaspecific figurable microfluidics instrumentation platform (shown in Figure 1) mentation needs. To addressthis matter, wepresent amodularrecon- design, simulate, program andoperatethe broad range ofLOC instru- the needofsoftwaredevices impose tools andhardware to instruments answer functionality. The growing complexity and integrationthe LOC of assaysto be implemented on a LOC providesthat device full sample-to- crofluidics withminiaturized methodsallows biomedicallab analytical thus implementing sample preparation protocols. Combining digital mi- can beprogrammatically dispensed, moved, mixed, react, andstored split terned withindividuallyaddressable electrodes. Microliter sized droplets devicemanipulation pat of liquids on achip-scaled of a small amount allows that (LOC) technology for Digital microfluidics is a lab-on-a-chip UB10.4 UB08.8 UB02.10 Timeslots: 3 visible in this setup.visible in operatingtop ofanadditionalhost on system, ofbothisnot the impact the Though VP isexecuted inalinuxbased VirtualBox machine virtual the samecomponentsimplemented asQEMU QOM hardware models. board withanSPI-CAN adapterandadisplay. Forthe VP integration, we VP. Forthe HiFive1 integration, wedeveloped anArdunio compliant the SiFivewith RISC-V HiFive1 development board andourQEMU based integrates ourin-housedeveloped 120GHzradar sensorviaCAN bus work forthe analysis of suchembedded applications. The demonstration totyping environments provide anadequate, stable, andefficient frame- This demonstrates widelyavailablethat pro opensource- basedvirtual compiledtarget software a visible difference without time. in reaction wherethe the processorVP and concurrently executethe same exactly cation withaRISC-V processor board andaRISC-V Virtual Prototype (VP) Our demonstration shows a small radar sensor in interactive communi- UB06.6 Timeslot: ler andChristophScheytt, Paderborn University, DE Authors: Peer Adelt, DenisZeinel, BastianKoppelmann, Wolfgang Muel- Georgi TanevAuthors: 1 DTU Compute, DK Technical University ofDenmark, DK; Thursday, 28March 2019 Wednesday, 27March 2019 Tuesday, 26March 2019 Wednesday, 27March 2019 1 , WinnieSvendsen 2 DTU Bioengineering, DK 2 and JanMadsen 1200 1600 1230 1200 – – – – 1430 1800 1500 1400 3 147 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - 2 1230 1500 – – 1500 – 1730 1400 – 1600 1600 – 1800 1030 1230 www.date-conference.com Synelixis Solutions LTD, GR Solutions LTD, Synelixis 2 and Ioannis Papaefstathiou 1 2019 26 March Tuesday, 2019 27 March Wednesday, 2019 27 March Wednesday, Tuesday, 26 March 2019 26 March Tuesday, 2019 26 March Tuesday, Technical University of Crete, GR; of Crete, University Technical 1 Luca Crocetti, Luca Baldanzi and Luca Fanucci, University of University Luca Baldanzi and Luca Fanucci, Authors: Luca Crocetti, IT Pisa, Timeslots: UB03.10 UB07.6 UB08.6 more and more industry in is automotive the integrate to trend Today’s functionalities and systems in order to offer electronics interconnected - also by adoption of wire servicesto orientated the autonomous driving, car Thus a connected 802.11p. Wi-Fi such as links less communication and to actresults networks thus and heterogeneous as a node of many demo The proposed being exposed to of the the IT field. typical threats ap real hypothetical a of vulnerabilities security the aims investigate to plication scenario exploiting the wireless links and to links targetwireless the exploiting scenario related the plication The possible attacks. to counteract required mechanisms cybersecurity boards thatof act two FPGA consists demo based 802.11p of a nodes as a laptop and unit, as one an infrastructure as and one car the network, attack. thatand performs Man-In-The-Middle acts a entity as malicious between the malicious node alters The emulated the communication as car node to FPGA threats the car-like nodes and expose two FPGA stealing. Authors: Tampouratzis Nikolaos Timeslots: UB01.5 UB02.5 in both embedded (e.g. auto- accelerators use of hardware The growing and high-endmotive) systems (e.g. demand triggers an urgent Clouds) manner all in an integrated that can simulate frameworks simulation for Accelerators) Hardware Networks, Memories, (i.e. CPUs, components the software By utilizing such a simulator, (SuD). of a system-under-design which results development with hardware in parallel design can proceed in of reduction the importantso the problem, main The time-to-market. - is a shortage frame is there of such simulation that currently however, (i.e. modelling full- applications user the most for used simulators works; lack any of supporttype tailor-made for system CPU/Mem/Peripherals) is the first framework open-source, known ACSIM accelerators. hardware - high-performancethat simulator can handle holistically system-of-sys The networks. and accelerators peripherals, processors, including tems GUI sophisticated with its together be will framework ACSIM complete presented. ADDRESSING MAN-IN-THE-MIDDLE CONNECTED CARS IN EXTENSIVELY THREAT AUTOMOTIVE AND NEXT-GENERATION NETWORKS ACSIM: A NOVEL, SIMULATOR FOR SIMULATOR A NOVEL, ACSIM: AND HETEROGENEOUS PARALLEL IN-CORPORATE THAT DISTRIBUTED SYSTEMS ACCELERATORS HARDWARE CUSTOM 148

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com UNIVERSITY BOOTH COMMUNICATION CONSTRAINTS ALGORITHMS ONMULTI WITH CHIP/FPGA ASAM: AUTOMATIC SYNTHESIS OF SMART-BUILDINGS APODOSIS: ADVANCED ORCHESTRATOR FOR also exhibits limitedcomputational complexity. inadistributedmanner,posed decision-makingisperformed whileit Incontrast cost. to similarapproaches,the energy to minimize the pro - production from renewable loads,the energy sources and isfeasible it gridenvironment.chestrator Byefficiently control ofasmart energy This workpresents adistributed systemfor advanced supporting or UB10.5 UB02.9 Timeslots: 1 UB03.4 Timeslots: University of Tokyo, JP saka, Akihiro Goda, AmirMasoudGharehbaghi andMasahiro Fujita, The Authors: AmirMasoudGharehbaghi, Tomohiro Maruoka, Yukio Miya- 2 well asfullyconnected layers. to convolutionaltions neural networks (CNNs) for convolution layers as from data-flow graphs (DFGs) andequations, specifically withapplica- neural networks. We willdemonstrate ourmappingsmethodsstarting as generalizationtechniques for large problems size as convolutional topology,with mesh assumingfine-grained reconfigurable cores, aswell topology, connectedfor withring multi-chip andmulti-core connected Specifically,for optimalmapping. wedemonstrate compilation methods considersthat communication architecturethe related and constraints we present andmulti-core ourcompilertools for systems multi-chip cores needssophisticated compilationthis demonstration, methods.In Mapping oflarge systems/computations onmultiplechips/multiple UB09.3 UB07.7 Authors: Kostas Siozios Department ofPhysics,Department AristotleUniversity of Thessaloniki, GR Aristotle University of Thessaloniki, GR Thursday, 28March 2019 Tuesday, 26March 2019 Tuesday, 26March 2019 Thursday, 28March 2019 Wednesday, 27March 2019 1 and StylianosSiskos 2 1200 1230 1500 1000 1400 – – – – – 1430 1500 1730 1200 1600 149 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - and 1 , Ales- , 3 1 1200 1200 1230 1400 1200 – – – – – 1000 1000 1030 1200 1000 www.date-conference.com , Tania Di Mascio Tania , 1 and Daniel Ménard 2 , Luigi Pomante1, Claudia Rinaldi Luigi Pomante1, , 2 Ministry of Education, IT Ministry of Education, , Federica Caruso Federica , 2 1 University of Rennes, INRIA/IRISA, FR of Rennes, University , Olivier Sentieys , 2 1 , Marco Pennese Marco , 1 2019 28 March Thursday, Wednesday, 27 March 2019 27 March Wednesday, Wednesday, 27 March 2019 27 March Wednesday, 2019 28 March Thursday, 2019 26 March Tuesday, 1 University of Lyon, FR; of Lyon, University FR - IETR, INSA Rennes University of L'Aquila, IT; of L'Aquila, University Marco Santic Marco 1 UB09.5 a serious as developed system, learning is an adaptive (CS) CrazySquare young teenager ap for specifically indicated music education, game for - direc the first music for proaching recent educative time. CS is based on directtions which consistto sound instead approach of using a more of alone. It by a paper-based the musical notation been inspired has - in an Italian middle school. CS repre used that is currently procedure in their students involving a supportsents such teachers who prefer for at the and, a playful pitch, and dimension of learning rhythmic notation such goals reach To a musical instrument. teaching playing same time, in the recent allexploits advances the fully CS way, cost-effective a in of mobile ap composed it framework is based on a domain. In fact, EDA tools HW/SW reality with augmented plications that will be integrated demo The proposed musical instruments. virtual/augmented to provide - implementa of CS framework the current will show the main features tion. Timeslots: UB05.5 Authors: Alberto Bosio Authors: 3 Federica Caruso Federica Authors: 1 UB06.9 UB09.10 how energydesign to effi- investigates (AxC) Computing Approximate performingof Instead systems. computing complex less and faster, cient, - a high amount of re requiring consequently, and, exact computation accuracy trading aims the specifications, relax AxC to selectively sources, present a Design is to The goal of this demonstrator, for efficiency. off the impact able explore to automatically framework Space Exploration accordingly application on a given operators approximate of different The HW architecture. and available the of accuracy level to the required variables of torelates optimization the word-length first demonstration energy) and qual- cost (e.g., system to explore or hardware in a software The and customized scalable both is tool targets solution. ity trade-off is demonstration The second arithmetic. and floating-point fixed-point demon- The proposed techniques. about the use of other approximate M03. Tutorial Monday with the DATE19 is linked strator Timeslots: UB01.7 DESIGN SPACE EXPLORATION FRAMEWORKS FRAMEWORKS EXPLORATION DESIGN SPACE COMPUTING FOR APPROXIMATE CS: CRAZYSQUARE CS: sandro D'Errico sandro 150

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com UNIVERSITY BOOTH BASED EMBEDDEDPLATFORMS DEPTHESTIMATIONMONOCULAR ONARM- EQ-PYD-NET: ENERGY-EFFICIENT ANALOG INTEGRATED CIRCUITS PROCEDURAL DESIGNAUTOMATION OF EDP PLAYER: ADESIGNASSISTANT FOR 1 Authors: Andrea Calimera Authors: Matthias Schweikardt without lossofbothdesignqualityandreliability.without power IC. to astrongThe usage ofEDPstime leads reduction ofdesign amplifier, abandgap, theautomated creation and of variants ofasmart three different examples: theautomated designofamilleroperational Cadence Virtuoso basedonCadencetool hasbeenutilized SKILL. forThe sign flow, calledEDPL(EDP-Language). toolisfullyintegrated The within de- typical manualanalogcircuit the tailoredto set sion ofaninstruction creation andexecution ofplainEDPs. tool providesThe apreliminary ver topologies. nologies and Wethe EDPPlayer, present the whichenables Design Plan).AnEDPcancover different parameters, performance tech- able script, whichmakes reusable. it We this principleEDP(Expert call knowledge-based strategy iscaptured ofhumanexperts inanexecut of analogintegrated circuits. Procedural automation means,the that this demonstration,In weaddress procedural designautomation circuit UB07.2 UB06.2 Timeslots: a Broadcom BCM2837chip-set. will bemaderunningonaRaspberry PIboardthe QPyD-Net powered by the livethe embeddeddomain. During demonstrationestablish itsusein the tradeoffaccuracy-energy monocular estimation to of unsupervised general-purpose architecturethe ARMCortex RISC of family, (ii)quantify the Quantized modelintoto demonstrate of a PyD-Net (i) the portability based onahardware-friendly fixed-point quantization. Theobjective is Then weintroduce anaccuracy-driven complexity reduction strategy to approach designed for and able state-of-the-art CPUs accuracy.CNN depthestimation network,the PyD-Net which consists ofalightweight power embeddedsystems. the demowe'reThroughto present going CPU monoculardepth estimationefficient forlow- using alow-cost The demonstrationthe implementationto show intends ofenergy- UB08.4 UB07.4 UB02.4 Timeslots: 1 teo Poggi Hochschule Reutlingen, DE; Politecnico di Torino, IT; 2 ,Fabio Tosi Wednesday, 27March 2019 Wednesday, 27March 2019 Wednesday, 27March 2019 Wednesday, 27March 2019 Tuesday, 26March 2019 2 and Stefano Mattoccia 2 Università diBologna, IT 1 , ValentinoPeluso 2 Infineon Technologies, DE 1 , HusniHabal 1 2 , Antonio Cipolletta 2 1400 1200 1600 1400 1230 and Jürgen Scheible – – – – – 1600 1400 1800 1600 1500 1 , Mat 1 151 - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - , 2 and Emilio 1 1200 1200 1230 – – – , Richard Membarth Richard , 1 IMT Lucca, IT Lucca, IMT 1000 1000 1030 2 , Marco Santic Marco , www.date-conference.com 1 , Bo Qiao , 1 1 ,Oliver Reiche ,Oliver 1 , Vittoriano Vittoriano Muttillo , 1 Wednesday, 27 March 2019 27 March Wednesday, 2019 28 March Thursday, 2019 26 March Tuesday, and Frank Hannig and Frank 1 2 Friedrich-Alexander-Universität Erlangen–Nürnberg (FAU), DE (FAU), Erlangen–Nürnberg Friedrich-Alexander-Universität DE Artificial (DFKI), Intelligence for Center German Research Università degli Studi dell'Aquila - DEWS, IT; - DEWS, dell'Aquila degli Studi Università Incerto 1 Jürgen Teich Jürgen Authors: M. Akif Oezkan Authors: Authors: Luigi Pomante Authors: 2 Timeslots: UB05.4 UB09.4 a for exploited recently been have architectures parallel Heterogeneous Embedded systems based domains. of embedded application wide range mem- cores, processor can include different on such kind of architectures es- ICs and a set among dedicated of connections them. Moreover, ories, even are they domains, application and aerospace pecially in automotive this demo addresses So, subjected more to mixed-criticality constraints. of mixed-criticality co-design embed- of the ESL HW/SW the problem it ded systems that exploit hypervisor (HPV) In particular, technologies. step, exploration space design CSP/SystemC-based an enhanced shows the sys- given flow co-design that, HW/SW of an existing in the context to propose able is designer: the (semi)automatically to specification tem - an HW/SW architecture; HPV-based parallel - a custom heterogeneous partitioning - a mapping of of partitionedthe the application; entities architecture. onto the proposed 1 Programming heterogeneous platforms to achieve high performance to achieve platforms heterogeneous Programming level tuning requires at a low code is laborious since writing efficient dif and is based on drastically optimizations with architecture-specific portability different across models. Performance programming fering the algorithm description from by decoupling can be achieved platforms Hipacc (http://hipacc-lang.org), present We the target implementation. DSL and a image processing of an open-source consisting a framework We from the same program. and FPGAs GPUs, to compiler target CPUs, computer real-world by considering Hipacc's productivity demonstrate (C++, code target generating and e.g. optical flow, vision applications, and GPU in a laptop and (CPU platforms C-based HLS)three for OpenCL, of images ac- processing we showcase real-time Finally, board). an FPGA on these platforms. by a USB camera quired Timeslot: UB01.4 HIPACC: SYNTHESIZING HIGH- HIPACC: PROCESSING PERFORMANCE IMAGE WITH HIPACC APPLICATIONS HEPSYCODE-MC: ELECTRONIC SYSTEM-LEVEL ELECTRONIC SYSTEM-LEVEL HEPSYCODE-MC: OF CO-DESIGN HW/SW FOR METHODOLOGY EMBEDDED SYSTEMS MIXED-CRITICALITY 152

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com UNIVERSITY BOOTH • • • • • • • PARTIALLY FUNCTIONS DEFINED FOR LOGICMINIMIZERS LOGIC MINIMIZER: BASED 802.15.4 ONIEEE PERSONALAREANETWORKSWIRELESS MANAGEMENT OFLOW DATA-RATE SW TOOLS, FORANALYSIS, DESIGNAND ACCESSIBLE RELATED TESTBEDS AND COMPOSED OFANUMBER OFREMOTELY ASAASFRAMEWORK,LABSMILING: Implementation of URL lists. Implementation ofURL Implementation ofrandom functions. Implementation ofEnglishdictionaries. Implementation addresstables. ofIP Implementation ofcode converters. to reduceA method variables bylineardecompositions. definedfunctions. Introduction ofpartially demonstration, aPCandposterareto show: used OutlineofDemonstrationthe list. table; In Englishword list; andURL clude implementations ofrandom code functions; converter; address IP transformations. usinglinear representthe function Applications in- functions. variablesThe minimizerto the input reduces the number of This demonstration shows a minimization system for defined partially UB08.2 UB05.2 Timeslots: chi, MeijiUniversity, JP Authors: Tsutomu Sasao, Kyu Matsuura, Kazuyuki Kai and Yukihiro Igu- QoS metrics. ing protocol compliances/extensions, runlowlevel packet sniffers with vanced are:testing scenario, services full-customizable validation/test down links, commands/messages/packets in/fromthenetwork).Ad- full control onsinglemotes(program, reset, physical poweron/off, up/ out-of-the-boxto fulfilldeveloper them designed needsgiving service physical devices (sensornodes)to developers. provides It acomfortable makethat SWtools available stillscalable)numberof ameaningful(but testbeds deployedconnects inareal-world-environmentthe related and heterogeneity. This demoshows LabSmiling: aSaaSframework which the exploitationthe network growstestbed as of a in complexity and SW 802.15.4standard (and basedonIEEE derivations, 15.4e), e.g. require tion, healthmonitoring. The development,testing of and deployment ly increasingtheir presencethe fieldsofIoT, in wearable, homeautoma- Low data-rate wireless personal area networks (LR-WPANs) are constant UB09.6 UB07.9 UB05.8 Timeslots: erti, University ofL'Aquila, IT Authors: Carlo Centofanti, LuigiPomante, Marco Santic and Walter Tib Wednesday, 27March 2019 Wednesday, 27March 2019 Thursday, 28March 2019 Wednesday, 27March 2019 Wednesday, 27March 2019 1600 1000 1000 1400 1000 – – – – – 1800 1200 1200 1600 1200 153 - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - Claudio Ru , 2 1230 1200 1500 1730 1400 – – – – – 1030 1000 1230 1500 1200 www.date-conference.com , Tiziana Tiziana Fanni , 2 , Carlo Sau Carlo , 1 University of Cagliari, IT of Cagliari, University 2 2 Tuesday, 26 March 2019 26 March Tuesday, 2019 27 March Wednesday, Tuesday, 26 March 2019 26 March Tuesday, 2019 27 March Wednesday, Tuesday, 26 March 2019 26 March Tuesday, and Luigi Raffo 1 Fanucci, University of Pisa, IT of Pisa, University Fanucci, University of Sassari, IT; of Sassari, University Timeslots: UB01.6 UB05.6 UNICA-Eolab and UNISS-IDEA of the capabilities booth is demonstrating Component (MDC) a model-basedfor tool: toolset the Multi-Dataflow cir (CGR) reconfigurable of virtual coarse-grain design and development optimization composition, multi-function substrate provides MDC cuits. environments. in real and integration kernels Inputs substrates. of CGR composition automatic Core: 1 Baseline description is RTL and target agnostic networks, as dataflow provided are [FPGA(1)/ASIC(2)] derived. to determine the optimal exploration design space automated 2 Profiler: [2] a set given of constraints. substrate multi-functional CGR - identi Model level minimization. power consumption Manager: 3 Power domains regions of to determine optimal power/clock fication the logic [1/2] strategies. and apply saving IPs and APIs. of Xilinx-compliant generation automatic 4 Prototyper: [1] MDC is part of the H2020 CERBERO toolchain. Material: http://sites. unica.it/rpct/ and IDEA Lab Channel www.goo.gl/7fXme3. Francesca Palumbo Authors: Francesca UB03.6 UB06.8 exploit machine learning technology Speech We to build Automatic a speech disorder people with dysarthria, (ASR) solutions for Recognition to many speaking and related of users’ by low intelligibility characterized assis- voice popular nowadays ASR, of field the Within disabilities. motor tant solutions (e.g.,Apple Siri) perform poorly on dysarthric- speech pro disabilities cannot so users with benefit suchcessing, from technologies custom a issues, these address To smart like home. scenarios, many in it- rec dependent approach: using a speaker ASR has been prototyped al- have disabled Italian persons who from keywords predefined ognizes platform our edge computing The demo shows their voices. shared ready computer and its usage within the field of human speech recognition for and to users allowing app mobile a record present to also We interaction. we enrich these data, With selected keywords. while say they voice share scenarios. application many our speech model in order to serve Marini and Marco Gabriele Meoni, Mulfari, Authors: Davide Luca Timeslots: UB02.6 1 MDC: MULTI-DATAFLOW COMPOSER TOOL: TOOL: COMPOSER MULTI-DATAFLOW MDC: COMPOSITION HARDWARE TO DATAFLOW OF RECONFIGURABLE AND OPTIMIZATION ACCELERATORS battu MASCARA: A MACHINE LEARNINGMASCARA: SPEECH RECOGNITION AUTOMATIC DYSARTHRIA FOR USERS WITH PLATFORM 154

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com UNIVERSITY BOOTH PRODUCTION PLANNING TOOL PRODUCTION PLANNING MICROPLAN: MICRO-SYSTEM DESIGNAND EDGE-COMPUTING PLATFORMS MECO: ANAUTONOMIC MANAGER FOR any visitor on their smartphone orcomputer.their smartphone any visitoron tion with X-Fab. requiretool doesn't The installation and can be used by andinclosecoopera project - tool isdevelopedthe MICROPRINCE within heterogeneous systemswithanemphasisonlowproduction costs. The to high production costs. However,tool allowsto design using our users performance, heterogeneous systemsare often rendered unviable due production for cost agiven order quantity. Being superiorwithregardto visualizationthe wafer of utilization andeventually acalculationthe of erogeneous micro-systems. tool consistsThe ofasimplelayout editor, a Weto layoutthe production ofhet enables andplan that tool present a UB10.3 UB06.3 UB03.1 UB01.3 Timeslots: Universität Dresden, DE Authors: Horst Tilman, Fischbach Robert andJens Lienig, Technische among different willbeillustrated functionalities aswell. use caseimplemented onaZynq Ultrascale+ SoC.Finally, acomparison the appropriate selects manager, will be shown by means of a reference ploits alibrarythen to composethe monitoringsystemand ofelements reconfiguration.dynamic partial Thewholedevelopment flow, that ex anddetermineswhetherisconvenientquality ofservice a to perform time manager, monitoring system,together with a smart evaluatesthe loop for edge-computingtargeting devices FPGAs. An adaptive run- figurability. So, thisdemopresents animplementation ofaself-adaptive the useFPGAs,world isleadingon their inherent run-timereconto due - the interactionskeepingthe physicalthe adaptabilityimposedby with to satisfy increasingable requirements incomputing performance, while the Cyber-Physical-SystemsIn word,the needfor hardware platforms UB09.9 UB07.8 UB05.9 Timeslots: acomo Valente, University ofL'Aquila, IT Authors: GabriellaD'Andrea, Tania DiMascio, LuigiPomante andGi- Thursday, 28March 2019 Wednesday, 27March 2019 Tuesday, 26March 2019 Tuesday, 26March 2019 Thursday, 28March 2019 Wednesday, 27March 2019 Wednesday, 27March 2019 1200 1200 1500 1030 1000 1400 1000 – – – – – – – 1430 1400 1730 1230 1200 1600 1200 155 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 and 3 , 1 2 1400 1800 1800 , Simon Moore , – – – 2 , Shane Fleming , 2 1200 1600 1600 www.date-conference.com and So Tamura 1 , Andrey Mokhov Andrey , 4 University of Southampton, GB of Southampton, University Newcastle University, GB Newcastle University, , Tarawneh Ghaith , 4 2 1 , Yasuhiro Nitta Yasuhiro , 1 Kyoto Universiy, JP Universiy, Kyoto 2 , Andrew Brown Andrew , 3 Wednesday, 27 March 2019 27 March Wednesday, Wednesday, 27 March 2019 27 March Wednesday, Wednesday, 27 March 2019 27 March Wednesday, 1 Imperial College London, GB; London, Imperial College GB; of Cambridge, University Kyoto University, JP; University, Kyoto Matthew Naylor Matthew David Thomas David UB08.9 robot ROS on based systems for platforms design researching are We sta- will present we the current In the booth, System). Operating (Robot a lightweight The first project is mROS, activities. tus of two research - com ROS-compatible a offers mROS nodes. of ROS environment runtime processor on the embedded mid-range to be operated library munication to utilizing low with Linux. contributes which cannot mROS be operated will show the case We system. into the ROS power embedded devices ZytleBot, is second The system. on of mROS camera study distributed the utilizing platform integrated an autonomous driving robot as an FPGA - performs preproc the FPGA ZytleBot, SoC. In programmable the Xilinx and calcula- from the camera acquired image essing of surface the road about achieved We signal detection. for calculation tion of HOG feature will demonstrate We performance by utilizing 5 the FPGA. times faster signal detection the real-time task on ZytleBotthe FPGA that FPT'18 won design competition. Timeslots: UB06.4 Timeslot: UB08.10 POETS number technology large is based on POETS the idea of an extremely communications parallel hardware, embedded in a fast, of small cores by is effected network communication The application infrastructure. This project is a few bytes). (a packets data hardware size fixed small, - and devel researching four effortUK universities, between collaborative methodologythe potential to realise and the hardware oping a software of demonstrations booth will consist of live of A POETS this architecture. al- Traversal Graph as such architecture, this from benefiting applications Dynamics. Particle Dissipative and Equations Heat Dissipation gorithms, and laptops display based in Cambridge, run on hardware Applications output data received from produced of these applications, visualisations real-time. allowing visitors Some to view in these applications via wi-fi, a visitor can affect the application interactive; are of the demonstrations and see how in real-time. this changes the outcome Jonathan Beaumont Jonathan Authors: 3 Authors: Hideki Takase Authors: 1 1 POETS: PARTIALLY ORDERED EVENT DRIVEN DRIVEN ORDERED EVENT PARTIALLY POETS: SYSTEMS MROS AND ZYTLEBOT: DESIGN PLATFORMS PLATFORMS DESIGN ANDMROS ZYTLEBOT: SYSTEMS ROBOT FOR EMBEDDED 156

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com UNIVERSITY BOOTH Simone Vuotto CONSISTENCY CHECKING REQV: FORMAL ATOOL FORREQUIREMENTS PLATFORMHETEROGENEOUS WITHPREESM OPTIMIZED ADAPTIVE SOFTWARE ONA PREESM: GENERATING ENERGY- 1 Authors: LucaPulina Authors: MaximePelcat UB03.8 UB03.8 Timeslots: designer to correct awrongdesigner specification. ofconflicting the minimalset requirements,extract the tohelp inorder requirements, ofinput the caseofinconsistencythe set of ReqV canalso Logic satisfiability solvers In the for formal consistency checkingpart. the contexttions in ofCyber-Physical Systems –andLinear Temporal to write useful requirementsmerical signals – which enables specifica- are anextension Specification ofProperty to Patterns constrained nu- prossimo.it/docs/ReqV_video.mp4. technologies usedinReqVThe basic tutorial iscurrentlylanguages. Avideo available at http://www.cluster- requirenot any background knowledgeofformal methodsandlogical ofrequirements aset as input expressed innatural language, does soit BERO (http://www.cerbero-h2020.eu/tools-and-tutorials/). ReqVtakes ency checkingdeveloped CER the contextthe H2020EUproject in of the demo wewill present ReqV,In tool for a requirements formal consist UB10.8 UB09.8 UB07.10 http://preesm.org toolchain. munity.the H2020CERBERO of are part andSPIDER PREESM are available onGitHub,tutorials andareactive by com andsupported - such asscheduling, use, memory andcore andSPIDER loads.PREESM takes mappingdecisions andprovides earlydesignspaceinformation tems (e.g., ARM, DSP, FPGA). 3-Prototype andRun your Design: PREESM tecture: simulates PREESM andgenerates code for awiderange ofsys- taflow language, to express designed parallelism. 2-Model your Archi- are:PREESM 1-Model your Application: provides PREESM you withada- statically Stepswhenusing mappedoradaptively managedbySPIDER. tions andgenerates code for multi/many-cores. Processing caneitherbe simulates PREESM stream processingmanager named SPIDER. applica- form. isarapid PREESM systemprototypingtool provided witharuntime gy-optimized sensor-based adaptive software onaheterogeneous plat tools generate This Boothdemonstrates ener andSPIDER howPREESM UB08.5 UB06.5 UB03.5 Timeslots: 1 Heulot restier INSA Rennes/IETR,INSA FR; University ofSassari, IT; 1 1 , Alexandre Honorat and Jean-François Nezan 1 Tuesday, 26March 2019 Thursday, 28March 2019 Thursday, 28March 2019 Wednesday, 27March 2019 Wednesday, 27March 2019 Wednesday, 27March 2019 Tuesday, 26March 2019 1 , MassimoNarizzano 2 UNISS, Rennes/IETR, INSA FR 1 2 , Karol Desnos University ofGenoa, IT 1 , ClaudioRubattu 1 1 , DanielMenard 2 ,Armando Tacchella 2 1500 1200 1000 1400 1600 1200 1500 , Antoine Morvan – – – – – – – 1730 1430 1200 1600 1800 1400 1730 1 , FlorianAr 2 1 and , Julien - 157 - - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 , 6 , 3 and 8 , Junchao Junchao , 2 , Thomas Thomas Lange , 5 , Dmytro Petryk Dmytro , 1230 1200 1230 1500 1600 1800 1200 1430 7 – – – – – – – – , Aneesh Bal- Aneesh , 4 1030 1000 1030 1230 1400 1600 1000 1200 Politecnico di Torino, Politecnico di Torino, www.date-conference.com 5 , Ahmet Bagbaba Cagri , 8 , Hoang M. Le1 and Rolf Rolf Hoang M. Le1 and , 2 Delft University of Technology, Technology, of University Delft 2 , Guilherme Cardoso Medeiros Cardoso Guilherme , , Shayesteh Masoumian Shayesteh , 1 University of Bremen, DFKI GmbH, DE DFKI GmbH, of Bremen, University 1 Intrinsic ID B.V., NL IDIntrinsic B.V., 2 7 , Daniel Große , 1 , Josie Esteban Rodriguez Condia Rodriguez Josie Esteban , 4 , Raphael Segabinazzi Ferreira Segabinazzi Raphael , 5 , Felipe Augusto da Silva Augusto Felipe , 1 2 Tuesday, 26 March 2019 26 March Tuesday, 2019 27 March Wednesday, Tuesday, 26 March 2019 26 March Tuesday, 2019 26 March Tuesday, 2019 27 March Wednesday, 2019 27 March Wednesday, 2019 28 March Thursday, 2019 28 March Thursday, BTU Cottbus-Senftenberg, DE; Cottbus-Senftenberg, BTU 4 , Xinhui Anna Lai Xinhui , 6 2 , Nevin George Nevin , 3 IHP, DE; IHP, 3 IROC Technologies, FR; IROC Technologies, 6 University of Bremen, DE; of Bremen, University Tallinn University of Technology, EE; Technology, of University Tallinn DE GmbH, Design Systems Cadence Maksim Jenihhin Maksim 1 Timeslots: UB01.9 UB05.10 - is gain Instruction Set (ISA), open and free being an Architecture RISC-V, (IoT) devices. in Internet-of-Things ISA ing huge popularity as processor (VP) dem- Prototype Virtual based RISC-V an open source propose We at (available onstrator http://www.systemc-verification.org/riscv-vp). using a generic SystemC compliant in standard VP is implemented Our At the heartVP is a 32 2.0 communication. TLM of our bus system with Instruction Set (ISS) with support Simulator (RV32IMAC) for bit RISC-V IoT devices VP that to emulate This enables our instructions. compressed can VP Our amountsmall a with work memoryof resources. limited and as well as and verification, development early SW for be used as platform SW provide support toolchain, We the GCC use cases. other system-level Our capabilities and support measurement FreeRTOS. coverage debug, we example For extensible platform. and VP is designed as configurable SiFive. from board HiFive1 for the RISC-V the configuration provide Troya Cagil Koylu Cagil Troya Aleksa Damljanovic Aleksa Cemil Cem Gürsoy Cem Cemil Authors: Drechsler Authors: Vladimir Herdt Authors: 8 NL; akrishnan Chen 1 Timeslots: UB01.8 UB02.8 UB07.1 UB08.1 UB09.2 UB10.2 a by toolsetof team developed EDA an introduce will demonstrator The RESCUE in The recent PhD students trends the H2020-MSCA-ITN project. of IoT, in systems include machine intelligence the era the computing for of tech- miniaturization extreme applications, safety-critical complex These trends with world. the physical interaction nologies and intensive design on mutually dependent extra-functional set tough requirements (function- reliability aspects. challenges for RESCUE on the key is focused PUF technol- security (tamper-resistance, errors), soft ageing, al safety, functional test, models, fault security) and quality (novel intelligent ogy, The methodologies. EDA related and verification/debug) FMEA/FMECA, TU UT, Tallinn team from cross-sectoral of objective the interdisciplinary is Bosch and to Cadence Intrinsic-ID, IROC, IHP, POLITO, Cottbus, BTU Delft, assessment modelling, toolset for EDA a holistic in collaboration develop design aspects.and enhancement of these extra-functional IT; RESCUE: EDA TOOLSET FOR FOR TOOLSET EDA RESCUE: INTERDEPENDENT OF ASPECTS IN SECURITY AND QUALITY RELIABILITY, DESIGN NANOELECTRONIC SYSTEMS RISC-V VP: RISC-V BASED VIRTUAL VIRTUAL RISC-V BASED RISC-V VP: AN OPEN SOURCE PLATFORM PROTOTYPE: FOR MODELING AND VERIFICATION 158

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com UNIVERSITY BOOTH INDUCED SOFTERRORS ONFPGAS INDUCED ANALYZING MITIGATING AND RADIATION- SETA-RAY: TOOL IDE FORPREDICTING, ANEW WITH AUTOMATIC DIAGRAM SYNTHESIS SUITE MODELING OPEN-SOURCE MODULAR SCCHARTS: SCCHARTS KIELER THE EDITOR -A tika 1 mission project that willbelaunchedin2021. that mission project space by ESAthe EUCLID and to has been applied It Thales Alenia Space. analysis. the performed basedon issupported original netlist This IDE implementedindustrial circuit onFlash-based FPGA andmitigatethe the commercial FPGAtool for design evaluatingthe the sensitivityof the SETAprovidedto the secondtool as developedtool integrated with the radiation.the deviceto exposedof The predicted source SETpulsein and interactionthe particles, angleof the material andphysical layout the featurescount the radiation of type, environmentthe suchas LET to ac- taking in the SETphenomenaby the source of to predict capable with commercial EDAtools. RAD-RAY andonlydeveloped tool the first as Therefore,two software including wepropose anIDE tools compatible tion suchasspaceandavionic fieldsis radiation-induced soft errors. the main concernOne of for FPGA adopted in mission critical applica- UB09.7 UB08.7 UB03.9 UB01.10 Timeslots: Torino, IT Authors: LucaSterpone, Boyang DuandSarah Azimi, Politecnico di Authors: Steven Smyth other languagesordomains. application andprototype development. The conceptsto canbeapplied ware. the compiler of frameworkThe modularconcept allows for rapid results,to different anddeployment platforms, bothsoftware andhard- compilation,The editorsupports automatic syntheses ofintermediate suite,the synchronous languageSCCharts using asmaindemonstrator. mations. SCCharts EditorThe KIELER is a modular, open-source modeling transforthe tial issuesandprovideto understanddetailsabout means to poten- the modeler tools shouldguide Modeling time consuming. less transformationworking with model systems becomestransparent and velopment process. Combinedtransienttechnologies, withmodern view fromtool developer aninteractivethe modeler can the benefit and de- ware domain.Byleveragingthe compilation toametalevel, workflow transparent andefficient development process, for thehard - example in When usinghigh-level DSLs,the model-basedapproach promises amore UB06.7 UB05.7 UB03.7 UB02.7 Timeslots: Kiel University, DE; 2 and Reinhard von Hanxleden Thursday, 28March 2019 Wednesday, 27March 2019 Tuesday, 26March 2019 Tuesday, 26March 2019 Wednesday, 27March 2019 Wednesday, 27March 2019 Tuesday, 26March 2019 Tuesday, 26March 2019 2 Lufthansa Technik,DE 1 , Alexander Schulz-Rosengarten 1 1000 1600 1500 1030 1200 1000 1500 1230 – – – – – – – – 1200 1800 1730 1230 1400 1200 1730 1500 1 , ChristianMo- 159 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - - 1200 1800 1730 1600 – – – – 1000 1600 1500 1400 www.date-conference.com Wednesday, 27 March 2019 27 March Wednesday, 2019 26 March Tuesday, 2019 27 March Wednesday, Wednesday, 27 March 2019 27 March Wednesday, Martin Schöberl, Luca Pezzarossa and Jens Sparso, Technical Technical Sparso, and Jens Luca Pezzarossa Martin Schöberl, Authors: DK of Denmark, University Timeslots: UB03.2 UB08.3 for lay methodology a new automation exemplifies This demonstration and Ar Wiring Self-organized circuits: out design of analog integrated on Based - the idea of decen Modules (SWARM). of Responsive rangement multi-agent system. it the addresses an innovative task with tralization, is letto - respon similar of a sheep herd, to the roundup Its basic principle, interact generators) as procedural modules (implemented layout sive Each module is allowedzone. to layout with each other in a user-defined - while a supervising con itself, and deform rotate autonomously move, to steer zone the interaction tightens the layout successively organ trol various Considering arrangements. compact layout increasingly towards the phenomenon able is to evoke SWARM principles of self-organization, each module only has a limited viewpoint although and of emergence: can solutions overall remarkable objectives, selfishly pursues its personal on emerge the global scale. UB07.5 real-time systems or control such as advanced systems, real-time Future but system a still powerful more need processors, recognition, image (WCET)time predicted. worst-casethe where execution be statically can processing one answer more to are the need for processors Multicore question how itto best- is still an open research organ However, power. - between process and implement ize communication time-predictable research for processor multicore is an open-source T-CREST ing cores. Pat of several In consists architecture. on computer time-predictable communication time-predictable by various connected mos processors on-chip access shared to memory, off-chip, access shared to structures: communication. inter-processor fast for and network-on-chip the Argo - such as compi is supportedtools, development by open-source T-CREST is only the T-CREST best of our knowledge, To analysis. WCET and lation multicore real-time on future research for architecture fully open-source architectures. Daniel Marolt and Jürgen Scheible, Hochschule Reutlingen, DE Hochschule Reutlingen, Scheible, Daniel Marolt and Jürgen Authors: Timeslots: UB05.3 T-CREST: THE TIME-PREDICTABLE THE TIME-PREDICTABLE T-CREST: T-CREST PROCESSOR MULTICORE SWARM: SELF-ORGANIZED WIRING AND SWARM: MODULES OF RESPONSIVE ARRANGEMENT 160

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com UNIVERSITY BOOTH SYSTEM SENSORNETWORKS FORWIRELESS DETECTION AINTRUSION TINYWIDS: FRAMEWORK FOREMBEDDEDPROCESSORS &POWERTIMING CHARACTERIZATION 1 Authors: Walter Tiberti features. ing andeven andFPU undocumented CPU behaviour whileusingcertain framework for anARMCortex-M microcontroller andpresent interest eratesthe desiredtiming and power data. We will demonstratethis orchestratesthe evaluationthe physical setupand software whichgen- a code-generator for characterization binaries, acontrol program which the processor's GPIOs. a logicanalyserobserving The software consists of a processor board, a power measurement device, a heating and element prone wepresent anautomated approach. The physical setup consists of working conditions. Sincemanualmeasurements aretedious anderror- datato cover needed the complete microprocessors' ISA indifferent the systematictiming andpower collection oflarge of amount supports different temperature varying conditions (e.g. andclockfrequency). It ing accurate models for energy/timing embedded processors covering We present aframework significantlythat theeffort for reduces creat UB06.1 UB05.1 UB02.1 UB01.1 Timeslots: Information Technology,DE Authors: MarkKettner andFrank Oppenheimer, OFFIS-Institutefor of secure WSN deployments. canevolve somebasicattackstects theneeds the IDS to fullfil andhow this demonstration, In detected. works, weshowhowourIDS de- howit the sues in the operators WSNto notify tentative whenanattack and is the exploits WIDS Weak potentialto classify Process securityis- Models a real-world application of our WSN Intrusion System Detection (WIDS). be applied. Focusingthe "Intrusion problem, Detection" on wepropose consumption,ergy normalnetwork-security relatedtechniques cannot the hard constraintsto Due lenging. onperformance, storage anden- their communicationsthe motes and is chal- to protect security solution the domainof In Wireless SensorNetworks (WSN), providing aneffective UB10.1 UB09.1 Timeslots: University ofL'Aquila, IT; Wednesday, 27March 2019 Wednesday, 27March 2019 Tuesday, 26March 2019 Tuesday, 26March 2019 Thursday, 28March 2019 Thursday, 28March 2019 1 and LuigiPomante 2 DEWS, IT 2 1200 1000 1230 1030 1200 1000 – – – – – – 1400 1200 1500 1230 1430 1200 161 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - - 1230 1500 – – 1030 1230 www.date-conference.com Tuesday, 26 March 2019 26 March Tuesday, Tuesday, 26 March 2019 26 March Tuesday, UB02.2 circuits class of digital that has a promising are circuits Asynchronous in especially counterparts, synchronous their over advantages numerous - None speed-independentthe domain of "little digital" controllers. (SI) which in part is attrib adoption has nottheir been widespread, theless, speci- for employed models complex uted into to entry of difficulty the electronic by (STGs), Graphs Transition Signal like circuits, SI of fication Graphs Transition Waveform a new model called propose We designers. to familiar very thatare the resembles which diagrams, timing (WTGs) for This semantics. formal behaviour its and defines circuit designers, in order STGs equivalent into WTGs of the enables translation malization logic and verification and for tools body of research the existing to reuse has WTGs of development The of speed-independent circuits. synthesis allow toolkit (https://workcraft.org), Workcraft in the been automated and synthesis. verification STGs, into ing conversion their Danil Sokolov, Newcastle University, GB University, Newcastle Danil Sokolov, Authors: Timeslots: UB01.2 WTG: WAVEFORM TRANSITION GRAPHS: GRAPHS: TRANSITION WAVEFORM WTG: FOR FORMALISM A DESIGNER-FRIENDLY CIRCUITSASYNCHRONOUS 162

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com [email protected] Andreas Vörg, edacentrum, DE Ioana Vatajelu,Elena TIMA,FR University BoothCo-Chairs BOOTH! UNIVERSITY AT THE SEE YOU UNIVERSITY BOOTH

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FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - Room Lunch Area 10 Room 10 Room 9 Room 10 Room 10 Room 9 Room Lunch Area between 1 and 4 rooms www.date-conference.com Title Welcome Reception & PhD Forum, hosted by hosted Forum, & PhD Reception Welcome and IEEE CEDA SIGDA, ACM EDAA, Meeting ETTTC Assembly General EDAA the Energy Reliably Scaling Limits in Exceeding Deployments Edge/Cloud for Servers Commodity 10.5 Group Meeting of the IFIPWorking Workshop AMASS Open Industrial - video pro high definition real-time Accelerate a Zynq- Z7, cessing designs with Digilent Zybo HLS Vivado Xilinx and 7000 AP SoC Platform Meeting Sister Events DATE F1/10 Autonomous Racing Demo International supported by IEEE CEDA Mohamed Ibrahim, Duke University, US University, Duke Mohamed Ibrahim, pose of the PhD Forum is to offer a forum for PhD students to discuss forum a is to offer pose of the PhD Forum andof work with people the design automation their thesis and research students a good opportunity for It represents system design community. on feedback valuable on to get and the job market to receive exposure their work. for Mobile Resource Management Runtime Adaptive CMPs through Self-awareness US Irvine, of California, University Donyanavard, Bryan Author: Biomolecular of Trustworthy Optimization Using Cyber-Physical Analysis Quantitative Microfluidic Platforms Lunch Area 1800 - 2100 Lunch Area AT Linz, University Johannes Kepler Wille, Robert Chair: PhD Forum kindly in- visitors are and exhibition delegates conference All registered - subsequentand Fo PhD Reception Welcome 2019 vited join to DATE the 1800 - 2100 from 2019, 25 March place on Monday, which will take rum, in the Lunch Area. venue at the DATE is a poster session and a buffet Conference of the DATE The PhD Forum Association Design Automation style dinner hosted by the European (SIGDA), on Design Automation Group Special Interest the ACM (EDAA), The pur (CEDA). and Design Automation the IEEE on Electronic Council Welcome Reception & PhD Forum, hosted by & PhD Forum, Reception Welcome and IEEE CEDA SIGDA, ACM EDAA, FM01-1 FM01-3 164 MON Date Date & Time A number of specialist interest groups will be holding their meetings at DATE 2019. The 2019. will be holding of specialistA number attheir meetings groups DATE interest at scheduled meetings are the moment. list A complete following meetings can of fringe www.date-conference.com homepage on the DATE also be found FRINGE MEETINGS & CO-LOCATED WORKSHOPS MEETINGSFRINGE CO-LOCATED & MON MON 1800 – 2100 TUE 1300 – 1430 TUE 1600 – 1800 WED 0830 – 1130 WED 1230 – 1430 THU 0830 – 1230 THU 0900 – 1500 THU 1230 – 1330 FRI – 1500 1000

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com FM01-5 & CO-LOCATEDFRINGE MEETINGS WORKSHOPS FM01-27 FM01-26 FM01-25 FM01-23 FM01-21 FM01-20 FM01-19 FM01-18 FM01-17 FM01-16 FM01-15 FM01-14 FM01-9 FM01-7 FM01-6 Author: SimonRokicki, Irisa, FR Translation targetingVLIW processors Hybrid-DBT: Hardware-Accelerated Dynamic Binary Author: Vladimir Herdt, University ofBremen, DE Theory, Implementation andApplication Prototype Efficient Virtual Verification Techniques: Author: Tobias Wiersema, Paderborn University, DE Bitstream-level Proof-CarryingHardware Sul, BR Author: Marcelo Brandalero, Universidade Federal doRioGrande do Architecture MuTARe: AMulti-Target Adaptive Reconfigurable Author: DanieleJahierPagliari, Politecnico di Torino, IT Systems Design Techniques forEnergy-Quality Scalable Digital Author: Sukarn Agarwal, IndianInstituteof Technology Guwahati, IN Cache Management inChip Multiprocessors Controlling Writes forEnergyEfficient Non-Volatile Author: DeepakMathew, University ofKaiserslautern, DE Embedded andHighPerformance Computing Systems Advanced 3D-Integrated MemorySubsystemsfor Author: JasminJahic, Fraunhofer IESE, DE Supervised Testing ofEmbeddedConcurrent Software Author: Satyajit Das, Université deBretagne-Sud, FR Systems Reconfigurable Accelerators inMulti-Core Embedded Architecture andProgramming ModelSupport For Institute of Technology, DE Authors: Damschen, Marvin LarsBauerandJoerg Henkel, Karlsruhe Reconfigurable Architectures Worst-Case Execution TimeGuarantees forRuntime- Author: Andreas Grimmer, JohannesKepler University Linz, AT Microfluidics Automatic MethodsfortheDesignofDroplet Author: Jonathan Beaumont, ImperialCollege London, GB Concepts Compositional Circuit Designwith Asynchronous Erlangen-Nürnberg,sität DE Authors: Tobias Schwarzer andJürgen Teich, Friedrich-Alexander-Univer Oriented Applications onMPSoCs System-level Mapping andSynthesis ofData Flow- Author: M.HassanNajafi, University of Lafayette,Louisiana at US Encoding toDeterministicProcessing New Views forStochastic Computing: FromTime- Author: AlwinZulehner, JohannesKepler University Linz, AT Computer-Aided DesignforQuantum Computing Author: Sukanta Dey, IndianInstituteof Technology Guwahati, IN VLSI Power Networks Grid Analysis andOptimization ofReliability Issuesof 165 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 , Meng-Fan Meng-Fan , 1 1 www.date-conference.com , John (Jack) Sampson , 1 National Tsing Hua University, TW Hua University, Tsing National 2 and Vijaykrishnan Narayanan Vijaykrishnan and 2 Penn State University US; US; University State Penn Author: Ahmedullah Aziz, Purdue University, US University, Purdue Ahmedullah Aziz, Author: for Design IP Protection Frameworks CAD Advanced US University, York New Patnaik, Satwik Author: of Big Data Acceleration Emerging Computing: Applications US San Diego, of California University Mohsen Imani, Author: Author: Mahdi Tala, University of Ferrara, IT of Ferrara, University Tala, Mahdi Author: Computing Knobs for Resource Efficient Adaptive FI Turku, of University Anil Kanduri, Author: Phase Co-design Employing Device-Circuit Digital Power for Low Materials Transitioning Applications Author: Gabriele Ciarpi, University of Pisa, IT of Pisa, University Gabriele Ciarpi, Author: Design based Memory Integration Monolithic-3D and in-memory Robust techniques towards computing Srinivasa Rangachar Srivatsa Authors: Methodology and Integration Synthesis Cross-Layer for Optical Networks-on-Chip of Wavelength-Routed Systems Computing Parallel 3D-Stacked HW/SW Co-Design Methodology for Mixed-Criticality for Mixed-Criticality Co-Design Methodology HW/SW and Real-Time Embedded Systems IT of L'Aquila, University Muttillo, Vittoriano Author: Circuits Handshake Bundled-Data Improving DE of Potsdam, University Hasso-Plattner-Institut, Norman Kluge, Author: with Converter DC/DC IC Design of an Inductorless CMOS Range in Low-Cost Voltage Wide Input Optimization and Analysis for Dependable Software Software for Dependable and Analysis Optimization Platforms Hardware on Unreliable DE of Dortmund, University Technical Chen, Kuan-Hsun Author: and Implementation NoC based Custom Multiple CMPs attain Energy Efficient to Distribution Traffic IN MNIT Jaipur, Singh Gaur, Laxmi and Manoj Vijay Yadav, Sonal Authors: for FPGAs Generators True Random Number BE Leuven, KU and iMinds, ESAT/COSIC Yang, Bohan Author: Author: Athanasios Stratikopoulos, The University of Manchester, GB of Manchester, The University Stratikopoulos, Athanasios Author: Based Assertion with Framework A Model driven Systems Design for Embedded Support Verification Automation of Sciences & University National Anwar, Waseem Muhammad Author: PK (NUST), Technology Low-power Architectures for Automatic Speech for Automatic Architectures Low-power Recognition ES Center, Supercomputing Barcelona Tabani, Hamid Author: for Path Storage & Energy Efficient Overhead Low Systems Computer Next Generation 1 (Marvin) Chang FM01-47 FM01-53 FM01-54 FM01-48 FM01-52 FM01-44 FM01-41 FM01-43 FM01-33 FM01-37 FM01-38 FM01-31 FM01-32 FM01-30 166 FM01-28 FRINGE MEETINGS & CO-LOCATED WORKSHOPS MEETINGSFRINGE CO-LOCATED &

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com WED WED TUE TUE & CO-LOCATEDFRINGE MEETINGS WORKSHOPS Meeting of the IFIP WorkingMeeting oftheIFIP Group 10.5 Deployments Limits inCommodity Servers forEdge/Cloud Exceeding Reliably theEnergyScaling EDAA General Assembly ETTTC Meeting technologies). nical Committees. This isameetingorganized by WG10.5 (VLSI related hasoverand otherworldbodies. It 100 Working Groups and13 Tech- tions Technologies and Sciences andisrecognized byUnitedNations multinational, non-politicalorganization inInformation &Communica - International Federation forthe leading Information is Processing (IFIP) Organiser: Masahiro Fujita, University of Tokyo, JP Room 101230-1430 (http://www.uniserver2020.eu/).2020 UniServer project The researchthe Horizon presented by this workshop in issupported vealing results challengesandlatest from academiaandindustry. Queen's University andUniversities ofAthens, Cyprus and Thessaly re- Research,The workshoptalks willincludebyIBM ARM, WorldSensing, eration inEdge andClouddeployments. source (Openstack) management layers for ensuringreliable systemop while presenting andrethe virtualization (Hypervisor) - mechanismsat the software layers for exceedingthe conservative scalinglimits, energy tion, wewilldiscusshowsuchmethodscanguideinformed decisionsat modern multicore andDRAMs CPUs withincommodity servers. Inaddi- time voltage/refresh-rate margins characterization andidentification in this workshop,In wewillpresent recent methodsandstudies ondesign- efficiency. theenergy significantly gins limit manufactured chipsandamongdifferent workloads; however suchmar variability amongdifferent cores/cells thesamechip, of amongdifferent tems undervarious operating conditions, accounting forthe inherent guarantee correct executionthe software of layers ofcomputing sys- Conservative designmargins inmodernprocessor/memory chipsmay Organiser: Georgios Karakonstantis, Queen’s University Belfast, GB Room 90830-1130 interested inElectronic DesignAutomation. General assembly meeting forthe members of EDAA, to everyone open Wehn,Organiser:Norbert University ofKaiserslautern, DE Room 101600-1800 to share informationogy onupcoming events andprojects. state-of-the This meetingprovides art. involvedtechnol- allactors test in solve engineeringproblemstest,to helpadvance inelectronic the and members' professional development andadvancement,them to help Computersored Society.the IEEE by TTTC's goalsareto contributeto our the of section TTTC. ETTTC isavolunteer professional organization spon- The European Test Technology Technical Council (ETTTC)the European is Organiser: Bosio, Alberto INL, FR Room 101300-1430 167 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - www.date-conference.com Lunch Area 1230 - 1330 Lunch Area DE of Kaiserslautern, University NorbertOrganiser: Wehn, and DATE DAC ICCAD, ASP-DAC, from Meeting of the represenatives Room 9 0900 - 1500 Room RO Cristina Dabacan, Digilent, Organiser: RO leader at Digilent, Team FPGA Elod Gyorgy, Speaker: hands-on, a providing of mission Digilent's with aligns workshop The will use open-ended Attendees to education. approach project-based, (5MP camera PCAM platform), SoC FPGA Zynq Xilinx Z7 (a Digilent Zybo HLx high definition to implement a real-time Vivado sensor) and Xilinx application. video processing - pro based on both high-level are in materials the workshop Examples description language (VHDL). language (C++) gramming and hardware and simulation usage, core IP HLS design flow, will demonstrate Trainers with instruc- the workshop debugging. will leave Participants hardware sensor so that can easily 5MP camera they and PCAM, tional materials and projects. technique in their own courses adopt this innovative covered: Topics execution and program parallelism Explain HLS Vivado and Architecture FPGA Xilinx Introduce Z7 and PCAM Digilent Zybo Introduce Vivado algorithm on Xilinx video processing Accelerate Z7 and PCAM design on Digilent Zybo Implement video processing Room 10 0830 - 1230 Room ES III Carlos Universidad de Mardrid, Vara, de la Jose Luis Organiser: project R&D a H2020-ECSEL is (https://www.amass-ecsel.eu/) AMASS - con and thatcreated has organisations industrybetween research and and ecosystem, open European-wide platform, tool solidated the de-facto certification and safety-critical of assurance for community self-sustainable goal of AMASS The ultimate systems (https://www.polarsys.org/opencert/). and mar features changing rapidly of face is costs in to lower certification ket needs. This has been achieved by establishing a novel holistic and reuse- by establishing a novel This has been achieved needs. ket with compatible (fully assurance architecture-driven for approach oriented and co-analysis (for multi-concern assurance for such as SysML), standards seamless interoper and for of e.g. aspects), security and safety co-assurance activities and engineering along with ability between assurance third-party workshop activities (e.g. and supplier assurance).The assessments external aiming to gain awareness and researchers is at both practitioners targeted - certification and safe of assurance cost-effective on of latestthe advances will We solutions work. and of how the corresponding ty-critical systems, of the main examples application aspects practical and concrete present in Introduction to concepts two main sessions: results the AMASS AMASS and methodology approach. of the AMASS and Application DATE Sister Events Meeting Sister Events DATE Accelerate real-time high definition video real-time high definition Accelerate Z7, Zybo Digilent processing designs with and Xilinx a Zynq-7000 AP SoC Platform HLS Vivado AMASS Open Industrial Workshop Industrial AMASS Open • • • • • 168 THU THU THU FRINGE MEETINGS & CO-LOCATED WORKSHOPS MEETINGSFRINGE CO-LOCATED &

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com FRI & CO-LOCATEDFRINGE MEETINGS WORKSHOPS • • • Demo supported by IEEE CEDADemo supported byIEEE International F1/10Autonomous Racing cordiallythe presentationto join invited area infront ofRoom 1. All participants, whoare registered forthe Friday oneof Workshops, are Workshops. the Fridaytakethe breaktimes of The demosessionswill placeduring the community!Join takeone will placeinMontreal, Canada inApril2019. ica, event itsfourth edition.Last andnowisat was in Turin, the next and The competitiontwice peryear Amer isheld between Europe and North community. networking, fosteringthe exchange ofideasandcooperationsthe in ers and makers fromtwo days all aroundthe world in of challenges and mous Racing Competition (http://f1tenth.org/), whichgathers research - the 4thF1/10InternationalThese vehicles in willparticipate Autono- challenging scenario tracking algorithms for andcollision avoidance object inacomplex and Head-to-head race sessions, wheretwo ormore vehicle exercisetheir meminimal,must anddriver reliabilitythe key is threemany lapsaspossiblein minutes, i.e., wherethe crashes hazard Long-stint sessions,the vehicleto complete wherethe goalof is as time possible lap alone,the shortest in trials,time Single-lap wherethe goalofvehiclesto complete is asingle sions of: bring itsfullyautonomousF1/10prototypes, demoses- andperform from University of Modena and Reggio Emilia will hipert.unimore.it/) the event,During the High-Performance Real-Time Lab (HiPeRT - https:// and drones. systems, vehicle dynamicscontrol, highly-cooperative fleetsof vehicles of computer vision, machine learning, real-time systems, autonomous rently usedbyuniversitiesto doresearchthe field aroundtheworld in one weekwithfewthousands euros followingtutorials, our andiscur Indeed, aF1/10vehicle featuring advanced most sensorscanbeset-up in autonomous andcooperative systems, makingautonomy more accessible. to fullscalesolutions. testbed enablesresearchThe F1/10 andeducation in ception, planning, control, andnetworking software are stacksthat similar autonomous vehicletestbed. The F1/10 carries a full suite of sensors, per The F1/10isanopen-source, affordable, 1/10 scale andhigh-performance Marko ModenaandReggio Bertogna, Emilia, IT Paolo Burgio, University ofModenaandReggio Emilia, IT Organisers: between rooms 1and41000-1500 169 - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com 170

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI EXHIBITION GUIDE www.date-conference.com COMPANY PROFILES LIST OFEXHIBITORS EXHIBITION FLOOR PLAN solution and/orto contact. person The company theright profilesyou infinding willassist beingpresentedthe conference.products andservices at detailsandinformationlisted withcontact their about All corporate exhibitors sponsorsandparticipating are welcoming youthe beautifulcityofFlorence, in Italy! you very muchfor visitingDATE 2019andareto happy the wholeOrganising Committee,On behalfof thank we GUIDE EXHIBITION 174 173 172 171

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 Cash Bar Cash Coffee

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DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com University Booth TETRAMAX Symbiotic EDA Springer Nature SPP1648 Software for Exascale Computing (SPPEXA) SEMI 7 Towards Self-Aware Automotive andSpace Vehicles Research Unit: FOR1800Controlling Concurrent Change– MNEMOSENE Microtest Mentor, ASiemensBusiness MathWorks 5 Invasive Computing -CRC/Transregio 89 Intel 11 IngeniArs S.r.l. Infineon Technologies Austria AG Embedded Architecture andCompilation HiPEAC –European NetworkonHighPerformance and Floadia Corporation FED4SAE EUROPRACTICE 3 Eurolab4HPC Embedded Systems Initiative (ESI) inFogBig-Data Analytics Computing Ecosystem ELASTIC. ASoftware Architecture for Extreme-Scale for Future Hardware DFG SPP2037–ScalableData Management Collaborative Research Centre 901–On-The-Fly Computing Information byResource-Constrained Data Analysis Collaborative Research Center SFB876–Providing Cobham GaislerAB Distribituted Software for BigData Analytics CLASS. Edge andCloudComputation: AHighly Circuits Multi-Projects (CMP) CAEN Advantest Europe GmbH Company Booth LIST OF EXHIBITORS 16 Sponsor |19 EP 1 EP 5 EP 1 EP 3 EP 1 EP 2 EP 2 EP 4 173 15 10 20 13 14 12 20 18 17 21 1 4 9 8 6 2

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com +49 89 993120 Small and portable personal tester with all signals, features and per features Small and portable personal with all signals, tester formance - migra data Multiple IPs to customize testing needs and simple EDA tion Easy GUItesting through interfaces in tester hardware No capital investment • • • • Cadence Academic Network GmbH Design Systems Cadence 2 Mozartstr. 85622 Feldkirchen Germany Klotz Anton Contact: M [email protected] W www.cadence.com The in 2007. launched by Cadence Academic Network was Cadence of leading-edge technologies the proliferation to promote aim was their engineering and for renowned and methodologies at universities A knowledge network among selected universities, design excellence. established to was industry Cadence advisors and institutes, research sharing of the technologyfacilitate expertise verification, of in areas the systems. of microelectronic design and implementation - Presenta Interactive is sponsoring Network Academic DATE the Cadence again. tions (IPs) Stefan-George-Ring 2 Stefan-George-Ring 81929 Munich Germany König Cassandra Contact: T M [email protected] W www.advantest.com of producer is a leading Advantest A world-class technologycompany, automatic test industrythe semiconductor equipmentpremier and a for used in - instruments of measuring the design and produc manufacturer Testing Cloud and systems. Our exhibit, instruments tion of electronic addresses CTS standard to test an alternative hardware. offers Service, design labs, R&D engineers, major chipmakers, the challenges facing testers to institutes to get and research access ATE universities to large per pay debug and test It devices. their set is specially up with a flexibly, R&D. ideal for use model, include: of CTS The main features www.cts-advantest.com/en ASIC and SOC Design: Signal) •Verification Themal, Analysis (Timing, Physical Test: • Silicon BIST) (ATPG, Automation Test Analysis • • Logic Test Design for Validation Advantest Europe GmbH Europe Advantest 174 COMPANY PROFILES COMPANY Sponsor Booth 21

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI Booth 2 EP 4 www.date-conference.com COMPANY PROFILES CAEN Prototyping •Foundry &Manufacturing Services: MEMS Design ASIC andSOCDesign: provided inawiderange ofplasticandceramic packages. tools andEngineeringkitsforCAD MEMSare available. Assembling is croelectronicsto 28nmFDSOI.Designkitsfor IC andamsdown most are available onCMOS, SiGeBiCMOS, HV-CMOS, CMOS-Opto from STMi - and 74different technologieshave beeninterfaced. Integrated Circuits 8100 projects have beenprototypedthrough 1100manufacturing runs, than 600Institutionsfrom 70countries have beenserved, morethan MEMS, for prototyping andlowvolume production. Since1981, more Circuits Multi-Projects (CMP) isamanufacturing broker for ICsand W https://mycmp.fr/ M [email protected] F T Contact: Jean-ChristopheCrebier France 38031 Grenoble 46 avenue Felix Viallet Circuits Multi-Projects (CMP) innovation, proudly delivering “Tools for discovery”. technological content levelthe next the to andpushing forward taking CAEN counts onmorethan 30electronic engineersandphysics PhDsare Francois andPeter Englert W. Higgs. culminatedthe awarding with the NobelPrize for of to Physics 2013 boson". the "Higgs knownas the particle This demonstrationistence of where ATLAS andCMSexperiments have recently demonstratedthe ex forthe main users is CERN, One of the LHC Big and Science. which hosts exhaustive: ofCAEN productionnumber isnot iscustomdesigned part developed,totaling morethan 250catalogue products. However,this large choiceofFront-End modulesimplemented usingASICsinternally sides acomplete range ofpowersupplyanddata acquisitionsystems, a todayto offer,CAENthe onlycompany isknown the worldable as in be- homeland security. RFID,experiences suchasUHF microelectronics, aerospace, biomed, and “Innovation Company”.this way In to itscore CAEN added businessnew into national andinternationaling part programs andbecoming areal Overthe years, CAEN hasdiversified itsoffer, extendingitsmarket, tak Physics Laboratories. Nuclear important data acquisitionchannelsnowworkinginallmost therethe field: are hundreds thousand CAEN of Low/High Voltage and physics researchtodaythe world’s andis among leadingcompanies in signs andmanufactures sophisticated for electronic equipment nuclear ics Research was founded Instituteandit in Viareggio in1979.CAEN de- spin-offs theItalianNuclearPhys- of important the most CAEN isoneof W www.caen.it M [email protected] T Contact: Alessandro Iovene Italy (LU)55049 Viareggio Via Vetraia,11 +33 476473814 +33 476574617 +39 0584388398 175 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com +34 93 4137172 Barcelona Supercomputing Center (BSC) Center Supercomputing Barcelona II 29 (Nexus Building) Girona Jordi 08034 Barcelona Spain Quiñones Eduardo Contact: T M [email protected] W www.class-project.eu to help big framework architecture software CLASSnovel a aims to develop data analytics distributing workloads alongto efficiently developers thedata way, edge and (from to cloud)transparent in a complete continuum compute This ability opens the door to guarantees. sound real-time while providing to providing them superior systems, real-time critical into the use of big data analyticsdata and autonomous capabilities intelligent to implement more applications. control on a real The capabilities of will be demonstrated the CLASS framework sensor a heavy featuring smart-city use case in the City of Modena (Italy), and three a wide urban area, across data to collectinfrastructure real-time and sensors/actuators equipped with heterogeneous vehicles connected V2X connectivity to enhance the driving experience. Horizon Union’s The CLASSthe European funding from project has received No agreement under the grant programme and innovation 2020 research 780622 CLASS. Edge and Cloud Computation: A Computation: and Cloud Edge CLASS. for Big Data Software Distributed Highly Analytics 176 COMPANY PROFILES COMPANY EP 2

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI Booth 6 www.date-conference.com COMPANY PROFILES Cobham Gaisler AB Data Communication •NetworkingSecurity Telecommunication IP:Application-Specific Test IP •On-ChipDebugProcessor Platformsnect •Synthesizable Libraries • •On-ChipBusIntercon &Controllers IP CPUs •Memory - IP •Encryption Semiconductor IP: FPGA &Reconfigurable Platforms •Development Boards Hardware: Compilers •Real Time Operating Systems •Software/Modelling Embedded Software Development: Design Consultancy Services: System Test Test: ing systems, bothcommercial andfree open-source. simulators, set sisting ofinstruction tools, debug compilers andoperat coreThe IP offering is complemented byasoftware infrastructure con- and otherlessconstrained environments. is complete suitablefor andperfectly complex SoCdesigninresearch index.php/products/ipcores/soclibrary. The open-source version ofGRLIB been distributedasfree open-source, available from http://gaisler.com/ One outstanding featurethe IP-core also has always of library it that is forward. technologies,ASIC makingsystem implementation quick and straight- integrationtechnology EDA target fortool and many existing FPGA and integration inexisting designs, designenvironment providesthe GRLIB Besidesoffering IP flexible set. cores stand-alone instruction ported for tecture (IEEE-1754),the LEONprocessor offers trulyopenandwellsup a count andlowpowerconsumption.the SPARC Implementing V8 archi- combines high and performance an advanced architecture with low gate are highlyconfigurable, andare suitable for SoCdesigns. The processor coreshundred IP (GRLIB). coresThe LEONprocessorthe library and ofIP with a full development environment and a library of well over one The keythe LEON synthesizable is processortogether product model radiation- hardened components forthe spacemarket. highly competitive application-specific SoCdesigns, aswellproviding tools. Our solutions help companies and research institutes develop sor cores, cores peripheral IP andassociated software anddevelopment Gaisler's productsofuser-customizable consist SPARC 32-bit V8 proces- vanced applicationsthe commercial in domain. andspaceflight Cobham Cobham GaislerABisaprovider (SoC)solutionsfor ad- ofsystem-on-chip W www.cobham.com/gaisler M [email protected] T Contact: ChristianSayer Sweden 41119 Goteborg Kungsgatan 12 +46 317758650 177 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com +49 231 7556033 TU DortmundTU University 44221 Dortmund Germany Morik Katharina Contact: T M [email protected] W http://sfb876.tu-dortmund.de/ CRC brings 876) (SFB 876 center together the research collaborative The statistics) machine learning, mining, (data analysis of data areas research and systems) systems,embedded and embedded systems (cyber-physical dynamic data distributed, from expands them such that information The on site. in real-time, decision processes for available masses becomes in biomedicine, of high-throughput experiments acquisition and storage the exceeds or particle-physical experiments telescopes astrophysical so that the analysis must be pushed to computers, capacity of today’s processes the analysis of production Also, to the sensor. i.e., the edge, for a better that leads or of to directthe prediction traffic interventions atmobility management benefit would least from a partial analysis di- - re data streaming distributed, The analysis of at sources. rectly the data account the resource into that take and models, algorithms novel quires out at we pointed Already the startrestrictions. that data our CRC of 876, platforms. on diverse analysis should inspect closely its execution more betweenrelation the demands of as the constraints resource defined We or device. and the analysing big data technical capabilities of a platform project.the DFG has been funding the major research In Since 2011, years. a further four for 2019 the CRC 876 funding has been guaranteed Sta- Computer Science, TU Dortmund: faculties of the five are Involved Mechanical Technology, Electricaland Information Engineering tistics, DortmundTU is working together with the The engineering and Physics. as well as Hospital Essen, the University of Duisburg-Essen, University Analytical e.V. Institute for Sciences -ISAS with the Leibniz- ASIC and SOC Design: & Optimisation Power Design: System-Level Co-Design • Hardware/Software & Emulation Acceleration Services: Training • Management and Collaboration • Data Prototyping Development: Embedded Software - Debuggers• Software/Mod • Systems Operating Time Real • Compilers elling Collaborative Research Center SFB 876 – SFB Center Research Collaborative by Resource- Information Providing Analysis Data Constrained 178 COMPANY PROFILES COMPANY Booth 17

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI ???Booth 18 www.date-conference.com COMPANY PROFILES On-The-Fly Computing Collaborative ResearchCentre 901– FPGA &Reconfigurable Platforms Hardware: Hardware/Software Co-Design System-Level Design: Verification ASIC andSOCDesign: those centers. by geneous OTF Compute Centersthe provision and ofconfigured services the stabilityandsecurity of markets,the organization ofhighlyhetero- ronments for on-the-fly computing andis concerned withquestionsof area Project C develops IT services. high-quality reliable execution envi- configurations andservice services on-the-fly aiming developmentat of tigates processesthe modeling, of composition and quality analysis of the markets. area in Project Binvesthe participants - to direct in order ticular and,the otherhand, on economic concepts for incentive systems izing large networks ingeneralthe interaction and innetworks inpar markets. This involves,the onehand, on algorithmicprocesses for organ- the algorithmicandeconomicwith basicsfor organizing large dynamic 901 is divided intoCRC four areas. area project Project A is concerned interaction indynamicallychangingmarkets.the participants of developmentoriented further ofmarkets,the to support andmethods clientsprotection ofparticipating andproviders,target- methodsforthe Centers,this involves developing methodsfor qualityassurancethe and special OTF providersthe provision service OTF and byso-called Compute are availablethe configuration onworld-widemarkets.Into addition by ration that ofbaseservices andprovision out ofindividualITservices to developtechniques andprocesses for automatic on-the-fly configu- 901–On-The-FlyThe objective ofCRC Computing (OTF Computing) –is W https://sfb901.uni-paderborn.de/ M [email protected] T Contact:Tobias Wiersema Germany 33098 Paderborn Warburger Str. 100 +49 5251604343 179 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com +39 055 29881 +39 055 2988122 P.zza Madonna degli Aldobrandini, 8 Aldobrandini, Madonna degli P.zza 50123 Florence Italy Marta Pieralli Contact: T F M [email protected] W www.conventionbureau.it Bu- Visitors and Convention Florence Destination since 1995, Operating with the mission to increase promoter, is the official destination reau weddings and luxury destination quality and importance of events, nearly 300 members, to have is proud Our company in Florence. market together and this, destination of the the top-qualityoffer representing allowed us with partnershipthe official Municipality, with the Florence to open clients. our the doors of the city for is heading for CVB Florence of Destination The activity of promotion markets. weddings and leisure destination M.I.C.E., is to Bureau, Convention called Firenze division, The aim of the M.I.C.E. to be conferences quality and importance of events, quantity, increase finding and suggesting the best thanks rates services and held in the city, to supportthe expert of our partners. corporate, FCBfor services offers and independent planners in order meeting to supportassociations - as well as in planning and produc selectionthem on process the venue events. and exhibitions conventions, incentives, meetings, successful ing including: about the city, of information a wide range FCB can provide such suppliers of local lists facilities, and transportation accommodation Management Destination (PCO), Organizers Congress Professional as inter hotels and party service suppliers such as AV, (DMC), Companies pretation services, sightseeing companies, unique venues and tourist unique venues companies, sightseeing services, pretation stand contractors. resources, Destination Florence Convention and Convention Florence Destination Bureau Visitors 180 COMPANY PROFILES COMPANY or Spons

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI Booth 8 www.date-conference.com COMPANY PROFILES for Future Hardware DFG SPP2037–Scalable Data Management ern andheterogeneous hardware aswellsystem-level services. mechanisms for emerging applications,the features andexploit ofmod- tensibility regarding new data models including processing and access flexible techniqueswhichprovide andscalabledata management ex the development andevaluation ofarchitectures andabstractions for the scientific questions theseissues.Asa to related result, we expect architectures. Thus,the priorityprogrammethe objective of to answer is becomes now, necessary it to fundamentally rethink current database together withexploitingthepotential offuture hardware generations the exemplarilyto open up In order mentioned application domains as wellhigh-speednetworks provide newopportunities. sors like GPUandFPGA, novel storagetechnologies like NVRAM andSSD current andfuture hardwaretrends suchasmany-core CPUs, co-proces - masteredtime the by same massive At scalability and online processing. volume andvelocity ofdata causedbyubiquitoussensorshaveto be formancethe requirements; shouldbeadaptableaccordingto the and be integrated; consistency guarantees whichreduce flexibility andper are requires; novel data modelsforthese application domainshave to ties: From auser’s perspective flexible domain-specificaccess interfaces such as eSciences, 4.0, Industry of Internet Things or Digital Humani- emerging application wellpreparedsystems are domains to support not the currentlythe observation based on that useddatabase concepts and and comprises 10projects from german universities. The programme is Hardware“the german research is funded by funding organization DFG The priorityprogramme 2037 „Scalable Data for Management Future W www.dfg-spp2037.de/ M [email protected] F T Contact: Kai-Uwe Sattler Germany 98684 Ilmenau PO Box 100565 ofComputerTU ScienceandAutomation Ilmenau/Department +49 3677694541 +49 3677694577 181 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com +34 93 4137172 Barcelona Supercomputing Center (BSC) Center Supercomputing Barcelona II 29 (Nexus Building) Girona Jordi 08034 Barcelona Spain Quiñones Eduardo Contact: T M [email protected] W www.elastic-project.eu - to distribute resourc architecture software a novel will produce ELASTIC a new of includes development the software The edge cloud. to from es ensuring smooth performancethe compute across concept of elasticity, The project environment. fog-computing in an innovative continuum analyticsextreme- aims the data increase of capabilities to significantly re- while fulfilling multiple non-functional workloads, scale big-data security and unstable energy efficiency, time, including real quirements, communications. a sensor network deploying smart-mobility includes a use case, ELASTIC The trams (Italy). to collect network of Florence from the tram the data - hetero connectivity, V21 architectures, embedded advanced feature will public/private improving access sensors and geneous resources, cloud to driving as- of advanced and allowing transportthe creation interaction sistance applications. Ho- Union’s funding from the European project has received The ELASTIC - agree under the grant programme and innovation 2020 research rizon ment No 825473 ELASTIC. A Software Architecture for Architecture A Software ELASTIC. in Fog Analytics Big-Data Extreme-Scale Ecosystems Computing 182 COMPANY PROFILES COMPANY EP 2

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI ???Booth 20 www.date-conference.com COMPANY PROFILES Embedded Systems Initiative (ESI) Design Consultancy •Prototyping Services: The ESIApplication Centre offers: ics arethe ESIApplication bundledin Centrethree in Labs: the complexityter offuture research andinnovations. Ourresearchtop the FAUof andappliedresearchthe Fraunhofer knowledgeof to mas- IIS search. The ESIApplication Centre buildsabridgebetweenbasicresearch Integrated iswell-knownfor Circuits itsknowledgeinappliedre (IIS) - cessfully developed embeddedsystems. The Fraunhofer Institutefor Along withbasicresearch, practicalto suc- userknowledgeisessential the EmdeddedSystemsNürnberg in Domain. eration betweencompanies andresearchthe FAU institutesof Erlangen- of various asacentral ESIfunctions sectors. for ofcontact point coop to offering diverse in andspecial cooperationexpertise with companies companies andresearchthe FAU institutesof Erlangen-Nürnberg, allow asacentral ESIfunctions berg. for ofcontact point cooperation between the Friedrich-Alexander-Universität of 15 departments Erlangen-Nürn- related inallaspects to embeddedsystemsdesignofcurrentlyexpertise The Interdisciplinary Centre for Embedded Systems (ESI) combinesthe W www.esi-anwendungszentrum.de M [email protected] F T Contact: TorstenKlie Germany 91058 Erlangen Martensstraße 3 Interdisziplinäres Zentrum fürEingebetteteSysteme (ESI) Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) • • • • • • • Scientific know-how the especiallyin following areas: search projects aswelleffective cooperations Many years ofresearch experience andsuccessfullyconcluded re- ded Systems accordingto your specifications development,Independent evaluation andimplementation ofEmbed- Interdisciplinary solutionsfocused onyour needs Fitness@ESI (wirelesstraining sensorsand assistence) Automotive@ESI (Sensorsanddriver assistencesystems) Automation@ESI (IndustrialAutomation, 4.0) Industry • Sensors Integrated • • • Systems Multicore • +49 91318525144 +49 91318525151

Wireless Communication andLocalisation Machine Learning, Pattern AnalysisandImageData Processing Design Methods, especiallyHardware-Software-Co-Design / 183 - - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com +32 16 281272 +32 9 2643373 structure a the HPCby adding members to develop community To high-quality cross- that engages in focused of excellence community stack activity. pipeline an innovation building by entrepreneurship promote To prototyping, business training, purpose entrepreneurial general from at a look Take funding. and helping with plan development business calendar. our events with other by connecting technol- stimulate technology transfer To seed funding for competitive activities and providing ogy transfer New open calls in 2019! HPC technology transfer. resources substantial by investing news community disseminate To Eurolab4HPC brand. a stronger creating activities, in dissemination EUROPRACTICE Center IC office & IC Manufacturing EUROPRACTICE imec p.a. 75 Kapeldreef 3001 Leuven Belgium Malisse Paul Contact: T M [email protected] W www.europractice-ic.com in 1989 to Commission launched by the European was EUROPRACTICE by markets world in position competitive their improve companies help in solutions their Microsystems or Module Multi-Chip ASIC, adopting and costs risks helps the perceived to reduce The program products. range users a with potential associated these technologies by offering entry reduced support, advice and ongoing initial including of services, and product supply. to chip manufacture a clear route and costs has bridged EUROPRACTICE the gap between academ- Since its creation, - than 600 Euro more ia and industry in world by offering the high-tech access to the latest institutes affordable and research pean universities reflected This is design tools and technologies. Circuits) IC (Integrated which from the best by universities IC design in provided the training in new IC products. innovation the SMEs for essential engineers emerge, industrial is European enhance to EUROPRACTICE of goal ultimate The services The EUROPRACTICE in the global marketplace. competitiveness institutes research (especially SMEs), open to industrial companies are and academic users. SMEs EUROPEAN TO OFFERED SERVICES INSTITUTIONS: AND ACADEMIC is European the of EUROPRACTICE to provide The mission statement smart develop to integrated industryplatform a with academia and The lat production. design to volume prototype advanced from systems, ter is achieved by providing affordable and easier access to a wide range and easier access to a wide affordable by providing ter is achieved and design technologies fabrication industry-grade state-of-the-art of UGENT – ELIS 9052 Gent Belgium Impe van Katrien Contact: T M [email protected] W https://www.eurolab4hpc.eu 2020 funded project to Horizon committed Eurolab4HPC is a 2-year in HPC technol- and innovation in academic research excel Europe make this goal it reach has defined 4 actions: To ogy. 1. 2. 3. 4. visitto forget eurolab4hpc.eu don’t and visit: our further information For 2019! at DATE stand here Eurolab4HPC 184 COMPANY PROFILES COMPANY Booth 3 EP 1

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com COMPANY PROFILES BY FOLLOWINGTHE CENTERS: EUROPRACTICE SERVICESTHE OFFERED ARE isalreadythat establishedfor 20yearsthe market. in expertise. all This fromyou EUROPRACTICE canget IC service, a service ing foundries, design services, and manufacturing high quality support tosiliconthe flexible access prototype lead- andproduction capacity at or high production volumes.of services Those companies will gain from those companiesalways especially who do not the full rangeports need market quicklyandcost-effectively. TheEUROPRACTICE ASIC route sup to designs to helpbringnewproduct the EUROPRACTICE using ICservice fromIndustry alloverthe world have rapidly discoveredthe benefitsof cess to design tools. duction, operations. packagingtest and Note, include ac- this does not and microsystem designservices, MPW prototyping, smallvolume pro- EUROPRACTICE alsooffers tomicroelectronic worldwideaccess industry SERVICES OFFERED TO GLOBALTHE INDUSTRY: critical stepswhichare needed. the customerinall to tools complementedtraining with andsupport • • • • • • • • • • Tyndall National Institute(Ireland) CMP (France) STFC Rutherford AppletonLaboratory (United Kingdom) ( Fraunhofer-Institut Schaltungen(Fraunhofer fürIntegrierte IIS) imec (Belgium) giesIC Training courses inadvanced designflows andon technolo- various to advanced systemintegrationAccess packaging andsmart than Moore) viaMPWruns Low-cost prototyping in varioustechnologies (bothASICandMore tools popularCADkits for the most celllibraries ofhigh-quality anddesign Distribution andfullsupport (CAD) tools Affordable toindustry-standard access andstate-of-the-art design Germany) 185 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com +33 4 38785970 technical expertise via advanced platforms, that are either innovative either innovative that are platforms, technical expertise via advanced to technical solutions or the product testbeds which add value - pro products being existing product support via industrial platforms, and embed- leaders in vided by market the domain of cyber-physical of maturity to a state which can bring the innovation ded systems, - innova your help to business, on focusing management, innovation tion get to via consortiumthe market and the FED4SAE the Smart ecosystem Anything Everywhere budget 70% of the declared representing up to €60,000 in funding, of the work done • • • • CEA/ DER/ Leti/ DACLE/ SSCPCEA/ DACLE/ DER/ Leti/ 17 rue des Martyrs - Cedex 38054 Grenoble France Dor Isabelle Contact: T M [email protected] W https://fed4sae.eu - Com the European Through the Smart initiative, Anything Everywhere is part FED4SAE of this industry. European mission is helping digitize small/ (startups, companies ‘small’ network of a large targeting strategy, including both technology special- and midcaps), medium enterprises request can solutions for These companies companies. ists and low-tech platforms industrial and advanced which FED4SAE’s specific use cases, - compo one of several will include solutions comprising This will provide. technology and actuators. fusion/processing data such as sensors, nents, which link - the physi systems, up cyber-physical make These components cal and digital worlds. - provid management, participants also helps with innovation FED4SAE networking and opportunities to identify ing coaching for - the best stake business angels, initiatives, national/regional investors, holders – private and so on. customers, potential companies: offers FED4SAE In summary, smart any which will be funded will address The kind of experiments sensor, industry, & well-being, health city, (mobility, domain application supported by platforms and industrial advanced both involving etc.), allowing the awarded shall be pan-European, The experiments FED4SAE. and in- platforms advanced with cross-border to collaborate company dustrial partners. just get need we will help you the idea and itto provide – to market You miss don’t this opportunity! FED4SAE 186 COMPANY PROFILES COMPANY EP 3

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Registration Opens and Conference Program Live April 3, 2019 DAC.COM #56DAC - - www.date-conference.com +32 9 2643379 +81 42 3465510 HiPEAC 126 Technologiepark-Zwijnaarde UGENT – ELIS 9052 Gent Belgium Wandels Vicky Contact: T M [email protected] W www.hipeac.net and Embedded Architecture (High Performance the HiPEAC Since 2004, researchers European a hub for project has provided and Compilation) biggestthe in kind its of the network, its systems; today, computing in members include both HiPEAC specialists. 2000 numbers around world, who want to shape top-class and industry representatives researchers systems. Members benefit a series of computing from the development peer- and recruitment training, industryincluding insight, advantages, of to-peer interaction. confer the HiPEAC per year: networking events four organizes HiPEAC HiPEAC - European Network on High - European Network HiPEAC Architecture and Embedded Performance and Compilation part As school. summer a and of Weeks Systems Computing two ence, to can also contribute HiPEAC the biennial you community, the HiPEAC technology European re- informs roadmap which influential an Vision, sup mobility projectthe training, offers addition, In areas. policy search and dissemination candidates computing excellent finding in help port, support. 1 December began on 5, HiPEAC of latestThe project, the incarnation It is funded led by Ghent University. by 13 partners, 2017 and is delivered - pro and innovation 2020 research Horizon by Union’s the European 779656. no. agreement grant under gramme email [email protected]. free join for To - visit furtherhttps://www.hipeac.net/network/#/indus information For 2019! to visit forget attry/ DATE and don’t our stand here Floadia Tokyo HQ Floadia Tokyo Kodaira-shi Higashi-cho, 1-30-9 Ogawa 187-0031 Tokyo, Japan T M [email protected] W www.floadia.com Easily and cost Effective power, Low provides Japanese company, Floadia, Memory world-class are experts in Non-Volatile We embedded Flash IPs. and costour testEnjoy effective production. and QA design, technology, - applica Automotive and AI, IoT, your for solutions eNVM quality high tions. IP:Semiconductor • Memory IP Signal IPAnalogue & Mixed • CPUs & Controllers Application-Specific IP: Signal IPAnalogue & Mixed Floadia Corporation Floadia 188 COMPANY PROFILES COMPANY EP 1 Booth 12

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI ad_mentor_training_100x210mm.pdf 4 30.01.2019 18:23:28

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K - www.date-conference.com +43 5 177719202 Infineon Technologies Austria AG Austria Technologies Infineon 2 Siemensstraße 9500 Villach Austria Simone Fontanesi Contact: T M [email protected] W www.infineon.com subsidiary Infineon of group a is AG Austria Technologies Infineon solutions of semiconductor a worldleading provider AG, Technologies Infineon from Microelectronics and greener. safer easier, life that make domestic ap electronics, of consumer the energyreduce consumption to a major contribution the make They pliances and industrial facilities. and enable secure and sustainability of vehicles, security convenience, Things. in transactions the Internet of Austria is Infineon the only subsidiary within the group Besides Germany, as well production and development, research for that pools competencies with further Villach, The head office is in as global business responsibility. from 4,201 employees With Vienna. Linz and Klagenfurt, in Graz, branches in the and development), (including 1,813 in research 60 countries around a turno- achieved company year 2018 (ending in September) the financial Infineon of €498 million makes rate of € 2.9 billion. An R&D expense ver in Austria. companys’ one of Austria the strongest industrial research at www.infineon.com/austria Further information ASIC and SOC Design: • Analogue and Verification Signal) • Themal, Analysis (Timing, Physical • MEMS Design • RF Design Design Mixed-Signal Design: System-Level Co-Design Analysis • Hardware/Software Physical Test: Test • Mixed-Signal BIST) (ATPG, Automation Test • Test Design for Development: Embedded Software Software/Modelling IP:Semiconductor • Embedded Software Signal IPAnalogue & Mixed • CPUs & Controllers IO Verification IP • Test IP • Application-Specific IP: Tele IPSignal • Security • Mixed & Analogue Processing Signal Digital • Communication Wireless • communication Contact: Kartik Patel Kartik Contact: M [email protected] W www.ieee-ceda.org established to was (CEDA) Design Automation on Electronic The Council at and systems all levels. circuits of electronic design automation foster and use implementation, spans field of interest the theory, The Council’s and systems. circuits electronic tools integrated to design of EDA/CAD and analysis, of includes This the design, tools levels all that automate up to and including software and embedded of hardware verification of technical in- enables the exchange working systems. CEDA complete and and workshops conferences by sponsoring publications, formation activities. volunteers local chapters for through please contact [email protected] or check our interested are If you about our activities a and how information to become more website for free. member for IEEE Council Design Electronic on (IEEE CEDA) Automation 190 COMPANY PROFILES COMPANY Booth 14 or Spons

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI Booth 11 Booth 13 www.date-conference.com COMPANY PROFILES IngeniArs S.r.l. about Intel newsroom.intel.com at about andintel.com. inbetween.Findthe edgeandeverything to morenetwork information the infrastructureto the smart, connected world–fromthe cloud of as wellhelpingsecure,the billions ofdevices and powerand connect ishelpingaddressthe world’sengineering expertise greatest challenges the foundation is that the world’s of ogy innovations. The company’s the data-centric future withcomputing andcommunicationstechnol- Intel (NASDAQ: INTC),the semiconductor industry, aleaderin isshaping W www.intel.com M [email protected] Contact: Jonathan AhSue Germany 85579 Neubiberg Am Campeon 10-12 Intel rity • Telecommunication Data Communication •DigitalSignalProcessing •NetworkingSecu- IP:Application-Specific Synthesizablenect • Libraries • Test IP • On-Chip Bus Intercon ded IP Software • Memory - IP • Encryption IP ConfigurableCPUs & IP • Controllers Logic •EmbeddedFPGA •Embed- Semiconductor IP: FPGA &Reconfigurable Platforms Hardware: Design Consultancy •Prototyping Services: Design for Test •System Test Test: ware/Software Co-Design Behavioural Modelling&Analysis•Acceleration &Emulation •Hard- System-Level Design: & Optimisation •Physical Analysis(Timing, Themal, • Signal) Verification Design Entry •Behavioural Modelling&Simulation •Synthesis •Power ASIC andSOCDesign: the EUHorizon Phase1and2projects. ning 2020SMEInstrument achievements, suchasobtainingprimecontractsthe ESA andwin- with electronics andembeddedsystems.IngeniArsalready hasseveral major softwarethe fulllifecycle products andmanaging ofelectronics, micro- healthcare andautomotive fields, offering highlyadvanced hardware/ ever-increasing demandfor innovationthe strategic in aerospace, computer science engineering research. The companythe respondsto founders’ extensivethe areas experience in ofelectronics andadvanced Innovative IngeniArs Italian was ofits start-up joint born in 2014 out W www.ingeniars.com M [email protected] T Contact: Camilla Giunti Italy 56121 Pisa via Ponte aPiglieri 8 +39 0506220532 191

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com +49 9131 8525153 +49 9131 8525149 Invasive Computing - CRC/Transregio 89 - CRC/Transregio Computing Invasive (FAU) Erlangen-Nürnberg Friedrich-Alexander-Universität (InvasIC) Rechnen Invasives 89: SFB/Transregio für Informatik Lehrstuhl (Hardware-Software-Co-Design) 11 Cauerstraße 91058 Erlangen Hannig Frank Contact: T F M [email protected] W http://www.invasic.de Computing” “Invasive Centre Research Collaborative Transregional In the Friedrich-Alexander- from the researchers scientific “InvasIC”) (abbr. as München Universität Technische the Erlangen-Nürnberg, Universität together a novel investigate Technology Institute of well as the Karlsruhe computing parallel of future the design and programming for paradigm systems. explicit handles to a programmer is characteristic unique Its give to in or required desired, requirements aboutspecify and argue resource an application command, Using an invade execution: phases of different memory instruct system may to claim a set of processors, the operating sub default, by a, for allocated being for resources communication and sequent exclusive use. In an infect phase, the application workload is workload application the use. infectan In phase, sequent exclusive A retreat on the obtained claim of resources. and executed then spread resume may and application the again, claim a frees finally command and resource- support of self-adaptive this idea To execution. sequential languages, concepts, programming not only novel programming, aware from had to be developed system concepts and operating compilers, changes in the design of architectural but also revolutionary scratch, system-on-a-chip) (multiprocessor including mechanisms MPSoCs to alon demand. resources and isolate locate 89 on www.invasic.de. out about more Find the CRC/Transregio ASIC and SOC Design: Verification • Optimisation & Power • Simulation & Modelling Behavioural Design: System-Level - • Hard & Emulation Modelling & Analysis • Acceleration Behavioural Co-Design ware/Software Test: Test System Development: Embedded Software • Software/Modelling Compilers Hardware: Platforms & Reconfigurable FPGA IP:Semiconductor Platforms • Processor • On-Chip Bus Interconnect CPUs & Controllers 192 COMPANY PROFILES COMPANY Booth 20

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI Booth 5 www.date-conference.com COMPANY PROFILES Design Consultancy • Training Services: System Test Test: Behavioural Modelling&Analysis•Hardware/Software Co-Design System-Level Design: Mixed-Signal Design Design•RF Behavioural Modelling&Simulation • Verification •Analogueand ASIC andSOCDesign: rangetechnical disciplines. of the worlduseMATLAB andSimulinkforteaching andresearch inabroad and medical devices. Morethan 5000 colleges and universities around communications andotherelectronics equipment, industrialmachinery, cluding automotive systems, aerospace flight control and avionics, tele- the designanddevelopment ofawiderange ofadvanced products, in- andcomputationalcial services biology. MATLAB andSimulinkenable modeling andsimulation inincreasinglytechnical fields, suchasfinan- tools forfundamental research anddevelopment. They are alsousedfor communications, electronics, andindustrialautomation industriesas MATLABthe automotive, andSimulinkarethroughout used aerospace, code generation.HDL taskscialized such as deep learning, computer vision, robotics, and C systems. The company produces nearly100additionalproducts for spe- tion andModel-BasedDesignofmultidomaindynamicembedded numeric computation. Simulink®is a graphical environment for simula- vironment for algorithmdevelopment, data analysis, visualization, and MATLAB®,technical computing,the language of is a programming en- atethe paceofdiscovery, innovation, anddevelopment. ware. Engineersandscientists worldwiderelyto acceler onitsproducts MathWorksthe leadingdeveloper is ofmathematical computing soft W www.mathworks.com United States 3 AppleHillDrive Natick, MA MathWorks 193 - -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com +49 89 57096131 Mentor, A Siemens Business A Siemens Mentor, Europe Marketing Ernst, Astrid Contact: T M [email protected] W www.mentor.com hardware in electronic is a world leader Business, a Siemens Mentor, services consulting products, providing design solutions, and software most electronic, successful support award-winning and the world’s for to develop enable companies We systems companies. and semiconductor - Our innova cost-effectively. and more faster products better electronic is design challenges. Mentor technol- complex help conquer products tive Design-for-Test Verification, Functional ogyfull chip emulation, leader in Calibre® and Tessent® Questa®, Veloce®, with its verification and physical management product lifecycle now part is Mentor of Siemens’ platforms. the world’s organization making the combined business, (PLM) software simula- product design, used for software leading supplier of industrial Visit www.mentor.com testing and manufacturing. verification, tion, ASIC and SOC Design: Design • Analogue and Mixed-Signal Verification • Design Entry Design: System-Level • PCB & MCM Design & Emulation Acceleration Test: Design Test for Development: Embedded Software Systems Operating Time • Real Compilers 194 COMPANY PROFILES COMPANY or Spons Booth 19

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI Booth 16 www.date-conference.com COMPANY PROFILES Security • Telecommunication • Wireless Communication •DigitalSignalProcessingAnalogue &Mixed •Networking SignalIP IP:Application-Specific •On-ChipDebug IP Memory Test • IP Verification IO •EmbeddedFPGAAnalogue &Mixed •EmbeddedSoftware SignalIP IP • Semiconductor IP: & ITInfrastructure FPGA &Reconfigurable Platforms •Development Boards • Workstations Hardware: • Trainingtion Design Consultancy • Prototyping •Data andCollabora Management - Services: Mixed-Signal TestSystem Test• Design for Test • Test Automation (ATPG, BIST) •Silicon Validation • Test: &MCMDesign PCB System-Level Design: tion • AnalogueandMixed-Signal Design Design•MEMSRF & Optimisation •Physical Analysis(Timing, Themal, • Signal) Verifica- Design Entry •Behavioural Modelling&Simulation •Synthesis •Power ASIC andSOCDesign: includes: of products andservices After itsfoundation house,test in1998 as a portfoliotoday the Microtest vanced electronic andmicroelectronic solutionsfor various applications. ability, for isareliable globalsupplierandpartner companies seekingad- Microtest, combining innovation, continuous improvement, andsustain- W www.microtest.net M [email protected] T Contact: GiuseppinaSaracco Italy 55011 Altopascio(LU) Via dellaGaleotta9/A S.r.l.Microtest Microtest • • • • APPLICATION BOARD TURN-KEY SOLUTIONS DESIGNHOUSE MICROELECTRONIC TEST HOUSE& TEST PROGRAM DEVELOPMENT ATE DESIGN&MANUFACTURING +39 0583269651 195

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - - www.date-conference.com Department Engineering of Computer /

+31 6 28802494 MNEMOSENE UniversiteitDelft Technische Mekelweg 4 Mekelweg 2628CD Delft Netherlands Hamdioui Said Contact: T M [email protected] W www.mnemosene.eu - Action address and Innovation MNEMOSENE is an ambitious Research to scale functional of new approaches per “Development ing the theme formance of information processing and storage substantially beyond beyond substantially storage and processing information of formance power and ultra-low on a focus technologies with the state-of-the-art 2020 ICT research Horizon Union’s of the European high performance” programme. and innovation demonstration and design MNEMOSENEon development, the focus will ar based on extending architecture (CIM) of a Computation-In-Memory logic with (memristors) devices switching resistive of non-volatile rays - inte allow CIM architectures functionalityarray. cell the around or inside at loca- the same physical and storage processing of information gration mem- and the communication eliminate the potential having to (a) tion, (b) support overall the to increase parallelism massive ory bottleneck, be cheaper (d) and energyenhance efficiency, (c) drastically performance, computing innovative of such a radically Development to manufacture. enabling the solution of many breakthrough, a real will be architecture en- at affordable than days rather in minutes problems computational in performance. of magnitude increase in orders resulting ergy and cost, the project consortium (NL), University Technical by Delft Coordinated Eindhoven countries: includes eight other partners six different from and IBM Research – Zurich ETH and IMEC (NL), Technology of University INRIA- (DE), (FR) and Intel Aachen University RWTH (UK), Arm (CH), Zurich (LU). Consultants ligentsia The MNEMOSENE Un- the European funding from Project has received under grant programme and innovation 2020 research Horizon ion’s number 780215. agreement ASIC and SOC Design: Modelling & Simulation Behavioural Design: System-Level & Emulation Modelling & Analysis • Acceleration Behavioural Development: Embedded Software Compilers IP:Semiconductor Memory IP • On-Chip Bus Interconnect 196 COMPANY PROFILES COMPANY EP5 Booth

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI Booth 9 www.date-conference.com COMPANY PROFILES Digital SignalProcessing •Security IP:Application-Specific FPGA &Reconfigurable Platforms Hardware: Embedded FPGA •EmbeddedSoftware IP Semiconductor IP: Real Time Operating Systems •Software/Modelling Embedded Software Development: Design for Test •System Test Test: Hardware/Software Co-Design System-Level Design: Verification ASIC andSOCDesign: Systems Design. lifethe Friday of demonstration DATE as part Workshop onAutonomous vehicles co-operating trust. pairwillalsogiveThe robot underlimited a for operation undervarying radiation stress, andasimulated group of orating pairwithdynamichardware mobilerobot self-reconfiguration contract-based integration andmonitoringofcriticalfunctions, acollab an autonomousroad vehicle controlled byself-managed software with lustratethe research approach andresults. The demonstrators include tures, methodsandmainachievements. Various demonstrators willil- the DATEDuring Conference 2019,the architec- posters will highlight the Researchtalk summarizing activities. clude a Unit mous platforms for spacerobotics. The DATE specialsession3.8willin- and self-awareness. Applications are vehicle automation andautono- cations usingself-adaptation withself-protection basedoncontracting group of8PIshasinvestigated automated integration ofcriticalappli- and hardware reconfigurations. theGermanDFG, from With support a tonomous systemswhichshallindependently managesoftware updates interferencefunction the designprocess, challenges inau- inparticular cality networked systems withnumerous shared resources. The resulting have moved from isolated componentsto highlyintegrated mixed criti- Embedded systemsfor safety criticalandhighavailability applications W www.ccc-project.org M [email protected] T Contact: Rolf Ernst Germany 38106 Braunschweig Hans-Sommer-Straße 66 Institute ofComputer andNetworkEngineering Automotive AndSpaceVehicles Concurrent Change –Towards Self-Aware Research Unit: FOR1800Controlling +49 5313913730 197 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com Fakultät für Informatik Fakultät / +49 30 3030807710 SPP1648 Software for Exascale Computing Computing for Exascale SPP1648 Software (SPPEXA) München Universität Technische 3 Boltzmannstraße 85748 Garching Germany Bungartz Hans-Joachim Contact: M [email protected] W www.sppexa.de of (SPPEXA) Computing" Exascale for "Software The Priority Programme research fundamental addresses (DFG) Foundation the German Research which is particularly urgent aspects of HPCon the various software, of ubiquitous era the entered against thathave we background the started in SPPEXA in 2013 and is implemented two parallelism. massive with 17 project consortiathan 40 and more phases, funding three-year institutions involved. the road to pave initiatives has joined national the other Thus,SPPEXA computing. exascale towards ASIC and SOC Design: Verification • & Optimisation Power Design: System-Level Co-Design Hardware/Software Test: Test System Services: Training Development: Embedded Software • Software/Modelling Compilers Hardware: Platforms Reconfigurable & FPGA Application-Specific IP: • Networking Communication Data SEMI SEMI Europe 2-9 Helmholtzstr. 10587 Berlin Germany Melvin Cassandra Contact: T M [email protected] W http://www1.semi.org/eu/ - profes million 1.3 and companies member 2,000 over connects SEMI® the sionals worldwide technologyto advance - of electron and business in the innovations for responsible ics manufacturing. SEMI members are and services that enable devices, software, equipment, design, materials, - prod electronic affordable and more powerful, more faster, smarter, and the MEMS & Sensors Alliance (FOA) Owners the Fab ucts. FlexTech, defined Partners, Association SEMI Strategic (MSIG) are Industry Group on specific 1970, technologies. Since within SEMI focused communities create SEMI has built helped its members prosper, connections that have SEMI industry challenges common together. and address new markets, Seoul, Hsinchu, Grenoble, Brussels, Berlin, offices in Bangalore, maintains - Washing and Tokyo, Singapore, Calif.), (Milpitas, Valley Silicon Shanghai, SEMI on and follow visit www.semi.org information, more For D.C. ton, LinkedIn and Twitter. 198 COMPANY PROFILES COMPANY artner Media Booth 10 P Booth 7

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI Sponsor Booth 15 Booth 4 www.date-conference.com COMPANY PROFILES high-quality, secure products. Learn more www.synopsys.com. at rity and quality, Synopsysto deliverthe solutions needed innovative, has software developer secu- require writingapplicationsthat the highest (SoC)designercreatingsystem-on-chip advanced semiconductors, ora leadership insoftware securityandqualitysolutions. Whether you’re a design automation (EDA) andisalsogrowing its andsemiconductor IP pany, Synopsys ofbeingagloballeaderinelectronic hasalonghistory plications we rely on every day.the world’s As software 15th largest com- novative companies developingthe electronic products and software ap Synopsys,the Siliconto Software (Nasdaq: is SNPS) Inc. W www.synopsys.com Synopsys solution for RISC-V cores. Symbiotic EDAthe onlyprovider formal is ofanend-to-end verification bugs within VHDL, Verilog, orSystemVerilog designs. tofind to findandfix hard verification necessary tools theeffort reduces proving safety. digitaldesignproductivity andfunctional Their formal Symbiotic EDA providestraining, software for services im- andsupport W symbioticeda.com M [email protected] T Contact: Edmund Humenberger Austria 1100 Wien Alaudagasse 11/107/6 Symbiotic EDA Director ([email protected]). to discussyour bookwithCharlesGlaser, next Springer exhibit Editorial the Please the attend Publisher Sessionandvisit their publishingeffort. authors individualized, relationships, expert the lifecycle throughout of globally, ourauthors’ workhasunparalleled, globalreach. We offer our accessed bymorethan 15,000academicandcorporate institutions research monographs, andmajorreference works. SinceSpringerlinkis cludes a variety of contenttypes, textbooks, including professional books, and avariety ofretail outlets, e.g., amazon.com. Ourbookpublishingin- knownasSpringerlink,online portal viaspringer.com aswellin-print year andover 3,000journals.Ourcontent isdistributedglobally, viaour technical bookandjournalcontent, includingovertitles per 12,000 book in over 50countries. Springerpublishesawidevariety ofscientific and ofSpringerNature,Springer ispart whichhasover 13,000employees W www.springernature.com M [email protected] T Sabine TrollmannContact: Germany 69121 Heidelberg Tiergartenstr. 17 NatureSpringer +43 69912301240 +49 6117878204 ™ partner for partner in- 199 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 - www.date-conference.com +49 511 76219686 (Andreas Vörg) +49 511 76219686 (Andreas Vörg) +49 511 76219695 (Andreas University Booth University edacentrum 32 Schneiderberg 30167 Hannover Germany de Grenoble-Alpes TIMA/CNRS/Université Viallet Félix avenue 46, 38031 Grenoble France FR TIMA, Vatajelu, DE and Elena Ioana edacentrum, Vörg, Andreas Contact: T F M [email protected] W https://www.date-conference.com/exhibition/u-booth of academic work to industry. the Booth fosters transfer The University of free is and exhibition 2019 partis Booth University The of DATE the TETRAMAX and Technologies Communication for Institute Aachen University, RWTH ICT cubes (ICE), Embedded Systems 16 Kopernikusstr. 52074 Aachen Germany Leupers Rainer Contact: T +49 241 8028301 M [email protected] W http://www.tetramax.eu action is to build on innovation TETRAMAX The mission of the EU-funded Computing activityin lines Low-Energy three of Customized the domain (1) stimu- Things: and the Internet of Systems Cyber-Physical for (CLEC) Technology cross-border different evaluating and co-funding, lating, CLEC technologies to first-time (TTX) via innovative Experiments Transfer (2) building and lev ICT industries, in European markets users and broad eraging a new European CLEC competence center network, offering tech- offering network, center CLEC a new European competence eraging one-stop shop assistance and CLEC to SMEs training nology brokerage, Digital Innovation new regional with a clear path towards and mid-caps, self-sustainability. towards the way and (3) paving Hubs (DIH), TTX, of application calls for open of a variety of the framework Within is supportto TETRAMAX industry50+ clients of ambition immediate the leading an estimated to technologies, innovative with Europe all over CLEC-based of €25m based on 50+ new or improved increase revenue as well as 30+ new initiated, new businesses/SMEs 10+ entirely products, cost in productpermanent jobs and significant savings manufacturing. accelerate will TETRAMAX DIH Being CLEC, the leading European for TETRAMAX industries. In within European the long term, digitalization and sustainable ecosystem a reinforced will be towards the trailblazer in- services and a continuous CLEC competence, providing infrastructure, as presence regional yet with strong scale, at European stream novation by SMEs. preferred Union’s funding from the European project has received TETRAMAX The - agree grant under programme and innovation 2020 research Horizon ment number 761349. ASIC and SOC Design: & Optimisation Power Design: System-Level Co-Design Hardware/Software Services: Training • • Prototyping Design Consultancy 200 COMPANY PROFILES COMPANY Booth 1 EP 1

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com COMPANY PROFILES cation • Wireless Communication cessing • Multimedia Graphics • Networking • Security • Telecommuni- •DataAnalogue &Mixed Communication SignalIP •DigitalSignalPro- IP:Application-Specific • Processor Platforms •Synthesizable Libraries • Test • IP Verification IO •On-ChipBusInterconnect •On-ChipDebugPhysical Libraries IP ory EmbeddedFPGA •EmbeddedSoftware •Mem- IP lers • •Encryption IP • ConfigurableAnalogue & Mixed Signal IP CPUs & IP • ControlLogic - Semiconductor IP: & ITInfrastructure FPGA &Reconfigurable Platforms •Development Boards • Workstations Hardware: Compilers •Real Time Operating Systems •Software/Modelling •Debuggers Embedded Software Development: e-commerce &Exchangetion •IP •Foundry &Manufacturing • Training Design Consultancy • Prototyping •Data andCollabora Management - Services: Signal TestSystem Test• Automation (ATPG, BIST) Scan•Silicon •Boundary Validation •Mixed- Design for Test • Design for Manufacture and Yield • Logic Analysis • Test Test: MCM Design Emulation •Hardware/Software Co-Design •Package & Design•PCB Behavioural Modelling&Analysis•Physical Analysis•Acceleration & System-Level Design: tion • AnalogueandMixed-Signal Design Design•MEMSRF & Optimisation •Physical Analysis(Timing, Themal, • Signal) Verifica- Design Entry •Behavioural Modelling&Simulation •Synthesis •Power ASIC andSOCDesign: [email protected] Andreas Vörg, edacentrum GmbH, DE Elena Ioana Vatajelu, TIMA, FR The University Boothisorganizedthe University by BoothCo-Chairs ps://www.date-conference.com/exhibition/ub-programme. The finalprogramme theUniversity of Boothis available online htt at https://www.date-conference.com/exhibition/u-booth.tails at mature prototypes andpre-commercial results canfindsubmissionde- Research institutesanduniversities interested indemonstratingtheir DATE exhibition area, withinadedicatedtime slot. and software demonstrations. All demonstrationsthe will be hosted in and publicresearch institutes areto present invited innovative hardware organized for EDA software andhardware demonstrations. Universities soredthe DATE by Sponsor'sCommittee. The University Boothwillbe charge for presenterstheir visitors. and The University Boothisspon- 201 -

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 www.date-conference.com 202

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI COMMITTEES TOPIC CHAIRS www.date-conference.com CHAIRS &TOPIC COMMITTEES 203

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 ded meets ded meets

ACM / ACM EDAA / IEEE SIGDA Chair PhD Forum CEDA Johannes Robert Wille, AT Linz, University Kepler Paderborn University, DE University, Paderborn Special “Model- Day Based Design of Intelligent Co-Chair Systems” Eindhoven Sander Stuijk, NL Technology, of University Chair Tutorials Monday Platzner, Marco DE University, Paderborn Co-Chair Workshops Friday Cazorla, Francisco Supercomputing Barcelona ES and IIIA-CSIC, Center Co-Chair Workshops Friday Michael Glaß, DE Ulm University, Special Day ous “Heterogene Embed Computing: Co-Chair Hyperscale and HPC” Christoph Hagleitner, CH Zurich, IBM Research Special Day ous “Heterogene Embed Computing: Co-Chair Hyperscale and HPC” Christian Plessl, Special “Model- Day Based Design of Intelligent Co-Chair Systems” Derler, Patricia US Instruments, National Special “Model- Day Based Design of Intelligent Co-Chair Systems” Eindhoven Geilen, Marc NL Technology, of University Executive Sessions Co-Chair Sessions Executive Casale-Rossi, Marco IT Synopsys, Co-Chair Sessions Executive Micheli, De Giovanni CH EPF Lausanne, Special Sessions Co-Chair Herkersdorf, Andreas Universität Technische DE München, Special Sessions Co-Chair National Mitra, Tulika SG of Singapore, University www.date-conference.com

TIMA, / TIMA, FR Past General Chair General Past Technical Jan Madsen, DK of Denmark, University EDAA General Chair – General EDAA Chair of the DSC of University Wehn, Norbert DE Kaiserslautern, Liaison Chair – CEDA Awards Sciuto, Donatella IT di Milano, Politecnico Audit Co-Chair DE DATE, Düppe, Volker Audit Chair – Chair Finance EDAA Herman Beke, BE Photonics, LUCEDA Finance Chair Finance Müller, Wolfgang DE University, Paderborn Co-Chair Finance Marian Verhelst, BE – MICAS, ESAT KU Leuven – Track A – Application A – Application Track Design Chair Institute Lyon Ian O’Connor, FR of Nanotechnology, E – Embedded and Track Chair Systems Cyber-physical Bertacco, Valeria US of Michigan, University Programme Chair – Programme D – Design, Track Chair Tools Methods and Fummi, Franco IT Verona, di Università Chair – Programme Vice T and – Test Track Dependability Cristiana Bolchini, IT di Milano, Politecnico Vice General Chair – General Vice Chair Proceedings Di Natale, Giorgio CNRS General Chair General Friedrich- Teich, Jürgen Alexander-Universität DE Erlangen-Nürnberg, 204 DATE EXECUTIVE COMMITTEE EXECUTIVE DATE

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com DATE EXECUTIVE COMMITTEE edacentrum GmbH, DE TIMA, FR Ioana Vatajelu,Elena University BoothCo-Chair University ofPisa, IT Luca Fanucci, and ICTCo-Chair Local Arrangement Exhibition Chair– edacentrum GmbH, DE Jürgen Haase, Chair Exhibition Theatre University Frankfurt, DE Jano Gebelein, Goethe- Chair Audio Visual INL, FR Bosio,Alberto Review Chair Kaiserslautern, DE Norbert Wehn, University of the DSC Chair of EDAA Chairand a, TIMA Laboratory, FR Presentations Chair Interactive Erlangen-Nürnberg, DE Alexander-Universität Frank Hannig, Friedrich- and ICTCo-Chair Local Arrangement University ofDenmark, DK Schoeberl, TechnicalMartin European ProjectsChair Andreas Voerg, University BoothCo-Chair Institute of Technology, DE Jörg Henkel, Karlsruhe Liaison ACM /SIGDA Politecnico diMilano, IT Donatella Sciuto, Council onEDAIEEE

GmbH Dresden, DE Kathleen Schäfer, K.I.T. Group Exhibition andSponsorship Conference Organization – GmbH Dresden, DE Jörg Herrmann, K.I.T. Group Accounting Conference Organization – GmbH Dresden, DE Eva Smejkal, K.I.T. Group Conference Manager Conference Organization – ESD Alliance, US Graham Bell, ESD AllianceLiaison ESD Alliance, US Bob Smith, ESD AllianceLiaison University, KR Soonhoi Ha, SeoulNational DATE at ESWEEK Representative Ritsumeikan University, JP Hiroyuki Tomiyama, DATE at ASP-DAC Representative Institute of Technology, DE Jörg Henkel, Karlsruhe ASPDAC andACM Liaison DATE Representative at (RAS), RU Russian Academy ofSciences Alexander Stempkovsky, Sciences (RAS) Russian Academy of University of Tübingen, DE Wolfgang Rosenstiel, ECSI Liaison ESD Alliance, US Graham Bell, ESD AllianceLiaison Leuven,Universiteit BE Georges Gielen, Katholieke SSCS Liaison

205

DATE SPONSORS COMMITTEE

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19

www.date-conference.com Karlsruhe Institute of Technology, DE Technology, Institute of Karlsruhe Tokyo Institute of Technology, JP Technology, of Institute Tokyo CNRS-LIRMM/University of Montpellier, FR CNRS-LIRMM/University of Montpellier, Università di Verona, IT Verona, di Università Emerging Design Technologies for Future Memories for Future Emerging Design Technologies Computing and Sustainable Power-efficient 4.0 Robotics and Industry Energy Systems and Smart Systems Automotive Logical and Physical Analysis and Design Analysis Logical and Physical Computing for Future Emerging Design Technologies Architectural and Microarchitectural Design and Microarchitectural Architectural and Power- Design, Low-Power Modeling, Power Optimization Aware Design System Aware and Variability Temperature and Optimization Computing Reconfigurable Network on Chip Network System Simulation and Validation Simulation System Verification Methods and Formal Circuits and Mixed-Signal for Analog Design and Test and MEMS and Systems, of Secure Systems Design and Test System Design, High-Level Synthesis, High-Level Design, System and Optimization System Specification and Modeling Specification System Stanford University, US University, Stanford Subhasish Mitra, Co-Chair: AT Wien), (TU Technology of University Vienna Muhammad Shafique, Chair: US University, San Diego State Baris Aksanli, Co-Chair: IT Verona, of University Fiorini, Paolo Chair: Kroeger, Torsten Co-Chair: IT Trento, of University Brunelli, Davide Chair: DE TUM, Sebastian Steinhorst, Co-Chair: Chair: Aida Todri-Sanial, Todri-Sanial, Aida Chair: FR University, Aix-Marseille Jean-Michel Portal, Chair: US of Utah, University Gaillardon, Pierre-Emmanuel Co-Chair: Complutense University of Madrid, ES of Madrid, University Complutense Ayala, Jose L. Chair: US University, Syracuse Qinru Qiu, Co-Chair: US Riverside, of California, University Philip Brisk, Chair: GB Warwick, of University Fahmy, Suhaib A. Co-Chair: Tiziano Villa, Chair: SE - KTH, Technology of Institute Royal Elena Dubrova, Co-Chair: Barcelona Supercomputing Center and IIIA-CSIC, ES and IIIA-CSIC, Center Supercomputing Barcelona Cazorla, Francisco Chair: INRIA, FR Olivier Sentieys, Co-Chair: KR KAIST, Chang, Naehyuck Chair: IT Torino, di Politecnico Calimera, Andrea Co-Chair: Université de Bretagne-Sud / Lab-STICC, FR / Lab-STICC, de Bretagne-Sud Université Coussy, Philippe Co-Chair: BE Leuven, KU Gielen, Georges Chair: ES Sevilla, CSIC and Univ. IMSE-CNM, Fernandez, V. Francisco Co-Chair: DE of Stuttgart, University Ilia Polian, Chair: NL Nijmegen, University Radboud Lejla Batina, Co-Chair: FR Institute of Nanotechnology, Lyon Sébastien Le Beux, Chair: SE Technology, Institute of Royal KTH Masoud Daneshtalab, Co-Chair: Chair: Yuko Hara-Azumi, Hara-Azumi, Yuko Chair: IT Verona, of University Pravadelli, Graziano Chair: IL - Haifa, IBM Research Ziv, Avi Co-Chair: AT Linz, University Johannes Kepler Armin Biere, Chair: IT Bruno Kessler, Fondazione Cimatti, Alessandro Co-Chair: KTH Royal Institute of Technology, SE Technology, Institute of Royal KTH Sander, Ingo Chair: FR of Nice Sophia Antipolis, University Mallet, Frederic Co-Chair: 206 A2 A3 A1 D14 D12 D13 D11 D10 D8 D9 D7 DT6 DT5 D3 D4 D2 D1 TECHNICAL PROGRAMME TOPIC CHAIRS

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com E5 E4 E3 E2 E1 DT6 DT5 T4 T3 T2 T1 A8 A7 A6 A5 A4 CHAIRS TOPIC PROGRAMME TECHNICAL Co-Chair: Davide Quaglia, University of Verona, IT Chair: Shiyan Hu, Michigan Technological University, US Co-Chair: EliBozorgzadeh, University ofCalifornia, Irvine, US Chair: Borzoo Bonakdarpour, Iowa State University, US Co-Chair: ToddAustin, Chair:Falcone, Ylies Co-Chair: SanderStuijk, Eindhoven University of Technology, NL Chair: Akash Kumar, Technische Universität Dresden, DE Co-Chair: DionisiodeNiz, Carnegie MellonUniversity, US Chair: Kai Lampka, Automotive Electrobit GmbH, DE Co-Chair: LejlaBatina, Radboud University Nijmegen, NL Chair: IliaPolian, University ofStuttgart, DE Co-Chair: Francisco V. Fernandez, IMSE-CNM, CSICandUniv. Sevilla, ES Chair: Georges Gielen, KU Leuven, BE Co-Chair: GeorgiosKarakonstantis, Queen'sUniversity Belfast, GB Center ofExcellence, University ofCyprus, CY Chair: MariaK. Michael, andComputer Electrical Engineering&KIOS Co-Chair: RamonCanal, UPC, ES Chair: JaumeAbella, Barcelona Supercomputing Center (BSC-CNS), ES Co-Chair: BerndBecker, University ofFreiburg, DE Chair: Patrick Girard, LIRMM, FR Co-Chair: JosePineda, NXPSemiconductors, NL Chair: SaidHamdioui, Delft University of Technology, NL Co-Chair: Wehn,Norbert Chair: Fabien Clermidy, CEA-Leti, FR Co-Chair:Yu Wang, Chair:Andy Tyrrell, Co-Chair: GillesSassatelli, /University ofMontpellier 2, CNRS LIRMM FR Chair: AntonioMiele, Politecnico diMilano, IT Co-Chair:Lionel Torres, Chair:Ingrid Verbauwhede, Co-Chair: ElisabettaFarella, Fondazione BrunoKessler (FBK), IT Chair: TheocharisTheocharides, Cyber-Physical Systems Design Tool Chains Embedded Software Architecture, Compilers and Embedded Systems Model-Based Design, Verification andSecurity for Embedded Systems forDeepLearning Real-time andDependable Systems Design andTest ofSecureSystems and Systems andMEMS Design andTest forAnalog andMixed-Signal Circuits System-Level Dependability Microarchitecture-Level Dependability and Diagnosis Test Generation, Test Architectures, DesignforTest Variability, andReliability Modeling andMitigation ofDefects, Faults, Industrial Papers Brief Experiences Applications ofEmergingTechnologies Self-adaptive andLearningSystems Secure Systems, Circuits andArchitectures Augmented Living andPersonalized Healthcare Nanjing University ofPosts and Telecommunications, CN University of York, GB University ofGrenoble Alpes, Inria, FR University ofMichigan, US University ofMontpellier, FR University ofKaiserslautern, DE KU Leuven -COSIC, BE University ofCyprus, CY 207

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 013 020 015 171 013 014 040 001 016 017 011 040 020 C02 C04 206–207 172–201 204–205 142–144 109–141 164–169 039–108 146–163 164–169 011–014 006–010 002–003 018–019 029–038 012–013 004–005 021–028 164 –166 www.date-conference.com

208 Overview Event Sessions Executive Guide Exhibition Reception Exhibition Theatre Programme Exhibition Workshops Friday Meetings Technical Fringe Information General Presentations Interactive Addresses Keynote Media Partners Opening Session PhD Forum Guide Programme Heterogeneous Wednesday: – Special Day Embedded Meets Hyperscale and HPC Computing: Model-Based Design of Thursday: – Special Day Systems Intelligent Special & EU Sessions Sponsors Programme Technical Chairs Topic Programme Technical Tutorials Booth Demonstrations University Exhibition Vendor Venue Plan Venue Reception Welcome Welcome Ceremony Awards DETAILED INDEX DETAILED Workshops Co-Located Secretariat Event Contact A Glance At DATE Committee Executive DATE Event | Networking Party DATE

DATE19 25 – 29 March 2019, Florence, Italy MON TUE WED THU FRI www.date-conference.com tion Theatre. University Booth, PhDForum andExhibi- Sessions,Tutorials, Friday Workshops, also encourages proposals for Special presentation. The Program Committee ard oral presentation orfor interactive Papers canbesubmittedeitherfor stand- 2019, via: www.date-conference.com electronically bySunday, 8September All papershaveto besubmitted of Papers Submission Topics ofinterest include,to: restricted are not but systems, embeddedsoftware, application design, andindustrialdesignexperiences. design methodologies, EDAtools, algorithmsand testing ofelectronic circuits and Withinthe scopethe conference, of the mainareas ofinterest are: embeddedsystems, Interest of Areas More detailsare giventhe DATE on website: www.date-conference.com. will alsobeallocatedtheir results. forto show EU-fundedprojects relevant issuesforthe designautomation, design, communities. Specialspace test and andexchangeto meet information portunities on and social events offers a wide variety of extra op university booth, aPhDforum, vendor presentations zation ofusergroup meetings, fringemeetings, a telecom andmultimediaapplications. The organi- application domains, suchasautomotive, wireless, design experiencesand (industrial) from different and other hardware platforms, embedded software, odologies, anddesignservices, IP reconfigurable tools, the state-of-the-arttest indesignand meth - utives. The scientific conference is complemented by a commercial exhibition showing panels, hot-topic sessions,tutorials, workshops, specialfocus days,track anda for exec- The five-day event consists of a conference invited withplenary papers, regular papers, Event the of Structure SoCs,technologies, emerging embeddedsystems, andembeddedsoftware. systems. DATE andsystems,technology putsstrong emphasisonboth covering ICs/ in hardware and software design,test, and manufacturing of electronic circuits and designers anddesignautomation users, researchers, andvendors, aswellspecialists The 23rd DATE conference andexhibitionthe main European is eventtogether bringing Event the of Scope PAPERS FOR DATE —CALL 2020 Emerging Technologies for Computing Systems Temperature ModelingandManagement Temperature-Aware Design Green Computing Systems andApplications Power Estimation andOptimization LowDesign of Power Systems and ValidationSimulation System Design, Synthesis, andOptimization System Specification andModeling Transportation Systems Systems Communication, Consumer, andMultimedia andPackagingInterconnect Modeling Analog andMixed-Signal CircuitsandSystems Physical Designand Verification Reconfigurable Computing Architectural andMicroarchitectural Design Network-on-Chip Formal Methodsand Verification Emerging Memory Technologies andApplications

Email: Fax: Phone: Bautzner Str. 117-119, 01099Dresden, DE c/o K.I.T. Group GmbHDresden Conference [email protected] Programme Chair: CristianaBolchini, Politecnico diMilano, IT [email protected] General Chair: Giorgio DiNatale, CNRS/TIMA, FR Chairs

- [email protected]

+49 3514956116 +49 3514967312 core, GPU-based, orHeterogeneous Systems Software andOptimization for MPSoCs, Many- Embedded Software andPrinciples Architectures ded Systems Model-based Designand Verification for Embed- Systems Compilers andCode Generation for Embedded Real-time andNetworked Systems On-Line TestingFault Toleranceand System Test Test Access, Design-for-Test, Test Compression, Test for Mixed-Signal, Analog, RF, MEMS Test Generation, Simulation, andDiagnosis Test for Defects, Variability, andReliability Reliable andDependableSystems Secure Systems Systems Generation,Energy Recovery, andManagement Systems Medical, Healthcare, andAssistive Technology CONFERENCE & EXHIBITION Alpexpo, Grenoble, France 09—13 March 2020 Organization

C03

FRI THU WED TUE MON 25 – 29 March 2019, Florence, Italy DATE19 VENUE PLAN

Overview of Firenze Fiera Padiglione Spadolini, Lower Floor

PADIGLIONE SPADOLINI Room 5 (Fortezza da Basso) Room 6 Main conference venue Room 1 Room 4 Poster Area Monday – Friday IP sessions Audio/Video University Cashbar Booth Room 10 Office Registration Desk Conference Bags Room 2 and Cloakroom Main Entrance Office 2

Coffee Office 1 AUDITORIUM Room 9 OF VILLA VITTORIA Exhibition Area Exhibition (Palazzo dei Congressi) Room 3 Industry Exhibition Coee Break Area Theatre Opening Session Tuesday morning (Room 8) Exhibition Reception

Coffee Coffee Room 7

Lunch Area PhD Forum & Welcome Reception Speaker’s Breakfast Lunch Break Area Technology brokerage event B2match Inspiring futures! Interviews

Walk between Auditorium and main conference venue