Best Practices for Soc Design Electronic Design Process Symposium 2014

Best Practices for SoC Design Electronic Design Process Symposium 2014

Kurt Shuler Vice President Marketing, Arteris [email protected]

Awards Customer Adoption 50 56 39

19 12 5 8 1

2006 2007 2008 2009 2010 2011 2012 2013

Timeline of Key Events*

Arteris is founded Charlie Janac Arteris secures Arteris ships second-generation Arteris Leading Arteris by Philippe joins Arteris funding in a round led NoC: FlexNoC. It closes funding becomes smartphone announces Boucard, Alain as CEO. by Synopsys and from Qualcomm Ventures profitable. models ship hiring of new Fanet and César moves headquarters (Europe), ARM (UK) and Innotech using Arteris engineering Douady in Paris. from Paris to Silicon (Japan) plus existing investors. interconnect leadership Valley. technology. team.

2003 2004 2005 2006 2007 2007 2009 2010 2011 2012 2013 2013 2014 Arteris ships its first Texas Instruments selects Arteris starts customer A majority (~60%) of the Arteris receives interconnect IP product the Arteris NoCSolution IP relationships with world’s mobility system-on- Qualcomm first funding from called “NoCSolution” for OMAP4 Application Samsung and chip projects adopt Arteris purchases Arteris Crescendo and closes US$ 1 Processor development. TI Qualcomm, ships FlexNoC Interconnect. Arteris IP and engineering Ventures, Ventech million in licenses works with Arteris to FlexLLI Interchip Link receives Inc. 500 and other team in unique and TVM Capital. almost immediately. productize NoC technology. IP products. awards for rapid growth. transaction.

*Timeline graphic courtesy of World Economic Forum

CPU Subsystem Design-Specific Subsystems Application IP DSP Subsystem (A/V) AES Subsystem A15 A15 A7 A7 IP IP IP IP IP IP 2D GR.

GPU Subsystem A15 A15 A7 A7 3D Graphics FlexWay® Interconnect FlexWay Interconnect MPEG

L2 cache L2 cache IP IP IP IP IP IP Etc.

Coherent ® Interchip LinksTM Interconnect FlexNoC Top Level Interconnect

Memory Scheduler Subsystem Interconnect WiFi HDMI

CRI Crypto Memory Controller USB 3 GSM Firewall MIPI PCIe Ethernet USB 2 (PCF+) LP DDR Wide IO LTE Display DDR3

PHY RSA- PHY PHY LTE Adv. PSS PMU 3.0, 2.0 Cert. Engine PHY PHY JTAG High Speed Wired Peripherals Wireless Subsystem

Memory Subsystem Arteris Interconnect IP Products Security Subsystem I/O Peripherals

FlexNoC Structural NoC Automated NoC Exploration Synthesis Verification FlexVerifier Observability System Verilog-based assertions can be reused at system level

Standard TTM is 18-24 Months Interconnect Interconnect Architecture Design Verification SoC system Verification A D V S

T/O IP Design IP Integration P Physical Design Platform Debug

18 – 24 Actual Customer Experience with Arteris NoC months A D V S

P T/O FPGA Emulation 9 – 12 Software Development 1-2 days iteration months

1. Internally-develop only your most important IP

2. Create a corporate “IP library”

3. Develop corporate design and verification methodologies

4. Use a platform and derivatives approach

FlexNoC Structural NoC Automated NoC Exploration Synthesis Verification FlexVerifier Observability System Verilog-based assertions can be reused at system level

Example Design and Verification Flow Interconnect Interconnect Architecture Design Verification SoC system Verification A D V S

T/O IP Design IP Integration P Physical Design Platform Debug

Design IP Semiconductor System House Service Provider Vendor Vendor or OEM or Channel

Apple $147.00 Microsoft $68.31 Google $48.09 Samsung $35.16 Sony $19.07 Intel $18.16 Qualcomm $13.28 Amazon $11.45 Ebay $9.41 TI $3.96 AMD $2.94 Toshiba $2.59 STMicroelectronics $2.49 Broadcom $2.37 Renesas Electronics $1.60 ARM $0.91 Synopsys $0.89 Cadence $0.72 Imagination $0.08 Sources: Morningstar, Forbes, Yahoo Finance, Wikinvest

○ SoC assembly is more critical to success than creating custom IPs

○ Best practices can enable semi vendors to make more and better chips, more efficiently

○ Semi customers are becoming competitors as chip design “democratizes”