Designing Advanced ASIC's with Synopsys Design Tool Suite

Radiation Hardened Electronics Technology (RHET)

Oct 25th, 2007 Clearwater, Florida

Designing Advanced ASIC’s with Synopsys Design Tool Suite

Synopsys Professional Services Synopsys Inc.

Rick Hayden

Predictable Success Agenda

• Today’s Program Management challenges • Today’s Technical design challenges • Synopsys Tool Suites • Synopsys Professional Services

HW & SW Operating System Co-development Drivers Software applications Reusable Standard Hardware Digital Hardware Design

Low Power Analog Consumption Circuit Design

Predictable Success PM’s Role: Case Study

Sound familiar?

100% 75% Cone of Uncertainty 50% Number of unknowns and corresponding 25% uncertainty in effort estimates through project life 0% -25% -50% -75%

Prod Refined Spec RTL Gates GDSII Defn Defn

• Early in the project you can have firm cost and schedule targets or a firm feature set, but not both. • Cone of Uncertainty implies that it is not only difficult to estimate projects accurately in the early stages but theoretically impossible.

• Due to the nature of ASICs, nearly every design: Complete systems on a single die (SoC) Often requires 3rd party IP Mixed signal designs are becoming prevalent • SERDES, USB, PCIe, etc. Verification is more complex Requires leading edge silicon technology

VIP VIP VIP VIP VIP • Accurate schedule and effort

WiUSB PHY USB PHY PCIe PHY SATA PHY XAUI PHY estimation is difficult to make in early Micro- processor WiUSB USB 10/100/ stages of design: DSP PCIe SATA 10GE 1GE VIP

Arbitration Design specification may not be + Decode AMBA™On-Chip AHB/ High AMBA Speed 3 Bus AXI + Control solidified VIP DDR3/2 Memory PHY Controller RAM ROM FLASH Bridge Unknowns in design flows, libraries, processes AMBAOn-Chip APB Peripheral Bus

rd I2C UART GPIO RTC Interrupt Integration of 3 party IP can be Controller underestimated VIP VIP VIP IP

Predictable Success More and More Moore’s Law MEMs… 32nm EM 45nm Gates 65nm SW 90nm 130nm 180nm DFM 250nm Tech. Nodes Power Sign. Int. Scale Complexity Scale Test Speed Area Analog Digital Systemic Complexity

100%

80% IR Drop Coupling Capacitance 60% Impact on RC delay total delay Cell Delay 40%

20%

0% 250nm 180nm 130nm 90nm 65nm • Interconnect delay, delay due to crosstalk, and delay due to IR drop are more dominant in smaller technologies. • Post-layout analysis with parasitics is required for accurate modeling.

250 100 Leakage Power )

Active Power 2 200 Power Density 75

150 50 100 Power(Watts) 25 50 Power Density Power(W/cm Density

0 0 250nm 180nm 130nm 90nm 65nm • Leakage power becomes more dominant at smaller technologies. • Multi-Vth libraries are used to provide balance between performance and leakage.

In sub-micron Wire-to-Wire Cap

Dominates ( CW >> C S) 8 Signal Integrity: problems in design that affect your timing CW – Crosstalk / Static Noise CS – Voltage (IR) drop

8 Reliability: long term current damages your chip – Electromigration

8 Manufacturability : charge effects Charge Build Up results in reducing yield – Process Antenna Effect

Damaged Gate

Predictable Success Synopsys Design Platforms

Design Services

Design Compiler System Studio Saber DCT DFT Compiler DCT DFT Compiler Design- Ware Power Compiler Design- Ware Power Compiler

JupiterXT

VCS VMM ICCICC PC/Astro LEDA Milkyway Milkyway

Formality SI PrimeTime SI PrimeTime Verification IP Verification IP Verification (DesignWare) (DesignWare) Star-RCXT SystemVerilogSystemVerilog SystemC / SystemC /

NanoSim HSPICE Hercules

Discovery ™ Verification Platform Galaxy ™ Design Platform

System Studio Saber

VCS VMM LEDA Formality Verification IP Verification IP Verification (DesignWare) (DesignWare) SystemVerilogSystemVerilog SystemC / SystemC /

NanoSim HSPICE

Predictable Success Verification Challenge Fueling Growth

“Validation is the biggest challenge going forward, limiting our ability to do more complex designs ” Intel

“Over 50% of our chip design resources are now committed to Verification ” Texas Instruments

? GapGap Property C++ Testbench Assertion Mixed -HDL Design Size Design Coverage ?

VHDL

Verilog

1-2µµµm .13 µµµm

Design for Verification Verification (Simulation)

GapGap Property C++ Testbench AssertionSystemVerilogSystemVerilog Mixed -HDL

Design Size Design Coverage

VHDL

Verilog

1-2µµµm .13 µµµm

• Easy communication between System Architects, Design Engineers and Verification Engineers

• Enables higher level of abstraction

• Provides code compaction

• Has specific language constructs that reduce mismatches between simulation, synthesis and formal verification tools

• Better Description of Hardware Specific Procedures

• Enhanced Readability

Design Compiler DCT DFT Compiler DCT DFT Compiler Design- Ware Power Compiler Design- Ware Power Compiler

JupiterXT

ICCICC PC/Astro Milkyway Milkyway PrimeTime SI PrimeTime SI PrimeTime

Star-RCXT

Hercules

Predictable Success Predictable Synthesis Topographical (Physically Aware) Technology

Timing • No need Galaxy Galaxy & Area Power for WLMs • Correlates to DesignDesign post-layout CompilerCompiler results • Reduces Signoff Signoff iterations ICIC CompilerCompiler • Easily adaptable Milkyway into existing design flows

Enables fastest TTR and Better Start Point for P&R

Traditional Routing Netlist TCL GUI

Physical DFT Physical Floor Power Planning Concurrent Optimization Yield P&R Opt Signoff SI Aware Routing Driven Milkyway GDSII

Predictable Success Global Technical Solutions

Pilot Design Environment

Configuration GUI

Flow Automation Pilot provides a mature, modular

Technology Metrics environment and flow to help maximize Input QA Preparation Reporting repeatability, efficiency, and productivity Design For Design RTL Synthesis Test Planning

Functional Place & Route Chip GDSII Verification Optimization Finishing

Data Structure Incoming Gates Quality checks and reviews ensure successful execution Step 1 Step 2 … Step n Tapeout of projects according to plans

Major Design Corporate / Central Centers Outgoing Gates Data Center

DesignSphere compute infrastructure helps ensure worldwide team execution

Customers, Partners, Remote Design Consultants Centers

• Open, ready-to-use, VDSM tested Pilot Design Environment Pilot Design Environment design system Configuration GUI Configurable for customer- specific environment Flow Automation New utilities for IP & lib-QA,

Technology Metrics technology file preparation & Input QA Preparation Reporting metrics reporting

Design For Design GUI for ease of flow setup RTL Synthesis Test Planning • Deployed to customers & used by

Functional Place & Route Chip Professional Services, WW GDSII Verification Optimization Finishing Enable consistent multi-site, multi-project IC development Data Structure • Updated & supported by Synopsys Professional Services

EDA Tool EDA Tool License Shortages Access by Program

Compute Resource Scalable Compute Limitations Platforms Scalable Design Engineering Skills & Services (ITAR Resources Shortages Compliant Resources)

Procurement of Reliable Robust, Proven IP IP Portfolio

System Specification Typical Entry Points: Development Verification 1 – Specification 1 2 – RTL Chip RTL RTL Refinement Specification 3 – Gate-Level Netlist Development Design and Optimization 2 Synthesis Honeywell-Synopsys Design Flow Design Flow DFT Entry DFT Floorplan Physical 3 Synthesis Place and Design Flow Route Exit

Package Requirements Package ASIC Development Fabrication

Test Assembly Requirements Requirements Test Test Development

Typical Responsibilities Screening

Customer Synopsys-Foundry Pilot Flow Honeywell

© 2007 Synopsys, Inc. (26) Predictable Success Design Collaboration Environment Scalable Infrastructure Honeywell Design Center Synopsys Design Center Customer Secure internet link Design Customer Centers Same Desktop View

• Scalable data center • Collaborative design infrastructure Server farm with 100’s of CPU’s • Enables customer, Honeywell and Synopsys LSF based job launching for parallel engineers to act as single design center computing Use a common Pilot flow Regular back-ups Physically secured and monitored 24x7x365 On-demand availability of tool licenses ITAR Compliant