Synopsys Insight
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GS40 0.11-Μm CMOS Standard Cell/Gate Array
GS40 0.11-µm CMOS Standard Cell/Gate Array Version 1.0 January 29, 2001 Copyright Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques, or apparatus described herein are the exclusive property of Texas Instruments. No disclosure of information or drawings shall be made to any other person or organization without the prior consent of Texas Instruments. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this war- ranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WAR- RANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. -
High-Level Synthesis Tools for Xilinx Fpgas
An Independent Evaluation of: High-Level Synthesis Tools for Xilinx FPGAs By the staff of Berkeley Design Technology, Inc. Executive Summary In 2009, Berkeley Design Technology Inc. (BDTI), an HLSTs provided roughly 40X better performance than a independent benchmarking and analysis firm, launched mainstream DSP processor, and that the high-level syn- the BDTI High-Level Synthesis Tool Certification Pro- thesis tools were able to achieve FPGA resource utiliza- gram™ to evaluate high-level synthesis tools for tion levels comparable to hand-written RTL code. FPGAs. Such tools take as their input a high-level repre- Furthermore, as we will discuss in this white paper, sentation of an application (written in C or MATLAB, for implementing our video application using the HLSTs example) and generate a register-transfer-level (RTL) along with Xilinx FPGA tools required a similar level of implementation for an FPGA. Thus far, two high-level effort as that required for the DSP processor. This find- synthesis tools, AutoESL’s AutoPilot and the Synopsys ing will no doubt be surprising to many, as FPGAs have Synphony C Compiler, have been certified under the historically required much more development time than program. DSPs. BDTI’s evaluation program uses two example appli- Based on our analysis, we believe that HLSTs can sig- cations, a video motion analysis application and a wireless nificantly increase the productivity of current FPGA receiver, to evaluate high-level synthesis tools (HLSTs) users. For those using DSP processors in highly demand- on a number of quantitative and qualitative metrics. As ing applications, we believe that FPGAs used with shown in Figure 1 and Figure 2, we found that the Xilinx HLSTs are worthy of serious consideration. -
Introduction to Intel® FPGA IP Cores
Introduction to Intel® FPGA IP Cores Updated for Intel® Quartus® Prime Design Suite: 20.3 Subscribe UG-01056 | 2020.11.09 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction to Intel® FPGA IP Cores..............................................................................3 1.1. IP Catalog and Parameter Editor.............................................................................. 4 1.1.1. The Parameter Editor................................................................................. 5 1.2. Installing and Licensing Intel FPGA IP Cores.............................................................. 5 1.2.1. Intel FPGA IP Evaluation Mode.....................................................................6 1.2.2. Checking the IP License Status.................................................................... 8 1.2.3. Intel FPGA IP Versioning............................................................................. 9 1.2.4. Adding IP to IP Catalog...............................................................................9 1.3. Best Practices for Intel FPGA IP..............................................................................10 1.4. IP General Settings.............................................................................................. 11 1.5. Generating IP Cores (Intel Quartus Prime Pro Edition)...............................................12 1.5.1. IP Core Generation Output (Intel Quartus Prime Pro Edition)..........................13 1.5.2. Scripting IP Core Generation.................................................................... -
NOTICE of ANNUAL MEETING of STOCKHOLDERS April 23, 2001 ______
NOTICE OF ANNUAL MEETING OF STOCKHOLDERS April 23, 2001 ________________ To the Stockholders of Synopsys, Inc.: NOTICE IS HEREBY GIVEN that the Annual Meeting of Stockholders of Synopsys, Inc., a Delaware corporation (the “Company”), will be held on Monday, April 23, 2001, at 4:00 p.m., local time, at the Company’s principal executive offices at 700 East Middlefield Road, Mountain View, California 94043, for the following purposes: 1. To elect eight directors to serve for the ensuing year or until their successors are elected. 2. To approve an amendment to the Company’s Employee Stock Purchase Plan and International Employee Stock Purchase Plan to increase the number of shares of Common Stock reserved for issuance thereunder by 1,200,000 shares. 3. To approve an amendment to the 1992 Stock Option Plan to extend the term of the Plan from January 2002 to January 2007. 4. To ratify the appointment of KPMG LLP as independent auditors of the Company for fiscal year 2001. 5. To transact such other business as may properly come before the meeting or any adjournment or adjournments thereof. The foregoing items of business are more fully described in the Proxy Statement accompanying this Notice. Only stockholders of record at the close of business on February 26, 2001 are entitled to notice of and to vote at the meeting. All stockholders are cordially invited to attend the meeting in person. However, to assure your representation at the meeting, you are urged to sign and return the enclosed proxy (the “Proxy”) as promptly as possible in the envelope enclosed. -
IEEE 802.3Da SPMD TF Meeting May 19, 2021 Prepared by Peter Jones
IEEE 802.3da SPMD TF meeting May 19, 2021 Prepared by Peter Jones Presentations posted at: https://www.ieee802.org/3/da/index.html Agenda/Admin - Chad Jones All times in Pacific Time (PT) 7:01am: The Chair reviewed the agenda in https://www.ieee802.org/3/da/public/051921/8023da_agenda_051921.pdf. The Chair asked if there were any corrections or additions to the agenda. There being no corrections or additions, the agenda stands approved. The Chair asked if anyone hasn’t had a chance to review the minutes for April 21, 2021. None responded. The Chair asked if there were any change to be made to the April 21, 2021 minutes. None responded. The April 21, 2021 minutes were approved by unanimous consent. 7:09am: Call for patents was made, no one responded. 7:14am: opening agenda slides complete. The meeting moves on to presentations. Presentations/Discussion. 7:14am: LTspice Model Validation Chris DiMinico, MC Communications/PHY-SI LLC/SenTekse/Panduit Bob Voss, Panduit Paul Wachtel, Panduit 7:21am: presentation done, start of Q&A. 7:30am: Q&A done. 7:30am: Startup sequence Michael Paul, ADI 8.05am: presentation & Q&A done. 8:05am: Editors comments George Zimmerman, CME Consulting/various 8:28am: Closing remarks Next meeting: May 26, 2021 , 7:00am PT. Meeting closed – 8:31am PT Attendees (from Webex + emails) Name Employer Affiliation Attended 05/19 Alessandro Ingrassia Canova Tech Canova Tech y Anthony New Prysmian Group Prysmian Group y Bernd Horrmeyer Phoenix Contact Phoenix Contact y Bob Voss Panduit Corp. Panduit Corp. y Brian Murray Analog Devices Inc. -
Microchip Technology Inc
Microchip Technology Inc. Watchdog Report ™ MCHP (NASDAQ Global) | CIK:827054 | United States | SEC llings The new model for duciary analysis Sep 24, 2021 Jan 1, 2020 Jan 1, 2016 RECENT PERIOD HISTORICAL PERIOD Key Facts 10-Q led on Aug 3, 2021 for period ending Jun 2021 Business address: Chandler, Arizona, United States Reporting Irregularities RECENT HISTORICAL Industry: Semiconductor and Related Device Manufacturing (NAICS Financial Restatements 334413) SEC ler status: Large Accelerated Filer as of Jun 2021 Revisions Index member: S&P 500, Russell 1000 Out of Period Adjustments Market Cap: $45.3b as of Sep 24, 2021 Late Filings Annual revenue: $5.44b as of Mar 31, 2021 Impairments Corporate Governance Changes in Accounting Estimates CEO: Ganesh Moorthy since 2021 Disclosure Controls CFO: Eric J. Bjornholt since 2009 1st level Internal Controls Board Chairman: Steve Sanghi since 1993 Critical / Key Audit Matters Audit Committee Chair: NOT AVAILABLE Anomalies in the Numbers 2nd level RECENT HISTORICAL Benford's Law Auditor: Ernst & Young LLP since 2001 Outside Counsel (most recent): Wilson Sonsini Goodrich & Rosati Beneish M-Score Osborn Maledon PA Accounting Disclosure Complexity 3rd level Securities & Exchange Commission Concerns RECENT HISTORICAL SEC Reviewer: (unknown) 4th level SEC Oversight SEC Letters to Management Revenue Recognition Non-GAAP Measures Litigation & External Pressures RECENT HISTORICAL Signicant Litigation Securities Class Actions Shareholder Activism Watchdog Research, Inc., offers both individual and group subscriptions, Cybersecurity data feeds and/or custom company reports to our subscribers. Management Review Subscribe: We have delivered 300,000 public company reports to over RECENT HISTORICAL 27,000 individuals, from over 9,000 investment rms and to 4,000+ public CEO Changes company corporate board members. -
Xilinx XAPP107: Synopsys/Xilinx High Density Design Methodology Using
Product Obsolete/Under Obsolescence Application Note 3 0 Synopsys/Xilinx High Density Design Methodology Using FPGA Compiler™ XAPP107 August 6, 1998 (Version 1.0) 03*Written by: Bernardo Elayda & Ramine Roane Summary This paper describes design practices to synthesize high density designs (i.e. over 100k gates), composed of large functional blocks, for today’s larger Xilinx FPGA devices using the Synopsys FPGA Compiler. The Synopsys FPGA Compiler version 1998.02, Alliance Series 1.5, and the XC4000X family were used in preparing the material for this application note. Introduction designs preserving some levels of hierarchy will lead to better placement routing results and shorter compile times. For smaller designs, optimal quality of results can often be achieved by ungrouping hierarchical boundaries (compile The designer must determine which trade-offs to make to -ungroup_all). For high density designs, designers tra- meet his design goals and timing requirements. ditionally partition their circuits into small 5-10k gate mod- High density designs require greater selectivity on which ules. With todays version of FPGA Compiler (1998.02) and hierarchical boundaries to eliminate for synthesis. Flatten- currently available workstation hardware it is no longer nec- ing a 150k gate design can lead to long compile times, and essary to partition a design into small 5K to 10K blocks for compromise results. The following guidelines will help in efficient synthesis. In fact, artificial partitioning the design choosing which blocks to flatten in a large design: can worsen optimization results by breaking paths into sep- 1. Eliminating boundaries between combinatorial blocks arate partitions and preventing FPGA Compiler from being allows the synthesis tool to optimize glue logic across able to optimize the entire path. -
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Case 5:19-cv-02082-LHK Document 48 Filed 06/26/19 Page 1 of 9 1 2 3 4 5 6 7 8 UNITED STATES DISTRICT COURT 9 NORTHERN DISTRICT OF CALIFORNIA 10 SAN JOSE DIVISION 11 12 SYNOPSYS, INC., Case No. 19-CV-02082-LHK 13 Plaintiff, ORDER GRANTING PRELIMINARY INJUNCTION 14 v. 15 INNOGRIT, CORP., 16 Defendant. 17 United States District Court District United States Northern District of California District Northern 18 On April 23, 2019, the Court denied Plaintiff’s ex parte application for a temporary 19 restraining order. ECF No. 16 at 6. However, the Court also ordered Defendant to show cause why 20 a preliminary injunction should not issue. Id. The Court permitted the parties to brief whether a 21 preliminary injunction is appropriate here. Before the Court is the question of whether to impose a 22 preliminary injunction in the instant case. Having considered the parties’ submissions, the relevant 23 law, and the record in this case, the Court GRANTS a preliminary injunction. 24 I. BACKGROUND 25 Factual Background 26 Plaintiff is a provider of electronic design automation (“EDA”). ECF No. 39 (first 27 amended complaint, or “FAC”) at ¶ 8. EDA refers to “using computers to design, verify, and 28 1 Case No. 19-CV-02082-LHK ORDER GRANTING PRELIMINARY INJUNCTION Case 5:19-cv-02082-LHK Document 48 Filed 06/26/19 Page 2 of 9 1 simulate the performance of electronic circuits.” Id. Plaintiff has invested substantial sums of 2 money in designing EDA software, and offers a variety of software applications to purchasers. -
GS30 Product Overview
GS30 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 February, 2001 Copyright Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques, or apparatus described herein are the exclusive property of Texas Instruments. No disclosure of information or drawings shall be made to any other person or organization without the prior consent of Texas Instruments. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this war- ranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WAR- RANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. -
Download Apps in Their Smartphones to Interact with Eot Devices
sensors Article Eyes of Things Oscar Deniz 1,*, Noelia Vallez 1, Jose L. Espinosa-Aranda 1, Jose M. Rico-Saavedra 1, Javier Parra-Patino 1, Gloria Bueno 1, David Moloney 2, Alireza Dehghani 2, Aubrey Dunne 2, Alain Pagani 3, Stephan Krauss 3, Ruben Reiser 3, Martin Waeny 4, Matteo Sorci 5, Tim Llewellynn 5, Christian Fedorczak 6, Thierry Larmoire 6, Marco Herbst 7, Andre Seirafi 8 and Kasra Seirafi 8 1 VISILAB, University of Castilla-La Mancha, E.T.S.I.Industriales, Avda Camilo Jose Cela s/n, Ciudad Real 13071, Spain; [email protected] (N.V.); [email protected] (J.L.E.-A.); [email protected] (J.M.R.-S.); [email protected] (J.P.-P.); [email protected] (G.B.) 2 Movidius, 1st Floor, O’Connell Bridge House, D’Olier Street, Dublin 2, Ireland; [email protected] (D.M.); [email protected] (A.D.); [email protected] (A.D.) 3 DFKI, Augmented Vision Research Group, Tripstaddterstr. 122, 67663 Kaiserslautern, Germany; [email protected] (A.P.); [email protected] (S.K.); [email protected] (R.R.) 4 Awaiba, Madeira Tecnopolo, 9020-105 Funchal, Portugal; [email protected] 5 nViso SA, PSE-D, Site EPFL, CH-1015 Lausanne, Switzerland; [email protected] (M.S.); [email protected] (T.L.) 6 THALES Communications & Security, 4 Avenue des Louvresses, 92230 Gennevilliers, France; [email protected] (C.F.); [email protected] (T.L.) 7 Evercam, 6-7 Granby Row, Dublin 1, D01 FW20, Ireland; [email protected] 8 Fluxguide, Burggasse 7-9/9, 1070 Vienna, Austria; andre@fluxguide.com (A.S.); kasra@fluxguide.com (K.S.) * Correspondence: [email protected] Academic Editors: Luca Roselli, Federico Alimenti and Stefania Bonafoni Received: 30 March 2017; Accepted: 17 May 2017; Published: 21 May 2017 Abstract: Embedded systems control and monitor a great deal of our reality. -
Analysis of the Movidius Platform Architecture From
D3.5 Test sets and results with Factor H2020-643924-EoT Form Board Horizon 2020 PROGRAMME ICT-01-2014: Smart Cyber-Physical Systems This project has received funding from the European Union’s Horizon 2020 research and innovation programme under Grant Agreement No 643924 D3.5 Test sets and results with Factor Form Board Copyright © 2015 The EoT Consortium The opinions of the authors expressed in this document do not necessarily reflect the official opinion of EOT partners or of the European Commission. Page 1 of 40 25/9/2017 D3.5 Test sets and results with Factor H2020-643924-EoT Form Board 1. DOCUMENT INFORMATION Deliverable Number D3.5 Deliverable Name Test sets and results with Factor Form Board Authors J. Parra (UCLM), N. Vallez (UCLM), J. M. Rico (UCLM), J. L. Espinosa-Aranda (UCLM), A. Dehghani (MOVIDIUS), S. Krauss (DFKI), R. Reiser (DFKI), A. Pagani (DFKI) Responsible Author Oscar Deniz (UCLM) e-mail:[email protected] phone: +34 926295300 Ext.6286 Keywords EoT Firmware, Tests, EoT Factor form board WP WP3 Nature R Dissemination Level PU Planned Date 01.06.2016 Final Version Date 25.09.2017 Reviewed by O. Deniz (UCLM) Verified by C. Fedorczak (THALES) Page 2 of 40 25/9/2017 D3.5 Test sets and results with EoT H2020-643924-EoT prototypes 2. DOCUMENT HISTORY Person Date Comment Version O. Deniz 30.05.2017 Initial 0.1 J. Parra-Patiño 14.07.2017 0.2 N. Vallez 04.09.2017 0.3 J.L. Espinosa- 25.09.2017 0.4 Aranda O. Deniz 25.09.2017 Final 0.5 Page 3 of 40 25/9/2017 D3.5 Test sets and results with EoT H2020-643924-EoT prototypes 3. -
To Bridge Neural Network Design and Real-World Performance: a Behaviour Study for Neural Networks
TO BRIDGE NEURAL NETWORK DESIGN AND REAL-WORLD PERFORMANCE:ABEHAVIOUR STUDY FOR NEURAL NETWORKS Xiaohu Tang 1 2 Shihao Han 3 2 Li Lyna Zhang 2 Ting Cao 2 Yunxin Liu 2 ABSTRACT The boom of edge AI applications has spawned a great many neural network (NN) algorithms and inference platforms. Unfortunately, the fast pace of development in their fields have magnified the gaps between them. A well-designed NN algorithm with reduced number of computation operations and memory accesses can easily result in increased inference latency in real-world deployment, due to a mismatch between the algorithm and the features of target platforms. Therefore, it is critical to understand the behaviour characteristics of NN design space on target platforms. However, none of existing NN benchmarking or characterization studies can serve this purpose. They only evaluate some sparse configurations in the design space for the purpose of platform optimization rather than the scaling in every design dimension for NN algorithm efficiency. This paper presents the first empirical study on the NN design space to learn NN behaviour characteristics on different inference platforms. The revealed characteristics can be used as guidelines to design efficient NN algorithms. We profile ten-thousand configurations from a cutting-edge NN design space on seven industrial edge AI platforms. Seven key findings as well as their causes and implications for efficient NN design are highlighted. 1 INTRODUCTION Numerous edge devices such as mobile phones, cameras and speakers provide real-world usage scenarios for NN technology. To enable affordable NN inference on edge devices, remarkable innovations have been achieved on the design of efficient NN algorithms and the development of inference platforms (including hardware accelerators and the corresponding inference frameworks on top).