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Portfolio Holdings Listing Select Semiconductors Portfolio As of June
Portfolio Holdings Listing Select Semiconductors Portfolio DUMMY as of August 31, 2021 The portfolio holdings listing (listing) provides information on a fund’s investments as of the date indicated. Top 10 holdings information (top 10 holdings) is also provided for certain equity and high income funds. The listing and top 10 holdings are not part of a fund’s annual/semiannual report or Form N-Q and have not been audited. The information provided in this listing and top 10 holdings may differ from a fund’s holdings disclosed in its annual/semiannual report and Form N-Q as follows, where applicable: With certain exceptions, the listing and top 10 holdings provide information on the direct holdings of a fund as well as a fund’s pro rata share of any securities and other investments held indirectly through investment in underlying non- money market Fidelity Central Funds. A fund’s pro rata share of the underlying holdings of any investment in high income and floating rate central funds is provided at a fund’s fiscal quarter end. For certain funds, direct holdings in high income or convertible securities are presented at a fund’s fiscal quarter end and are presented collectively for other periods. For the annual/semiannual report, a fund’s investments include trades executed through the end of the last business day of the period. This listing and the top 10 holdings include trades executed through the end of the prior business day. The listing includes any investment in derivative instruments, and excludes the value of any cash collateral held for securities on loan and a fund’s net other assets. -
GS40 0.11-Μm CMOS Standard Cell/Gate Array
GS40 0.11-µm CMOS Standard Cell/Gate Array Version 1.0 January 29, 2001 Copyright Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques, or apparatus described herein are the exclusive property of Texas Instruments. No disclosure of information or drawings shall be made to any other person or organization without the prior consent of Texas Instruments. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this war- ranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WAR- RANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. -
LPC47N267 Product Brief
LPC47N267 100-Pin LPC Super I/O with X-Bus Interface Product Features • Enhanced Digital Data Separator - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 • 3.3 Volt Operation (5V tolerant) Kbps Data Rates • Programmable Wakeup Event Interface - Programmable Precompensation Modes (IO_PME# Pin) • Serial Ports • SMI Support (IO_SMI# Pin) - Two Full Function Serial Ports • GPIOs (29) - High Speed NS16C550 Compatible UARTs • Four IRQ Input Pins with Send/Receive 16-Byte FIFOs • X-Bus Interface - Supports 230k and 460k Baud - Supports up to 4 external components - Programmable Baud Rate Generator - Supports I/O cycles (No Memory Support) - Modem Control Circuitry - 8-Bit Data Transfer • Infrared Communications Controller - 16-Bit Address Qualification - IrDA v1.2 (4Mbps), HPSIR, ASKIR, Con- - Write Protection for each component sumer IR Support • XNOR Chain -2 IR Ports • PC99 and ACPI 1.0b Compliant - 96 Base I/O Address, 15 IRQ Options and 3 • 100-pin STQFP Package DMA Options • Intelligent Auto Power Management • Multi-Mode Parallel Port with ChiProtect • 2.88MB Super I/O Floppy Disk Controller - Standard Mode IBM PC/XT, PC/AT, and PS/2 - Licensed CMOS 765B Floppy Disk Controller Compatible Bidirectional Parallel Port - Software and Register Compatible with - Enhanced Parallel Port (EPP) Compatible - Microchip's Proprietary 82077AA Compatible EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) Core - IEEE 1284 Compliant Enhanced Capabilities - Supports One Floppy Drive Directly Port (ECP) - Configurable Open Drain/Push-Pull Output - ChiProtect Circuitry for -
Microchip Technology Announces Financial Results for Third Quarter of Fiscal Year 2020
EXHIBIT 99.1 NEWS RELEASE INVESTOR RELATIONS CONTACT: J. Eric Bjornholt -- CFO..... (480) 792-7804 MICROCHIP TECHNOLOGY ANNOUNCES FINANCIAL RESULTS FOR THIRD QUARTER OF FISCAL YEAR 2020 ◦ Net sales of $1.287 billion, down 3.8% sequentially and down 6.4% from the year ago quarter. The midpoint of our updated net sales guidance provided on January 6, 2020 was $1.285 billion. ◦ On a GAAP basis: gross margin of 61.0%; operating income of $131.2 million; net income of $311.1 million; and EPS of $1.20 per diluted share. Our guidance provided on December 3, 2019 was GAAP (loss) earnings per share of $(0.03) to $0.04 per diluted share. ◦ On a Non-GAAP basis: gross margin of 61.5%; operating income of $452.1 million and 35.1% of net sales; net income of $340.8 million and EPS of $1.32 per diluted share. Our guidance provided on December 3, 2019 was Non-GAAP EPS of $1.19 to $1.30 per diluted share. ◦ End-market demand of $1.324 billion was $36.1 million higher than net sales. ◦ Cash flow from operations of $395.5 million. ◦ Paid down $257.0 million of debt in the December 2019 quarter. Cumulatively paid down almost $2 billion of debt over the last six quarters. ◦ Record quarterly dividend declared of 36.70 cents per share. CHANDLER, Arizona - February 4, 2020 - (NASDAQ: MCHP) - Microchip Technology Incorporated, a leading provider of smart, connected and secure embedded control solutions, today reported results for the three months ended December 31, 2019 as summarized in the following table: (in millions, except per share amounts and percentages) Three Months Ended December 31, 2019 Net sales $1,287.4 % of Net % of Net GAAP Sales Non-GAAP1 Sales Gross margin $785.5 61.0% $791.2 61.5% Operating income $131.2 10.2% $452.1 35.1% Other expense $(120.6) $(89.5) Income tax (benefit) provision $(300.5) $21.8 Net income $311.1 24.2% $340.8 26.5% Net income per diluted share $1.20 $1.32 (1) See the "Use of Non-GAAP Financial Measures" section of this release. -
AN2534 PAC193X Integration Notes for Microsoft® Windows® 10 Driver Support Author: Razvan Ungureanu TABLE 2: REVISION HISTORY Microchip Technology Inc
AN2534 PAC193X Integration Notes for Microsoft® Windows® 10 Driver Support Author: Razvan Ungureanu TABLE 2: REVISION HISTORY Microchip Technology Inc. Rev# Date Description 1.0 20-June-2017 The information in this INTRODUCTION document apply to the This document describes the basic steps for integrating PAC193X driver releases: the PAC193X DC Power Monitor device in a Microsoft® 1.0, 1.1 and 1.2 Windows® 10 host system in order to enable support of the Windows® 10 PAC193X driver. HARDWARE INTEGRATION As the PAC193X device can be used in multiple ways The hardware integration must first address all the and in different system configurations, there are some electrical details specified in the device data sheet. For 2 specific hardware and BIOS configuration details that example, the device VDD IO must match the I C bus need to be addressed before loading the Windows® voltage. But the following hardware notes address only device driver. the hardware details that need specific configuration in ® The details about the PAC193X Windows® 10 device order to make them compatible with the Windows 10 driver loading, feature set and software interfaces are device driver: included in the PAC193X Windows® 10 Driver User’s •I2C bus controller Windows® support Guide that complements the information presented by • PAC193X VDD and SLOW/ALERT pin connections this document. • Channel shunt resistor values . TABLE 1: GLOSSARY OF TERMS AND • Channel polarity ACRONYMS I2C Bus Controller Windows® Support Acronym Term 2 E3 Energy Estimation Engine The PAC193X device I C/SMBus interface is by default configured in the I2C Mode. Mind that the SMBus EMI Energy Metering Interface protocol is not currently supported by Windows®. -
Stoxx® Global Automation & Robotics Index
STOXX® GLOBAL AUTOMATION & ROBOTICS INDEX Components1 Company Supersector Country Weight (%) SNAP 'A' Technology United States 4.24 NVIDIA Corp. Technology United States 2.80 Nidec Corp. Technology Japan 2.42 HEXAGON B Technology Sweden 2.38 TERADYNE Technology United States 2.31 KLA Technology United States 2.23 MARVELL TECHNOLOGY Technology United States 2.16 Intuitive Surgical Inc. Health Care United States 2.12 ADVANCED MICRO DEVICES Technology United States 2.12 Qualcomm Inc. Technology United States 2.09 Apple Inc. Technology United States 2.06 Advantest Corp. Technology Japan 2.05 LASERTEC Technology Japan 2.04 Garmin Ltd. Consumer Products & Services United States 2.02 Emerson Electric Co. Industrial Goods & Services United States 2.02 Microchip Technology Inc. Technology United States 1.98 Ametek Inc. Industrial Goods & Services United States 1.96 Toyota Industries Corp. Automobiles & Parts Japan 1.96 Xilinx Inc. Technology United States 1.95 SERVICENOW Technology United States 1.88 DASSAULT SYSTEMS Technology France 1.82 Rockwell Automation Corp. Industrial Goods & Services United States 1.74 Fanuc Ltd. Industrial Goods & Services Japan 1.74 Autodesk Inc. Technology United States 1.68 Keyence Corp. Industrial Goods & Services Japan 1.63 Ansys Inc. Technology United States 1.61 HALMA Industrial Goods & Services Great Britain 1.56 PTC INC Technology United States 1.53 Omron Corp. Technology Japan 1.52 OPEN TEXT (NAS) Technology Canada 1.49 COGNEX Industrial Goods & Services United States 1.48 Yaskawa Electric Corp. Industrial Goods & Services Japan 1.40 SAP Technology Germany 1.40 MINEBEA MITSUMI Industrial Goods & Services Japan 1.24 Intel Corp. -
High-Level Synthesis Tools for Xilinx Fpgas
An Independent Evaluation of: High-Level Synthesis Tools for Xilinx FPGAs By the staff of Berkeley Design Technology, Inc. Executive Summary In 2009, Berkeley Design Technology Inc. (BDTI), an HLSTs provided roughly 40X better performance than a independent benchmarking and analysis firm, launched mainstream DSP processor, and that the high-level syn- the BDTI High-Level Synthesis Tool Certification Pro- thesis tools were able to achieve FPGA resource utiliza- gram™ to evaluate high-level synthesis tools for tion levels comparable to hand-written RTL code. FPGAs. Such tools take as their input a high-level repre- Furthermore, as we will discuss in this white paper, sentation of an application (written in C or MATLAB, for implementing our video application using the HLSTs example) and generate a register-transfer-level (RTL) along with Xilinx FPGA tools required a similar level of implementation for an FPGA. Thus far, two high-level effort as that required for the DSP processor. This find- synthesis tools, AutoESL’s AutoPilot and the Synopsys ing will no doubt be surprising to many, as FPGAs have Synphony C Compiler, have been certified under the historically required much more development time than program. DSPs. BDTI’s evaluation program uses two example appli- Based on our analysis, we believe that HLSTs can sig- cations, a video motion analysis application and a wireless nificantly increase the productivity of current FPGA receiver, to evaluate high-level synthesis tools (HLSTs) users. For those using DSP processors in highly demand- on a number of quantitative and qualitative metrics. As ing applications, we believe that FPGAs used with shown in Figure 1 and Figure 2, we found that the Xilinx HLSTs are worthy of serious consideration. -
Introduction to Intel® FPGA IP Cores
Introduction to Intel® FPGA IP Cores Updated for Intel® Quartus® Prime Design Suite: 20.3 Subscribe UG-01056 | 2020.11.09 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction to Intel® FPGA IP Cores..............................................................................3 1.1. IP Catalog and Parameter Editor.............................................................................. 4 1.1.1. The Parameter Editor................................................................................. 5 1.2. Installing and Licensing Intel FPGA IP Cores.............................................................. 5 1.2.1. Intel FPGA IP Evaluation Mode.....................................................................6 1.2.2. Checking the IP License Status.................................................................... 8 1.2.3. Intel FPGA IP Versioning............................................................................. 9 1.2.4. Adding IP to IP Catalog...............................................................................9 1.3. Best Practices for Intel FPGA IP..............................................................................10 1.4. IP General Settings.............................................................................................. 11 1.5. Generating IP Cores (Intel Quartus Prime Pro Edition)...............................................12 1.5.1. IP Core Generation Output (Intel Quartus Prime Pro Edition)..........................13 1.5.2. Scripting IP Core Generation.................................................................... -
MCP3426/7/8 16-Bit, Multi-Channel ΔΣ Analog-To-Digital Converter with I2C™ Interface and On-Board Reference
MCP3426/7/8 16-Bit, Multi-Channel ΔΣ Analog-to-Digital Converter with I2C™ Interface and On-Board Reference Features Description • 16-bit ΔΣ ADC with Differential Inputs: The MCP3426, MCP3427 and MCP3428 devices - 2 channels: MCP3426 and MCP3427 (MCP3426/7/8) are the low noise and high accuracy - 4 channels: MCP3428 16 Bit Delta-Sigma Analog-to-Digital (ΔΣ A/D) Con- verter family members of the MCP342X series from • Differential Input Full Scale Range: -V to REF Microchip Technology Inc. These devices can convert +V REF analog inputs to digital codes with up to 16 bits of reso- • Self Calibration of Internal Offset and Gain per lution. Each Conversion The MCP3426 and MCP3427 devices have two • On-Board Voltage Reference (V ): REF differential input channels and the MCP3428 has four - Accuracy: 2.048V ± 0.05% differential input channels. All electrical properties of - Drift: 15 ppm/°C these three devices are the same except the • On-Board Programmable Gain Amplifier (PGA): differences in the number of input channels and I2C - Gains of 1,2, 4 or 8 address bit selection options. • INL: 10 ppm of Full Scale Range These devices can output analog-to-digital conversion • Programmable Data Rate Options: results at rates of 15 (16-bit mode), 60 (14-bit mode), or 240 (12-bit mode) samples per second depending on - 15 SPS (16 bits) the user controllable configuration bit settings using the - 60 SPS (14 bits) two-wire I2C serial interface. During each conversion, - 240 SPS (12 bits) the device calibrates offset and gain errors • One-Shot or Continuous Conversion Options automatically. -
NOTICE of ANNUAL MEETING of STOCKHOLDERS April 23, 2001 ______
NOTICE OF ANNUAL MEETING OF STOCKHOLDERS April 23, 2001 ________________ To the Stockholders of Synopsys, Inc.: NOTICE IS HEREBY GIVEN that the Annual Meeting of Stockholders of Synopsys, Inc., a Delaware corporation (the “Company”), will be held on Monday, April 23, 2001, at 4:00 p.m., local time, at the Company’s principal executive offices at 700 East Middlefield Road, Mountain View, California 94043, for the following purposes: 1. To elect eight directors to serve for the ensuing year or until their successors are elected. 2. To approve an amendment to the Company’s Employee Stock Purchase Plan and International Employee Stock Purchase Plan to increase the number of shares of Common Stock reserved for issuance thereunder by 1,200,000 shares. 3. To approve an amendment to the 1992 Stock Option Plan to extend the term of the Plan from January 2002 to January 2007. 4. To ratify the appointment of KPMG LLP as independent auditors of the Company for fiscal year 2001. 5. To transact such other business as may properly come before the meeting or any adjournment or adjournments thereof. The foregoing items of business are more fully described in the Proxy Statement accompanying this Notice. Only stockholders of record at the close of business on February 26, 2001 are entitled to notice of and to vote at the meeting. All stockholders are cordially invited to attend the meeting in person. However, to assure your representation at the meeting, you are urged to sign and return the enclosed proxy (the “Proxy”) as promptly as possible in the envelope enclosed. -
PICMASTER™ Support of Microsoft ® Windows™
PICMASTER Support of Microsoft Windows DDE AN584 PICMASTER™ Support of Microsoft® Windows™ DDE The PICMASTER system supports Windows Dynamic 5. You will see the trace buffer fill with instructions and Data Exchange (DDE). This feature allows the contents data if those instructions were executed and trace of the trace buffer to be transferred to other windows enabled. If you do not see any instructions in the applications such as Microsoft Excel™. This feature is trace buffer, check the Trace Settings in (1) and look invaluable to control systems designers who would like for loops or deadlock situations that would prevent to plot real-time data to debug and fine tune an applica- your program from executing these instructions. tion. This application note will show how to set this up Note: PICMASTER must be running and the trace and graph system data. buffer open with data displaying in order to use DDE for other Windows applications (such as THE TRACE BUFFER Microsoft Excel as described in the next section). The PICMASTER contains a 8K x 40 bit trace buffer. The fields within this buffer are broken up into three SETTING UP EXCEL categories: After starting Excel with a blank spread sheet, select 100 (1) Current Address of instruction 16-Bits (ADDRESS) rows in the first column by pressing the left mouse button (2) Data/Opcode Field 16-Bits (DATA) and holding it down to drag across all cells. Next Type the following string in the box: (3) External Logic Analyzer inputs 8-Bits (EXT) 5 ————— =PICMASTR|’c:\path\test.hex’!’data 0 99’ 40-Bits and hit CNTRL+SHIFT+ENTER Any instruction can be optionally traced or not traced; the The format for this command is as follows: trace for each instruction is enabled by the “T” field on the =PICMASTR|’<hex_file>‘!’<string> far left column of the program memory dump window. -
AN1630A USB to I2C Bridge Reference Guide
AN1630A USB to I²C Bridge Reference Guide Author: Dale Herman Microchip Technology INTRODUCTION Microchip’s SCSI USB to I²CTM bridge devices provide a USB to I²C bridge. The I²C bridge utilizes SCSI pass-through commands using the Mass Storage Class driver. The internal hub can have e.g., three ports enabled with two exposed externally. This document includes the following topics: • Example of a USB to I²C Bridge Environment on page 1 • SCSI Pass-through Commands on page 3 EXAMPLE OF A USB TO I²C BRIDGE ENVIRONMENT Figure 1 provides an example how the USB to I²C bridge can be integrated in an environment. FIGURE 1: USB TO I²C BRIDGE ENVIRONMENT (EXAMPLE) Automotive Head Unit / Navigation USB Cable Microchip USB Hub with SCSI USB to I²C Bridge 3-Port USB 2.0 HS Hub I²C Bridge Conversion USB HS Flash Media Reader USB 2.0 Down-stream Port 2.0 Down-stream USB Port 2.0 Down-stream USB USB I²C nReset Cable USB Device I²C Slave 2014 Microchip Technology Inc. DS00001630A-page 1 AN1630A Figure 2 depicts which function blocks are involved in such an example environment. FIGURE 2: USB TO I²C BRIDGE AS FBLOCK IN THE EXAMPLE ENVIRONMENT Head Unit Application Operating System Application Protocol USB - I²C Bridge Other USB Mass Storage HUB Driver HID Class Device Class Class USB EHCI Driver or Equivalent DS00001630A-page 2 2014 Microchip Technology Inc. AN1630A SCSI PASS-THROUGH COMMANDS General Description of the Write_I²C_Stream Command A Write I²C Stream command sends any length of data over the I²C interface.