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Synopys VCS and VCS-MX Support, Quartus II Handbook Volume 3 3. Synopsys VCS and VCS MX Support November 2012 QII53002-12.1.0 QII53002-12.1.0 This chapter provides specific guidelines for simulation of Quartus® II designs with the Synopsys VCS or VCS MX software. You can also refer to the following for more information about EDA simulation: ■ For overview and version support information, Simulating Altera Designs in the Quartus II Handbook and About Using EDA Simulators in Quartus II Help. ■ For detailed GUI steps, Preparing for EDA Simulation and Running EDA Simulators in Quartus II Help. ■ The VCS User Guide installed with the VCS software, and the Synopsys VCS Simulation Design Example page. Quick Start Example (VCS Verilog) You can adapt the following RTL simulation example to get started quickly with VCS: 1. Specify your EDA simulator and executable path in the Quartus II software: set_user_option -name EDA_TOOL_PATH_VCS <VCS executable path>r set_global_assignment -name EDA_SIMULATION_TOOL "VCS"r 2. Compile simulation model libraries using one of the following: ■ Run NativeLink RTL simulation to compile required design files, simulation models, and run your simulator. Verify results in your simulator. Skip steps 3 through 4. ■ Use Simulation Library Compiler to generate the simlib_comp.vcs options file that contains VCS command-line arguments specifying required simulation models. 3. Modify the simlib_comp.vcs file to specify your design and testbench files. 4. Run the VCS simulator: vcs -R -file simlib_comp.vcs VCS and VCS MX Guidelines The following guidelines apply to simulating Quartus II designs in the VCS or VCS MX software: ■ Do not specify the -v option for altera_lnsim.sv because it defines a systemverilog package. ■ Add -verilog and +verilog2001ext+.v options to make sure all .v files are compiled as verilog 2001 files, and all other files are compiled as systemverilog files. © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its ISO semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008 services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Quartus II Handbook Version 13.1 Volume 3: Verification November 2012 Twitter Feedback Subscribe 3–2 Chapter 3: Synopsys VCS and VCS MX Support VCS and VCS MX Guidelines ■ Add the -lca option for Stratix V and later families because they include IEEE- encrypted simulation files for VCS and VCS MX. ■ Add -timescale=1ps/1ps to ensure picosecond resolution. Disabling Timing Violation on Registers In certain situations, you may want to ignore timing violations on registers and disable the “X” propagation that occurs (for example, timing violations in internal synchronization registers in asynchronous clock-domain crossing). By default, the x_on_violation_option logic option applying to all design registers is On, resulting in an output of “X” at timing violation. To disable “X” propagation at timing violations on a specific register, set the x_on_violation_option logic option to Off for that register. The following command is an example from the Quartus II Settings File (.qsf): set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to \ <register_name> Simulating Transport Delays By default, the VCS software filters out all pulses that are shorter than the propagation delay between primitives. Turning on the transport delay options in the VCS software prevents the simulation tool from filtering out these pulses. Use the following options to ensure that simulation results include all signal pulses. Table 3–1 describes the transport delay options. Table 3–1. Transport Delay Options Option Description Use when simulation pulses are shorter than the delay in +transport_path_delays a gate-level primitive. You must include the +pulse_e/number and +pulse_r/number options. Use when simulation pulses are shorter than the +transport_int_delays interconnect delay between gate-level primitives. You must include the +pulse_int_e/number and +pulse_int_r/number options. 1 The +transport_path_delays and +transport_path_delays options apply by default during NativeLink gate-level timing simulation. The following VCS software command runs a post-synthesis simulation: vcs -R <testbench>.v <gate-level netlist>.v -v <Altera device family \ library>.v +transport_int_delays +pulse_int_e/0 +pulse_int_r/0 \ +transport_path_delays +pulse_e/0 +pulse_r/0 r Generating Power Analysis Files To run power analysis in the Quartus II software, you must first generate a Verilog Value Change Dump File (.vcd) in the Quartus II software, and then run the .vcd from the VCS software. You can then use this .vcd for power analysis in the Quartus II PowerPlay power analyzer. To use a.vcd for power analysis, follow these steps: Quartus II Handbook Version 13.1 November 2012 Altera Corporation Volume 3: Verification Chapter 3: Synopsys VCS and VCS MX Support 3–3 VCS and VCS MX Guidelines 1. In the Quartus II software, click Settings on the Assignments menu. 2. Click Simulation under EDA Tool Settings. 3. Turn on Generate Value Change Dump file script, specify the type of output signals to include, and specify the top-level design instance name in your testbench. 4. On the Processing menu, click Start Compilation. 5. Include the script in your testbench file where the design under test (DUT) is instantiated: include <revision_name>_dump_all_vcd_nodes.v r 1 Include the script within the testbench module block. If you include the script outside of the testbench module block, syntax errors occur during compilation. 6. Run the simulation with the VCS command. Exit the VCS software when the simulation is finished and the <revision_name>.vcd file is generated in the simulation directory. f For detailed instructions about generating a .vcd file and running power analysis, refer to the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook. Simulation Setup Script Example The Quartus II software can generate a simulation setup script for IP cores in your design. The scripts for VCS and VCS MX are vcs_setup.sh (for Verilog HDL or SystemVerilog) and vcsmx_setup.sh (combined Verilog HDL and SystemVerilog with VHDL). The scripts contain shell commands that compile the required simulation models in the correct order, elaborate the top-level design, and run the simulation for 100 time units by default. You can run these scripts from a Linux command shell. Read the generated .sh script to see the variables that are available for override when sourcing the script or redefining directly if you edit the script.To set up the simulation for a design such as Example 3–1, use the command-line to pass variable values to the shell script, as illustrated in Example 3–2 on page 3–4 and Example 3–3 on page 3–4. You can alternatively create a shell script that contains these commands. Example 3–1. Using Command-line to Pass Simulation Variables sh vcsmx_setup.sh\ USER_DEFINED_ELAB_OPTIONS=+rad\ USER_DEFINED_SIM_OPTIONS=+vcs+lic+wait November 2012 Altera Corporation Quartus II Handbook Version 13.1 Volume 3: Verification 3–4 Chapter 3: Synopsys VCS and VCS MX Support Document Revision History You can edit the .sh script to add simulator commands that compile the top-level simulation HDL file. Example 3–2. Example Top-Level Simulation Shell Script for VCS-MX # Run generated script to compile libraries and IP simulation files # Skip elaboration and simulation of the IP variation sh ./ip_top_sim/synopsys/vcsmx/vcsmx_setup.sh SKIP_ELAB=1 SKIP_SIM=1 QSYS_SIMDIR="./ip_top_sim" #Compile top-level testbench that instantiates IP vlogan -sverilog ./top_testbench.sv #Elaborate and simulate the top-level design vcs –lca –t ps <elaboration control options> top_testbench simv <simulation control options> Example 3–3. Example Top-Level Simulation Shell Script for VCS # Run script to compile libraries and IP simulation files sh ./ip_top_sim/synopsys/vcs/vcs_setup.sh TOP_LEVEL_NAME=”top_testbench”\ # Pass VCS elaboration options to compile files and elaborate top-level passed to the script as the TOP_LEVEL_NAME USER_DEFINED_ELAB_OPTIONS="top_testbench.sv"\ # Pass in simulation options and run the simulation for specified amount of time. USER_DEFINED_SIM_OPTIONS=”<simulation control options> Document Revision History Table 3–2 shows the revision history for this chapter. Table 3–2. Document Revision History (Part 1 of 2) Date Version Changes November 2012 12.1.0 Relocated general simulation information to Simulating Altera Designs. June 2012 12.0.0 Removed survey link. Template update. November 2011 11.0.1 Minor editorial updates. ■ Linked to Help for Stratix V Libraries May 2011 11.0.0 ■ Added SystemVerilog HDL information ■ Editorial updates throughout December 2010 10.0.1 Changed to new document template. No change to content. ■ Linked to Quartus
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