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Libero Soc Design Flow User Guide

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Libero Soc Design Flow User Guide SmartFusion®2, IGLOO®2, RTG4™ Libero® SoC Design Flow User Guide Introduction Microchip Libero System-on-Chip (SoC) design suite offers high productivity with its comprehensive, easy to learn, easy to adopt development tools for designing with Microchip’s power efficient flash FPGAs, SoC FPGAs, and Rad- Tolerant FPGAs. To access datasheets and silicon user guides, visit www.microsemi.com, select the relevant product family and click the Documentation tab. Tutorials, Application Notes, Development Kits & Boards are listed in the Design Resources tab. Click the following links for additional information: • Libero SoC– Learn more about Libero SoC including Release Notes, a complete list of devices/packages, and timing and power versions supported in this release. • Programming – Learn more about Programming Solutions. • Power Calculators – Find XLS-based estimators for device families. • Licensing – Learn more about Libero licensing. © 2020 Microchip Technology Inc. User Guide DS00003765A-page 1 SmartFusion®2, IGLOO®2, RTG4™ Table of Contents Introduction.....................................................................................................................................................1 1. Libero SoC v12.6 Overview.................................................................................................................... 6 1.1. Welcome to Microchip Libero SoC v12.6..................................................................................... 6 1.2. Libero SoC Design Flow - SmartFusion2, IGLOO2, and RTG4................................................. 13 1.3. Constraint Flow and Design Sources.........................................................................................15 1.4. Supported Families.................................................................................................................... 17 1.5. File Types in Libero SoC............................................................................................................ 17 1.6. Software Tools - Libero SoC.......................................................................................................19 1.7. Software IDE Integration............................................................................................................ 19 2. Libero Design Flow SmartFusion2, IGLOO2, and RTG4...................................................................... 21 2.1. Starting the Libero GUI...............................................................................................................21 2.2. Design Report............................................................................................................................ 22 2.3. Using the Libero SoC New Project Wizard.................................................................................23 3. Create and Verify Design...................................................................................................................... 33 3.1. System Builder........................................................................................................................... 33 3.2. MSS - SmartFusion2 only.......................................................................................................... 33 3.3. Create with SmartDesign........................................................................................................... 35 3.4. Create Core from HDL............................................................................................................... 42 3.5. Designing with HDL....................................................................................................................44 3.6. Designing with Block Flow..........................................................................................................47 3.7. Verify Pre-Synthesized Design - RTL Simulation....................................................................... 47 4. Libero SoC Constraint Management.....................................................................................................52 4.1. Invocation of Constraint Manager from the Design Flow Window..............................................52 4.2. Libero SoC Design Flow.............................................................................................................52 4.3. Introduction to Constraint Manager............................................................................................53 4.4. Import a Constraint File..............................................................................................................57 4.5. Constraint Types........................................................................................................................ 61 4.6. Constraint Manager – I/O Attributes Tab....................................................................................62 4.7. IO Advisor (SmartFusion2, IGLOO2, and RTG4).......................................................................64 4.8. Constraint Manager – Timing Tab.............................................................................................. 70 4.9. Derived Constraints....................................................................................................................73 4.10. Constraint Manager – Floor Planner Tab................................................................................... 74 4.11. Constraint Manager – Netlist Attributes Tab...............................................................................75 5. Implement Design................................................................................................................................. 77 5.1. Synthesize..................................................................................................................................77 5.2. Verify Post-Synthesized Design................................................................................................. 81 5.3. Configure Flash*Freeze............................................................................................................. 82 5.4. Configure Register Lock Bits......................................................................................................83 5.5. Constraint Flow in Implementation.............................................................................................84 5.6. Place and Route - SmartFusion2, IGLOO2, RTG4.................................................................... 89 5.7. Multiple Pass Layout Configuration (SmartFusion2, IGLOO2, RTG4)....................................... 93 5.8. Resource Usage (SmartFusion2, IGLOO2, RTG4)....................................................................95 © 2020 Microchip Technology Inc. User Guide DS00003765A-page 2 SmartFusion®2, IGLOO®2, RTG4™ 5.9. Global Net Report.......................................................................................................................96 5.10. Verify Post Layout Implementation...........................................................................................102 6. Configure Hardware............................................................................................................................ 124 6.1. Programming Connectivity and Interface................................................................................. 124 6.2. Select and Configure Actions and Procedures.........................................................................125 6.3. Programmer Settings............................................................................................................... 126 6.4. Select Programmer.................................................................................................................. 128 7. Program Design.................................................................................................................................. 130 7.1. Generate FPGA Array Data..................................................................................................... 130 7.2. Configure Actions and Procedures...........................................................................................135 7.3. Configure I/O States During JTAG Programming.....................................................................138 7.4. Configure Programming Options (SmartFusion2 and IGLOO2)...............................................139 7.5. Configure Programming Options (RTG4 Only)........................................................................ 141 7.6. Configure Security....................................................................................................................144 7.7. Configure Bitstream..................................................................................................................153 7.8. Generate Bitstream.................................................................................................................. 154 7.9. Run Programming Device Actions - SmartFusion2, IGLOO2, RTG4.......................................154 8. Debug Design..................................................................................................................................... 166 8.1. Generate SmartDebug FPGA Array Data................................................................................ 166 8.2. SmartDebug............................................................................................................................. 166 8.3. Identify Debug Design..............................................................................................................167
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