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EEC 170: Computer Architecture Summary of Multicycle Datapath Example Multicycle Datapath Our Control Model Control Spec For

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EEC 170: Computer Architecture Summary of Multicycle Datapath Example Multicycle Datapath Our Control Model Control Spec For Summary of Multicycle Datapath Differences from single cycle: EEC 170: Computer Architecture • All intermediate results -> intermediate registers • Logical RTL -> more complex physical RTL • Possible reuse of hardware (as in book) Goal: Multicycle Control / • Not all instructions take same amount of time Microprogramming •Savings from shorter instructions • Costs: •More hardware (intermediate registers, control) •Imbalance between cycles © John Owens / UCD 2003 This is only an intermediate representation! Example Multicycle Datapath Our Control Model State => set up control logic for Register Transfer State + Inputs => next state RegDst State + Inputs => next state Equal RegWr MemToReg MemRd MemWr nPC_sel E ALUctr ALUSrc ExtOp Transfer occurs upon exiting state (same clock edge) Reg A S Reg. File inputs (conditions) File Ext ALU IR PC B Next PC M Next State Mem State X Access Logic Register Transfer Control Points Data Mem Fetch Fetch Control State Operand Instruction Result Store Depends on Input Critical Path? Output Logic outputs (control points) Control Spec for multicycle proc Traditional FSM Controller IR <= MEM[PC] “instruction fetch” next state op cond state control points A <= R[rs] “decode / operand fetch” B <= R[rt] LW R-type ORi SW BEQ Truth Table S <= A fun B S <= A or ZX S <= A + SX S <= A + SX PC <= next control points Next(PC,Equal) State 11 Execute Equal 6 M <= MEM[S] MEM[S] <= B PC <= PC + 4 Memory R[rd] <= S R[rt] <= S R[rt] <= M 4 State PC <= PC + 4 PC <= PC + 4 PC <= PC + 4 op NextState = f(state, Write-back datapath State op, conditions) 1 datapath + state diagram ⇒⇒ control) Mapping Register Transfers to Control Points IR <= MEM[PC] “instruction fetch” Translate RTs into control points imem_rd, IRen A <= R[rs] Assign states B <= R[rt] “decode” Aen, Ben, Een LW Then go build the controller R-type ORi SW BEQ S <= A fun B S <= A or ZX S <= A + SX S <= A + SX PC <= ALUfun, Sen Next(PC,Equal) Execute M <= MEM[S] MEM[S] <= B PC <= PC + 4 R[rd] <= S PC <= PC + 4 Memory RegDst, R[rt] <= S R[rt] <= M RegWr, PC <= PC + 4 PCen PC <= PC + 4 Write-back Assigning States (Mostly) Detailed Control Specs (missing⇒0) State Op field Eq Next IR PC Ops Exec Mem Write-Back IR <= MEM[PC] “instruction fetch” 0000 en sel A B E Ex Src ALU S R W M R-M Wr Dst 0000 ?????? ? 0001 1 A <= R[rs] “decode” 0001 BEQ x 0011 1 1 1 B <= R[rt] 0001 R-type x 0100 1 1 1 -all same in Moore machine 0001 0001 ORI x 0110 1 1 1 0001 LW x 1000 1 1 1 Setting control signals: not LW R-type ORi SW 0001 SW x 1011 1 1 1 much different than SC! BEQ S <= A fun B S <= A or ZX S <= A + SX S <= A + SX PC <= Next(PC) BEQ: 0011 xxxxxx 0 0000 1 0 x 0 x 0100 0110 1000 1011 0011 0011 xxxxxx 1 0000 1 1 x 0 x Execute R: 0100 xxxxxx x 0101 0 1 fun 1 0101 xxxxxx x 0000 1 0 0 1 1 M <= MEM[S] MEM[S] <= B ORi: 0110 xxxxxx x 0111 0 0 or 1 PC <= PC + 4 1001 0111 xxxxxx x 0000 1 0 0 1 0 1100 Memory LW: 1000 xxxxxx x 1001 1 0 add 1 R[rd] <= S R[rt] <= S R[rt] <= M 1001 xxxxxx x 1010 1 0 1 PC <= PC + 4 PC <= PC + 4 PC <= PC + 4 1010 xxxxxx x 0000 1 0 1 1 0 0101 0111 1010 SW: 1011 xxxxxx x 1100 1 0 add 1 Write-back 1100 xxxxxx x 0000 1 0 0 1 0 Controller Design Example: Jump-Counter The state diagrams that define the controller for an i i instruction set processor are highly structured zero0000 inc load Use this structure to construct a simple i+1 “microsequencer” Control reduces to programming this very simple device Map ROM None of above: Do nothing op-code • ⇒ microprogramming sequencer datapath control (for wait states) control • Goal: Simpler implementation! microinstruction zero inc Counter micro-PC load sequencer 2 Using a Jump Counter Our Microsequencer IR <= MEM[PC] “instruction fetch” 0000 inc A <= R[rs] “decode” B <= R[rt] 0001 load taken LW R-type ORi SW BEQ datapath control S <= A fun B S <= A or ZX S <= A + SX S <= A + SX PC <= Next(PC) Z I L 0100 0110 1000 1011 0011 Execute inc inc inc inc Micro-PC Zero zero M <= MEM[S] MEM[S] <= B Increment 1001 PC <= PC + 4 op-code 1100 Memory Load inc Map ROM R[rd] <= S R[rt] <= S R[rt] <= M PC <= PC + 4 PC <= PC + 4 Stores “Load” -> Simpler than next state PC <= PC + 4 zero 0101 0111 1010 zero zero Write-back zero Microprogram Control Specification Adding the Dispatch ROM µPC Taken NextIR PC Ops Exec Mem Write-Back Sequencer-based control en sel A B Ex Sr ALU S R W M M-R Wr Dst • Called “microPC” or “µPC” vs. state register 0000 ? inc 1 0001 x load 1 1 Control Value Effect 00 (Zero) Next µaddress = 0 0011 0 zero 1 0 BEQ 0011 0 zero 1 0 0011 1 zero 1 1 01 (Load) Next µaddress = 1 R: 0100 x inc 0 1 fun 1 dispatch ROM 0101 x zero 1 0 0 1 1 10 (Inc) Next µaddress = Adder microPC ORi: 0110 x inc 0 0 or 1 µaddress + 1 0111 x zero 1 0 0 1 0 Mux 1000 x inc 1 0 add 1 LW: 2 1 0 1001 x inc 1 0 1 0 1010 x zero 1 0 1 1 0 ROM: R-type 000000 0100 1010 x zero 1 0 1 1 0 µAddress ROM SW: 1011 x inc 1 0 add 1 BEQ 000100 0011 Select 1100 x zero 1 0 0 1 0 ori 001101 0110 Logic LW 100011 1000 SW 101011 1011 Opcode Example: Controlling Memory Controller handles non-ideal memory This controller is powerful! IR <= MEM[PC] “instruction fetch” wait Example: What to do if memory is not ready? ~wait A <= R[rs] “decode / operand fetch” B <= R[rt] PC taken datapath LW addr control R-type ORi SW BEQ InstMem_rd Instruction PC <= S <= A fun B S <= A or ZX S <= A + SX S <= A + SX Memory IM_wait Z I L Stall = !ZIL Next(PC) data Execute Inst. Reg IR_en Micro-PC M <= MEM[S] MEM[S] <= B op-code ~wait wait Memory ~wait wait Map ROM R[rd] <= S R[rt] <= S R[rt] <= M PC <= PC + 4 PC <= PC + 4 PC <= PC + 4 PC <= PC + 4 Write-back 3 Multicycle Control Summary Announcements What’s the same as SC: • Midterm coming up next Wednesday (11/9) • Setting of control signals, generally • You can pick up your graded hw • HW #4 (chapter 5) is posted on class webpage What’s different from SC: • As usual, due Friday (11/11) at 5pm. • Must handle intermediate registers • Try to finish it before the mid-term. • New concept: states • I will be out of town next Monday (11/7) • Need way to get from one state to another • Christophe will be here to teach the class •Traditional FSM Controller • Mid-term review, problem solving, and questions •Jump table • Additional office hours before the test •Microcode • Wednesday (11/9) 11am-1pm End of Midterm Material Microprogramming sequencer datapath control For the midterm, you need to know up to this Inputs control slide µ-Code ROM • Know: microinstruction (µ) •Single cycle datapath/control •Multiple cycle datapath micro-PC µ-sequencer: Decode Decode fetch,dispatch, •Multiple cycle control, traditional FSM sequential To DataPath •Multiple cycle control, micro-sequencing Opcode Dispatch – This is actually in the CD (section 5.7 of the book) ROM • Reading: Up to and including Ch. 5 Microprogramming is a fundamental concept • implement an instruction set by building a very simple processor and interpreting the instructions • essential for very complex instructions and when few register transfers are possible • overkill when ISA matches datapath 1-1 Microprogramming “Macroinstruction” Interpretation Microprogramming is a convenient method for implementing User program plus Data structured control state diagrams: Main ADD Memory Random logic replaced by microPC sequencer and ROM SUB this can change! • AND . • Each line of ROM called a µinstruction: . contains sequencer control + values for control points . one of these is • limited state transitions: (jump table) DATA mapped into one of these branch to zero, next sequential, execution branch to µinstruction address from dispatch ROM unit Horizontal µCode: one control bit in µInstruction for every CPU control AND microsequence control line in datapath (like what we’ve done before) memory e.g., Fetch Instr Vertical µCode: groups of control-lines coded together in Fetch Operand(s) Calculate OR µInstruction (e.g. possible ALU dest) (new!) Save Answer(s) Control design reduces to Microprogramming • Part of the design process is to develop a “language” that describes control and is easy for humans to understand 4 Designing a Microinstruction Set Again: Alternative multicycle datapath (book) 1) Start with list of control signals Goal here: Horizontal -> Vertical Microcode 2) Group signals together that make sense (vs. PCWr PCWrCond PCSrc Zero random): called “fields” IorD MemWr IRWr RegDst RegWr ALUSelA 1 Mux 32 32 3) Place fields in some logical order PC 0 0 32 Mux Zero (e.g., ALU operation & ALU operands first and Instruction Reg Rs 0 Ra 32 Mux RAdr 5 32 ALU Rt ALU Out microinstruction sequencing last) 32 Rb busA A 1 32 Ideal 5 32 Mem Reg Data Reg File 1 0 Memory Rt Mux 4 0 4) To minimize the width, encode operations that Rw 32 WrAdr 32 B 32 Rd 1 32 Din Dout busW busB 32 will never be used at the same time - vertical 1 2 32 ALU 1 Mux 0 3 5) Create a symbolic legend for the microinstruction << 2 Control format, showing name of field values and how they set the control signals Extend Imm • Use computers to design computers 16 32 ALUOp ExtOp MemtoReg ALUSelB 1&2) Start with list of control signals, grouped into fields Compression of Fields Signal name Effect when deasserted Effect when asserted ALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs] Only look at writeback control signals: RegWrite None Reg.
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