High Frequency Inverter Using Power MOSFET

電気学会論文誌B 790

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UDC 621.314.572.018.3:621.382.323

Yoichi Hayashi Yoichi Okano Noriaki Sato Member Member Member

Summary In this article, characteristics of a square-wave inverter using power MOSFETs are described with 1 kW, 2 MHz breadboard model. Digital simulation of switching transients are performed with a practical equivalent circuit to evaluate switching losses. Although the time constant of the internal, gate circuit including the Miller effect of the gate-to-source capacitance is dominant factor, drain-to-source capacitance and circuit stray inductance significantly alter the switching transient at the turn-off period of power MOSFET. The drain-to-source capacitance increases the switching time, although it slightly decreases switching energy. The circuit stray inductance must be minimized to decrease the transient overvoltage and switching energy.

losses are investigated with a practical equivalent 1.Introduction circuit. The latest semiconductor device technology is In the analysis of the switching transients of the achieving a remarkable progress. Especially, power power MOSFETs, the drain-to-surce capacitance MOSFETshave developed into practical application has been unually ignored assuming that its effect is since 1977as a new promisingdevice which is classified relatively small compared to the Miller effect of the into self turn-off capability. Power MOSFETshave a gate-to-drain capacitance. However, when the out- number of major advantages over bipolar transistors. put impedance of the gate-drive circuit is small and First, they have extremely fast switching speed free fast switchings occur, the drain-to-source capacitance from the minority carrier storage effect, because of cannot be ignored. The drain-to-source capacitance their majority carrier devices""". Second, they have acts like a snubber, decreases the rate of rise of the wider safe operating area without forming hot-spots drain-to-source voltage and reduces the Miller effect and easy parallel operation are obtained because of of the gate-to-drain capacitance. In order to evaluate the positive temperature coefficientof the on-resist- the switching loss more accurately, digital simulation ance°1. Third, they are voltage controlled; gate drive of the swithcing transients is performed considering power is negligible and control circuit becomessimple. the drain-to-source capacitance as well as other Usage of power MOSFETshaving these advantages parameters. is expected to increase greatly""". One of the major 2.Square-Wave Inverter Circuit applications is high frequency oscillator which plays a central role in ultrasonic generators, induction In Fig. 1, the tested square-wave voltage-fed bridge heating, electromagneticlevitation and so on. Power inverter circuit is shown. Each arm of the inverter MOSFETsincrease the frequency range up to a few consists of four power MOSFETs in parallel and a fast MHz where bipolar transistor could not apply. recovery diode connected in anti-parallel. Comple- In this article, characteristics of a square-wave mentary p-channel and n-channel MOSFETs are inverter using power MOSFETs are described with used. The maximum ratings and the typical electrical 1 kW, 2 MHz breadboard model, where switching characteristics are shown in Table 1. In Fig. 2, block diagram of the gate control scheme and the gate drive Yoichi Hayashi, Yoichi Okano & Noriaki Sato are with Department circuit are shown. The outline of control circuit is as of Electrical and Electronic Engineering, Tokyo Institute of Tech- nology. Manuscript received June 25, 1983, revised Feb. 20, 1984. follows. The frequency of inverter is determined by

本稿はSection E(Trans. I. E. E. of Japan, Vol. 104, No.7/8, July/Aug., p.153)からの転載である。

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Fig. 1. Main circuit of bridge-type square-wave inverter. Table 1. Absolute maximum ratings and typical electrical characteristics of power MOSFETs and fast recovery diode. (a) Power MOSFETs. Fig. 3. Voltages of logic circuit, gate voltages and output voltage.

100ns between each pulse as shown in Fig. 3. The signals VAand VVin turn produce gate drive voltages from Vg,to Vg, which have two levels; +5 V or -5 V for off-periods and + 10 V or -10 V for on-periods. The time intervals of 100ns prevent the short- circuit through MOSFETs T1 and T2 (or T3 and T4). The output impedances of the gate drive circuits are reduced by connecting V-groove MOSFETs in series in order to shorten the charge and discharge times of gate-to-source capacitances of main power MOSFETs. 3.Analysis of Switching Loss Considerthe case of parallel number of MOSFETs being unity for simplicity,then the equivalent circuit (b) Fast recovery diode (UES1306) for MOSFET is shown in Fig. 4, where Cgs, Cd5 and Cgd are gate-to-source, drain-to-source and gate-to-drain capacitances at switching,respectively. Resistances rg and rds and inductance ld belong to the bulk of MOSFET and cannot be neglected at switching. The transfer characteristics of MOSFET can be approximatedby the following equations.

The equivalent circuit of the inverter is shown in Fig. 5, when load current flows from T3 via load to T2 and then off-gate-signals are applied to T2 and T3, which corresponds to t•¬to in Fig. 3. The load Fig. 2. Block diagram of control circuit, and gate current is assumed constant, because the load in- drive circuit. ductance of most resistive loads is large enough to voltage controlled oscillator (VCO). The signal from keep a smooth current during the switching interval VCO is shaped to complementary square wave with of MOSFET. Then, the following relations exist. 50% duty cycle by Flip Flop circuit, then Logic circuit produces voltage VA and VB which have intervals of

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Fig. 4. Equivalent circuit for power MOSFET at switching.

Fig. 6. Theoretical waveforms for switching of T2 (n-channel MOSFET) from on Fig. 5. Equivalent circuit of inverter at swithcing state to off state. of T2 from on state to off state. state to active state. The internal gate voltage changes by the following relation after the step change of external gate voltage.

If we put vas-v85, at the end of delay time, load current l becomes k(vgs1- Vr)2/2 where Vr is threshold voltage. Calculated delay time for n-channel and p-channel MOSFETs by Eq. (8) are 22 ns and 12 ns, respectively. Rise time 1 begins from the transition to active state and ends when the anti-paralleled diode of complementary MOSFET conducts. The rate of rise of drain-to-source voltage ad5nis so large that current flows through the capacitance Cgdn to gate, which delays the exponential rise of gate-to-source voltage and slows down the rate of rise of Vd5nand switching speed. This negative feedback effect is larger for p- channel. MOSFET than n-channel MOSFET. The rates of rise of VdS,,for n-channel and p-channel MOSFET are calculated 8.0 V/ns and 6.4V/ns, respec- where is is the instant when diode D1 begins to con- tively. Rise time 2 begins when the anti-paralleled duct and suffixes p and n designate p-channel and n- diode of complementary MOSFET conducts and ends channel, respectively. From Eqs. (1) (7), calculated when the drain current of the switched MOSFET examples of voltage and current versus time at switch- ceases conducting. Ringing occurs in this time by the ing of T2 from on-state to off-state are shown in Fig. circuit of DC source voltage, inductances and 6. In this case, the drain-to-source capacitance Cdap, capacitances around switched MOSFET and comple- Cdsn,are varied as a function of the drain-to-source mentary MOSFET. voltage, which is determined by the experiments. It is noticed here that the switching loss at turn-on The turn-off switching time is divided into three interval is essentially null, because the current flowing intervals ; delay time ti, rise time 1 (t2 to t1) and rise anti-paralleled diode keeps the drain-to-source volt- time 2 (t3 to t2). The delay time is the time between age nearly zero while the internal gate voltage is the step change of external gate voltage (from +10 V brought to enough level for transition from off-state to to -5 V) and the beginning of the transition from on on-state.

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Table 2. Effect of circuit stray inductance on switching energy.

Fig, 7. Effects of drain-to-source capacitance Fig. 8. Oscillograms of voltages and currents on switching transients. of inverter at 1 MHz, Vb=60 V, Io= 4.4 A. The switching loss energies per a transition for p-

and n-channel MOSFETs are calculated at 19.5 pJ and that of current probe. Voltage and current waveforms 12.7ƒÊJ, respectively. The effect of circuit stray in- at 1 MHz are shown in Fig. 8. Current i and i2 were ductance l1 on switching energy is shown in Table 2. sums of drain current and anti-paralleled diode cur- To clarify the effects of the drain-to-source rent. From gate current and gate-to-source voltage capacitances on switching transients, two calculated waveforms, internal gate resistance re and gate

examples for different values of the drain-to-source capacitance Cgs for n-channel MOSFET are calcu- capacitance are shown in Fig. 7. The drain-to-source lated at 69ƒ¶ and 790 pF, respectively. capacitance Cdsp , Cdsn, are 20 pF in Fig. 7 (a) and 200 Drain current and anti-paralleled fast-recovery pF in Fig. 7 (b). Although other parameters are iden- diode current at 250 kHz are shown in Fig. 9. Reverse tical, switching waveformes of (a) and (b) are current flows in n-channel MOSFET when current

greatly different from one other. The drain-to-source flows in anti-paralleled diode, because p-n junction capacitances slows down the rise of the drain-to- between drain and substrate acts as a parasitic diode

source voltage and speeds up the fall of the drain through the connection of source and substrate and its current. The switching loss energy per a turn off threshold voltage is comparable to that of the anti-

interval calculated at 12.2 ƒÊJ for (b) and 25% less paralleled diode. On the otherhand, at p-channel than 16.5 ƒÊJ for (a). These results show that the MOSFET, threshold voltage of this parasitic diode

output capacitances must be considered for the accu- (1.0 V) is higher than that of the anti-paralleled diode rate evaluation of the switching transients. (0.6 V). Thus, no reverse current flows. In Fig. 10, waveforms at transition to off for n- 4.Results channel MOSFET are shown with expanded time scale.

Oscillograms were taken in the case of parallel Where load current I0= 6.3 A and DC supply voltage number of MOSFETs being unity, because insertion Vb=100 V. Drain current lags drain-source voltage impedance of the current probe (0.2 0 at 25 MHz) by 20 ns because of the delay time of the current probe.

disturbed the current sharing between paralleled Theoretical waveforms in Fig. 10 agree with the oscil- MOSFETs whose on-resistances were comparable to logram. Switching energy ES was calculated at 12.3 ƒÊJ

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Fig. 10. Drain voltage and current of N-channel MOSFET at turn-off interval (right, theoretical waveforms).

Fig. 9. Oscillograms of drain and anti- paralleled diode current at Fig. 11. Switching energy ES versus input 250 kHz. DC voltage.

from measured waveforms, considering the delay time in Fig. 9 with N=4, Ps is expressed as of drain current caused by the current probe, and agreed with the theoretical value of 12.7 p3. Rise time On the other hand, conduction loss Pr is expressed as tr of drain-to-source voltage and fall time tf of drain current are about 18 ns and 50 ns, respectively. For p- channel MOSFET, these values were a little large (tr =25 ns, tf=60 ns), because of the large time constant Cgsrg and gate-to-drain capacitance. In Fig. 11, relations of measured switching energy ES and power supply voltage Vb are shown. Load and frequency are the same as those for Fig. 10. It is found where that Es for both n-and p-channel MOSFET are nearly proportional to Vb3.The reason is that not only drain current but also switching time is nearly proporitional to Vb, because the rate of rise of drain-to-source ronp and ronn are on-resistances of p-and n-channel voltage and the rate of fall of drain current are limited MOSFETs, respectively. The initial value of load by Miller effect and the time constant Cpsrg, respec- current I0 is expressed as follows. tively. In spite of the larger values of tr and tf, switching energy of p-channel MOSFET was almost

the same with that of n-channel MOSFET, because Examination of Eq. (11) reveals that conduction loss is the transient peak value (122 V at Vb=100 V) of drain- independent of frequency when a (and power factor)

to-source voltage was smaller than that of n-channel is constant. MOSFET (137 V). Switching and conduction losses versus frequency

Switching loss of the inverter Ps is given by the are shown in Fig. 12, with a (or power factor) as a

following equation. parameter, where Vb=100 V, I0=25.2 A, ronp=ronn= 1ƒ¶ and N=4. Crossover frequency is 1.0 MHz for

where N is number of paralleled MOSFETs, Eep and power factor of 0.85 and it becomes lower for smaller Esn, are switching energy per switching for p-and n- power factor. channel MOSFETs, respectively. Under the condition Output power is given by the following relation.

<92> 104巻11号 795 パワーMOSFET高周波インバータ

Fig. 12. Switching and conduction losses of Fig. 14. Efficiency of inverter versus output inverter Ps, Pr versus frequency at power as parameters of load resistance and frequency.

Above relation shows that efficiency is determined only by the ratio of load resistance to on-resistance of MOSFET. In Fig. 14, efficiency of about 85% is

obtained for resistive load of 10ƒ¶ at frequency of 2 MHz and output of 1kW. Efficiency decreases as frequency increases, because of the increase of switching and no-load losses. With higher frequency, efficiency decreases as output power increases, because

Fig. 13. No-load loss Pc versus input DC switching loss increases nearly proportional to the voltage for several frequency. cube of DC input voltage. The current sharing in four paralleled MOSFETs could not be measured, because insertion impedance of current probe is comparable to on-resistance.

However, excess heating of any MOSFET in parallel When Vb=100 V, I0=25.2 A, f=250 kHz, RL= 2.67 ƒ¶ was not observed and stable parallel operation(up to and LL=2.88 ƒÊH, output power, switching and con- total power dissipation of 30% of absolute maximum duction losses and efficiency are estimated at 723 W, rating) could be obtained without special selection

46 W, 110 W and 82.2%. of MOSFETs. At no-load, there exists losses caused by charging 5.Conclusion and discharging of drain-to-source capacitances.

Dissipation energy CdsV2b per one cycle of charging Digital simulation of switching transients for a

and discharging results in no-load loss Pc of the square-wave bridge inverter using power MOSFETs inverter given as follows. and experiments for a breadboard model are performed. It was loaded maximum 1 kW at 2 MHz by In Fig, 13, measured Pc versus Vb are shown with four paralleled MOSFETs which had rated drain frequency as a parameter. In this figure, no-load loss voltage of 200 V and maximum drain loss of 125 W by is almost proportional to frequency and nearly propor- designing the gate drive circuit with a sufficient high tional to the square of Vb, because drain-to-source speed. capacitance decreases as Vb increases. The maximum frequency of the inverter for the

In Fig. 14, measured efficieny for resistive loads inductive loads is mainly determined by the switching

(10ƒ¶ and 2.5ƒ¶) are shown for various values of time at the turn-off period. The switching transients frequency. If frequency is low enough to neglect at the turn-on can be ignored because the regenerative switching and no-load losses, efficiency of the inverter current through the anti-paralleled diode keeps the for resistive load is derived from.Egs.(11) and (13). drain-to-source voltage nearly zero. Although the

gate-to-source capacitance, internal gate resistance and the gate-to-drain capacitance are dominant factors

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for the switching at turn-off, the drain-to-source References capacitance and the circuit stray inductance alter the (1) S. Clemente & B. R. Pelly: "Understanding power MOSFET transients waveforms significantly. The drain-to- switching performance", IEEE IAS Conference Record, p. 763 (1981) source capacitance increases the switching time, (2) J. B. Forsythe : "Predicting MOSFET dynamic switching although it slightly decreases the switching loss performance by Q-Loci",Proc. of IEEE/ISPCC, Orland,p. 45 energy. The circuit stray inductance must be minim- (1982) ized to decrease the ouervoltage transient at the turn (3) J. B. Forsythe : "Paralleling of power MOSFETs for higher -off power output", IEEE IAS Conference Record, p. 777 (1981) . In the breadboard model, the overvoltage tran- (4) International Rectifier, HEXFET DATABOOK (1981) sient was less than 40% of the DC supply voltage (5) P. Freudel :"Power MOSFETs or bipolar power transistors without any additional snubber circuit. for converter circuits?", Proc. of IEEE/ISPCC, Orland,p. 38 (1982)

〈94〉 104巻11号