Electronic Tuning Square-Wave Generators with Improved Linearity Using Operational Transresistance Ampliﬁer

Journal of Low Power Electronics and Applications

Article Electronic Tuning Square-Wave Generators with Improved Linearity Using Operational Transresistance Ampliﬁer

Pittala Chandra Shaker 1 and Avireni Srinivasulu 2,*

1 Department of Electronics and Communication Engineering, MLR Institute of Technology, Hyderabad 500043, India; [email protected] 2 Department of Electronics and Communication Engineering, JECRC University, Jaipur 303905, India * Correspondence: [email protected] or [email protected]; Tel.: +91-950-222-3336

Received: 25 March 2020; Accepted: 12 April 2020; Published: 14 April 2020

Abstract: Two new electronic tuning current-mode square-wave generators are introduced in the ensuing paper. In the first proposed square-wave generator circuit, one Operational Trans-resistance Amplifier (OTRA) and two passive components are involved, along with two NMOS depletion mode transistors. This circuit generates a square-wave with almost equal and fixed duty cycles. The second proposed circuit is able to control both on-duty and off-duty cycles independently with the help of two passive components, two NMOS depletion mode transistors, and two diodes connected to the circuit. The frequency of the proposed circuits can be adjusted with the passive components connected to the circuit. Moreover, electronic tuning can also be achieved with the proposed circuits. The measured results that are included in the paper show the linear variation of a time period as compared with existing OTRA based square waveform generator. The performance of the proposed circuits is examined while using SPICE models. These circuits are built on a laboratory breadboard using commercially available Current Feedback Operational Amplifier (AD844 AN) and passive components are connected externally and tested for square waveform generation. The obtained results demonstrate good agreement with the theoretical values.

Keywords: waveform generators; operational transresistance ampliﬁer; analog integrated circuit design; current mode waveform generators

1. Introduction The square-wave generator is widely operated in many electronic fields, such as digital, instrumentation, and communication systems. Conventionally, Operational Amplifier (Op-Amp) is used to generate square waveform along with some passive components. These voltage-mode (Op-Amp) circuits pose some drawbacks, such as complex internal circuitry, lower slew rate, constant gain bandwidth product, and more passive components are, however, required to generate the waveforms [1]. Recently, an alternative approach, called current-mode technology, has attracted considerable attention for analog circuit designers, due to its advantage over voltage-mode devices, like high performance, high linearity, wide dynamic range, low power consumption, simple circuitry, and versatility over voltage-mode devices [2]. Several waveform generators have been proposed using current-mode devices; these waveform generator circuits offer several advantages over voltage-mode waveform generators. The circuits that are given in [3–14] are designed with Voltage Differencing Buffered/Inverted Amplifier (VDIBA), Multiple Output Current Through Transconductance Amplifiers (MO-CTTA), Controlled Gain Current and Differential Voltage Amplifier

J. Low Power Electron. Appl. 2020, 10, 12; doi:10.3390/jlpea10020012 www.mdpi.com/journal/jlpea J. Low Power Electron. Appl. 2020, 10, 12 2 of 16 J. Low Power Electron. Appl. 2020, 10, x FOR PEER REVIEW 2 of 16

(CG-CDVA), Differential Voltage Current Conveyors (DVCC), and Operational Transconductance Transconductance Amplifiers (MO-CTTA), Controlled Gain Current and Differential Voltage Amplifier (OTA). These square-wave generators require external voltage or current biasing to produce Amplifier (CG-CDVA), Differential Voltage Current Conveyors (DVCC), and Operational the square waveform. Current Feedback Operational Amplifier (CFOA) based waveform generator Transconductance Amplifier (OTA). These square-wave generators require external voltage or was introduced in [15]. However, this waveform generator requires more passive components and two current biasing to produce the square waveform. Current Feedback Operational Amplifier (CFOA) active components. A single CFOA based waveform generator was proposed in [16]. The configuration based waveform generator was introduced in [15]. However, this waveform generator requires more of the circuit is simple with a few passive components. However, the oscillation frequencies are limited passive components and two active components. A single CFOA based waveform generator was to few kHz. Second generation Current Conveyor (CCII+) based waveform generators were proposed proposed in [16]. The configuration of the circuit is simple with a few passive components. in the literature [17–21]. These waveform generators provide some advantages, like higher slew rate However, the oscillation frequencies are limited to few kHz. Second generation Current Conveyor (CCII+)and wider based bandwidth. waveform However, generators some were of these proposed waveform in the generators literature require[17–21] more. These than waveform one active device and more passive components. Square-wave generators with single CCII+ were proposed generators provide some advantages, like higher slew rate and wider bandwidth. However, some of thesein [ 20 waveform]. These waveform generators generators require more have than the advantage one active of device less power and more consumption. passive components. However, the Squareoscillation-wave frequencies generators ofwith these single circuits CCII+ are were limited proposed to only in few [20 kHz.]. These The waveform square-wave generators generator have using thethree advantage operational of less transconductance power consumption. amplifier However, (OTA) the and oscillation three passive frequencies components of these was circuits proposed are limitedin [22 ]. to The only advantage few kHz. of The this s waveformquare-wave generator generator would using be three that it operational can control transconductance the amplitude and amplifierfrequency (OTA) independently and three by passive changing components the resistance was or proposed changing inthe [ biasing22]. The current. advantage However, of this this waveformwaveform generator generator would consumes be that more it powercan control and the the use amplitude of three OTAs and requiresfrequency more independently chip area. Table by 1 changingshows the the comparison resistance of or active changing devices. the biasing current. However, this waveform generator consumes more power and the use of three OTAs requires more chip area. Table 1 shows the Table 1. Performance comparison of active devices. comparison of active devices. Parameters Op-amp CFOA CCII+ CDBA OTA OTRA Table 1.Performance comparison of active devices. Power Supply 0.8 V 1.8 V 1.8 V 1.5 V 0.5 V 1.8 V TechnologyParameters 0.18Opµm-amp 0.18CFOAµm CCII+ 0.18 µ mCDBA 0.18 µmOTA 0.18 µmOTRA 0.18 µm Power Supply 0.8 V 1.8 V 1.8 V 1.5 V 0.5V 1.8V Power Dissipation 190 µW – 206 µW 194 µW 215 µW 210 µW Technology 0.18 µm 0.18 µm 0.18 µm 0.18 µm 0.18 µm 0.18 µm OpenPower Loop Dissipation Gain 66 dB190 µW 75 dB-- 206 78 µW dB 194 µW 85 dB 215 µW 52 dB210 µW 96 dB Gain BandOpen Width Loop Product Gain 3.4 MHz66 dB 2375dB MHz 78 dB – 85 100 dBMHz 52 dB 7.5 MHz96 dB 152 MHz Gain Band Width Product 3.4MHz 23MHz -- 100MHz 7.5 MHz 152 MHz

Recently,Recently, an an active current-mode current-mode device, device called, called an operational an operational transresistance transresistance ampliﬁer amplifier (OTRA), (OTRA)has come, has to come limelight to limelight with the with introduction the introduction of several of high several performances high performances CMOS OTRA CMOS realizations. OTRA realizations.Several waveform Several generators waveform using generators an operational using an transresistanceoperational transresistance ampliﬁer (OTRA) amplifier were (OTRA) reported wereearlier reported in the earlier literature in the [23 literature–42]. Square-waveform [23–42]. Square- generatorwaveform using generator single using OTRA single and OTRA a few and passive a fewcomponents passive components was proposed was proposed in [28]. Figurein [28]1. Figureshows 1 this shows proposed this proposed circuit. circuit. The architecture The architecture of the of circuit the circuit is simpler is simpler than the than voltage-mode the voltage waveform-mode waveform generators. generators. This circuit This generates circuit oscillations generates up oscillationsto a few MHz. up to However,a few MHz. this However, circuit exhibits this circuit non-linear exhibits variation non-linear of timevariation period of time with period respect with to the respectresistance to theR 2resistance. R2.

I-

OTRA Vo

VC I+

C R2

FigureFigure 1. Conventional 1. Conventional Operational Operational Trans-resistance Trans-resistance Amplifier (OTRA Ampliﬁer) based (OTRA) square- basedwave generator square-wave [28]. generator [28]. In this paper, two new square-wave generators based on single OTRA are presented. The proposed circuits are able to overcome the non-linear variation of the time period with respect to the passive components. The remaining sections of the paper are designed, as follows. In Section 2, the

J. Low Power Electron. Appl. 2020, 10, 12 3 of 16

In this paper, two new square-wave generators based on single OTRA are presented. The proposed circuits are able to overcome the non-linear variation of the time period with respect to the passive

J. Lowcomponents. PowerJ. Low Electron. Power Electron. Appl. The 20 remaining Appl.20, 10 20, x20 FOR, 10 sections, PEERx FOR REVIEW PEER of the REVIEW paper are designed, as follows. In Section2, the function3 of 163 of 16 the OTRA is introduced first and then the operation of the proposed configurations is described along functionwithfunction of the the non-idealities. ofOTRA the OTRA is introduced Section is introduced3 presentsfirst and first simulated then and tthenhe operation and the experimental operation of the ofproposed results.the proposed Finally, configurations configurations the conclusion is is describedisdescribed drawn along in Section along with the with4. n on the-idealities. non-idealities. Section Section 3 presents 3 presents simulated simulated and experimental and experimental results. results. Finally,Finally, the conclusion the conclusion is drawn is drawn in Section in Section 4. 4. 2. Circuit Description and Operation 2. Circuit Description and Operation 2. CircuitThe Description OTRA is and a three Operation terminal current-mode analog device with two low-impedance input terminalsThe OTRAThe and OTRA is one a three is low-impedance a three terminal terminal current output current-mode terminal- mode analog [27 analog device,28]. deviceThe with input two with terminals low two-impedance low of-impedance the OTRA input input are terminalsvirtuallyterminals and grounded, one and low one-impedance this low leads-impedance to output the circuits output terminal that terminal are[27 insensitive,28 ][.27 The,28] . input Theto the input terminals parasitic terminals capacitances. of the of OTRA the OTRA Figure are 2 are virtuallyshowsvirtually grounded, the circuitgrounded, this symbol leads this oftoleads thethe to OTRA.circuits the circuits Thethat inputare that insensitive andare insensitive output to terminalthe toparasitic the relationsparasitic capacitances. ofcapacitances. an OTRA Figure can Figure be 2 showscharacterized2 shows the circuit the circuit bysymbol the symbol following of the ofOTRA. the matrix. OTRA. The For input The ideal inputand operation, output and output terminal the transresistanceterminal relations relations of an gain OTRAof Ranm OTRAapproaches can be can be infinity, forcing the input currents to be equal. m characterizedcharacterized by the by following the following matrix. matrix. For ideal For operation,ideal operation, the transresistance the transresistance gain Rgainm approaches R approaches infinityinfinity, forcing, forcing the input the inputcurrents currents to be equal.to be equal.     V+   0 0 0  I+  V  V 0  0 00I 0I    V  =  0 0 0  I  (1)  −       −   V  0 0 0 I  (1) VVo 0 R m0 R0mI0  Io (1)    −   V  VRo  RRm 0RmI 0Io   o   m m  o  V+ = V = 0 and Vo = Rm(I+ I ) (2) + − − o m + −− V+ = VV− = =0 Vand = V0 oand = R mV(I += − R I−)(I − I ) (2) (2)

V+ V+ + + I+ I+ V OTRAOTRA Vo o I _ _ Io o V_ V_ I_ I_

FigureFigureFigure 2. OTRA 2. 2.OTRA OTRAsymbol. symbol. symbol.

2.1. Proposed2.1.2.1. Proposed Proposed Circuit Circuit-1 Circuit-1 -1 FigureFigureFigure 3 shows3 shows 3 shows the thefirst the ﬁrst proposed first proposed proposed square square-wave square-wave- wavegenerator. generator. generator. This This square This square-wave square-wave- wavegene generatorrator gene consistsrator consists consists of 1 of oneoneof active active one active element element element (OTRA), (OTRA), (OTRA), one one resistor resistor one resistorR 1R, one1, one capacitorR , capacitor one capacitorC, and C, and two C depletion, two and depletion two mode depletion mode NMOS mode NMOS transistors. NMOS 1 2 transistors.Thetransistors. two The NMOS two The transistorsNMOS two NMOS transistors M1 transistorsand MM21 areand M operated M and2 are M operated in are the operated triode in the region intriode the and triode region they region and act as they and a linear act they as resistor. acta as a linear linearresistor. resistor. R1 R1

I− VX I− VX Vo Vo - - I Io M M2o OTR OTR 2 M1 M1 + A + A

I C I+ + C

Figure 3. The ﬁrst proposed current-mode square-wave generator conﬁguration. FigureFigure 3. The 3.first The pr firstoposed proposed current current-mode -squaremode square-wave -generatorwave generator configuration. configuration.

Equation (3) depicts the equivalent amount of resistance R2 realized from the parallel combination Equation (3) depicts the equivalent amount of resistance R2 realized from the parallel ofEquation NMOS transistors (3) depicts as shownthe equivalent in Figure 4 amount. of resistance R2 realized from the parallel combinationcombination of NMOS of NMOS transistors transistors as shown as shown in Fig urein Fig 4. ure 4. 1 R2 = (3) µnCox(W/L)(VX 2VT) − VX VX R2 R2 M1 M M1 M2 2

FigureFigure 4. Resistor 4. Resistor realization realization using twousing NMOS two NMOS transistors transistors [43]. [43].

J. Low Power Electron. Appl. 2020, 10, x FOR PEER REVIEW 3 of 16 function of the OTRA is introduced first and then the operation of the proposed configurations is described along with the non-idealities. Section 3 presents simulated and experimental results. Finally, the conclusion is drawn in Section 4.

2. Circuit Description and Operation The OTRA is a three terminal current-mode analog device with two low-impedance input terminals and one low-impedance output terminal [27,28]. The input terminals of the OTRA are virtually grounded, this leads to the circuits that are insensitive to the parasitic capacitances. Figure 2 shows the circuit symbol of the OTRA. The input and output terminal relations of an OTRA can be characterized by the following matrix. For ideal operation, the transresistance gain Rm approaches infinity, forcing the input currents to be equal.

V   0 0 0I       V    0 0 0I  (1) V  R  R 0I   o   m m  o  V+ = V− = 0 and Vo = Rm(I+ − I−) (2)

V+ + I+ OTRA Vo

_ Io V_ I_ Figure 2. OTRA symbol.

2.1. Proposed Circuit-1 Figure 3 shows the first proposed square-wave generator. This square-wave generator consists of one active element (OTRA), one resistor R1, one capacitor C, and two depletion mode NMOS transistors. The two NMOS transistors M1 and M2 are operated in the triode region and they act as a linear resistor. R1

I− VX Vo - I M o OTR 2 M1 + A

I+ C

Figure 3. The first proposed current-mode square-wave generator configuration.

J. Low Power Electron. Appl. 2020, 10, 12 4 of 16 Equation (3) depicts the equivalent amount of resistance R2 realized from the parallel combination of NMOS transistors as shown in Figure 4.

J. Low Power Electron. Appl. 2020, 10, x FOR PEER REVIEW 4 of 16 VX R2 M1 M12 R2  (3) nCox (W / L)(VX  2VT ) Figure 4 4.. ResistorResistor realization realization using using two NMOS t transistorsransistors [ 43]].. This circuit generates a square-wave with almost equal and fixed on-duty and off-duty cycles, i.e., 50%This duty circuit cycles. generates Figure a square-wave 5 shows the with corresponding almost equal output and fixed waveform on-duty of and the firsoff-dutyt proposed cycles, circuit.i.e., 50% From duty Figure cycles. 5, Figure it could5 shows be construed the corresponding that the output waveformsquare-wave of the(Vo) first has proposed two saturation circuit.   V V+ levelsFrom FigureVsat and5, it V couldsat . Let be us construed assume that that V theo is outputat any one square-wave of these two ( osaturation) has two saturationlevels. If V levelso changessat and Vsat− . Let us assume that Vo is at any one of these two saturation levels. If Vo changes its state from its state from+ Vsat to Vsat , it implies that the current at the non-inverting terminal I+ becomes more Vsat− to Vsat, it implies that the current at the non-inverting terminal I+ becomes more than the current than the current at the inverting terminal I− of the OTRA. At this moment, the voltage VC of the at the inverting terminal I of the OTRA. At this moment, the voltage VC of the capacitor C begins to capacitor C begins to increase− from the lower threshold value VTL+ to the final valueVsat . From Figure increase from the lower threshold value VTL to the final value Vsat. From Figure3, the current Io at the 3output, the current terminal Io at and the theoutput current terminalI at theand inverting the current input I− at terminal the inverting of the input OTRA terminal can be written, of the OTRA as can be written, as − VVoVVC IIo = o − C (4) o R2 (4) R2 VVC I = C (5)(5) − R1 R1

+ T1 Vsat

VTH

0 t

VTL

- Vsat T2

FigureFigure 5. 5. OutputOutput waveform waveform of of the the proposed proposed square square-wave-wave generators. generators.

SubsequentlySubsequently,, the the non non-inverting-inverting input input terminal terminal current current II++ cancan be be expressed expressed as as

VVo VVC VCV I   o C C (6) I+ = R− R (6) R22 − R1 1 From the terminal relations presented in Equation (1), Vo changes its state when the From the terminal relations presented in Equation (1), Vo changes its state when the non-inverting non-inverting terminal current is equal to the inverting terminal current I+ = I−. The capacitor voltage terminal current is equal to the inverting terminal current I+ = I . The capacitor voltage can be derived can be derived from Equations (5) and (6) by putting I+ = I−. − from Equations (5) and (6) by putting I+ = I . −  V C  R1 / 2R 2  R1 V o (7) ∴ VC = (R1/2R2 + R1)Vo (7) The capacitor voltage changes between VTH and VTL. Subsequently, VTH and VTL can be derived from Equation (7) by substituting threshold and saturation values The capacitor voltage changes between VTH and VTL. Subsequently, VTH and VTL can be derived from Equation (7) by substituting threshold and saturation values VTH  R1 / 2R2  R1 Vsat (8)

+ VTH = (R1/2R2 + R1)V (9)(8) VTL  R1 / 2R2  R1 Vsatsat

The time evolution equation for the capacitor voltage VC, when it starts to increase from VTL  towards its final value Vsat can be expressed as t

 R2C  (10) VC (t)  (VTL Vsat )e Vsat

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VTL = (R1/2R2 + R1)Vsat− (9)

The time evolution equation for the capacitor voltage VC, when it starts to increase from VTL + towards its ﬁnal value Vsat can be expressed as

t + R−C + V (t) = (VTL Vsat )e 2 + V (10) C − sat

Time period T1 can be derived by making VC(t) = VTH

+ + T = R C ln(VTL V )/(VTH V ) (11) 1 2 − sat − sat

By substituting VTH and VTL values from Equations (8) and (9)

+ (R1/2R2 + R1)Vsat− Vsat T1 = R2C ln − (12) (R /2R + R )V+ V+ 1 2 1 sat − sat From the output waveform, it can be written as

+ V = V− (13) sat − sat

( R1/2R2 + R1) 1 T = R2C ln − − (14) 1 (R /2R + R ) 1 1 2 1 − ∴ T1 = R2C ln(1 + (R1/R2)) (15)

The above Equation (15) is meant for on-duty cycle (TON). At the end of the on-duty cycle, the + capacitor voltage VC is charged up to the upper threshold voltage VTH, instead of Vsat. At this point of time, the current at the non-inverting terminal I+ becomes less than the current at the inverting terminal I of the OTRA. Subsequently, the output changes its state from the upper saturation level + − Vsat to the lower saturation level Vsat− and the capacitor starts discharging. When the voltage across capacitor C starts to decrease from VTH, it can be expressed, as

t R−C V (t) = (VTH V− )e 2 + V− (16) C − sat sat

Time period T2 can be derived by setting VC(t) = VTL

T = R C ln(VTH V− /VTL V− ) (17) 2 2 − sat − sat

By substituting VTH and VTL values in the above Equation (16) and following the same demonstration as the on-duty cycle T1, we obtain:

T2 = R2C ln(1 + (R1/R2)) (18)

The above Equation (18) is for oﬀ-duty cycle (TOFF). The ﬁnal time period (T) of the waveform is the sum of the T1 and T2 cycles. T = TON + TOFF = T1 + T2

T = 2R2C ln(1 + (R1/R2)) (19)

For ﬁxed duty cycles, the R1,R2, and C values will be obtained from the above Equation (19) for a required time period T. The required value of the resistor R2 is calculated from (3) by adjusting the voltage VX. J. Low Power Electron. Appl. 2020, 10, 12 6 of 16

2.2. Proposed Circuit-2 The second proposed circuit that is shown in Figure6 is designed to vary both the duty cycles independently with the help of resistors R11 and R12. The voltage drops across these resistors used + to control the operation of the diodes D1 and D2. The capacitor C starts charging towards Vsat when non-inverting terminal current is more than the inverting terminal current. This makes diode D1 becomes forward bias and D2 reverse bias. The diode D1 and resistor R11 controls the amount of current at the inverting input terminal. Consequently, the on-duty cycle is more as compared to the oﬀ-duty cycle. Similarly, the diode D2 becomes forward bias and D1 reverse bias and capacitor starts + J. Lowdischarging Power Electron. towards Appl. 20V20sat, 10. The, x FOR resistor PEER REVIEWR12 and diode D2 controls the inverting input terminal6 current. of 16 Due to this, the oﬀ-duty cycle is more when compared to the on-duty cycle.

R12 D2

I- R11 VX _ Vo Io OTRA M2 M1 +

I+ C

FigureFigure 6. 6.TheThe second second proposed proposed square square-wave-wave generator generator configuration. conﬁguration. When considering ideal diodes (zero voltage drop), capacitor threshold voltages can be described When considering ideal diodes (zero voltage drop), capacitor threshold voltages can be by the following equations: described by the following equations: + VTH = (R12/2R2 + R12)V (20) sat VTH  (R12 / 2R2  R12 )Vsat (20) VTL = (R11/2R2 + R11)Vsat− (21)  V  (R / 2R  R )V (21) Time period T1 (TON) can be obtainedTL 11 from Equations2 11 sat (20) and (21), while following the same

demonstrationTime period reported T1 (TON) incan Section be obtained 2.1 for from the proposed Equations circuit-1 (20) and (21), while following the same demonstration reported in Section 2.1 for the proposed+ circuit-1 + T1 = R2C ln(VTL V /VTH V ) (22) −  sat −  sat T1  R2C ln(VTL  V sat /VTH  V sat ) (22)  +  (R11/2R2 + R11)V− V  sat sat  TON = T1 = R2Cln(R / 2R  R )V −V  (23) T  T  R C ln  (11R /2R2 + R11 )Vsat+ Vsat+ (23) ON 1 2  12 2 12 sat − sat  (R12 / 2R 2  R12 )V sat  V sat  TON = R2C ln(1 + (R11/R2)) (24) (24) TON  R 2 C ln (1  (R11 / R 2 )) Similarly for TOFF OFF Similarly for T TOFF = R2C ln(1 + (R12/R2)) (25) T  R C ln (1  (R / R )) The total time period (T) for theOFF proposed2 square-wave12 generator2 in Figure6 can be expressed(25) as T =TheTON total+ T OFFtime period (T) for the proposed square-wave generator in Figure 6 can be expressed as T = TON + TOFF T = R2C ln((1 + (R11/R2)(1 + (R12/R2)) (26)

2.3. Non-Ideal Analysis T  R 2 C ln ((1  ( R 11 / R 2 )(1  ( R 12 / R 2 )) (26) An equivalent circuit model of the OTRA built with two current feedback ampliﬁers (CFAs) is 2.3.shown Non-Ideal in Figure Analysis7a to consider the non-ideal and parasitic e ﬀects on the proposed circuits. An equivalent circuit model of the OTRA built with two current feedback amplifiers (CFAs) is shown in Figure 7a to consider the non-ideal and parasitic effects on the proposed circuits.

J. Low Power Electron. Appl. 2020, 10, x FOR PEER REVIEW 7 of 16 J. Low Power Electron. Appl. 2020, 10, 12 7 of 16

(a) OTRA implementation with two AD844AN.

(b) Non-ideal model of the adopted OTRA.

Figure 7. OTRAOTRA Equivalent Equivalent Model Model [25 [25––31]31]..

A practical practical CFA CFA (AD844AN (AD844AN IC) IC) can canbe modeled be modeled as a positive as a positive second-generation second-generation current conveyor current conveyor(CCII+) cascading (CCII+) cascading a voltage bu a ffvoltageer with buffer finite parasitic with finite resistances parasitic and resistances non-zero currentand non tracking-zero cur errors.rent trackingFigure7a errors. reveals Figure a more 7a detailed reveals circuit a more model detailed of the circuit OTRA model that isofgiven the OTRA in Figure that7 b.is given Where in RFigureX and 7Rb.Z areWhere the parasiticRX and R resistancesZ are the parasitic and α represents resistances the and current α represents tracking the error current factor tracking from the error terminal factorTz fromwith respectthe terminal to the Tz inverting with respect terminal. to the The inverting standard terminal. values The of R standardX, RZ, and valuesα are givenof RX, inRZ, AD844AN and α are givendatasheet in AD844AN are α = 0.98, datasheetRX = 50 areΩ α, and= 0.98,RZ R=X =3 50 M ΩΩ,. and Figure RZ7 =a 3 indicates MΩ. Figur thee 7a resultant indicates expressions the resultant of expressionsthe related currents. of the related The voltage currents. tracking The error voltage effect tracking between error the CCII effect+ input between terminals the CCII+ are skipped input terminals(eliminated) are in skipped the circuit (eliminated) model, because in the of circuit the non-inverting model, because terminal of the for eachnon- CCIIinverting+ being terminal connected for eachto ground. CCII+ being connected to ground.

2.3.1. Non Non-Ideal-Ideal Analysis Analysis of of Proposed Proposed Circuit Circuit-1-1 For the proposed circuits, the non-idealnon-ideal analysis gives the following equations  V  (R /(R  (R R / R  R )  R ))V+ (27) VTHTH = (αR1 1/(αR1 1 + (R22RZZ/RXX + RZZ) + R22α))Vsatsat (27)  V  (R /(R  (R R / R  R )  R  ))V (28) VTLTL = (αR1 1/(αR1 1 + (R22RZZ/RXX + RZZ) + R2α2 ))Vsat− sat (28) Substituting these higher and lower threshold voltages into Equations (11) and (17), the non-ideal time period of the proposed circuit in Figure 3 can be expressed, as

T  2 R 2 C ln 1  ( 2 R 1 /( R 2 R Z / R X  R Z )  R 2   (29)

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2.3.2. Non-Ideal Analysis of Proposed Circuit-2 J. Low PowerThe non Electron.-ideal Appl. equation2020, 10, for 12 the second proposed circuit in Figure 6 is given in Equation (32)8 of 16

 V TH  (R12 /(R12  ( R 2 R Z / R X  R Z )  R 2 ))V sat (30) Substituting these higher and lower threshold voltages into Equations (11) and (17), the non-ideal  (31) time period of the proposedVTL  circuit(R11 in/( FigureR11 3 (canR2 R beZ expressed,/ RX  RZ as)  R2 ))Vsat 2R 2R T = 2R C ln(1 + (112αR /(R RZ/RX + RZ) + R α) 12 (29) T  R 2 C ln((1  2 1 2 )(1  2 )) (32) (R 2 R Z /( R X  R Z ))  R 2 (R 2 R Z /( R X  R Z ))  R 2 2.3.2. Non-Ideal Analysis of Proposed Circuit-2 It can be easily verified that Equations (29) and (32) reduces to Equations (19) and (26), as expected,The non-ideal for ideal equationOTRA when for theα ≈ second1 and R proposedX≈ 0. circuit in Figure6 is given in Equation (32)

+ 3. Simulation and ExperimentalVTH = (α ResultsR12/(αR 12 + (R2RZ/RX + RZ) + R2α))Vsat (30) The proposed circuits were simulated using SPICE CMOS model parameters with a supply VTL = (αR11/(αR11 + (R2RZ/RX + RZ) + R2α))Vsat− (31) voltage of ±1.8 V. Figure 8 provides the CMOS realization of the OTRA. Table 2 depicts the aspect 2αR 2αR ratios of theT = transistors,R C ln((1 biasing+ voltages,11 and biasing)( 1 currents.+ Figure 912 provides th))e simulated(32) 2 ( ( + )) + ( ( + )) + output results of the proposedR 2circuits.RZ/ RX RZ R2α R2RZ/ RX RZ R2α ItFor can generating be easily veriﬁed the square that Equations-wave of the(29) firstand (32) proposed reduces circuit to Equations in Figure (19) 3,and the (26), required as expected, time forperiod ideal is OTRA chosen when first. αSubsequently1 and R , the0. ratio of R1/R2 is taken care of and the value of capacitor C is ≈ X ≈ arbitrarily determined from Equation (19). The voltage VX is adjusted to realize the desired value of 3. Simulation and Experimental Results resistance R2 from (3). However, with this circuit the on-duty and off-duty cycles are fixed. The first proposedThe proposed circuit was circuits designed were simulatedwith the following using SPICE passive CMOS components model parameters R1 = 15 withkΩ, R a2 supply = 1.5 kΩ voltage (W = of5µm,1.8 L V.= Figure180 nm,8 provides VX= 80 mV) the, CMOS and C realization= 1 nF to generate of the OTRA. the square Table2 waveform. depicts the Figure aspect 9a ratios shows of the the ± transistors,simulated output biasing waveform voltages, andof the biasing proposed currents. circuit Figure in Figure9 provides 3 with thea time simulated period outputof 7.56 resultsµs, which of theis close proposed to the circuits.theoretical time period of 7.19 µs.

FigureFigure 8.8. The device level circuit diagramdiagram ofof thethe OTRAOTRA [[3131].].

Table 2. Aspect ratios of the circuit shown in Figure8. Table 2. Aspect ratios of the circuit shown in Figure 8. µ TableTable W W (µm) ( m) L(nm) L (nm) MM1-M1-M6 6 44 180 180 M7M-M7-M1010 66 180 180 M11M-M11-M1212 2020 180 180 M ,M 2 180 14M14, M2020 2 180 M13,M18 12 180 M13, M18 12 180 M15 12 180 M15 12 180 M16,M19 4 180 M16, M19 4 180 M17 3.3 180 M17 3.3 180 Vg1 = Vg2 = 0.8 V and I0 = 40 µA Vg1 = Vg2 = 0.8 V and I0= 40 µA

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For the second proposed circuit in Figure 6, the values of resistors R11 = R12, equivalent resistance R2 and capacitor C, are derived from the above process as stated in fixed duty cycles. Then the resistors R11 and R12 are tuned independently in order to set the required on-duty and off-duty cycles. If resistor R11 is chosen to be greater than the resistor R12, then the on-duty cycle is more than the off-duty cycle. These values will be (R12>R11) reversed to set the off-duty cycle more than the on-duty cycle. The passive components R2 =1.5 kΩ (W = 5µm, L = 180 nm, VX= 80 mV), R11= 1.5 kΩ, R12= 5 kΩ, and C=0.1µF were used to design the second proposed circuit in Figure 6. Figure 9b, and 9c provide the corresponding simulated output waveforms for the second proposed circuit. From FigureJ. Low Power 9b, Electron.and 9c, Appl. the 2020simulated, 10, 12 time period is 0.36 ms, which is close to the theoretical time period9 of 16 of 0.32 ms.

(a) Output waveform of the proposed circuit-1 (TON =TOFF).

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(b) Output waveform of the proposed circuit-2 (TON>TOFF).

Figure 9. Output waveforms of the proposed square square-wave-wave generators.

ForAD844AN generating is adopted the square-wave to construct of thethe ﬁrstproposed proposed circuits circuit on ina laboratory Figure3, the breadboard required time in order period to isverify chosen the ﬁrst. theoretical Subsequently, study. the The ratio commercial of R1/R2 is taken IC AD844AN care of and w theith value current of capacitor feedbackC is architecture arbitrarily (configuration) is used to implement the OTRA, as shown in Figure 7a [27,28]. Therefore, the behavior of the OTRA is obtained with the schematic shown in Figure 7a. For the proposed circuit in Figure 3, the required time period is chosen first. Subsequently, suitable values of passive components (R1, R2, and C) are derived from Equation (19). In all measurements, the passive component R2 value is the same as the resistance R2 value calculated from Equation (3). For higher sensitivity of the time period with respect to the resistor, the resistor R2 is chosen to be less than 2 kΩ. The experimental output waveform of the proposed circuit-1 is given in Figure 10 with a time period of 7 µs.

Figure 10. Output waveform with almost equal and fixed duty cycles (TON = TOFF). Scale: X-axis 2 µs/div and Y-axis 1 V/div.

Similarly, in the case of the second proposed circuit, the suitable passive component values will be obtained from Equation (26) to a chosen time period. If the required time period is 0.32 ms with 60% on-duty and 40% off-duty cycles then the capacitor C is slightly increased to set the required time period. The resistor R11 and R12 values will be reversed to set the 40% on-duty and 60% off-duty cycles. The output waveforms for the second proposed circuit are given in Figure 11a,b with a time period of 0.31 ms.

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determined from Equation (19). The voltage VX is adjusted to realize the desired value of resistance R2 from (3). However, with this circuit the on-duty and off-duty cycles are fixed. The first proposed circuit was designed with the following passive components R1 = 15 kΩ, R2 = 1.5 kΩ (W = 5µm, L = 180 nm, VX = 80 mV), and C = 1 nF to generate the square waveform. Figure9a shows the simulated output waveform of the proposed circuit in Figure3 with a time period of 7.56 µs, which is close to the theoretical time period of 7.19 µs. For the second proposed circuit in Figure6, the values of resistors R11 = R12, equivalent resistance R2 and capacitor C, are derived from the above process as stated in fixed duty cycles. Then the resistors R11 and R12 are tuned independently in order to set the required on-duty and off-duty cycles. If resistor R11 is chosen to be greater than the resistor R12, then the on-duty cycle is more than the off-duty cycle. These values will be (R12 > R11) reversed to set the off-duty cycle more than the on-duty cycle. The passive components(cR) 2Output=1.5k waveformΩ (W = 5 ofµm, the L proposed= 180 nm, circuitVX -=2 (80TON mV),

Figure 10.10. Output waveform with almost equal and ﬁxedfixed dutyduty cyclescycles ((TTONON = TTOFFOFF).). Scale: Scale: X-Xaxis-axis 2 2µs/divµs/div and and YY-axis-axis 1 1V/div. V/div.

Similarly, inin thethe casecase ofof thethe second proposed circuit, thethe suitable passive component values will be obtained from Equation (26) to a chosenchosen time period.period. If the required time period is 0.32 ms with 60% on-dutyon-duty andand 40%40% o ﬀoff-duty-duty cycles cycles then then the the capacitor capacitorC is C slightly is slightly increased increased to set to the set required the required time period.time period. The resistor The resistorR11 and R11R and12 values R12 values will bewill reversed be reversed to set to the set 40% the on-duty 40% on and-duty 60% and o ﬀ60%-duty off cycles.-duty Thecycles. output The waveformsoutput wavefor for thems secondfor the proposedsecond proposed circuit are circuit given are in Figuregiven in11 Figurea,b with 11 aa,b time with period a time of 0.31period ms. of 0.31 ms.

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(a) Output waveform with variable on-duty cycle (TON>TOFF). Scale: X-axis 0.2 ms/div and Y-axis 1 V/div.

(b) Output waveform of with variable off-duty cycle (TON

Figure 11. ExperimentalExperimental output output waveforms waveforms of of the the second second proposed proposed circuits.

Several experiments experiments were were performed performed on on the the laboratory laboratory bread bread board board to test to test the thetunability tunability of the of proposedthe proposed circuits circuits against against the passive the passive components components R1, R2,R and1, R C2,. andThe resultsC. The are results prese arented presented in Figures in 12Figures to 15 12for– 15the for proposed the proposed circuit circuit configuration conﬁguration in Figure in Figure 3. T3he. Thesupply supply voltage voltage of ± of6 V was6 V wasused used for ± allJ.for Low measurements all Power measurements Electron. Appl. on tunability. on2020 tunability., 10, x FOR PEER REVIEW 12 of 16 Figures 12–14 denote the time period variation against the passive components R1, R2, and C. For the tunability of resistor R1, the selected passive component values are R2 = 12 kΩ and C = 1 nF and R1 was varied from 800 Ω to 10 kΩ. A linear like variation of time period was exhibited by the circuit and it is presented in the form of plot in Figure 12. Similarly, for the capacitor C, the selected parameter values are resistors R1 = 15 kΩ and R2 = 1.5 kΩ. The capacitor C was varied from 0.1 nF to 100 nF. Figure 13 plots the practical and theoretical time period variation against the capacitor C. Likewise, for the resistor R2, the circuit was built with resistor R1= 15 kΩ, capacitor C = 1 nF and R2 was varied from 200 Ω to 3 kΩ.

Figure 12. Variation of time period against resistorresistor RR11..

Figure 13. Tunability against capacitor C.

Figure 14. Tunability against resistor R2.

From Figures 12–14, the variation of the time period with respect to the passive components is linear. Figure 1 shows the OTRA based square-wave generator proposed in [28]. For generating the square-wave in the circuit shown in Figure 1, it is necessary to maintain the resistor R2 value less than the resistor R1 and as it will not generate the waveform when R1

J. Low Power Electron. Appl. 2020, 10, x FOR PEER REVIEW 12 of 16 J. Low Power Electron. Appl. 2020, 10, x FOR PEER REVIEW 12 of 16

J. Low Power Electron. Appl. 2020, 10, 12 12 of 16 Figure 12. Variation of time period against resistor R1. Figure 12. Variation of time period against resistor R1.

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Figures 3 and 6 will generate the waveform independent of the resistor values and exhibit more linear curve than the conventional circuit in Figure 1. Figure 15 shows the comparison between Figure 13. TunabilityTunability against capacitor C. conventional OTRA square-waveFigure generator 13. Tunability circuit against[28] and capacitor proposed C. square-wave generator circuit in Figure 3. For the plot in Figure 15 the parameters values are R1 = 15 kΩ and C = 1 nF, and R2 was varied from 200 Ω to 18 kΩ. From Figure 15, it can be construed that the proposed circuit exhibits more linear curve than the conventional circuit. The proposed circuits can generate the oscillations up to 1.2 MHz. A detailed tally of the proposed circuit with the other square-wave generators in the literature are presented in Table 3 in order to highlight the advantage of the proposed circuit in Figure 3. Form this comparison table, the proposed circuit outperforms with most of the listed square wave generators. The square waveform generators reported in [12] and [15] generates a high frequency of oscillations when compared with the proposed circuits. With two active components along with passive component consume a high amount power and occupy large silicon area. The square wave generator that is given in [44] requires two passive components (one resistor and one capacitor) and one passive component to produce high frequency oscillations. However, the active device Dual-X Current Conveyor Transconductance Amplifier (DXCCTA) is very bulky with eight input terminals and one output terminal. The total number of transistors to construct the DXCCTA is also large. A greater number of transistors and input terminals increase the silicon area and power consumption. Figure 14. Tunability against resistor R22.. Figure 14. Tunability against resistor R2.

From Figures 12–14, the variation of the time period with respect to the passive components is From Figures 12–14, the variation of the time period with respect to the passive components is linear. Figure 1 shows the OTRA based square-wave generator proposed in [28]. For generating the linear. Figure 1 shows the OTRA based square-wave generator proposed in [28]. For generating the square-wave in the circuit shown in Figure 1, it is necessary to maintain the resistor R2 value less square-wave in the circuit shown in Figure 1, it is necessary to maintain the resistor R2 value less than the resistor R1 and as it will not generate the waveform when R1

Figure 15. Time period variation betweenbetween conventional and proposed circuitscircuits againstagainst RR22..

FiguresTable 3. 12Comparison–14 denote of the the time proposed period circuit variation in Fig againsture 3 with the passive the conventional components circuitsR1 , inR 2 the, and C. For theliterature. tunability of resistor R1, the selected passive component values are R2 = 12 kΩ and C = 1 nF R and 1 was varied fromNo. of 800ActiveΩ to 10 kNo.Ω. of Passive Total Maximum Supply References Components Components Components Frequency Range Voltage [9] 2 DVCC 4 (1 C & 3 R) 6 860 kHz ±10 V [12] 2 VDIBA 3 (1 C & 2 R) 5 2.8 MHz ±5 V [15] 2 CFOA 5 (1 C & 4 R) 7 15 MHz, 1S ±5 V [16] 1 CFOA 4 (1 C & 3 R) 5 71 kHz -- [17] 3 CCII+ 7 (1 C & 6 R) 10 574 kHz ±6 V [19] 2 CCII+ 4 (1 C & 3 R) 6 260 kHz ±5 to ±15 V [20] 2 CCII+ 6 (1 C & 5 R) 8 737 kHz ±15 V [21] 1 CCII+ 4 (1 C & 3 R) 5 2 kHz 1.5 V, 3I.S. [22] 3 OTA 3 (1 C & 2 R) 6 16 kHz ±5 V ±2.5 V, 1S [44] 1 CDTA 2 (1 C & 1 R) 4 600 kHz ±9 V, 2H [45] 1DXCCTA 2 (1 C & 1 R) 3 20.6 MHz ±1.25 V,1S [28] 1 OTRA 3 (1 C & 2 R) 4 1.0 MHz ±15 V Proposed 3+2 NMOS 1.5 MHz, 1S ±1.8 V, 1S Figure 3 1 OTRA 2 (1 C & 1 R) Transistors 1.2 MHz,2H ±6 V, 2H circuit 1S = Simulation, 2H =Hardware Implementation, 3I.S. = Integrate Solution.

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A linear like variation of time period was exhibited by the circuit and it is presented in the form of plot in Figure 12. Similarly, for the capacitor C, the selected parameter values are resistors R1 = 15 kΩ and R2 = 1.5 kΩ. The capacitor C was varied from 0.1 nF to 100 nF. Figure 13 plots the practical and theoretical time period variation against the capacitor C. Likewise, for the resistor R2, the circuit was built with resistor R1 = 15 kΩ, capacitor C = 1 nF and R2 was varied from 200 Ω to 3 kΩ. From Figures 12–14, the variation of the time period with respect to the passive components is linear. Figure1 shows the OTRA based square-wave generator proposed in [ 28]. For generating the square-wave in the circuit shown in Figure1, it is necessary to maintain the resistor R2 value less than the resistor R1 and as it will not generate the waveform when R1 < R2. The proposed circuits in Figures3 and6 will generate the waveform independent of the resistor values and exhibit more linear curve than the conventional circuit in Figure1. Figure 15 shows the comparison between conventional OTRA square-wave generator circuit [28] and proposed square-wave generator circuit in Figure3. For the plot in Figure 15 the parameters values are R1 = 15 kΩ and C = 1 nF, and R2 was varied from 200 Ω to 18 kΩ. From Figure 15, it can be construed that the proposed circuit exhibits more linear curve than the conventional circuit. The proposed circuits can generate the oscillations up to 1.2 MHz. A detailed tally of the proposed circuit with the other square-wave generators in the literature are presented in Table3 in order to highlight the advantage of the proposed circuit in Figure3. Form this comparison table, the proposed circuit outperforms with most of the listed square wave generators. The square waveform generators reported in [12,15] generates a high frequency of oscillations when compared with the proposed circuits. With two active components along with passive component consume a high amount power and occupy large silicon area. The square wave generator that is given in [44] requires two passive components (one resistor and one capacitor) and one passive component to produce high frequency oscillations. However, the active device Dual-X Current Conveyor Transconductance Ampliﬁer (DXCCTA) is very bulky with eight input terminals and one output terminal. The total number of transistors to construct the DXCCTA is also large. A greater number of transistors and input terminals increase the silicon area and power consumption.

Table 3. Comparison of the proposed circuit in Figure3 with the conventional circuits in the literature.

No. of Active No. of Passive Total Maximum Supply References Components Components Components Frequency Range Voltage [9] 2 DVCC 4 (1 C & 3 R) 6 860 kHz 10 V ± [12] 2 VDIBA 3 (1 C & 2 R) 5 2.8 MHz 5 V ± [15] 2 CFOA 5 (1 C & 4 R) 7 15 MHz, 1S 5 V ± [16] 1 CFOA 4 (1 C & 3 R) 5 71 kHz – [17] 3 CCII+ 7 (1 C & 6 R) 10 574 kHz 6 V ± [19] 2 CCII+ 4 (1 C & 3 R) 6 260 kHz 5 to 15 V ± ± [20] 2 CCII+ 6 (1 C & 5 R) 8 737 kHz 15 V ± [21] 1 CCII+ 4 (1 C & 3 R) 5 2 kHz 1.5 V, 3I.S. [22] 3 OTA 3 (1 C & 2 R) 6 16 kHz 5 V ± 2.5 V, 1S [44] 1 CDTA 2 (1 C & 1 R) 4 600 kHz ± 9 V, 2H ± [45] 1DXCCTA 2 (1 C & 1 R) 3 20.6 MHz 1.25 V, 1S ± [28] 1 OTRA 3 (1 C & 2 R) 4 1.0 MHz 15 V ± Proposed 3+2 NMOS 1.5 MHz, 1S 1.8 V, 1S 1 OTRA 2 (1 C & 1 R) ± Figure3 circuit Transistors 1.2 MHz,2H 6 V, 2H ± 1S = Simulation, 2H = Hardware Implementation, 3I.S. = Integrate Solution. J. Low Power Electron. Appl. 2020, 10, 12 14 of 16

4. Conclusions In this paper, two new square-wave generators are proposed. These circuits use only one OTRA and a few passive components, the proposed circuits are simpler than the voltage-mode (op-amp based) waveform generators. The attentive features of these topologies are that they are realized while using commercially available ICs AD 844 AN. The proposed circuits exhibit linear variation of the time period with respect to the passive component. Additionally, the time period of the proposed circuits can be electronically tuned by adjusting the voltage (VX). The results exhibited by such topologies congruent with the simulated as well as the theoretical values. The proposed circuits can generate oscillations up to 1.2 MHz (experimental). These circuits can be expected to ﬁnd wider applications in many applied electronics, communications, instrumentation, and signal processing applications.

Author Contributions: Circuit implementation, software and hardware validation, investigation, resources, data curation, P.C.S.; writing—original draft preparation, writing—review, corrections and editing, supervision, A.S. All authors have read and agreed to the published version of the manuscript. Funding: This research received no external funding. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References

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