MIPS-Lite Processor Datapath Design Overview

MIPS-Lite Processor Datapath Design

COE608: Computer Organization and Architecture

Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering

Ryerson University

Overview

• Design a processor: step-by-step • Requirements of the Instruction Set • MIPS-Lite Instructions • Components and Clocking • Assembling an adequate Datapath • Controlling the Datapath

Chapter 4 (4.1, 4.2 & 4.3) of the textbook

Processor design (data path, alu and control) It determines • Clock cycle time • Clock cycles per instruction

Single cycle processor: Advantage:

Disadvantage:

Analyze Instruction Set => Data path Requirements

Meaning of each instruction is given by register transfers

1. Analyze the Instruction Set Interconnection to support RT

2. Select set of data path components and establish clocking methodology

3. Assemble data path meeting the requirements

4. Analyze the implementation of each instruction.

5. Assemble the control logic.

© G.N. Khan Computer Organization & Architecture – coe608: MIPS- Datapath Page: 3 MIPS Instruction Formats All MIPS instructions are 32 bits long. There are three instruction formats: 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 0 op target address 6 bits 26 bits

funct

rs, rt, rd

shamt

address/immediate

target address

2631 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

OR immediate

2631 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits

LOAD and STORE Word

2631 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits

BRANCH

2631 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits

All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ]

inst Register Transfers

ADDU PC <= PC + 4

SUBU PC <= PC + 4

ORi R[rt] <= R[rs] || zero_ext(Imm16);

LOAD R[rt] <= MEM[ R[rs] +sign_ext(Imm16)];

STORE MEM[ R[rs]+sign_ext(Imm16) ] <= R[rt];

BEQ if ( R[rs] == R[rt] ) then PC <= PC + 4 + {sign_ext(Imm16), 2’b 00} else PC <= PC + 4

Memory

Registers (32 x 32)

Extender

Add and Subtract register or extended immediate

Components of the Datapath

Combinational Logic Elements

CarryIn A

32 Adder Adder Sum 32 B Carry 32

Select

A MUX 32 MUX Y 32 B 32

OP A 32 ALU Result ALU 32 B 32

Write Enable: N N

Clk Register File Details of Register Reading

R e ad r e g i st er n u m b er RA R e g is t e r 0 R e g is t e r 1 M

u Rea d d a t a busA

x R e gi s t er n – 1 R e g is t e r n

R e ad r e g i st er n u m b er RB

M u Rea d d a t a busB x

Writing into a Register

Write Enable C 0 Re gi st e r 0 1 D n - to-1 C R eg is te r n um b e r de coder Re gi st e r 1 RW D n – 1 n

C Reg is te r n – 1 D C R e gi st e r n Re gi st er d at a D busW

Clock input (C or CLK)

During read operation, register file behaves as a combinational logic block:

• Register File consists of 32 registers • Two 32-bit output busses

• One 32-bit input bus RW RA RB Write Enable 5 5 5 busA busW 32 32-bit 32 32 Registers Clk busB 32

• Register Read ♦ RA (number) selects a register to put (data) on the busA ♦ RB (number) selects the register to put on busB (data) • Register Write ♦ RW (number) selects the register to be written via busW (data) when Write Enable is 1.

One input bus One output bus

Write Enable Address

Data In DataOut 32 32 Clk

Memory word is selected by ♦ Address

♦ Write Enable = 1

Clock input (CLK) ♦ CLK only required during write operation ♦ For read operation, memory behaves as a combinational logic.

Clocking Methodology

An edge triggered methodology Typical execution: ♦ Read contents of some state elements. ♦ Send values through some combinational logic. ♦ Write results to one or more state elements

St a t e St a t e el e m e n t Co m b i n a t i o n a l lo g i c el e m e n t 1 2

Cl o c k cy c l e

Clk Setup Hold Setup Hold Don’t Care

......

State State element 1 element 2

Edge triggered clocking methodology

All storage elements are clocked by the same clock edge.

Cycle Time = CLK-to-Q + Max-Delay-Path + Setup + Clock Skew

(CLK-to-Q + Min-Delay Path - Clock Skew)

Fetch the Instruction: mem[PC] Update the program counter: Sequential Code Branch and Jump

Clk PC

Next Address Logic

Address Instruction Word Instruction 32 Memory

R[rd] <= R[rs] op R[rt] For example: addU rd, rs, rt • Ra, Rb and Rw come from rs, rt and rd fields • ALUctr and RegWr

31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Rd Rs Rt RegWr ALUctr 5 5 5 busA Rw Ra Rb ALU busW 32 32-bit 32 Result 32 Registers 32 Clk busB 32

Clk Clk-to-Q PC Old Value New Value Instruction Memory Access Time Rs, Rt, Rd, Old Value New Value Op, Func Delay through Control Logic ALUctr Old Value New Value

RegWr Old Value New Value Register File Access Time busA, B Old Value New Value ALU Delay busW Old Value New Value

Two actions in parallel. 1. The control unit decode the Opcode and Func field and set the control signals ALUctr and RegWr. 2. While this is happening the register file is also read.

R[rt] <= R[rs] OR ZeroExt(imm16)

Example: ori rt, rs, imm16

31 26 21 16 11 0

op rs rt immediate

6 bits 5 bits 5 bits rd? 16 bits

Rd Rt RegDst Mux Rs ALUctr RegWr 5 5 5 busA Rw Ra Rb

busW ALU 32 32-bit 32 Result 32 Registers 32 Clk busB 32 Mux

ZeroExt

imm16 16 32 ALUSrc

Two MUX are needed

R[rt] <= Mem[R[rs] + SignExt(imm16)]

Example: lw rt, rs, imm16

31 26 21 16 0

op rs rt immediate 6 bits 5 bits 5 bits 16 bits

Rd Rt RegDst Mux Rs ALUctr RegWr 5 5 5 busA W_Src Rw Ra Rb

busW ALU 32 32-bit 32 32 Registers 32 Clk busB

MemWr Mux Mux 32 Extender WrEn Adr Data In 32 imm16 32 Data 16 32 Memory Clk ALUSrc

ExtOp

Mem[ R[rs] + SignExt(imm16) ] <= R[rt]

Example: sw rt, rs, imm16

Rd Rt ALUctr MemWr W_Src RegDst Mux Rs Rt RegWr 5 5 5 busA Rw Ra Rb busW ALU 32 32-bit 32 32 Registers 32 busB Mux

Clk Mux 32 Extender WrEn Adr Data In 32 32 Data imm16 32 16 Memory Clk

ExtOp ALUSrc

2631 21 16 0 op rs rt immediate 6 bits5 bits 5 bits 16 bits

beq rs, rt, imm16

mem[PC] Fetch the instruction from memory

Equal <= (R[rs] = = R[rt]) Calculate branch condition

if (COND eq 0) Calculate the next instruction’s address then PC <= PC + 4 + { SignExt(imm16), 2b"00 } else PC <= PC + 4

beq rs, rt, imm16

Datapath generates the (equal) condition

Inst Address Cond

nPC_sel Rs Rt 4 RegWr

Adder 5 5 5 32 busA Rw Ra Rb

00 busW 32

Mux 32 32-bit

PC Registers Clk busB Equal? Adder 32 PC Ext imm16

Clk

Next Address

Logic

Putting it All Together

<21:25> <16:20> <11:15>

<0:15> Instruction<31:0> Inst Memory Adr Rs RdRt Imm16

RegDst nPC_sel Equal ALUctr MemWr MemtoReg Rd Rt 1 0 Rs Rt 4 RegWr

Adder 5 5 5 busA Rw Ra Rb =

busW ALU 00 32 Mux 32 32-bit PC 32 Registers busB 32 0 0 Mux Mux

Adder 32

Clk Extender 32 PC Ext WrEn Adr 1 Clk 1 Data In imm16 32 Data 16 Memory Clk imm16

ExtOp ALUSrc

During read operation:

Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Access Time + Register File Access Time + ALU 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew

Ideal Instruction Instruction Memory Rd Rs Rt Imm 5 5 5 16 Instruction Address A Data Rw Ra Rb 32 Address 32 32 ALU Ideal 32 32-bit Data

PC Registers B Data Memory In Next Address Clk Clk 32 Clk Clk

Ideal Control Instruction Instruction Control Signals Conditions Memory Rd Rs Rt 5 5 5 Instruction Address A Data Data Rw Ra Rb 32 Address 32 32 ALU Ideal Out 32 32-bit Data

PC Registers B Data Memory In Next Address Clk Clk 32 Clk Clk Datapath

Logical vs. Physical Structure