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Chipyard Documentation Chipyard Documentation Berkeley Architecture Research Aug 26, 2021 Contents 1 Getting Help 3 2 Table of Contents 5 2.1 Chipyard Basics.............................................5 2.1.1 Chipyard Components.....................................5 2.1.2 Development Ecosystem....................................7 2.1.3 Configs, Parameters, Mixins, and Everything In Between...................8 2.1.4 Initial Repository Setup..................................... 11 2.2 Simulation................................................ 15 2.2.1 Software RTL Simulation.................................... 15 2.2.2 FPGA-Accelerated Simulation................................. 18 2.3 Included RTL Generators........................................ 20 2.3.1 Rocket Chip........................................... 20 2.3.2 Rocket Core........................................... 22 2.3.3 Berkeley Out-of-Order Machine (BOOM)........................... 24 2.3.4 Hwacha............................................. 25 2.3.5 Gemmini............................................ 25 2.3.6 IceNet.............................................. 29 2.3.7 Test Chip IP........................................... 30 2.3.8 SiFive Generators........................................ 32 2.3.9 SHA3 RoCC Accelerator.................................... 33 2.3.10 CVA6 Core........................................... 34 2.3.11 NVDLA............................................. 34 2.3.12 Sodor Core........................................... 35 2.4 Development Tools............................................ 35 2.4.1 Chisel.............................................. 35 2.4.2 FIRRTL............................................. 35 2.4.3 Treadle and FIRRTL Interpreter................................ 36 2.4.4 Chisel Testers.......................................... 36 2.4.5 Dsptools............................................. 36 2.4.6 Barstools............................................ 36 2.4.7 Dromajo............................................. 39 2.5 VLSI Flow................................................ 39 2.5.1 Building A Chip........................................ 40 2.5.2 Core Hammer.......................................... 41 2.5.3 Configuration (Hammer IR).................................. 41 i 2.5.4 Tool Plugins........................................... 41 2.5.5 Technology Plugins....................................... 42 2.5.6 Using Hammer To Place and Route a Custom Block...................... 42 2.5.7 ASAP7 Tutorial......................................... 49 2.5.8 Advanced Usage........................................ 53 2.6 Customization.............................................. 54 2.6.1 Heterogeneous SoCs...................................... 55 2.6.2 Integrating Custom Chisel Projects into the Generator Build System............. 57 2.6.3 Adding a custom core...................................... 57 2.6.4 RoCC vs MMIO........................................ 65 2.6.5 Adding a RoCC Accelerator.................................. 66 2.6.6 MMIO Peripherals....................................... 67 2.6.7 Dsptools Blocks......................................... 73 2.6.8 Keys, Traits, and Configs.................................... 79 2.6.9 Adding a DMA Device..................................... 82 2.6.10 Incorporating Verilog Blocks.................................. 85 2.6.11 Memory Hierarchy....................................... 89 2.6.12 Chipyard Boot Process..................................... 90 2.6.13 Adding a Firrtl Transform................................... 91 2.6.14 IOBinders and HarnessBinders................................. 93 2.7 Target Software.............................................. 95 2.7.1 FireMarshal........................................... 95 2.7.2 The RISC-V ISA Simulator (Spike).............................. 95 2.7.3 Baremetal RISC-V Programs.................................. 96 2.8 Advanced Concepts........................................... 96 2.8.1 Tops, Test-Harnesses, and the Test-Driver........................... 96 2.8.2 Communicating with the DUT................................. 98 2.8.3 Debugging RTL......................................... 104 2.8.4 Debugging BOOM....................................... 105 2.8.5 Accessing Scala Resources................................... 106 2.8.6 Context-Dependent-Environments............................... 106 2.8.7 Creating Clocks in the Test Harness.............................. 108 2.9 TileLink and Diplomacy Reference................................... 109 2.9.1 TileLink Node Types...................................... 109 2.9.2 Diplomacy Connectors..................................... 114 2.9.3 TileLink Edge Object Methods................................. 115 2.9.4 Register Router......................................... 119 2.9.5 Diplomatic Widgets....................................... 122 2.10 Prototyping Flow............................................. 130 2.10.1 General Setup and Usage.................................... 130 2.10.2 Running a Design on VCU118................................. 131 2.10.3 Running a Design on Arty................................... 135 3 Indices and tables 137 ii Chipyard Documentation Chipyard is a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip. Important: New to Chipyard? Jump to the Initial Repository Setup page for setup instructions. Contents 1 Chipyard Documentation 2 Contents CHAPTER 1 Getting Help If you have a question about Chipyard that isn’t answered by the existing documentation, feel free to ask for help on the Chipyard Google Group. 3 Chipyard Documentation 4 Chapter 1. Getting Help CHAPTER 2 Table of Contents 2.1 Chipyard Basics These sections will walk you through the basics of the Chipyard framework: • First, we will go over the components of the framework. • Next, we will go over how to understand how Chipyard configures its designs. • Then, we will go over initial framework setup. Hit next to get started! 2.1.1 Chipyard Components Generators The Chipyard Framework currently consists of the following RTL generators: Processor Cores Rocket Core An in-order RISC-V core. See Rocket Core for more information. BOOM (Berkeley Out-of-Order Machine) An out-of-order RISC-V core. See Berkeley Out-of-Order Machine (BOOM) for more information. CVA6 Core An in-order RISC-V core written in System Verilog. Previously called Ariane. See CVA6 Core for more information. 5 Chipyard Documentation Accelerators Hwacha A decoupled vector architecture co-processor. Hwacha currently implements a non-standard RISC-V exten- sion, using a vector architecture programming model. Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface. See Hwacha for more information. Gemmini A matrix-multiply accelerator targeting neural-networks SHA3 A fixed-function accelerator for the SHA3 hash function. This simple accelerator is used as a demonstration for some of the Chipyard integration flows using the RoCC interface. System Components: icenet A Network Interface Controller (NIC) designed to achieve up to 200 Gbps. sifive-blocks System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator. These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices. AWL (Analog Widget Library) Digital components required for integration with high speed serial links. testchipip A collection of utilities used for testing chips and interfacing them with larger test environments. Tools Chisel A hardware description library embedded in Scala. Chisel is used to write RTL generators using meta- programming, by embedding hardware generation primitives in the Scala programming language. The Chisel compiler elaborates the generator into a FIRRTL output. See Chisel for more information. FIRRTL An intermediate representation library for RTL description of digital designs. FIRRTL is used as a formal- ized digital circuit representation between Chisel and Verilog. FIRRTL enables digital circuits manipulation between Chisel elaboration and Verilog generation. See FIRRTL for more information. Barstools A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL. See Barstools for more information. Dsptools A Chisel library for writing custom signal processing hardware, as well as integrating custom signal pro- cessing hardware into an SoC (especially a Rocket-based SoC). Dromajo A RV64GC emulator primarily used for co-simulation and was originally developed by Esperanto Tech- nologies. See Dromajo for more information. Toolchains riscv-tools A collection of software toolchains used to develop and execute software on the RISC-V ISA. The include compiler and assembler toolchains, functional ISA simulator (spike), the Berkeley Boot Loader (BBL) and proxy kernel. The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.). Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the Chipyard framework. esp-tools A fork of riscv-tools,
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