Release Notes Fedora Electronic Lab 12 'Constantine'
Total Page：16
File Type：pdf, Size：1020Kb
Load more
Recommended publications
-
Amateur Radio Software Distributed with (X)Ubuntu LTS Serge Stroobandt, ON4AA
Amateur Radio Software Distributed with (X)Ubuntu LTS Serge Stroobandt, ON4AA Copyright 2014–2018, licensed under Creative Commons BY-NC-SA Introduction Amateur radio (also called “ham radio”), is a technical hobby Many ham radio stations are highly integrated with computers. Radios are interfaced with com- puters to aid with contact logging, propagation prediction, station spotting, antenna steering, signal (de)modulation and filtering. For many years, amateur radio software has been a bastion of Windows™ ap- plications developed by However, with the advent of the Rasperry Pi, amateur radio hobbyists are slowly but surely discovering GNU/Linux. Most of the software for GNU/Linux is available through package repositories. Such package repositories come by default with the GNU/Linux distribution of your choice. Package management systems offer many benefits in the form of security (you know what you are getting from whom) and ease-of-use (packages are upgraded automatically). No longer does one need to wander the back corners of the internet to find wne or updated software, exposing oneself to the risk of catching a computer virus. A number of GNU/Linux distributions offer freely installable ham-related packages under the “Amateur Radio” section of their main repository. The largest collection of ham radio packages is offeredy b OpenSuse and De- bian-derived distributions like Xubuntu LTS and Linux Mint, to name but a few. Arch Linux may also have whole bunch of ham related software in the Arch User Repository (AUR). 1 Synaptic One way to find and tallins ham radio packages on Debian-derived distros is by using the Synaptic graphical package manager (see Figure 1). -
Development of Systemc Modules from HDL for System-On-Chip Applications
University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Masters Theses Graduate School 8-2004 Development of SystemC Modules from HDL for System-on-Chip Applications Siddhartha Devalapalli University of Tennessee - Knoxville Follow this and additional works at: https://trace.tennessee.edu/utk_gradthes Part of the Electrical and Computer Engineering Commons Recommended Citation Devalapalli, Siddhartha, "Development of SystemC Modules from HDL for System-on-Chip Applications. " Master's Thesis, University of Tennessee, 2004. https://trace.tennessee.edu/utk_gradthes/2119 This Thesis is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Masters Theses by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications." I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted in partial fulfillment of the equirr ements for the degree of Master of Science, with a major in Electrical Engineering. Dr. Donald W. Bouldin, Major Professor We have read this thesis and recommend its acceptance: Dr. Gregory D. Peterson, Dr. Chandra Tan Accepted for the Council: Carolyn R. Hodges Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications". -
A Fedora Electronic Lab Presentation
Chitlesh GOORAH Design & Verification Club Bristol 2010 FUDConBrussels 2007 - [email protected] [ Free Electronic Lab ] (formerly Fedora Electronic Lab) An opensource Design and Simulation platform for Micro-Electronics A one-stop linux distribution for hardware design Marketing means for opensource EDA developers (Networking) From SPEC, Model, Frontend Design, Backend, Development boards to embedded software. FUDConBrussels 2007 - [email protected] Electronic Designers Problems Approx. 6 month design development cycle Tackling Design Complexity Lower Power, Lower Cost and Smaller Space Semiconductor Industry's neck squeezed in 2008 Management (digital/analog) IP Portfolio FUDConBrussels 2007 - [email protected] FUDConBrussels 2007 - [email protected] A basic Design Flow FUDConBrussels 2007 - [email protected] TIP: Use verilator to lint your verilog files. Most of the Veripool tools are available under FEL. They are in sync with Wilson Snyder's releases. FUDConBrussels 2007 - [email protected] FUDConBrussels 2007 - [email protected] GTKWaveGTKWave Don'tDon't forgetforget itsits TCLTCL backendbackend WidelyWidely usedused togethertogether withwith SystemCSystemC FUDConBrussels 2007 - [email protected] Tools Standard Cell libraries FUDConBrussels 2007 - [email protected] BackendBackend designdesign Open Circuit Design, Electric FUDConBrussels 2007 - [email protected], Toped gEDA/gafgEDA/gaf Well known and famous. A very good example of opensource -
Simulator for the RV32-Versat Architecture
Simulator for the RV32-Versat Architecture João César Martins Moutoso Ratinho Thesis to obtain the Master of Science Degree in Electrical and Computer Engineering Supervisor(s): Prof. José João Henriques Teixeira de Sousa Examination Committee Chairperson: Prof. Francisco André Corrêa Alegria Supervisor: Prof. José João Henriques Teixeira de Sousa Member of the Committee: Prof. Marcelino Bicho dos Santos November 2019 ii Declaration I declare that this document is an original work of my own authorship and that it fulfills all the require- ments of the Code of Conduct and Good Practices of the Universidade de Lisboa. iii iv Acknowledgments I want to thank my supervisor, Professor Jose´ Teixeira de Sousa, for the opportunity to develop this work and for his guidance and support during that process. His help was fundamental to overcome the multiple obstacles that I faced during this work. I also want to acknowledge Professor Horacio´ Neto for providing a simple Convolutional Neural Net- work application, used as a basis for the application developed for the RV32-Versat architecture. A special acknowledgement goes to my friends, for their continuous support, and Valter,´ that is developing a multi-layer architecture for RV32-Versat. When everything seemed to be doomed he always had a miraculous solution. Finally, I want to express my sincere gratitude to my family for giving me all the support and encour- agement that I needed throughout my years of study and through the process of researching and writing this thesis. They are also part of this work. Thank you. v vi Resumo Esta tese apresenta um novo ambiente de simulac¸ao˜ para a arquitectura RV32-Versat baseado na ferramenta de simulac¸ao˜ Verilator. -
Elementary Filter Circuits
Modular Electronics Learning (ModEL) project * SPICE ckt v1 1 0 dc 12 v2 2 1 dc 15 r1 2 3 4700 r2 3 0 7100 .dc v1 12 12 1 .print dc v(2,3) .print dc i(v2) .end V = I R Elementary Filter Circuits c 2018-2021 by Tony R. Kuphaldt – under the terms and conditions of the Creative Commons Attribution 4.0 International Public License Last update = 13 September 2021 This is a copyrighted work, but licensed under the Creative Commons Attribution 4.0 International Public License. A copy of this license is found in the last Appendix of this document. Alternatively, you may visit http://creativecommons.org/licenses/by/4.0/ or send a letter to Creative Commons: 171 Second Street, Suite 300, San Francisco, California, 94105, USA. The terms and conditions of this license allow for free copying, distribution, and/or modification of all licensed works by the general public. ii Contents 1 Introduction 3 2 Case Tutorial 5 2.1 Example: RC filter design ................................. 6 3 Tutorial 9 3.1 Signal separation ...................................... 9 3.2 Reactive filtering ...................................... 10 3.3 Bode plots .......................................... 14 3.4 LC resonant filters ..................................... 15 3.5 Roll-off ........................................... 17 3.6 Mechanical-electrical filters ................................ 18 3.7 Summary .......................................... 20 4 Historical References 25 4.1 Wave screens ........................................ 26 5 Derivations and Technical References 29 5.1 Decibels ........................................... 30 6 Programming References 41 6.1 Programming in C++ ................................... 42 6.2 Programming in Python .................................. 46 6.3 Modeling low-pass filters using C++ ........................... 51 7 Questions 63 7.1 Conceptual reasoning ................................... -
Getting Started in High Performance Electronic Design
Getting started in high performance electronic design Wojtek Skulski Department of Physics and Astronomy University of Rochester Rochester, NY 14627-0171 skulski _at_ pas.rochester.edu First presented May/23/2002 Updated for the web July/03/2004 Wojtek Skulski May/2002 Department of Physics and Astronomy, University of Rochester Getting started with High performance electronic design • 3-hour class • Designing high performance surface mount and multilayer boards. • What tools and resources are available? • How to get my design manufactured and assembled? • Board design with OrCAD Capture and Layout. • When and where: • Thursday, May/23/2002, 9-12am, Bausch&Lomb room 106 (1st floor). • Slides updated for the web July/03/2004. • Reserve your handout. • Send e-mail to [email protected] if you plan to attend. • Walk-ins are invited, but there may be no handouts if you do not register. • See you there! Wojtek Skulski May/2002 Department of Physics and Astronomy, University of Rochester The goal and outline of this class • Goal: • Describe the tools available to us for designing high performance electronic instruments. • Outline • Why do we need surface mount and multilayer boards? • What tools and resources are available? • How to get my PCB manufactured? • How to get my board assembled? • Designing with OrCAD Capture and OrCAD Layout. • The audience • You know the basics of electronics. • … and you need to get going quickly with your design. Wojtek Skulski May/2002 Department of Physics and Astronomy, University of Rochester Disclaimer • I am describing tools and methods which work for me. • I do not claim that this information is complete. -
Nanoelectronic Mixed-Signal System Design
Nanoelectronic Mixed-Signal System Design Saraju P. Mohanty Saraju P. Mohanty University of North Texas, Denton. e-mail: [email protected] 1 Contents Nanoelectronic Mixed-Signal System Design ............................................... 1 Saraju P. Mohanty 1 Opportunities and Challenges of Nanoscale Technology and Systems ........................ 1 1 Introduction ..................................................................... 1 2 Mixed-Signal Circuits and Systems . .............................................. 3 2.1 Different Processors: Electrical to Mechanical ................................ 3 2.2 Analog Versus Digital Processors . .......................................... 4 2.3 Analog, Digital, Mixed-Signal Circuits and Systems . ........................ 4 2.4 Two Types of Mixed-Signal Systems . ..................................... 4 3 Nanoscale CMOS Circuit Technology . .............................................. 6 3.1 Developmental Trend . ................................................... 6 3.2 Nanoscale CMOS Alternative Device Options ................................ 6 3.3 Advantage and Disadvantages of Technology Scaling . ........................ 9 3.4 Challenges in Nanoscale Design . .......................................... 9 4 Power Consumption and Leakage Dissipation Issues in AMS-SoCs . ................... 10 4.1 Power Consumption in Various Components in AMS-SoCs . ................... 10 4.2 Power and Leakage Trend in Nanoscale Technology . ........................ 10 4.3 The Impact of Power Consumption -
FPGA-Accelerated Evaluation and Verification of RTL Designs
FPGA-Accelerated Evaluation and Verification of RTL Designs Donggyu Kim Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2019-57 http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-57.html May 17, 2019 Copyright © 2019, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. FPGA-Accelerated Evaluation and Verification of RTL Designs by Donggyu Kim A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Krste Asanovi´c,Chair Adjunct Assistant Professor Jonathan Bachrach Professor Rhonda Righter Spring 2019 FPGA-Accelerated Evaluation and Verification of RTL Designs Copyright c 2019 by Donggyu Kim 1 Abstract FPGA-Accelerated Evaluation and Verification of RTL Designs by Donggyu Kim Doctor of Philosophy in Computer Science University of California, Berkeley Professor Krste Asanovi´c,Chair This thesis presents fast and accurate RTL simulation methodologies for performance, power, and energy evaluation as well as verification and debugging using FPGAs in the hardware/software co-design flow. Cycle-level microarchitectural software simulation is the bottleneck of the hard- ware/software co-design cycle due to its slow speed and the difficulty of simulator validation. -
Static Analysis to Improve RTL Verification
Static Analysis to Improve RTL Verification Akash Agrawal Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Master of Science in Computer Engineering Michael Hsiao, Chair Haibo Zeng A. Lynn Abbott February 16, 2017 Blacksburg, Virginia Keywords: Static Analysis, ATPG, RTL, Reachability Analysis Copyright 2017, Akash Agrawal Static Analysis to Improve RTL Verification Akash Agrawal ABSTRACT Integrated circuits have traveled a long way from being a general purpose microprocessor to an application specific circuit. It has become an integral part of the modern era of technology that we live in. As the applications and their complexities are increasing rapidly every day, so are the sizes of these circuits. With the increase in the design size, the associated testing effort to verify these designs is also increased. The goal of this thesis is to leverage some of the static analysis techniques to reduce the effort of testing and verification at the register transfer level. Studying a design at register transfer level gives exposure to the relational information for the design which is inaccessible at the structural level. In this thesis, we present a way to generate a Data Dependency Graph and a Control Flow Graph out of a register transfer level description of a circuit description. Next, the generated graphs are used to perform relation mining to improve the test generation process in terms of speed, branch coverage and number of test vectors generated. The generated control flow graph gives valuable information about the flow of information through the circuit design. -
Performed the Most Often. in FPGA Design Flow, Functional and Gate
performed the most often. In FPGA design flow, functional and gate-level timing simulation is typically performed when designers suspect that there might be a mismatch between RTL and functional or gate-level timing simulation results, which can lead to an incorrect design. The mismatch can be caused for several reasons discussed in more detail in Tip #59. Note that the nomenclature of simulation types is not consistent. The same name, for instance “gate-level simulation”, can have slightly different meaning in simulation flows of different FPGA vendors. The situation is even more confusing in ASIC simulation flows, which have many more different simulation types, such as transistor-level, and dynamic simulation. The following figure shows simulation types designers can perform during Xilinx FPGA synthesis and physical implementation process. Figure 1: Simulation types Xilinx FPGA designers can perform simulation after each level of design transformation from the original RTL to the bitstream. The following example is a 12-bit OR gate implemented in Verilog. module sim_types(input [11:0] user_in, output user_out); assign user_out = |user_in; endmodule XST post-synthesis simulation model is implemented using LUT6 and LUT2 primitives, which are parts of Xilinx UNISIMS RTL simulation library. wire out, out1_14; LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFE )) out1 ( .I0(user_in[3]), .I1(user_in[2]), .I2(user_in[5]), .I3(user_in[4]), .I4(user_in[7]), .I5(user_in[6]), .O(out)); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFE )) out2 ( .I0(user_in[9]), .I1(user_in[8]), .I2(user_in[11]), .I3(user_in[10]), .I4(user_in[1]), .I5(user_in[0]), .O(out1_14)); LUT2 #( .INIT ( 4'hE )) out3 ( .I0(out), .I1(out1_14), .O(user_out) ); Post-synthesis simulation model can be generated using the following command: $ netgen -w -ofmt verilog -sim sim.ngc post_synthesis.v Post-translate simulation model is implemented using X_LUT6 and X_LUT2 primitives, which are parts of Xilinx SIMPRIMS simulation library. -
Pcb-20050609 an Interactive Printed Circuit Board Layout System for X11
1 Pcb-20050609 an interactive printed circuit board layout system for X11 harry eaton i Table of Contents Copying ...................................... 1 History ....................................... 2 1 Overview .................................. 4 2 Introduction ............................... 5 2.1 Symbols .................................................... 5 2.2 Vias........................................................ 5 2.3 Elements ................................................... 5 2.4 Layers ...................................................... 7 2.5 Lines ....................................................... 8 2.6 Arcs........................................................ 9 2.7 Polygons ................................................... 9 2.8 Text ...................................................... 10 2.9 Nets....................................................... 10 3 Getting Started........................... 11 3.1 The Application Window ................................... 11 3.1.1 Menus ................................................ 11 3.1.2 The Status-line and Input-field ......................... 14 3.1.3 The Panner Control.................................... 14 3.1.4 The Layer Controls .................................... 15 3.1.5 The Tool Selectors ..................................... 16 3.1.6 Layout Area........................................... 18 3.2 Log Window ............................................... 18 3.3 Library Window ........................................... 18 3.4 Netlist Window -
RTL Design and Implementation of a Framebuffer for a RISC-V Processor
Universitat Politècnica de Catalunya (UPC) BarcelonaTech Facultat d’Informàtica de Barcelona (FIB) RTL design and implementation of a framebuffer for a RISC-V processor Educational Cooperative Agreement with Barcelona Supercomputing Centre (BSC) Computer Engineering Degree Final Project Author: Narcís Rodas Quiroga Supervisor: Miquel Moretó (Computer Architecture Department DAC) Co-supervisor: Guillem Cabo Specialization: Computer Engineering Date of oral defense: 28th of October 2020 Abstract The RISC-V instruction set architecture (ISA) and the foundation that supports it continue to grow rapidly as an open-source alternative for hardware designs. Despite open-source software already being established as an important part of all the software solutions, open-source hardware has only recently begun to expand. Before that, the market was entirely made of proprietary ISAs (mostly from the US) that controlled it. This Final Degree Thesis shows the design, implementation and testing of a VGA (Video Graphics Array) framebuffer for the RISC-V processor being developed in the DRAC project by the Barcelona Supercomputing Centre. This document explains the various steps taken along the way and the reasoning behind the decisions that were taken. Keywords: RISC-V, VGA, RTL, Verilog, Framebuffer, AXI. Resumen El conjunto de instrucciones o ISA (del inglés instruction set architecture) RISC-V y la fundación que lo respalda siguen creciendo rápidamente como una alternativa open-source para los diseños hardware. Aunque el software open-source ya representa una parte importante de todas las soluciones software, el hardware open-source todavía está empezando a expandirse. Antes de esto, el mercado estaba compuesto íntegramente de ISAs propietarias (la gran mayoría provenientes de los E.E.