Universitat Politècnica de Catalunya (UPC) BarcelonaTech Facultat d’Informàtica de Barcelona (FIB) RTL design and implementation of a framebuffer for a RISC-V processor Educational Cooperative Agreement with Barcelona Supercomputing Centre (BSC) Computer Engineering Degree Final Project Author: Narcís Rodas Quiroga ​ Supervisor: Miquel Moretó (Computer Architecture Department DAC) ​ Co-supervisor: Guillem Cabo ​ Specialization: Computer Engineering ​ Date of oral defense: 28th of October 2020 ​ Abstract The RISC-V instruction set architecture (ISA) and the foundation that supports it continue to grow rapidly as an open-source alternative for hardware designs. Despite open-source software already being established as an important part of all the software solutions, open-source hardware has only recently begun to expand. Before that, the market was entirely made of proprietary ISAs (mostly from the US) that controlled it. This Final Degree Thesis shows the design, implementation and testing of a VGA (Video Graphics Array) framebuffer for the RISC-V processor being developed in the DRAC project by the Barcelona Supercomputing Centre. This document explains the various steps taken along the way and the reasoning behind the decisions that were taken. Keywords: RISC-V, VGA, RTL, Verilog, Framebuffer, AXI. ​ Resumen El conjunto de instrucciones o ISA (del inglés instruction set architecture) RISC-V y la ​ ​ fundación que lo respalda siguen creciendo rápidamente como una alternativa open-source para los diseños hardware. Aunque el software open-source ya representa una parte importante de todas las soluciones software, el hardware open-source todavía está empezando a expandirse. Antes de esto, el mercado estaba compuesto íntegramente de ISAs propietarias (la gran mayoría provenientes de los E.E. U.U.) que lo controlaban. Este Trabajo de Final de Grado muestra el diseño, implementación y el testing de un framebuffer VGA para el procesador RISC-V que se está desarrollando en el proyecto DRAC por el Barcelona Supercomputing Centre. En este documento se muestran los diversos pasos seguidos y el razonamiento detrás de las decisiones tomadas. Palabras clave: RISC-V, VGA, RTL, Verilog, Memoria de video, AXI. ​ 1 Resum El conjunt d’instruccions o ISA (de l’anglès instruction set architecture) RISC-V i la ​ ​ fundació que el recolza segueixen creixent ràpidament com una alternativa open-source per als dissenys hardware. Tot i que el software open-source ja representa una part important de totes les solucions software, el hardware open-source encara està començant a expandir-se. Abans d’això, el mercat estava format íntegrament per ISAs propietàries (la gran majoria provinents dels EUA) que el controlaven. Aquest Treball de Final de Grau mostra el disseny, implementació i el testing d’un framebuffer VGA pel processador RISC-V que s’està desenvolupant en el projecte DRAC del Barcelona Supercomputing Centre. En aquest document s’expliquen els diversos passos seguits i el raonament darrera les decisions preses. Paraules clau: RISC-V, VGA, RTL, Verilog, Memòria de vídeo, AXI. ​ 2 Index 1. Context and scope 5 1.1. The project in the BSC framework 5 1.2. Definition of terms and concepts 6 1.3. Identification of the problem and project justification 6 1.4. Stakeholders 7 1.5. Comparison with alternatives 7 1.6. Scope 8 1.6.1. General and sub-objectives 8 1.6.2. Functional and non-functional requirements 8 1.7. Obstacles and risks 9 2. Initial work plan 10 2.1. Work methodology 10 2.2. Monitoring tools 11 2.3. Description of tasks 11 2.3.1. Description, time estimation and dependencies 11 2.3.2. Required human and material resources 13 2.3.3. Summary table 14 2.3.4. Alternative tasks 15 2.3.5. Additional resources 15 2.3.6. Gantt chart 16 2.4. Budget 17 2.4.1. Staff costs 17 2.4.2. General costs 17 2.4.3. Contingency and incidentals 17 2.4.4. Cost estimates 18 3. Final work plan 20 3.1. Changes in the tasks and time assignments 20 3.2. Changes in resources 23 3.3. Changes in the budget 23 4. Background 24 4.1. Open-source hardware 24 4.2. DRAC core and SoC 24 4.3. VGA protocol 25 4.4. AXI protocol 27 4.4.1. Full AXI 27 3 4.4.2. AXI-Lite 27 5. RTL design and testing 29 5.1. Initial state of the art research and setup 29 5.2. Design of the PCB for the integration 30 5.3. Design decisions and comparison between options 31 5.4. First implementation on the BlackIce Mx FPGA 33 5.5. Tests of other resolutions 35 5.6. Mutation tests 36 5.7. DRAC environment setup and AXI diagram 38 5.8. AXI wrapper design 40 5.9. Integration with the DRAC core 41 5.10. Tests with the KC705 and the PCB 44 6. Sustainability report 49 6.1. Self-evaluation 49 6.2. Economic dimension 49 6.2.1. PPP 49 6.2.2. Exploitation 49 6.2.3. Risks 50 6.3. Environmental dimension 50 6.3.1. PPP 50 6.3.2. Exploitation 50 6.3.3. Risks 50 6.4. Social dimension 51 6.4.1. PPP 51 6.4.2. Exploitation 51 6.4.3. Risks 51 7. Conclusions 52 8. References 53 4 1. Context and justification 1.1. The project in the BSC framework This work is a part of the Barcelona Supercomputing Centre DRAC (Designing RISC-V-based Accelerators for the next generation Computers) project. The main goal of the DRAC is the design of a RISC-V based general-purpose processor with accelerators for future computers [1][2] and it will include the developed framebuffer to add a VGA controller to the integrated circuit. The targets of the project are specific applications in the fields of safety, genomics and autonomous driving. The first of these processors, the Lagarto, was built at the end of 2019 as the first open-source chip developed in Spain [3]. It is made with TSMC 65 nm transistors, produced by the Taiwanese company following the indications they had been given. The addition of the framebuffer and VGA controller designed in this project to the DRAC chip will allow it to be used independently from other systems, making it easier to use and also to debug in case of errors. Parallel to the DRAC project, BSC is also currently working on the European Processor Initiative (EPI) with the main goal of designing low power processors for high-performance computing and embedded systems [4]. These will exclusively be made with European and open source technology to help mitigate the dependence on United States hardware. Figure 1. The preDRAC printed circuit board with the Lagarto core (left) [2] 5 1.2. Definition of terms and concepts ● RTL: acronym of Register Transfer Level. It is an abstraction used to define the ​ digital phase of design [5]. It is one of the first steps in integrated circuit design, right after defining the microarchitecture and the instruction set. RTL design is usually made using a hardware description language like VHDL or Verilog, and later it is synthesized to begin the physical design step. ● RISC-V: free and open RISC (Reduced Instruction Set Computer) type ISA ​ (Instruction Set Architecture) that promotes open collaboration to advance to the next era in the innovation of processors [6]. It offers more freedom in software and hardware of computer engineering, avoiding royalties. ● Framebuffer: memory region that stores the colour of the pixels (usually on a matrix) ​ of an image projected on a screen. Each pixel can store a value that represents the exact shade it will have when displayed. ● FPGA: Field Programmable Gate Arrays are a matrix of configurable logic blocks ​ (made of logic gates) that can be programmed, more than once, to provide different functionalities [7]. The programming is done using a hardware description language (like Verilog) that describes the structure and behaviour of digital logic circuits. ● ASIC: stands for Application-Specific Integrated Circuit and is a microchip designed ​ for a certain application in mind [8]. Unlike common processors, it can only perform a limited set of tasks it has been made for. The RTL design and simulation can be implemented on an FPGA to verify the performance on physical hardware and later move it onto an ASIC. ● AXI: communication interface part of the Arm Advanced Microcontroller Bus ​ Architecture (AMBA) specification [9]. ● PCB: a Printed Circuit Board is composed of a non-conductive substrate with ​ conductive tracks to connect electronic components [10]. 1.3. Identification of the problem and project justification In the previous tapeout, the DRAC chip communicates with other hosts through the serial port, to where it sends its commands. If we want the DRAC processor to provide a video output, the data has to be sent through this port and the host has to generate the output. The problem of doing it this way is that it occupies the serial port and makes the chip dependent on the host to display the video output. To overcome this limitation, we propose to add a stand-alone VGA connector, with its respective controller and framebuffer. This way, the next tapeout of the DRAC chip will have 6 an independent video output that will not need any other device to manage it and the serial port will be freed. 1.4. Stakeholders This section lists the people or organizations that participate directly in the development of the framebuffer and the VGA controller mentioned or that are interested in the results of this project: ● DRAC’s development team: everyone in the group is working hard on their respective parts to make the final result as good as possible.