An Open Source Approach for ASIC Design Flow Kesari Ananda Samhitha Y
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Journal of Interdisciplinary Cycle Research ISSN NO: 0022-1945 An Open Source approach for ASIC Design Flow Kesari Ananda Samhitha Y. David Solomon Raju M.Tech Associate Professor Holy Mary Institute of Technology Holy Mary Institute of Technology and ScienceAffiliated to JNTU, and Science Affiliated to JNTU, Hyderabad. Hyderabad. Email: [email protected] Email: davidsolomonraju.y@ gmail.com Abstract: In this paper, we are going to study In this paper, number of open-source and the process of implementation of ASIC freeware CAD tools are presented and design flow with the help of open source evaluated. Based on the objectives of the EDA tools. In order to design our own user, this paper furnishes guidelines that circuitry without any other expensive help in selecting the most appropriate licenced tools, we apt the open source open-source and freeware VLSI CAD tool tools. The design of electronic circuits can for teaching a VLSI design course. be achieved at many different refinement Keywords: VLSI, CAD Tools, Electric, levels from the most detailed layout to the Magic, Alliance, Comparative Study most abstract architectures. Introduction: Given the complexity of Very Large Scaled Integrated Circuits (VLSI) ASIC design flow is a very mature which is far beyond human ability, process in silicon turnkey design. The computers are increasingly used to aid in ASIC design flow and its various steps in the design and optimization processes. It is VLSI engineering that we describe below no longer efficient to use manual design are based on best practices and proven techniques, in which each layer is hand methodologies in ASIC chip designs. This etched or composed by laying tape on film paper attempts to explain different steps in due to the time-consuming process and the ASIC design flow, startingfrom ASIC lack of accuracy. design concept and moving from specifications to benefits. Therefore, Computer Aided Design (CAD) tools are heavily involved in the ASIC design flow: design process. In today’s market, there are plenty of VLSI CAD tools; however, ASIC design flow is a mature and most of them are expensive and require silicon-proven IC design process which high performance platforms. Selecting an includes various steps like design appropriate CAD tool for academic use is conceptualization, chip optimization, considered as one of the key challenges in logical/physical implementation, and teaching VLSI design courses. design validation and verification. Let’s have an overview of each of the steps involved in the process. Volume XII, Issue VIII, August/2020 Page No:1028 Journal of Interdisciplinary Cycle Research ISSN NO: 0022-1945 Two different teams are involved at this juncture: Design team: Generates RTL code. Verification team: Generates test bench. Step 2. Design Entry / Functional Verification: Functional verification confirms the functionality and logical behavior of the circuit by simulation on a design entry level. This is the stage where the design team and verification team come into the cycle where they generate RTL code using test-benches. This is known as behavioural Figure 1: ASIC design flow simulation. Steps involved in ASIC design flow: In this simulation, once the RTL code (RTL code is a set of code that checks whether the RTL implementation meets the design verification) is done in HDL, a lot of code coverage metrics proposed for HDL. Engineers aim to verify correctness of the code with the help of test vectors and trying to achieve it by 95% coverage test. This code coverage includes statement coverage, expression coverage, branch coverage, and toggle coverage. There are two types of simulation tools: Functional simulation tools: After the testbench and design code, functional simulation verifies Figure 2: Steps involved in ASIC design logical behavior and its flow implementation based on design entry. Timing simulation tools: Step 1. Chip Specification: Verifies that circuit design meets the timing requirements and This is the stage at which the confirms the design is free of engineer defines features, circuit signal delays. microarchitecture, functionalities (hardware/software interface), specifications (Time, Area, Power, Speed) with design guidelines of ASIC. Volume XII, Issue VIII, August/2020 Page No:1029 Journal of Interdisciplinary Cycle Research ISSN NO: 0022-1945 Step 3. RTL block synthesis / RTL different stages of the design cycle. Telling Function: the customers that the chips have fault when you are already at the production Once the RTL code and testbench stage is embarrassing and disruptive. are generated, the RTL team works on RTL description – they translate the RTL It’s a situation that no engineering code into a gate-level netlist using a team wants to be in. In order to overcome logical synthesis tool that meets required this situation, design for test is introduced timing constraints. Thereafter, a with a list of techniques: synthesized database of the ASIC design is created in the system. When timing Scan path insertion: A methodology of linking constraints are met with the logic all registers elements into one long synthesis, the design proceeds to the design for testability (DFT) techniques. shift register (scan path). This can help to check small parts of design Step 4. Chip Partitioning: instead of the whole design in one go. This is the stage wherein the engineer follows the ASIC design layout Memory BIST (built-in Self- Test): requirement and specification to create its In the lower technology structure using EDA tools and proven node, chip memory requires lower methodologies. This design structure is area and fast access time. MBIST going to be verified with the help of HLL is a device which is used to check programming languages like C++ or RAMs. It is a comprehensive System C. solution to memory testing errors After understanding the design and self-repair proficiencies. specifications, the engineers partition the ATPG (automatic test pattern entire ASIC into multiple functional generation): blocks (hierarchical modules), while ATPG is a method of keeping in mind ASIC’s best performance, creating test vectors / sequential technical feasibility, and resource input patterns to check the design allocation in terms of area, power, cost and for faults generated within various time. Once all the functional blocks are elements of a circuit. implemented in the architectural document, the engineers need to Step 6. Floor Planning (blueprint your brainstorm ASIC design partitioning by chip): reusing IPs from previous projects and After, DFT, the physical procuring them from other parties. implementation process is to be followed. Step 5. Design for Test (DFT) Insertion: In physical design, the first step in RTL- to-GDSII design is floorplanning. It is the With the ongoing trend of lower process of placing blocks in the chip. It technology nodes, there is an increase in includes: block placement, design system-on-chip variations like size, portioning, pin placement, and power threshold voltage and wire resistance. Due optimization. to these factors, new models and techniques are introduced to high-quality Floorplan determines the size of testing.ASIC design is complex enough at the chip, places the gates and connects them with wires. While connecting, Volume XII, Issue VIII, August/2020 Page No:1030 Journal of Interdisciplinary Cycle Research ISSN NO: 0022-1945 engineers take care of wire length, and clock tree with a minimum buffer insertion functionality which will ensure signals will and lower power consumption of chips. not interfere with nearby elements. In the end, simulate the final floor plan with post-layout verification process. Step 9. Routing: A good floorplanning exercise Global Routing: should come across and take care of the Calculates estimated values for below points; otherwise, the life of IC and each net by the delays of fan-out of its cost will blow out: wire. Global routing is mainly divided into line routingand maze Minimize the total chip area. routing. Make routing phase easy Detailed Routing: (routable). In detailed routing, the actual Improve signal delays delays of wire is calculated by Step 7. Placement: various optimization methods like timing optimization, clock tree Placement is the process of placing synthesis, etc. standard cells in row. A poor placement requires larger area and also degrades As we are moving towards a lower performance. Various factors, like the technology node, engineers face complex timing requirement, the net lengths and design challenges with the need for hence the connections of cells, power implanting millions of gates in a small dissipation should be taken care. It area. In order to make this ASIC design removes timing violation. routable, placement density range needs to be followed for better QoR. Placement Step 8. Clock tree synthesis: density analysis is an important parameter Clock tree synthesis is a process of to get better outcomes with a smaller building the clock tree and meeting the number of iterations. defined timing, area and power Step 10. Final Verification (Physical requirements. It helps in providing the Verification and Timing): clock connection to the clock pin of a sequential element in the required time and After routing, ASIC design layout area, with low power consumption. undergoes three steps of physical verification, known as signoff checks. This In order to avoid high power stage helps to check whether the layout consumption, increase in delays and a working the way it was designed to. The huge number of transitions, certain following checks are followed to avoid any structures can be used for optimizing CTS errors just before the tapeout: structure such as Mesh Structure, H-Tree Structure, X-Tree Structure, Fishbone Layout versus schematic (LVS) is a Structure and Hybrid structure.With the process of checking that the help of these structures, each flop in the geometry/layout matches the clock tree gets the clock connection. schematic/netlist. Design rule checks (DRC) is the During the optimization, tools process of checking that the insert the buffer to build the CTS structure.