Technical University of Munich Department of Electrical and Computer Engineering Chair of Electronic Design Automation
Fast RTL-based Fault Injection Framework for RISC-V Cores
Master’s Thesis
Johannes Geier
Technical University of Munich Department of Electrical and Computer Engineering Chair of Electronic Design Automation
Fast RTL-based Fault Injection Framework for RISC-V Cores
Master’s Thesis
Johannes Geier
Advisor : M.Sc. Uzair Sharif Advising Professor : Prof. Dr.-Ing. habil. Daniel M¨uller-Gritschneder Topic issued : 01.09.2019 Date of submission : 06.03.2020
Johannes Geier Hopfenstraße 29 85309 P¨ornbach [email protected]
Abstract
The growing demand of processing power in an increasing number of embedded systems de- ployed in various circumstances has led to new challenges towards the development of such systems. One of these challenges is a digital system’s resiliency against soft errors that can alter internal states and lead to unforeseen and sometimes critical behavior. Simulating such errors at a system’s early design phases can help with integrating and evaluating counter- measures. This work introduces a fast Register Transfer Level (RTL)-based fault injection framework for soft-error evaluations of RISC-V processor cores. To enable injections, a tool was developed that transforms the RTL model and builds a specific injection Application Pro- gramming Interface (API) from the core’s hardware description. The modified RTL and built API were put to test in a proof of concept framework evaluating an open-hardware RISC-V core’s behavior towards random bit flips in its internal states. The framework is characterized by its utilization of automatically generated, however, core-specific sources which enable a high fault injection capability while maintaining low simulation overhead. The evaluation results were analyzed with respect to the probability of a certain error occurring after a random bit flip and the probability of a specific injection target being the cause for a certain error. 4 Contents
1. Introduction 15 1.1. Motivation ...... 15 1.2. Contributions ...... 16 1.3. Tasks ...... 16
2. Background 19 2.1. Fault Model ...... 19 2.1.1. Soft Errors ...... 19 2.1.2. Injection Model ...... 20 2.1.3. Fault Effect Classification ...... 20 2.2. Verilator RTL ...... 22 2.2.1. Verilator ...... 22 2.2.2. Fault Injection ...... 23 2.2.3. RegPicker ...... 24 2.3. Simulation Target: RI5CY ...... 24 2.3.1. Pipeline ...... 24 2.3.2. Configuration ...... 25 2.3.3. Injection Targets ...... 25 2.4. LLVM ...... 27
3. Verilator RTL Modification 29 3.1. Verilator Evaluation ...... 29 3.1.1. Synthesis ...... 29 3.1.2. Fault Injection ...... 31 3.2. Modification ...... 32 3.2.1. Target Variables as Extended Data Structures ...... 32 3.2.2. Source Transformation ...... 34 3.3. Implementation ...... 37 3.3.1. Injection API Builder ...... 38 3.3.2. Injection Rewriter ...... 39
4. Simulation 43 4.1. Simulation Framework ...... 43 4.1.1. Modified VRTL Core ...... 44 4.1.2. Reduced Virtual System on Chip ...... 44 4.1.3. Injection Scheduler ...... 45 4.1.4. User Interface ...... 46 4.2. Simulation Setup ...... 48 4.2.1. Target Software ...... 48
5 Contents
4.2.2. Evaluation ...... 49
5. Evaluation 51 5.1. Error Classification ...... 51 5.2. Results Analysis ...... 53 5.2.1. Statistical Fault Effect Probability ...... 53 5.2.2. Data Processing and Visualization ...... 55
6. Results 59 6.1. Fault Effect Probability ...... 59 6.2. Fault Effect Causation ...... 64 6.2.1. Hang-up Errors ...... 64 6.2.2. System Errors ...... 67 6.2.3. Application Errors ...... 68 6.3. Conclusion ...... 71
7. Summary 73
A. Appendix 75
Bibliography 85
6 List of Figures
2.1. Simple register stage ...... 19 2.2. Single-bit target fault ...... 20 2.3. Verilator flow ...... 22 2.4. Signal types and classification ...... 23 2.5. RI5CY block diagram ...... 24 2.6. RI5CY injection target cluster ...... 26 2.7. Clang tooling ...... 27
3.1. VRTL example stimuli model ...... 29 3.2. Fault injection example ...... 30 3.3. Injection call with target dictionary ...... 37 3.4. API Builder process ...... 38 3.5. Injection API use case diagram ...... 38 3.6. Injection API target dictionary class diagram ...... 39 3.7. VRTL source transformation algorithm ...... 40 3.8. LLVM Tool - Finding sequential injection assignments ...... 41
4.1. Simulation framework ...... 43 4.2. Simulation framework toolchain ...... 48 4.3. Evaluation run ...... 50
5.1. Fault effect classification ...... 52 5.2. Evaluation cluster ...... 54 5.3. Erroneous fault effects, ALU test - heat map ...... 57
6.1. Hang-up pipeline stall, ALU test - causation cluster ...... 64 6.2. Hang-up logic stall, ALU test - causation cluster ...... 66 6.3. System error, ALU test - causation cluster ...... 67 6.4. Application error, ALU test - causation cluster ...... 69
A.1. RI5CY injection target cluster ...... 75 A.2. RI5CY hierarchy - modules and cell instances ...... 76 A.3. (HP) Pipeline stall, ALU test ...... 79 A.4. (HL) Logic stall, ALU test ...... 79 A.5. (HP) Pipeline stall, MUL test ...... 79 A.6. (HL) Logic stall, MUL test ...... 79 A.7. (HP) Pipeline stall, AES test ...... 79 A.8. (HL) Logic stall, AES test ...... 79 A.9. (SI) Illegal instruction, ALU test ...... 80
7 List of Figures
A.10.(SM) Memory access, ALU test ...... 80 A.11.(SI) Illegal instruction, MUL test ...... 80 A.12.(SM) Memory access, MUL test ...... 80 A.13.(SI) Illegal instruction, AES test ...... 80 A.14.(SM) Memory access, AES test ...... 80 A.15.(AO) Output, ALU test ...... 81 A.16.(AP) Program flow, ALU test ...... 81 A.17.(AO) Output, MUL test ...... 81 A.18.(AP) Program Flow, MUL test ...... 81 A.19.(AO) Output, AES test ...... 81 A.20.(AP) Program flow, AES test ...... 81 A.21.Hang-up pipeline stall, ALU test - heat map ...... 82 A.22.Hang-up logic stall, ALU test - heat map ...... 82 A.23.System errors, ALU test - heat map ...... 83 A.24.Application errors, ALU test - heat map ...... 83
8 List of Tables
2.1. RISC-V integer registers ...... 25 2.2. RISC-V privilege levels ...... 26
3.1. Performance overloaded VRTL ...... 34 3.2. Performance source-transformed VRTL ...... 34 3.3. Instruction transmission VRTL ...... 36
4.1. User interface input table ...... 47 4.2. Target software test properties ...... 49
5.1. Fault effect priority levels ...... 51 5.2. Evaluation error margins for given confidence levels ...... 55
6.1. Fault effect probability, ALU test - all targets ...... 59 6.2. Fault effect probability, MUL test - all targets ...... 60 6.3. Fault effect probability, AES test - all targets ...... 60 6.4. Fault effect probability, ALU test - CSR targets ...... 61 6.5. Fault effect probability, ALU test - GPR targets ...... 62 6.6. Fault effect probability, ALU test - micro-architectural targets ...... 63 6.7. Hang-up pipeline stall - influential targets ...... 65 6.8. Hang-up logic stall - influential targets ...... 66 6.9. System error causation - influential targets ...... 68 6.10. Application error causation - influential targets ...... 70
A.1. Fault effect probability, MUL test - GPR targets ...... 77 A.2. Fault effect probability, MUL test - CSR targets ...... 77 A.3. Fault effect probability, MUL test - micro-architectural targets ...... 77 A.4. Fault effect probability, AES test - GPR targets ...... 78 A.5. Fault effect probability, AES test - CSR targets ...... 78 A.6. Fault effect probability, AES test - micro-architectural targets ...... 78
9 List of Tables
10 Listings
2.1. Example AST source ...... 27 2.2. Example AST dump ...... 27
3.1. Example SystemVerilog ...... 30 3.2. Example Verilator sequential body ...... 30 3.3. Pseudo-modified example Verilator sequential body ...... 32 3.4. Pseudo overloading class - extended data structure ...... 33 3.5. Injection macro ...... 38
4.1. Virtual SoC clock-spin ...... 45 4.2. Injection scheduler hook ...... 45 4.3. Simulation run output ...... 50
11 Listings
12 13 Listings
Acronyms
API Application Programming Interface AST Abstract Syntax Tree CPU Central Processing Unit CSR Control and Status Register FSM Finite and State Machine GCC GNU Compiler Collection GNU GNU Debugger GPR General Purpose Register HDL Hardware Description Language IPS Instructions Per Second ISA Instruction Set Arichitecture ISS Instruction Set Simulation LSU Load-Store Unit MPU Memory Protection Unit MSB Most Significant Bit OS Operating System PULP Parallel Ultra Low Power Platform PRNG Pseudo Random Number Generator RISC Reduced Instruction Set Computer RTL Register Transfer Level SET Single Event Transient SoC System on Chip UI User Interface VP Virtual Prototype VRTL Verilator Register Transfer Level VSoC Virtual System on Chip XML eXtensible Markup Language
14 1. Introduction
1.1. Motivation
Most physical processes are controlled by information technology systems. Decentralization of control systems, access through large scale networks and more complex application software and inclusion of full-scale operating systems (OS) have lead to generally higher loads on embedded systems. This growing demand of processing power for a previously reasonably complex part of modern electronics has been met by the possibility to feature a much greater amount of components in an increasingly smaller form factor. At the same time, testing and even more so verification struggles to keep up with this growth. One way to encounter this development can be to utilize virtual prototypes (VPs) of such systems in early stages of design.
While designer’s of application-level software use VP sockets to study and optimize properties of code and its means of employment, hardware developers might have to look into more than just the behavior of cross-compiled code. Since the deployed unit will manipulate our physical world, the same can be the case vice versa in an unintended way. A case of this are soft errors, where data storage elements inside the digital system are corrupted by unpredictable manipulators. These errors normally do not damage the system’s hardware, however, might lead to erroneous behavior, thus, output of the system to the physical world. Soft errors can manifest themselves often by biased or unbiased bit-flips in sequential logic caused by radiation particles hitting such elements. Elaborating the impact of these errors on the system’s application is a major concern on the design strategies which questions the coverage of simulating soft errors in virtual prototypes.
Current research tasked itself not only with investigating the impact of soft-errors but also how one should approach their modeling with respect to the level of abstraction. The most promi- nent idea is to do so on a functional or instruction level. There, instructions of the simulation target instruction set architecture (ISA) are translated just-in-time to equivalents of the host’s ISA, where the simulation is performed. Prominent examples for this type of are QEMU and ETISS (TUM EI EDA n.d.). A more detailed approach is taken, when instructions are not only translated to the host ISA but interpreted. Here, the resulting traceable and instruction-wise execution emulates the ISA behavior (SiFive n.d.). Both ideas have in common that the small- est notion of time is one target instruction, therefore, can be summarized as instruction set simulation (ISS). A more fine-grained abstraction level is register transfer level (RTL). While ISS only mimics the system’s behavior, an RTL simulation imitates the hardware itself. To clarify the dimensions of those levels, a gearbox simulation could be imagined. Depending on the observational goals, a simple equation describing how speed and momentum are translated from input to output could be enough. For processing systems, such equations would corre-
15 1. Introduction spond to the ISS level. This equation will not yield any information about the gearbox’s inner workings that enable the translation nor how certain parts interact with each other. With the assumption of an unbreakable gearbox, an equation would be enough. However, problems arise when a designer wants to introduce faults, where no information about alterations to the gearbox’s behavior is known, e.g. a gear’s teeth breaks and there is no information about how this affects the translation. In contrast, simulating the gearbox more precisely would not depend on information about the system’s changed behavior as the new behavior is described through the changes in the hardware itself. For processing systems, an executable model of the gearbox’s hardware would correspond to RTL.
Since the smallest notion of data storing elements in ISS are general purpose registers (GPRs) and optionally control and status registers (CSRs), a large portion of possible soft error victims are left out from simulation. Research has shown that high-level error injection methodologies, i.e. only injecting in registers and memory, can lead to highly imprecise results (Cho et al. 2013). Therefore, RTL would be the obvious choice for the level of abstraction in soft error simulations. However, a more fine-grained simulation comes with costs. In this case, computational effort to simulate these additional hardware components. Minimizing this simulation effort by modifying highly optimized cycle-accurate RTL simulators for soft error evaluation is the focus of this work.
1.2. Contributions
In this work, the generation of an executable RTL model for a Reduced Instruction Set Com- puter (RISC) that enables guaranteed fault injection is explored. The focus lays on;
• understanding Verilator as the main tool building the host-executable model from the hardware description language (HDL) sources,
• modifying the Verilator RTL model in order to enable cycle-accurate, and target-explicit injection of errors,
• proposing a proof-of-concept RTL fault injection toolchain that builds an injection frame- work from HDL sources and with minimal manual input,
• interpreting the results of a fault injection evaluation for a RISC example (RISC-V core).
1.3. Tasks
First, the tool generating the executable model (VRTL), Verilator, has to be explored. This concludes understanding the VRTL to find ways to perform guaranteed fault injections on fault injection viable components, exclusively. Thus, injection targets have to be identified,
16 1.3. Tasks located and classified in order to optimize the overall simulation process by avoiding injections in model variables that do not correspond to real-world soft error victims.
Next, an algorithm must be developed and implemented that modifies the VRTL sources to allow cycle-accurate injections. Then, the modified VRTL is incorporated in a simulation and fault injection framework for a RISC-V core enabling execution of cross-compiled application code and fault injection scheduling. At last, space (bit) and time (execution cycle) random faults are injected and their impact on the processor core analyzed.
17 1. Introduction
18 2. Background
2.1. Fault Model
2.1.1. Soft Errors
As a type of transient errors in digital systems, soft errors can be mostly traced back to effects of neutron and alpha particle impacts on circuitry. The resulting fault can be modeled as a single event transient (SET) (Maniatakos et al. 2011) or sometimes also referred to as sin- gle event upsets (SEUs) (Baumann 2005). SEUs can affect combinational or sequential logic. However, sequential soft error victims, such as flip-flops and D-latches, have more impact on a system’s behavior since their state is stored in-between system clock cycles and their state is only updated during a short latch-up phase. On the other side, combinational logic is continu- ously driven and converging to a stable state, thus, should have an inherent resiliency against SEUs where the transient impact is much smaller than the clock period. In designs with large propagation delays, thus, low clock frequencies, a SEU seldomly has an impact on combina- tional logic since the SEU has to happen during the relatively short latch-up phase. However, in high frequency designs a SEU might propagate more easily through the combinational logic, thus, increasing the chance of latching the error (Baumann 2005). Correct investigation of soft errors on combinational logic requires either a gate level model of the system or a RTL model with a modified net list. For this thesis, the following assumptions are made regarding the soft error model:
i) SEUs in combinational logic are disregarded.
ii) SEUs are modeled as bit flips in data storage elements.
iii) Bit flips occur right after a correct latch-up.
fault inject fault inject q1 q2 d and xor d
q or q
clk Figure 2.1.: Simple register stage
19 2. Background
Fig. 2.1 shows a simple register stage. Register q2 is driven by combinational logic fed by q1. Both q1 and q2, are possible victims of a soft error modeled by a fault inject.
2.1.2. Injection Model
Considering the RTL representation of a synthesized digital systems, thousands of nets and registers can be identified. Exploring a spatial and time explicit SEU, requires defining pre- liminary modeling rules for fault injections. In this thesis, an faulty model FI for one SEU is described by
FI = {M, b, c, T }
Variable b refers to a single-bit of a clocked data storage element in the bit-representation of a model M, e.g. a micro-architectural register, and c to a specific clock cycle in the observation period. The injection type T describes whether the target’s value is flipped unbiased or biased towards a specific state, i.e. a logically high register injected with a high-biased injection, would not be affected, whereas a logically low one would flip to logic high. However, in this thesis, only unbiased flips are considered.
fault 0 v(F I, t) vc−2 vc−1 T (vc) vc+1
v(M, b, t) vc−2 vc−1 vc vc+1
0 c − 2 c − 1 c c + 1 c + 2 t/clock
Figure 2.2.: Single-bit target fault
Fig. 2.2 shows a timing diagram for a single-bit fault injection. Equation v(M, b, t) describes the clean value of bit b of model M over a simulation time t. v(F I, t) refers to the value over simulation time with the faulty model. To guarantee an injection, the assumption is made, that at the moment of injection the target is stable, i.e. retaining the faulty state (T (vc)) at least until the next clock cycle.
2.1.3. Fault Effect Classification
SEU do not necessarily produce errors in the affected system. Furthermore, if an error is generated, its observed impact during and after simulation time can vary. Based on the idea of basic fault effect classes described in (Cho et al. 2013), this work handles fault effects through the following after-simulation-time classification:
20 2.1. Fault Model
• Application Errors: The application finishes, however, output or program flow is unexpected and varies from an error-free reference run. Additionally, in-system hardware is not capable of detecting these errors.
(AO) Output: The output memory differs from an expected, golden value. This includes peripherals’ in a System on Chip (SoC) context.
(AP) Program Flow: The program execution trace varies from an expected one. Consid- ering these errors often is important for applications demanding a specific execution time, e.g. control applications, where the controller is designed with a worst case execution time in mind.
• System Errors: The system detects its erroneous behavior. Exceptions can be issued and could then be handled by dedicated processes in software.
(SM) Memory Access: An invalid access to a protected memory region was detected by a dedicated hardware component, e.g. a Memory Protection Unit (MPU).
(SI) Illegal Instruction: An invalid instruction in the pipeline has been caught.
• Application Finished Correctly: The program finishes as expected and no errors were detected.
(MSK) Soft Error Masked: After execution no difference to the reference run can be identified. This means, output memory, execution cycles, and micro-architectural state of the model match the reference.
(NSK) Soft Error Not Masked: After execution no difference to the reference run can be identified. However, the micro-architectural states differ from an expected one.
• Hang-up Error: The application does not finish and no system error is detected.
(HL) Logic Stall: The pipeline is active, i.e. instructions still progress through the pipeline, however, no application progress can be made. Reason can be that the program is stuck in an endless loop because the loop’s exit check continuously fails. Both software, e.g. an OS, and hardware, e.g. a watchdog, might be able to solve this issue.
(HP) Pipeline stall: The pipeline is inactive, i.e. continuously stalled. This state can only be left by reset.
21 2. Background
2.2. Verilator RTL
2.2.1. Verilator
The open-source tool Verilator synthesizes hardware descriptions, specified in Verilog and Sys- temVerilog hardware description language (HDL), to executable C++ or SystemC modules. The more general implementation as a source library enables a convenient integration of Veri- lator RTL (VRTL) in various applications.
hardware
description Verilator
files translate & optimize hardware description RTL model
C/C++ compiler executable compile RTL model binary and calling testbench Testbench
Figure 2.3.: Verilator flow (Geier 2019)
In contrast to simulators using HDL built-in simulation techniques, Verilator performs an actual synthesis process. The output is a cycle-accurate and efficient, i.e. fast, model (Veripool n.d.). However, due to the optimization during synthesis some issues arise:
i) Flattened hierarchy: The output’s hierarchy does not correspond the underlying hi- erarchical design in HDL. Verilator supports different ways to access internal variables, however, all require adding keywords in the input sources, i.e. non-functional modifica- tion to HDL sources.
ii) Data types: In VRTL, there are no data types representing the bit length of a variable.
iii) Omitting non-storing elements: Since Verilator performs a full synthesis, not all elements of combinational logic are required. Verilog nets, e.g. wires, that connect module instances in a hierarchical design are often left out. This saves execution time otherwise spent on updating signals in simulator delta-cycles.
iv) Legibility: HDL sources are synthesized to thousands of lines of mostly incompre- hensible C++ code. This makes debugging the VRTL near impossible resulting in a ”black-box” situation.
Fig. 2.3 shows a basic Verilator use case utilizing VRTL and a C++ testbench to build an executable binary for a given SystemVerilog project. Outputs are updated by stimulating input
22 2.2. Verilator RTL variables of the synthesized top module and calling its evaluation method. Those outputs can be handled in the hosting framework which, in this case, is a testbench instantiating the VRTL model.
2.2.2. Fault Injection
The issues resulting from Verilator’s optimizations described in 2.2.1 propagate to a possible fault injection application, nonetheless. Omitted nets make soft error simulation on combina- tional logic impossible. Code size and legibility aggravate any manual insertion of injection points for hardware projects at complexity levels of modern processor cores. Furthermore, flat- tened hierarchy and the indifference of data types, both in VRTL as in Verilog/SystemVerilog, hinders locating possible injection targets in the first place.
As fault injections into wires or variables that are actually constants in hardware, e.g. look- up tables or hard-wired signals, would be unnecessary, variables in the VRTL model require classification. SystemVerilog, unfortunately, does not specify whether a declared signal is going to be continuously, i.e. a wire, or sequentially, i.e. a register, assigned at declaration time. Although this SystemVerilog supports such explicit declarations, implicit signal declarations are resolved during synthesis (IEEE Computer Society 2001, IEEE Computer Society 2009). This results in many hardware descriptions using only the signal type keyword ”logic” for all signal declarations. g
o stimulate RTL l
i signal save original manipulate
r logic[a:b] x = ‘init_val‘ model w/o e
L declaration x* := x x := ~x
V reset cylces D
m continious procedural H e t
s restore y assignments x: net x: variable manipulate S original x: variable x = x* ? x := ~x x := x*
l Yes e
r behavior x: wire x: constant x: register d
o x: wire o t save stimulate RTL
a Yes
l
m
i
r manipulate model w/ x = x´ ? x: constant L e variable
T No V unsigned
Figure 2.4.: Signal types and classification (Geier 2019)
A possible solution to this is proposed in (Weinzierl 2017); An algorithm categorizes VRTL variables based on their behavior inside the VRTL model, which is illustrated in Fig. 2.4. On the left, the difference between a signal declaration in HDL and its corresponding variable declaration in the C++ VRTL is shown, as well as the underlying behavior. On the right, the signal classification algorithm is shown. Each input signal x is classified as either a wire, a constant, or a registers.
23 2. Background
2.2.3. RegPicker
In (Geier 2019), the stand-alone tool RegPicker was developed which implements the classifi- cation algorithm described in sec. 2.2.2. Furthermore, the HDL’s underlying hierarchy lost in the Verilator synthesis is reconstructed. Together with its classification, the signal’s location is put out in an Extensible Markup Language file (XML). The XML constitutes a sufficient basis for a fault injection framework.
2.3. Simulation Target: RI5CY
This work focuses on applying the fault model described in sec. 2.1 to RTL models of cores implementing the open-hardware RISC-V ISA. Recent developments, including adaptions in commercial products, established RISC-V as an interesting topic for research.
Figure 2.5.: RI5CY block diagram (Traber et al. 2019)
As a proof-of-concept simulation target, a 32-bit core executing cross-compiled RISC-V bench- mark software is chosen. RI5CY is an open-source 32-bit RISC-V derivative developed by researchers at ETH Z¨urich and the University of Bologna, in context of the Parallel Ultra Low Power Platform (PULP) project (ETH Z¨urich n.d.a, ETH Z¨urich n.d.b).
2.3.1. Pipeline
RI5CY has full support of RISC-V Base Integer Instruction Set, Standard Extension for Com- pressed Instructions, Integer Multiplication and Division Instruction Set Extension (RV32I, RV32C, RV32M), and PULP-specific ISA extensions, which are not surveyed in this work. Fig. 2.5 shows a block diagram of the 32-bit core and depicts its 4-stage pipeline:
24 2.3. Simulation Target: RI5CY
IF Instruction Fetch. Configured to start fetching from memory address 0x80 through a 128-Bit or 4-word cache line prefetcher.
ID Instruction Decode: Interprets the fetched machine code including compressed instruc- tions. Additionally, interrupts on illegal instructions.
EX Execute: Takes decoded instructions and schedules execution on the respective unit.
WB Write-Back: Manages storage to data memory through the Load-Store Unit (LSU) and an optional Physical Memory Protection (PMP).
2.3.2. Configuration
The RI5CY project provides either a latch-based or flip-flop-based GPR file. In this work, the flip-flop-based implementation of the register file is used and instantiated inside the core’s hierarchy. Furthermore, no floating point unit is added which means the GPR’s memory is reduced to the RISC-V integer register specification shown in tab. 2.1. All simulations are performed on machine privilege level, however, the privilege functionality might be affected by soft errors. The levels and their respective encoding are shown in tab. 2.2.
register name description x0 zero Hard-wired zero x1 ra Return address x2 sp Stack pointer x3 gp Global pointer x4 tp Thread pointer x5 t0 Temporary/alternate link register x6-7 t1-2 Temporaries x8 s0/fp Saved register/frame pointer x9 s1 Saved register x10-11 a0-1 Function arguments/return values x12-17 a2-7 Function arguments x18-27 s2-11 Saved registers x28-31 t3-6 Temporaries
Table 2.1.: RISC-V integer registers from: (Krste Asanovic, Rimas Avizienis, Jacob Bachmeyer, Christopher F. Batten et al. 2017)
2.3.3. Injection Targets
Feeding RI5CY’s HDL description into RegPicker yields 327 VRTL variables as possible injec- tion targets comprising 5753 single-bit targets.
25 2. Background
level encoding name 0 00 user / application 1 01 supervised 2 10 reserved 3 11 machine
Table 2.2.: RISC-V privilege levels from: (Waterman et al. 2014)
Fig. 2.6 shows the RI5CY fault injection target cluster. The cluster is generated from RegPicker analyzing the RI5CY HDL sources and transforming the output to a directed graph description. Nodes of the graph are variables of the VRTL model. Edges between nodes, although hidden, describe a weighted hierarchical relation between variables and their parent cell, where a cell is an instance of an HDL module. Each edge’s weight corresponds to the bit-length of a variable. Registers, thus injection targets, are colored green, wires and constants, thus for fault injection of no concern, colored red and purple respectively. The coordinate of each node in the force-directed graph is calculated with a converging force-layout algorithm Force Atlas in the visualization tool Gephi (Gephi n.d.). For further clarification on RI5CY’s hierarchy, i.e. cell relations, fig. A.2 in the appendix shows a graph of Verilator’s own XML output.
ResInv_SP
cs_registers_i ResInv_SN div_i is_pcmr
RemSel_SP
Cnt_DP
is_pcer mcause_n ABComp_S
LoadEn_S RemSel_SN
PCCR_q
BRegEn_S PCER_n
priv_lvl_n CompInv_SP
ucause_q
AddMux_D cnt_l1
mtvec_n
State_SP
cnt_l3 AReg_DN State_SN
ucause_n mscratch_n dscratch1_q
exception_pc
OutMux_D
dscratch1_n
alu_i cnt_l2
Cnt_DN ResRegEn_S index_lut
PCCR_n
index_nodes
ResReg_DP
ResReg_DN shift_arithmetic
PCCR_inc alu_popcnt_i
mepc_q
ResReg_DP_rev shuffle_reg0_sel
is_pccr cnt_l4
pccr_all_sel sel_nodes
ARegEn_S AReg_DP f_is_nan alu_ff_i pmp_reg_n
AddTmp_D cmp_result
ff_input BReg_DP pmp_reg_q dcsr_n div_ready
radix_2_rev
div_shift BReg_DN PCMR_n cnt_result
mepc_n CompInv_SN
mstatus_n shuffle_r1_in is_greater
operand_a_rev adder_op_b_negate adder_result_expanded
pmpcfg_we
shift_use_round
pmpaddr_we operand_a_neg_rev shift_amt_int dscratch0_n csr_wdata_int
PCER_q shift_result utvec_n csr_we_int
pack_result
perf_rdata cmp_signed
adder_in_a is_equal
dscratch0_q utvec_q shuffle_r0_in
uepc_q
shift_amt mscratch_q priv_lvl_q shuffle_through
shift_left_result
csr_rdata_int div_valid shift_op_a
mtvec_q
mstatus_q depc_q dcsr_q shuffle_result div_op_a_signed bmask
shuffle_r1
depc_n
bextins_result
PCCR_inc_q sel_minmax
shuffle_r0
id_valid_q is_equal_clip adder_op_a
PCMR_q shuffle_byte_sel mcause_q result_minmax
uepc_n
pccr_index radix_4_rev
shift_amt_left
radix_8_rev PCCR_in
is_equal_vec adder_result adder_op_b shift_left
adder_in_b
is_greater_vec minmax_b shuffle_reg_sel shift_right_result
shuffle_reg1_sel
bitop_result f_is_greater mult_i
short_subword ex_stage_i mulh_clearcarry riscv_core_i mulh_signed data_load_event_ex
mulh_NS dot_short_op_b
mulh_ready id_valid
csr_access_ex regfile_waddr_lsu mult_result
mulh_active
mult_clpx_img_ex dot_char_mul csr_save_ex top data_req_ex csr_save_id short_op_b regfile_we_lsu dot_short_result
dot_char_op_b mult_sel_subword_ex dot_char_op_a csr_restore_mret_id irq_sec_i data_req_pmp
mulh_save alu_result
regfile_alu_we_fw
data_gnt_pmp u_irq_enable pc_set short_mac instr_req_o data_gnt_i
regfile_we_wb clpx_shift_result dot_short_op_a
illegal_c_insn_id
mulh_shift_arith clk_i m_irq_enable
data_type_ex is_compressed_id
irq_id_o
csr_hwlp_we exc_pc_mux_id data_sign_ext_ex
instr_req_int
useincr_addr_ex
sec_lvl_o
short_result dot_short_mul ex_ready data_rvalid_i data_we_o mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rvalid_i
csr_save_if mulh_carry_q
data_misaligned_ex mult_operand_a_ex mult_signed_mode_ex bmask_a_ex data_be_o branch_in_ex csr_restore_uret_id instr_rdata_id
irq_id_i short_op_a
bmask_b_ex mulh_subword core_ctrl_firstfetch mulh_CS
clk_en rstn_i data_rdata_i instr_gnt_i regfile_alu_we_ex mult_clpx_shift_ex
alu_clpx_shift_ex mult_dot_op_c_ex
debug_csr_save
core_clock_gate_i regfile_alu_wdata_fw data_addr_o
alu_operand_b_ex
short_shift_arith alu_operand_a_ex
data_req_o
mult_dot_signed_ex
clear_instr_valid apu_en_ex debug_req_i csr_addr_int instr_addr_o alu_is_subrot_ex
data_wdata_o csr_cause perf_pipeline_stall
csr_rdata pc_ex irq_ack_o
pc_id
regfile_alu_waddr_ex
id_ready core_busy_o data_reg_offset_ex
irq_i is_hwlp_id trap_addr_mux
lsu_rdata
fetch_enable_i alu_operand_c_ex
mult_dot_op_b_ex imm_vec_ext_ex instr_valid_id
mult_imm_ex
lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp
ctrl_busy mem mult_operand_c_ex
mult_operand_b_ex
exc_cause pc_mux_id alu_vec_mode_ex riscv_register_file_i
is_decoding
data_err_ack alu_operator_ex
is_fetch_failed_id data_misaligned
debug_cause
regfile_waddr_ex data_we_id hwlp_dec_cnt_id csr_op_ex
if_valid halt_if
csr_hwlp_regid mult_operator_ex
rega_used_dec
csr_status
offset_fsm_cs hwlp_dec_cnt regfile_we_ex ebrk_insn
alu_is_clpx_ex
apu_lat_ex
lsu_ready_ex fencei_insn_dec we_a_dec mult_multicycle valid we_b_dec
j csr_save_cause hwloop_regid
ex_valid
mult_is_clpx_ex reg_d_wb_is_reg_a_id hwloop_we
hwloop_start_mux_sel fetch_addr_n mult_dot_signed
hwloop_controller_i hwlp_target csr_restore_dret_id rdata_offset_q fetch_ready clk
data_we_ex
data_type_id operand_a_fw_mux_sel registers_i
instr_req_pmp alu_en_ex
data_rdata_ext fetch_rdata exc_kill alu_op_a_mux_sel
mult_en_ex bmask_b_mux
pc_is_end_addr uret_insn_dec
fetch_is_hwlp hwloop_cnt_int
mult_operator
CS instr_gnt_pmp instr_decompressed rdata_q mult_imm_mux
data_addr_int bmask_b_id_imm
hwlp_dec_cnt_if operand_c_fw_mux_sel
uret_dec hwloop_we_masked
exc_pc alu_op_b_mux_sel
trap_base_addr
reg_d_ex_is_reg_a_id regfile_data_ra_id
is_hwlp_id_q data_sign_ext_q operand_a_fw_id
bmask_a_mux illegal_c_insn alu_vec_mode
hwloop_cnt branch_taken_ex rdata_b_ext jump_target_mux_sel data_type_q id_stage_i
jump_in_id branch_req
rdata_h_ext fetch_valid
imm_b_mux_sel
alu_operand_b
offset_fsm_ns imm_b
mret_dec data_sign_ext_id mult_int_en deassert_we imm_i_type wdata_offset data_we_q csr_access
compressed_decoder_i alu_operand_a NS
imm_vu_type
load_store_unit_i regb_used_dec operand_b
scalar_replication ecall_insn_dec mult_dot_en
operand_c is_subrot hwloop_start_int if_stage_i alu_operator mult_signed_mode
jump_target
operand_b_fw_mux_sel
regc_used_dec load_stall operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel hwloop_target pipe_flush_dec
alu_en
regfile_alu_waddr_id
MODE_rule is_clpx regfile_addr_rc_id mret_insn_dec mask_addr
regfile_alu_we_id operand_b_vec R_rule
dret_insn_dec data_err_state_q
alu_op_c_mux_sel mult_sel_subword
bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall
reg_d_ex_is_reg_b_id dret_dec
illegal_insn_dec
data_req_id data_err_state_n alu_bmask_a_mux_sel
hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id
stop_addr start_addr prepost_useincr
data_load_event_id regfile_alu_waddr_mux_sel
fetch_valid hwloop_valid
halt_id
exc_ack
CS hwlp_start_q instr_match_region alu_bmask_b_mux_sel
use_hwlp regc_mux hwlp_end_q next_valid
data_match_region
W_rule hwloop_cnt_mux_sel rdata_unaligned
hwlp_counter_n imm_a_mux_sel do_fetch jump_in_id int_controller_i addr_n hwloop_regs_i next_is_crossword pmp_unit_i
rdata
EN_rule exc_ctrl_cs X_rule
mult_dot_en csr_op
addr_real_next
irq_id_q
hwlp_counter_q
do_hwlp
valid
addr_int irq_sec_q rdata_last_q
regfile_alu_we
hwloop_we NS
use_last
data_req
regfile_mem_we
addr_q
hwlp_is_crossword
csr_illegal save_rdata_last L0_buffer_i busy_L0
mult_int_en
do_hwlp_int
is_hwlp_q
CS
addr_q instr_addr_int decoder_i save_rdata_hwlp
is_crossword
illegal_insn_n
next_upper_compressed
is_hwlp_n
L0_buffer ebrk_force_debug_mode
ctrl_fsm_ns
jump_done_q
NS
irq_enable_int
ctrl_fsm_cs
instr_valid_irq_flush_q
branch_in_id
illegal_insn_q
jump_done prefetch_buffer_i instr_valid_irq_flush_n
debug_mode_q
debug_mode_n
controller_i data_err_q jump_in_dec
Figure 2.6.: RI5CY injection target cluster
26 2.4. LLVM
2.4. LLVM
LLVM, formerly Low Level Virtual Machine, comprises a compartment of modular compiler and toolchain technologies (LLVM Foundation n.d.). The LLVM core libraries can be utilized to build custom tools for various applications. However, this work mostly utilizes tools revolving around LLVM’s C/C++/Objective-C compiler (Clang) Abstract Syntax Tree (AST).
Clang Tool FunctionDecl 0x55d1792f94c0
The AST is an intermediate representation of C/C++ source code. Listing 2.2 shows the AST for the brief example code (listing 2.1). An AST Matcher, e.g. FunctionDecl for declarations of functions orArraySubscriptExpr for accesses to array elements, can be decorated further with more specific names to refine locating granularity. Together with Clang Tooling, the AST Matcher library enables callbacks to specific elements in the AST; Whenever the ClangTool traverses the AST and a previously defined condition is matched, a callback function is initiated with a reference to the matching AST element. This allows the user application (LLVM Frontend) to handle the code section in a desired way, e.g. analysis of transformation. In fig. 2.7 a simple Clang Tool is shown that modifies a given source file. The tooling library generates the AST which is then traversed in the AST Consumer.Actions can perform various transformations on the source file, while the AST Matchers and their respective callbacks locate the corresponding code sections.
27 2. Background
28 3. Verilator RTL Modification
3.1. Verilator Evaluation
As described in Sec. 2.2.2, the VRTL model requires modifications to enable some form of fault injection methodolgy. Difficulties arising from flattened hierarchy and missing data type specifications can be handled by RegPicker (Sec. 2.2.3).
Legibility is more an indirect issue, since manually accessing variables and inserting injections inside the VRTL would not be feasible after all and the actual injections will be scheduled by an automated framework. The remaining problem is one of Verilator’s greatest feats; Faster models through design optimization.
3.1.1. Synthesis
At first glance, omitted nets seem to be of no concern, since no injections are performed on combinational logic. Thus, the smallest notion of time for this VP would be one clock cycle or rather half of a clock cycle, which would comply with the fault model proposed in Sec. 2.1. However, simply changing values of internal signals of the VRTL between calls to the evaluation method has occasionally shown no effect, i.e. auto-masking the fault. Inspecting the VRTL source has shown that read-after-write occurrences for registers one stage before a module output, i.e. sequential elements driving remaining wires. Reasons can be found with Verilator’s optimization of these output assignments: Since a net normally takes on the value of its most dominant driver nearly immediately, Verilator simply inserts this continuous assignment right after the driver is updated in the sequential evaluation method. This saves costly evaluation time of combinational logic, however, results in the masking issue.
foo o1 o1 a a VRTL o2 o2 model eval() o3 o3
Figure 3.1.: VRTL example stimuli model
29 3. Verilator RTL Modification
1 module foo( foo 2 input logic clk, 3 input logic a, q1 4 output logic o1, o2, o3 d o1 5 ); a 6 // declarations q2 7 logic q1, q2, q3; 8 q d 9 // cont. body 10 assign o1 = q1; 11 assign o2 = q2; q 12 assign o3 = q3; o2 13 q3 14 always_ff @(posedge clk) 15 // seq. body d 16 else 17 q1 <= a; 18 q2 <= q1; q 19 q3 <= !q1; o3 20 end 21 endmodule
Figure 3.2.: Fault injection example Listing 3.1: Example SystemVerilog
Fig. 3.2 describes a simple SystemVerilog module foo, the left-hand side diagram illustrates the module as a conceptual implementation. Outputs o1, o2, and o3 are driven by q1, q2, and q3 respectively by the assign statement, thus, making them equivalent to nets or wires. In general SystemVerilog provides more than one always keyword type supporting latch, combinational or sequential procedures. The SystemVerilog keyword always ff enables procedural blocks modeling sequential logic behavior sensitive to the expression following the keyword. In this example, q1, q2, and q3, are sequentially updated by a non-blocking assignment (<=) in the clock (clk) -sensitive block. Non-blocking means that at sufficient sensitivity, the current state of each right-hand side non-blocking assignment is elaborated, however, the actual assignment is scheduled separately and updated at the end of the evaluation period. This means that, even though in line 17 of the listing 3.1, q1 is apparently updated before q2 in line 18, q2 will be updated with the value of q1 when the always ff is entered. SystemVerilog simulators, thus Verilator, too, have to conform to these and more specifications in (IEEE Computer Society 2009).
1 VL_INLINE_OPT void Vfoo::_sequent__TOP__1(Vfoo__Syms* __restrict vlSymsp) { 2 // Get internal variables from symbol table 3 Vfoo* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; 4 5 // Body 6 vlTOPp->foo__DOT__q2 = vlTOPp->foo__DOT__q1; 7 vlTOPp->foo__DOT__q3 = (1U & (~ (IData)(vlTOPp->foo__DOT__q1))); 8 vlTOPp->o2 = vlTOPp->foo__DOT__q2; 9 vlTOPp->o3 = vlTOPp->foo__DOT__q3; 10 vlTOPp->foo__DOT__q1 = vlTOPp->a); 11 vlTOPp->o1 = vlTOPp->foo__DOT__q1; 12 } Listing 3.2: Example Verilator sequential body
30 3.1. Verilator Evaluation
Listing 3.2 shows foo’s VRTL (Vfoo) sequential evaluation method. The method is called each time a positive clock edge is recognized by Vfoos’s main evaluation function which is called by the simulation host. Furthermore, during one evaluation each register-like variable must not be assigned more than once, since only nets can be driven by multiple sources. Fig. 3.1 illustrates the example’s stimulus, input a and clock signal together with a call to the main evaluation function, and outputs o1, o2, o3.
3.1.2. Fault Injection
Considering a fault injection between clock cycles, e.g. by accessing Vfoo’s variables through the VRTL symbol table vlSymsp the following observations can be made assuming no resets are done and clock-edges are triggered, thus, applying the fault model of sec. 2.1:
• FI = {Vfoo, q1, c, flip}:
c+1: Fault propagates to q2 and q3 through q1, thus outputs o2 and o3 are updated with a faulty state. Injection target q1 is updated by input a and o1 is assigned the new q1.
c + 2: Fault has left the model.
Problem: o1 never sees the injected flip.
• FI = {Vfoo, q2, c, flip}:
c + 1: q1 updates injection target q2, o2 is assigned the new value of q2. Fault has left the model.
Problem: o2 never sees the injected flip.
• FI = {Vfoo, q3, c, flip}:
c + 1: q1 updates injection target q3, o3 is assigned the new value of q3. Fault has left the model.
Problem: o3 never sees the injected flip.
Consequence of this auto-masking of a section of possible injection targets is that injections between clock cycles, i.e. between evaluation calls, violates the fault model for VRTL.
31 3. Verilator RTL Modification
3.2. Modification
Injecting the fault right after the assignment statement, would also enable updating module outputs with faulty states. Listing 3.3 shows a pseudo-modified Vfoo that will always result in faulty outputs. However, manually inserting these injection points in VRTL is not feasible.
1 void pseudo_inject(CData& target){ 2 #definecINJECTION_CLOCK 3 #definebINJECTION_BIT 4 5 // Check for injection clock cycle 6 if(clock_counter == c){ 7 // flip target bit with bit-wiseXOR 8 target = target ^ (0x1 << b); 9 } 10 } 11 12 VL_INLINE_OPT void Vfoo::_sequent__TOP__1(Vfoo__Syms* __restrict vlSymsp) { 13 // Get internal variables from symbol table 14 Vfoo* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; 15 16 // Body 17 vlTOPp->foo__DOT__q2 = vlTOPp->foo__DOT__q1; 18 pseudo_inject(vlTOPp->foo__DOT__q2); 19 vlTOPp->foo__DOT__q3 = (1U & (~ (IData)(vlTOPp->foo__DOT__q1))); 20 pseudo_inject(vlTOPp->foo__DOT__q3); 21 vlTOPp->o2 = vlTOPp->foo__DOT__q2; 22 vlTOPp->o3 = vlTOPp->foo__DOT__q3; 23 vlTOPp->foo__DOT__q1 = vlTOPp->a); 24 pseudo_inject(vlTOPp->foo__DOT__q1); 25 vlTOPp->o1 = vlTOPp->foo__DOT__q1; 26 } Listing 3.3: Pseudo-modified example Verilator sequential body
3.2.1. Target Variables as Extended Data Structures
Concept
One solution would be to extend each targets variable data type to return the correct or faulty value on demand. Originally, Verilator synthesizes bit vectors to the smallest possible trivial C/C++ data type, i.e. size-modified unsigned. Substitution of the targets data-type with a class-like data-type at declaration can enable more specific handling of the element during evaluation runtime. Overloading all possible arithmetic operators and conversions generates automatic call-back functionality for each extended variable. Additionally, this would only require changing the class definitions of the VRTL modules by modifying its member’s decla- ration types to the overloading class type.
32 3.2. Modification
1 template
Listing 3.4 shows a heavily shortened implementation of an extended data structure for VRTL variables. Since Verilator generates arrays of 32-bit elements for SystemVerilog variables longer than 64 bits, the actual data is stored in the mVar member, an array of the base or rather original data type in VRTL specified through a template argument during compilation. Besides arithmetic operators, implicit conversion (line 29) are overloaded to enable interaction with more trivial data types. The protected read method returns a clean or possibly faulty version of the data, while a write method handles correct assignment operations to the extended VRTL variable.
Evaluation
(Dittrich 2017) already utilized overloading C++ classes as extended data-types for variables in VRTL to support tracing in mixed-level simulations. While, this overloading approach allows a lot of flexibility and additional functionality, e.g. run-time tracing, simulation performance suffers.
Tab. 3.1 shows the results of a performance evaluation of the overloading approach. A VRTL model of a 32-bit RISC (OpenRisc1000) is set against a modified VRTL according to the
33 3. Verilator RTL Modification
host execution time GCC opt GCC opt at 1M target cycles -O3 -O0 VRTL 0.514 s 1.511 s VRTL (modified) 8.106 s 17.861 s slowdown 15.77 11.82
Table 3.1.: Performance overloaded VRTL previously introduced concept. The RTL model is run for one million cycles on a modern x86 host with Linux OS. The execution time is measured in user space yielding the actual time spent inside the process hosting the VRTL models. Although not important for execution times of eventually heavily optimized simulation frameworks, a look into how a compiler handles any further modifications to the VRTL sources is interesting; Without optimizations for the Gnu Compiler Collection (GCC) C++ compiler enabled, basic VRTL is about 12 times faster than the modified one. However, for a strong level of optimization (O3), non-modified VRTL is more than 15 times faster. The assumption can be made that operator overloading is not as easily handled by the compiler with respect to code optimization as the mainly arithmetic-intensive core of VRTL is.
The basic idea of using Verilator as a tool for RTL simulation is its speed compared to other available simulators. Slowing down the simulation for fault injection would eliminate the benefits of VRTL in the first place, thus, the usage.
3.2.2. Source Transformation
Concept
While the previous approach in sec. 3.2.1 mostly relied on introducing additional functionality to VRTL variables, thus, modifying their declarations in VRTL classes, another option is to transform the VRTL’s sources. The fundamental idea is to insert injection points in the model source code according to the concept introduced by listing 3.3.
host execution time GCC opt GCC opt at 1M target cycles -O3 -O0 VRTL 2.341 s 8.165 s VRTL (modified) 2.622 s 10.057 s slowdown 1.12 1.23
Table 3.2.: Performance source-transformed VRTL
34 3.2. Modification
Evaluation
Tab. 3.2 shows the results of a performance evaluation of the source transformation concept. A VRTL model of a 32-bit RISC-V core (RI5CY) is set against source-transformed VRTL. Again, the RTL model is run for one million clock cycles on a x86 host and the simulation’s execution time is measured as process user time. Without GCC optimization, original VRTL is 1.23 times faster than the modified VRTL. With optimization, the original is just 1.12 times faster. Although no injections are performed, checks for a injection at each possible injection point have to be performed which generates simulation overhead. Nonetheless, source-transformation seems to be more efficient, since most of the overhead can be resolved during compile time, where as overloading data types mostly influences the runtime.
Performance
Measuring execution time of the respective simulation process is a straight-forward way to compare the two solutions on a common host. Additionally, measuring instructions per second is commonly used and a somewhat meaningful benchmark. However, for a more independent, therefore, sophisticated, statement regarding a simulation’s performance it is not sufficient. Reasons for this lay with the host. OS, implementation of the native libraries, and most of all the hardware itself can vary a lot between different simulation setups. These host-dependent influences can be reduced by comparing the number of instructions needed by the host to perform a certain number of target instructions in the simulation setup. This instruction transmission figure is still affected by the host’s architecture, however, not so much by the host’s other hardware, e.g. memory, cache, and CPU.
The instruction transmission measurement is setup up as followed: The simulation framework instantiates the VP. The VP executes a cross-compiled binary for a certain number of target clock cycles. In order to stimulate the VP, a clock spin is performed which is two consecutive VRTL evaluation cycles where one is with the input clock logically high and one logically low. For measuring the required host instructions, the whole setup is ran inside a GNU Debugger (GDB) process. The GDB is initiated with two breakpoints; The first where the initialization phase is done and clock spins start and the second where the program is finished. When the debugger reaches the first breakpoint, all further execution is performed step-wise, i.e. host instruction by host instruction, while the steps are counted. As an example target program a Arithmetic Logic Unit (ALU) test program is used which covers a good amount of general purpose computing in the target.
The transmission factor tI can then be calculated with
I i = host Itarget
35 3. Verilator RTL Modification
Variable Ihost refers to the number of host instructions and Itarget to the number of instructions executed on the simulation target.
ALU test on x86 Ihost iALU Itarget = 4, 662 VRTL 115, 656, 447 24, 808 modified VRTL 131, 660, 131 28, 241 slowdown 1.13
Table 3.3.: Instruction transmission VRTL
Tab. 3.3 lists the instruction transmission results for 1000 target clock cycles both on VRTL and source-modified VRTL with compiler optimization enabled. For the used target software an instruction transmission of 28, 241 was achieved. This means that on average, for every RISC-V instruction on the VP, about 28 thousand host instructions have to be executed. Additionally, the transmission factors should mirror the execution time slowdown effects of modified VRTL presented in tab. 3.2; the modified VRTL needs about 1.14 times more instructions than its unmodified counterpart for the same task. Additionally, since for both measurements the ALU test was used, an instructions per second (IPS) benchmark can be formulated. For example, while the host, an Intel I5 with 3.4 GHz, might yield 10 Giga-IPS, the simulation target, following iALU for modified VRTL, achieves only about 354 Kilo-IPS.
36 3.3. Implementation
3.3. Implementation
The following sections of this chapter describes how the VRTL modifier was implemented as a stand-alone tool. For generating a RTL-custom injection framework, two major problems have to be solved by the modifier tool:
1. API Builder: Providing an API for managing injections in a project integrating the modified VRTL.
2. Injection Rewriter: Locating sequential assignments of targets in the AST and insert- ing injections
Both problems are basically decoupled. The only interaction happens, when an injection call accesses variables of the fault model set by the API. The API provides the user (framework) and injection call a common target dictionary holding information about each target’s name, bit length, and reference to the original data element in the VRTL model. Furthermore, each target dictionary entry holds data for the injection purpose including a general injection enable, injection counter to avoid multiple injections per clock cycle, and a mask field specifying which bit of a multi-bit target has to be affected and which not.
Simulation Framework TD: Target Dictionary mod. VRTL idx name data & bits en counter mask ... 0 foo 0x... 32 1 0 0x01 vlTOPp ->foo = 0x55; 1 bar 0x... 1 0 0 0x00 SEQ_INJ_TARGET(TD.foo); foobar vlTOPp ->bar = vlTOPp →foo; 2 0x... 722 0 0 0x00 SEQ_INJ_TARGET(TD.bar); … ... n-1 barfoo 0x... 1 0 0 0x00
Figure 3.3.: Injection call with target dictionary
Fig. 3.3 illustrates the interaction between modified VRTL and the target dictionary. The VRTL calls the injection macro SEQ INJ TARGET with the respective target dictionary entry. Both, location and arbitration of the injection call have to be managed by the Injection Rewriter (sec. 3.3.2) during the source transformation.
37 3. Verilator RTL Modification
1 #defineFI_UNLIKELY(x) __builtin_expect(!!(x), 0) 2 3 #defineSEQ_INJ_TARGET(TDentry){\ 4 if(FI_UNLIKELY((TDentry).enable)) { \ 5 if(((TDentry).counter <= 0) and (TDentry).mask) { \ 6 *((TDentry).data) = *((TDentry).data) ^ (TDentry).mask; \ 7 (TDentry).counter++; \ 8 }\ 9 }\ 10 } Listing 3.5: Injection macro
Listing 3.5 contains the injection macro. Since most of the time and for the majority of all targets no injections are performed, an additional macro helps the compiler predict control flow for better simulation performance.
3.3.1. Injection API Builder
The API Builder handles generating a corresponding injection API for a given VRTL model. The information provided by RegPicker (sec. 2.2.3) suffices as input, i.e. all targets/registers, their location and bit length, etc.
VRTL Injection API Target Injection RegPicker read raw target data APIDictionary Target- template prepare injection templates XML Injection arm injection API access TD entry API Builder Classes Simulation disarm injection modified Framework/User VRTL Figure 3.4.: API Builder process Figure 3.5.: Injection API use case diagram
Fig. 3.5 shows the use cases for the injection API. On the one hand, modified VRTL accesses the API’s underlying target dictionary. On the other hand, a simulation framework or API/VRTL user, instantiating both API and modified VRTL, configures and schedules the injections, thus accessing the target dictionary. Scheduling means arming or disarming an injection at the exact injection cycle, which has to be managed by the simulation framework.
Target information is taken from RegPicker’s output XML and translated into corresponding C++ classes, the target dictionary entries (Fig. 3.4). Template files contain all RTL-invariant features, e.g. the target dictionary class, injection macros and a general injection API wrapper class. The templates get extended by the modifier program with RTL-variant, or rather specific, contents mostly related to the dictionary.
The simplified class diagram in fig. 3.6 describes the relations of the injection API’s different classes. A common pure-abstract base class TDentry acts as an interface to each specific entry
38 3.3. Implementation
TDentry + set_maskBit(bit: unsigned):void + reset_maskBit(): void + read_data(pData: uint8_t*):void + arm(): void 0 ..* TD_API + disarm(): void + register(newEntry: Tdentry*): int + prepare_inject( index, bit ): int + index: const unsigned 1 + prepare_inject( name, bit ): int + name: const char * + mTD: sTD_t + bits: const unsigned + mEntryList: vector
Figure 3.6.: Injection API target dictionary class diagram
(
3.3.2. Injection Rewriter
The modifier’s scheme for rewriting the VRTL sources to support guaranteed injections is illustrated as an abstract control flow in fig. 3.7. The sequential injection assignments (SIA) have to be extracted from VRTL source file before they can be appended with their respective injection call.
The underlying nature of inserting or rather transforming size-wise unmanageable source files justifies the development of an LLVM-based tool for this VRTL modification.
39 3. Verilator RTL Modification
read-in source: src VRTL source get set of targets: T target get sequential injection file assignments of src: SA[ ]
init current assignment: c := SA[0]
Get current assignee: a := c[assignee]
No a ∈ T ? set to next assignment: c := c(next) Yes Append injection to c
No c = last(SA) ?
Yes mod. rewrite src VRTL source
Figure 3.7.: VRTL source transformation algorithm
Extracting Sequential Injection Assignments
Utilizing the AST Matchfinder to efficiently extract sequential assignments that are of interest for injection requires analyzing the properties of such assignments:
i) The assignee is a target identified beforehand, e.g. by RegPicker,
ii) the assignment is located inside a sequential evaluation method,
iii) the assignment is the last inside one compound, i.e. basic block.
40 3.3. Implementation
While i) and ii) are straight-forward essential properties, iii) traces back to the source’s language boundaries. In C/C++ the largest possible bit-size of a variable is capped, e.g. 64 bit. However, in HDLs vectors of much larger bit-size can be specified. As described in sec. 3.2.1, Verilator handles this by specifying arrays where each field has up to 32-bit and essentially breaks up assignments into multiple field-individual ones executed one after another in the same compound. In addition, when variables have to be accessed bit-wise, i.e. not the full bit-vector is assigned a new value, Verilator synthesizes this similarly to multiple field access, however, for a single field in the same compound. Inserting the injection macro at the first occurrence of a target’s assignment in the same compound could then lead to a self-masking process, i.e. an injection-following assignment might overwrite the injection. This issue is engaged by ensuring only the last, or rather, dominant, assignment for a single target in a compound statement has an injection point.
Sequential Eval Non-sequental Eval Compound Statement Assignment Function Declaration Function Declaration
AST Consumer /AST Matchfinder
Sequential Function: Non-Sequential Function: Compound Assignment
aSF = new Func(..) if aSF: if aSF: if aSF and aSF.activeC: SIAs += aSF.getSIA()) newC = new Compound(..) newA = new Assignment(..) delete (aSF) aSF.addCompound(newC) if newA in targetList: aSF.activeC = newC aSF.activeC.addA(newA) SIAs: Global sequential injection assignments Else: delete(newA) Targets: Global list of injection targets aSF: Active sequential function newA: New assignment activeC: Active compound statement of active newC: New compound statement sequential function Figure 3.8.: LLVM Tool - Finding sequential injection assignments
Fig. 3.8 shows a simplified interpretation of the LLVM/Clang AST Matcher-Callback setup for SIAs in the VRTL sources. There are four concurrently running AST Matcher-Callback pairs in use:
• Sequential Eval Function Declaration: Matches function declarations that corre- spond to VRTL sequent function declarations. On callback, a new active sequential function (aSF) ob is generated.
• Compound: Matches all braced statements. If an active sequential function is found, the new compound object is added to the function object. The function objects saves the last found compound statement (active compound).
41 3. Verilator RTL Modification
• Assignment: Matches all assignments. If the new assignment is found in the previously defined target list, it gets added to the active sequential function object’s active compound statement.
• Non-Sequential Function: Matches all miscellaneous function declarations, i.e. non- sequential function. If a sequential function is active when this matcher is raised, the AST traversal left this aSF’s declaration’s body. Therefore, the aSF was fully analyzed and its SIAs can be extracted. The extraction iterates over all compounds returning only the dominant sequential assignments. Afterwards, the aSF gets discarded which avoids further assignments or compounds being added.
42 4. Simulation
4.1. Simulation Framework
The simulation framework manages the modified VRTL core, an injection scheduler, and a user interface (UI). Additionally, a reduced virtual SoC (VSoC) is modeled. For better simulation performance, the framework is implemented in C++, which allows an efficient executable. Fig. 4.1 shows the framework’s components and structure.
User Interface
load_binary( ), mem_read( ) reset( ), configure( ) info( ) run( ) schedule( ) data_read( ) Target Dictionary hook( ) i namedatabitsen cntr mask Injection arm( ) 0 foo 0x.. 32 1 0 0x01 1 bar 0x.. 1 0 0 0x00 Scheduler disarm( ) 2 foobar 0x.. 22 0 0 0x00
n barfoo0x... …1 0 0 0x00 injects data, data, clock, data_rq, modified reset, VRTL core instr_rq, ......
Simulation Framework/ Virtual SoC
Figure 4.1.: Simulation framework
43 4. Simulation
4.1.1. Modified VRTL Core
The modified VRTL core, as described in section 3.2, is integrated in the simulation as gen- erated by the modification tool. Further modifications would break the abstraction layer generated by the automated design flow.
4.1.2. Reduced Virtual System on Chip
The simulation framework also mocks a reduced VSoC for the VRTL core. Although Verilator enables a SystemC model for better transaction-level modeling, the C++ output is used as the focus of this work is on the RISC cores and not on any additional peripherals. Therefore, the VSoC has to provide only the memory for the core to interface with. Since RI5CY has a data memory interface and an instruction memory interface, both have to be modeled by the VSoC and their transactions forwarded to the virtual memory.
Interface to VRTL
In short, the following functionality has to be provided by the virtual SoC component to the VRTL model:
i) Clock spin: Stimulate with clock clock cycles.
ii) Control: Set control outputs, e.g. enable instruction fetch, reset, ...
iii) Instruction memory: Provide instruction fetch with instruction data in the virtual memory.
iv) Data memory: Support load and store access to the virtual data memory.
Interface to Simulation Framework
Additionally, these tasks issued by the simulation framework have to be handled:
i) Boot: Load a cross-compiled binary to the virtual instruction memory and initliaze control signals.
ii) Execute: Run the model for a certain amount of clock cycles.
iii) Reset: Set the model to a pre-defined state.
44 4.1. Simulation Framework
iv) Injection hook: Before evaluating a new clock cycle a possible injection scheduler hook function is called.
The simulation framework poses the first instance of manual input for each new RTL model in the proposed simulation toolchain. The reason is that it has an interface with the VRTL core, which is not standardized. For example, the examined RI5CY RISC-V core has a slim input/output profile assuming that more complex interfaces are implemented on top of it, e.g. connect the memory interfaces with a on-chip bus. On the other hand, cores like the OpenRisc1000 implement an on-chip wishbone-bus interface on the RTL’s top module.
4.1.3. Injection Scheduler
The injection scheduler block acts as an interface to the target dictionary API generated by the modification stage. Additionally, a hook method can be called by the main clock- spin evaluation method in the framework, thus, allowing the scheduler to decide whether an injection should be performed in the current cycle. Injections can be scheduled by passing the target’s index or name in the dictionary to the scheduler. Additionally, either the exact bit and clock cycle can be specified or both selected randomly. For random bit, a pseudo random number generator (PRNG) selects a bit within the bit-length of the target. For random clock cycle, the PRNG generates a random number within a configurable interval, e.g. before the faulty simulation, a reference run could be used to determine the actual program cycle count, thus, an injection-effective time interval.
1 void RV32_SoCFrame:: 1 void TargetInjectScheduler:: 2 clockspin(uint64_t cycles) { 2 hook (void){ 3 for (; cycles; cycles--) { 3 4 //Call injection scheduler hook 4 if(mInjListSet.size()<=0) return 5 TIS->hook(); 5 6 6 if(mPU->mCycles < 7 //Low clock evaluate 7 mInjListSet[0]->mInjectionCycle) return; 8 mCore->clk_i = 0; 8 else 9 mInst_I->update(mCore->clk_i); 9 { 10 mData_I->update(mCore->clk_i); 10 if(PU->mCycles <= 11 mCore->eval(); 11 mInjListSet[0]->mInjectionCycle) 12 12 { 13 //High clock evaluate 13 mInjListSet[0]->arm(); 14 mCore->clk_i = 1; 14 } 15 mInst_I->update(mCore->clk_i); 15 else 16 mData_I->update(mCore->clk_i); 16 { 17 mCore->eval(); 17 mInjListSet[0]->disarm(); 18 18 mInjListDone.push_back(mInjListSet[0]); 19 //Increment cycle count 19 mInjListSet.erase(mInjListSet.begin()); 20 mPU->mCycles++; 20 } 21 } 21 } 22 } 22 } Listing 4.1: Virtual SoC clock-spin Listing 4.2: Injection scheduler hook
For each simulation run multiple injections can be scheduled. Each injections in stored in a buffer sorted for earliest first, i.e. lowest clock cycle injection first. Listing 4.1 shows the
45 4. Simulation simulations clock-spin method calling the injection scheduler hook in line 5. Inside the hook, checks are performed whether any injections are scheduled (line 3) and the current clock cycle (mPU->mCycles) is an injection cycle (line 5, 6, 9 and 10). If an injection cycle is reached, the injection is armed meaning the enable flag in the respective target dictionary gets set. On the next call to the hook function the injection gets disarmed, deleted from the todo-list (mInjListSet) and appended to a done-list mInjListDone. Considering the hook method being called in every clock cycle, the sorted list ensures better performance, since no iterations over the injection list have to be performed.
4.1.4. User Interface
For individual handling of the simulation framework, a UI provides dynamic configuration and execution. The GDB inspired command line interface supports the inputs listed in tab. 4.1. The inputs are grouped in help, soc, mem, and inject;
help displays interface help for all groups or a specific one,
soc includes commands controlling the simulation target,
mem lets the user read virtual memory content, and hash the virtual memory,
inject can return information regarding the target dictionary and scheduled injections. Additionally, the interval for random injections can be set. The load and store func- tions enable reproducing injection schedules, e.g. a previously stored configuration can be reloaded from configuration file. Injections can be added explicitly or randomly. Fur- thermore, a hash function performs a hash over all data elements registered in the target dictionary.
On soc run commands the UI returns the following:
• Application finished: The application finished its execution. This is detected by a return from the target software’s main function
• Cycles done: The model was executed for the set amount of cycles without detecting any system errors.
• System level fault: The system detected an exception, e.g. an illegal instruction.
• Core hang-up: A maximum amount of clock cycles was reached without finishing the program or set amount of clock cycles.
46 4.1. Simulation Framework
group command required options example help help soc run [cycles: int] soc run 100 load
Table 4.1.: User interface input table
47 4. Simulation
4.2. Simulation Setup
The simulation setup can be partitioned in a simulation run and a classification of its results. Both are performed by individual Python scripts. To gather meaningful information about soft error effects on the core under test a large number of random injections have to be managed. The sum of all individual simulation runs is called an evaluation.
hardware Verilator description VRTL translate & optimize model hardware description Stage I: files Verilation
RegPicker RegPicker Target- extract & classify XML signal variables Stage II: Extraction
VRTL modifier Injection API modVRTL insert injection points model & build Injection API Stage III: Modification
Virtual SoC C/C++ compiler
UI compile modVRTL model and framework Stage IV: Framework Build executable model
Figure 4.2.: Simulation framework toolchain
4.2.1. Target Software
An application program has to be generated. This is done by invoking the GNU RISC-V GCC for the target architecture (RISC-V n.d.). A custom linker script ensures correct linkage with the VSoCs memory space. Furthermore, a simple assembly startup file defines correct program boot behavior and exception handling. The resulting cross-compiled binary can then be passed
48 4.2. Simulation Setup
req. executed data memory data memory instruction eval. clocks instructions reads writes fetches ALU 5,904 4,658 1,823 383 1,393 MUL 16,528 11,706 4,813 1,610 3,443 AES 142,355 106,101 34,737 12,205 33,985
Table 4.2.: Target software test properties through the UI to the simulation framework.
The bare-metal code is based on RISC-V test suits provided by the PULP project. The tests normally confirm whether a core implementing the RISC-V ISA operates as expected. Besides checking the basic functionality of the ISA, each test frequently accesses data memory, where its results are stored. Tab. 4.2 lists some properties, such as read and write accesses to memory, of the tests under normal circumstances, i.e. neither errors nor injections. Evaluation of the RI5CY core was done for an Arithmetic Logic Unit (ALU) test, a Multiplier (MUL) test, and an Advanced Encryption Standard (AES) test. In used prefetch buffer configuration, RI5CY reads 128-bit of instruction data per fetch from memory, which translates to four non-compressed instructions.
4.2.2. Evaluation
To generate a multitude of simulation results as fast as possible, a cluster of linux host machines is used. Each host runs a Python script interacting with the simulation framework’s UI by opening a pipelined sub-process. The individual result of a simulation run is appended to a host-unique result file in a simulation setup common directory on the server.
Fig. 4.3 shows the control flow and result for a complete evaluation. The simulation run is initialized with the executable model from the simulation framework toolchain’s output and a cross-compiled application software. Listing 4.3 shows an example for a single simulation result returned by the framework’s UI. For clarification, the UI commands invoked by the python script are inserted as green lines in the listing and output from the UI in purple. Each simulation run gets a simple header with an index and time stamp determining its start and identity. At first, the framework gets passed the cross-compiled binary’s file-location which initiates the VSoC (line 5). Then, the injection interval is set to a significant value, e.g. the expected executing cycles, and a random injection is added and read back (lines 7-9). The simulation is now set up and a endless run invoked (line 13). When the scheduler hook injects the fault, the action is reported by the UI (line 14). In this example, the application software’s main function returns to the startup files call to main(), which indicates its finishing state in line 15. Finally, internal information of the VSoC is read out (line 16). This includes the total number of clock cycles and instructions, a hash over the data and instruction memory, a hash over all target dictionary entries’ data, and two memory access flags. The memory access flags indicate whether the load script-defined address spaces were violated, i.e. a write to the
49 4. Simulation
1 2 29 NEW_LOG: 18/02/2020 15:49:33 application executable 3 ######################################################### binary model 4 # Ri5cy SoCFrame command lineUI v0.9# 5 ######################################################### 6 // soc load application.bin 7 #[CORE] Core settings:PULP_SECURE= 1,N_PMP_ENTRIES= 16,N_PMP_CFG4 8 // inject interval 0:5904 Simulation Script 9 // inject add HostHost 0 0 10 // inject info schedule HostHostsimulation 0 0 simulate framework 11 #TODO: simulation 12 #LEGEND:(index): target-name[bits]-
Figure 4.3.: Evaluation run Listing 4.3: Simulation run output instruction ram was performed or a read from an invalid address.
The memory hashes are used to reduce the amount of data needed to store each simulation result of an evaluation. Due to hashing, information is lost and a fine-grained statement about a soft-errors effect is harder to make. However, fault effect classification is still possible, since mostly a general effect on the system and not on the individual application is investigated.
50 5. Evaluation
5.1. Error Classification
The individual simulation results of one evaluation are classified according to the fault effects listed in sec. 2.1.3. The errors are prioritized such that a more severe core hang-up that also generated a memory corruption is declared a hang-up fault and not an application level fault. Tab. 5.1 shows the possible fault effects and their priority level. Fault effects on the same priority level can overlap, e.g. a simulation run can be classified both as an Application Output Error (AO) and an Application Program Flow Error (AP).
key priority type HP 0 Hang Error - Pipeline Stall HL 1 Hang Error - Logic Stall SI 2 System Error - Illegal Instruction SM 3 System Error - Memory Access AO 4 Application Error - Output AP 4 Application Error - Program Flow NSK 5 Soft Error Not Masked MSK 6 Soft Error Masked
Table 5.1.: Fault effect priority levels
Fig. 5.1 illustrates the classification process. After the simulation result, including execution result, memory hashes, instruction count and total clock cycles, is read, a check is performed whether a hang-up was detected. If additionally, the maximum instruction count was reached, i.e. instructions were still executed, the fault is declared a logic hang-up. This means, the core still executed instructions, however, no program termination was accomplished. In reverse, i.e. the maximum instruction count was not reached, a pipeline hang-up occurred. If the simulation returned a system error, either an illegal memory access or an illegal instruction was detected. The next priority level involves application level faults. Here, output corruption is checked by comparing the memory hash value with an expected one. Additionally, the program flow could have been corrupted which is checked by comparing the simulation’s instruction and cycle count. At last, meaning the application must have finished without errors, the algorithm checks the hashed injection target data for deviations to an error-free run. No deviation means that the soft-error was fully masked.
51 5. Evaluation
read-in simulation result Sim. result
result = Yes Hang-up?
Instruction Yes count < expected? HP
result = Yes HL System Error?
Yes Illegal Instruction? SI
SM Memory hashes Yes AO deviate?
Instruction or Yes cycle count bad? AP
Instruction Yes or cycle count AP deviate?
Target data Yes NSK hash deviates?
MSK
Figure 5.1.: Fault effect classification
52 5.2. Results Analysis
5.2. Results Analysis
There are different ways and dimensions to analyze the simulation results. Since injections are randomized in space (bits) and time (clock cycle), relations between fault effects and both dimensions can be formulated. In this work’s proof-of-concept evaluations, however, the focus is on the space dependency of specific fault effects with only a small notion to individual time dependencies. Information gathered from fault effect classification of all simulation runs in the evaluation is used to observe the following relations:
i) Fault effect probability: Assuming that every injection target bit has an equal prob- ability being affected by a soft-error, what is the probability of a certain fault effect occurring. Furthermore, the effect that different application code has on the effect is examined.
ii) Fault effect causation: Assuming that a certain fault effect occurred, what is the probability that a soft-error in an specific injection target was the cause. Additionally, with a large enough statistical sample size, time dependencies of certain fault effect causes can be observed.
5.2.1. Statistical Fault Effect Probability
For each evaluation (ALU, MUL, AES) a finite number of unique injections exist, i.e. the initial population N. This number can be calculated by multiplying the vector of all target bits with the vector of the individual application execution cycles. For the evaluation-common target RI5CY, RegPicker identified 327 target registers making up 5753 individual target bits. For the ALU evaluation, this results in an initial population NALU of 33.97e6. For MUL and AES, 95.09e6 and 818.97e6 respectively. These huge population sizes mean that a verification- level evaluation, i.e. all possible simulations are evaluated, would take a very long time. For example, verifying the AES test would take 818.97e6 × 142, 355 total simulation cycles on the model or 818.97e6×106, 101 instructions under perfect conditions, e.g. no evaluation overhead or simulations with time-outs. Assuming the estimated IPS of 354e3 (see sec. 3.2.2) for the modified VRTL, this would result in a total 245e6 seconds, or 7.8 years, of simulation time for a single-core simulation process. Obviously, not a worthwhile figure.
(Leveugle et al. 2009) introduced a way how a minimum sample size n for a given initial population N, a desired margin of error e and confidence t (cut-off point with respect to a normal distribution), can be calculated. The prerequisites are that n is uniformally distributed over N and the probability of a specific fault effect p is unknown.
N n = (5.1) 2 N−1 1 + e × t2×p×(1−p)
53 5. Evaluation
Equation 5.1 shows (Leveugle et al. 2009)’s formula to calculate the sample size. Since p is unknown and the most conservative approach is a large sample size, the highest n is gained by assuming p = 0.5 regardless of a rational probability of an effect. Furthermore, eq. 5.1 can be converted to calculate a margin of error for a given confidence level, sample size, and initial population:
rp × (1 − p) N − n e = t × × (5.2) n N − 1
For each evaluation of the RI5CY core, the sample size varied. For example, the ALU test was simulated about 4.6 million times. Assuming each bit and cycle has an equal probability being selected for injection, at 5753 injection bits and approximately 6000 simulation clock cycles about one seventh of all possible injections were evaluated. The uniformity of the injections is illustrated in fig. 5.2 for the ALU test. Each dot represents a single simulation with its target bit displayed on the vertical axis and the injection cycle on the horizontal axis.
Figure 5.2.: Evaluation cluster
With eq. 5.2, each evaluation’s fault effect probability results can be given with the addition
54 5.2. Results Analysis that this result is within a margin of error at a fixed confidence level. Applied to the statistical fault injection proposed by (Leveugle et al. 2009), this results in the error margins listed in tab 5.2 for the various evaluations done on the RI5CY core. For example, for the ALU test a probability of 3.49% for a random injection resulting in an application level fault was observed. This figure can now be said to be with a confidence of 99.8% within the unknown correct probability for application level faults and an error margin of 0.0663%. For the AES test, which has a large population size and small sample size with respect to the other two tests, a higher margin of error has to be considered when formulating statements regarding fault effect probabilities. The error margins should be kept in mind when evaluating the statistical results for all tests.
initial sample t = 1.96 t = 2.5758 t = 3.0902 eval. population N size n 95% conf. 99% conf. 99.8% conf. ALU 33,965,712 4,683,165 e = 0.0420% e = 0.0553% e = 0.0663% MUL 95,085,584 3,704,735 e = 0.0499% e = 0.0656% e = 0.0787% AES 818,968,315 2,590,085 e = 0.0608% e = 0.0799% e = 0.0959%
Table 5.2.: Evaluation error margins for given confidence levels
5.2.2. Data Processing and Visualization
Although a confident statement about error probabilities can be formulated with a relatively small sample size, interpreting effect causes requires looking at more than just the end result of a simulation run. To evaluate relations between injection space and time more easily, the evaluation data is further processed and visualized.
Causation Clusters
The evaluation results are analyzed and fault effect occurrences counted. To examine fault causation, the effect is set in relation to a specific injection target (space) being the initial cause for deviations from the golden reference model. The resulting statistic yields a space dependent probability for faults. For better interpretation of the individual fault effect causes, each multi-bit target is one possible cause. This has the consequence, that a large target, e.g. the register files memory element with 1024 bits, will naturally have a larger impact during the evaluation due to its inherent size, thus, occurrence ratio in random injections. Therefore, two analysis cases are taken into account:
a) Unweighted causation statistic: A large target might have an inherently higher impact factor
b) Weighted causation statistic: All causes are inversely weighted with their size, i.e. the smaller the target, the higher is its impact factor
55 5. Evaluation
For visualization purposes, the cause statistics are merged with the models hierarchy and formed to a force-directed graph analog sec. 2.3.3. Fig. A.1, showing the RI5CY target cluster, can be used as a reference graph identifying the RISC-V core’s components and its purple-colored injection targets. The visualization tool Gephi takes data in XML-like formats. For this use case, the RegPicker XML file was transformed to a node/edge representation and each target, i.e. node, is decorated with its proportional share in the various fault effects as XML attributes. The tool can be configured to display node colors and their label size in relation to one of its attributes’ value. For example, all nodes have an attribute signalClass according to RegPicker’s classification and the tool can color each node depending on this attributes’ value, e.g. green for wires and purple for registers. Similarly, all nodes can be colored depending on their respective proportional cause for a fault effect, e.g. a hang-up.
Heat Maps
Furthermore, execution time dependency can be evaluated, e.g. does a target always result in a specific effect or only at particular instants in the execution. For this, the sparse evaluation sample (matrix S˜) is mapped to a more coarse-grained, thus dense, representation of the initial population (matrix Z˜). The matrix rows N represent the injection space (bits) and the matrix columns M the injection time (execution cycles). To allow better comparisons between different evaluations, the matrix size (M × N) is constant for all evaluations. Each element zm,n holds a value calculated from the occurrences of a specific fault effect resulting from a injection in the respective sector (multiplicities of unique simulation parameters are filtered out). For example, the ALU test normally has 5904 execution cycles in the reference model and 5753 injection bits. Since not all possible simulations (5904 × 5753) are performed, each simulation run is mapped to a sector of the initial population size, i.e. an element of Z˜. For each individual fault effect, one Z˜-matrix is generated and all evaluation results mapped to the respective matrix and its element. The array of Z˜-matrices is referred to as ζ and its construction is described in the pseudo code algorithm 1. Each Z˜-matrix of ζ is initialized with some form of invalid or Not-a-Number (NaN) value. Reason is that this allows distinguishing sectors not creating a specific effect from ones where no information regarding an effect is available. In other words, a sector where no data is available must not be interpreted as fault-free.
The Z˜-matrices can be visualized by so called heat maps. Fig. 5.3 shows the heat map gained from mapping the evaluation sample and all results of erroneous fault effects of the ALU test to a (1000 × 250)-Z˜-matrix. Therefore, one element of Z˜ covers a sector of 6 × 23 cycles and bits respectively. Erroneous fault effects refer to all fault effect classes excluding NSK and MSK. Dark blue coloration means the section mostly results in masking effects, while a bright yellow means high amounts of error effects. The pattern allows to identify vulnerable injection targets and also their time dependency. For example, a bright continuous line could mean, that a target or bit space almost always results in a fault, while a discontinuous one points to a error-dependency towards certain stages in the model’s execution. The heat map is not intended to actually determine which injection bit and which cycle was responsible for a fault. However, this type of visualization can be a starting point for more fine-grained inspections.
56 5.2. Results Analysis
Algorithm 1: Mapping sparse evaluation results to dense effect matrices
1 function Z-Map (N,M,B,C,R,F ); Input : Maximum number of rows N and columns M, sum of all injection bits B and maximum injection cycle: C, set of all fault injection evaluation results: R, set of all fault effects: F Output: Set of Z˜-matrices for each effect in F : ζ 2 Function scaleInt(x, X, Y) is 3 y = x × Y/X; 4 return byc; 5 end 6 for f in F do 7 ζ[f] = NaN(M × N); /* Initialize ζ with Not-a-Number-matrices */ 8 end 9 for r in R do 10 Z˜ = ζ[faultEffect(r)] ; /* Get Z˜-matrix w.r.t. the result’s fault effect */ 11 m =scaleInt(injectCycle(r),C,M); /* Scale result’s injection cycle */ 12 n =scaleInt(injectBit(r),B,N); /* Scale result’s injection bit */
13 zm,n = Z˜[m][n] 14 if zm,n = NaN then 15 zm,n = 0 ; /* Initialize if element was not accessed yet */ 16 end 17 zm,n = zm,n + 1 ; /* Increment element value */ 18 end 19 return ζ;
normed effect count 1 5000
0.8 4000
0.6 3000
0.4
space [targetbit] 2000
0.2 1000
0 0 0 1000 2000 3000 4000 5000
time [exe. cycle] Figure 5.3.: Erroneous fault effects, ALU test - heat map
57 5. Evaluation
58 6. Results
6.1. Fault Effect Probability
After classification, a script counts the occurrences of a specific fault effect and sets these in proportion to the total number of simulation runs. The resulting statistic yields a probability figure for a random soft-error resulting in a certain fault. Additionally, the evaluation is further split into pure micro-architectural injections and injections into register file like parts of the model. All probability values have to be taken into consideration with respect to the confidence levels listed in tab. 5.2. First of all, the sum of all results is examined.
All Targets
group count % key count % MSK Hang-Up Pipeline 4,374 0.0934 HP Hang-Up Logic 31,707 0.677 HL SM 123,294 60.0 41.9 % System Error 205,448 4.39 SI 82,154 40.0 0.77 % AO 102,519 62.8 4.39 % H* Application Error 163,335 3.49 3.49 % AP 106,478 65.2 S* 49.5 % Not Masked 2,317,138 49.5 NSK A* Masked 1,961,163 41.9 MSK NSK P 4,683,165
Table 6.1.: Fault effect probability, ALU test - all targets
Tab. 6.1 lists the ALU evaluation results for both micro-architectural and register file injections, i.e. all targets. Overall, 4374, or rather 0.0934 percent, of all injections lead to a hang-up where the pipeline gets stalled and 0.677 percent result in a hang where instructions are executed, but the application never finishes. Around 4.39 percent result in system faults of which about 40 percent are due to illegal instructions in the pipeline and 60 percent due to invalid memory access. These faults can be detected and handled during run-time. On the other side, silent corruptions in form of application errors make up about 3.49 percent of the simulations. Here, output memory is corrupted with a chance of 63 percent and program or execution flow with another 65 percent meaning an overlap of those two fault effects, i.e. the error corrupted both
59 6. Results output and resulted in program execution deviations. 42 percent of all injections were entirely masked once a simulation run was completed, while about half of all the runs showed some deviation in the architectural states of the model but no error.
group count % key count % MSK Hang-Up Pipeline 4,855 0.0975 HP Hang-Up Logic 39,082 0.785 HL SM 123,266 59.7 43.1 % System Error 206,399 4.14 SI 83,133 40.3 AO 125,135 67.1 4.140.88 % H* Application Error 186,538 3.75 3.75 % AP 114,991 61.6 S* 48.1 % Not Masked 2,397,535 48.1 NSK A* Masked 2,145,771 43.1 MSK NSK P 4,980,180
Table 6.2.: Fault effect probability, MUL test - all targets
group count % key count % MSK Hang-Up Pipeline 2,305 0.0980 HP Hang-Up Logic 14,031 0.761 HL 43.8 % SM 39,786 50.6 System Error 78,599 3.34 SI 38,813 49.4 AO 47,350 63.9 3.340.86 % H* Application Error 74,089 3.15 3.15 % AP 69,355 93.6 S* 48.9 % A* Not Masked 1,150,042 48.9 NSK Masked 1,030,264 43.8 MSK NSK P 2,353,196
Table 6.3.: Fault effect probability, AES test - all targets
Comparing the different application or target software results with each other, there seems to be not much difference between the various application softwares with respect to fault effect probabilities. The AES test shows a smaller overall ratio of system and application level errors, however, almost all (94 %) of application level faults can be classified as program flow errors. The numbers for MUL and AES can be found in tab. 6.2 and 6.3.
60 6.1. Fault Effect Probability
Control and Status Registers
group count % key count % Hang-Up Pipeline 0 0 HP
Hang-Up Logic 0 0 HL MSK SM 0 0 System Error 0 0 12.1 % SI 0 0 2.57 % AO 0 0 85.4 % AP Application Error 32,170 2.57 AP 32,170 100.0 NSK Not Masked 1,069,434 85.4 NSK Masked 150,972 12.1 MSK P 1,252,576
Table 6.4.: Fault effect probability, ALU test - CSR targets
Next, a look at injections into targets related to register file like hardware components is taken. This includes the components making up the GPR and CSR. Tab. 6.4 shows the ALU fault effect statistics for CSR target injections. In general, the statement can be made that these injections rarely result in hang-ups and system errors. However, program flow seems to be affected. The reason for this is, that the simulation framework uses the CSR to evaluate the number of executed instructions. With the classification from 5.1 that uses the returned instruction count from the framework, obviously, a deviation in execution flow occurs. This result has to be taken with a grain of salt, since only the instruction count storage might be affected and not the actual program flow. Manual inspection of these simulation runs confirm this. The instruction count is in a higher than possible number due to the maximum amount of clock cycles performed. After all, these errors can still be seen as such since application software might depend on performance and status registers. The results for the MUL and AES test are nearly equivalent to the ALU test. For completeness, the numbers can be found in tab. A.2 and A.5 in the appendix.
61 6. Results
General Purpose Registers
group count % key count % Hang-Up Pipeline 0 0 HP Hang-Up Logic 28,664 3.56 HL MSK SM 9,742 77.3 System Error 42,867 5.32 13.9 % SI 33,125 22.7 74.6 % 3.56 % AO 20,660 95.2 NSK 5.32 % HL Application Error 21,703 2.69 2.69 % AP 11,678 53.8 S* Not Masked 601,125 74.6 NSK A* Masked 111,842 13.9 MSK P 806,201
Table 6.5.: Fault effect probability, ALU test - GPR targets
Tab. 6.5 shows the fault effect statistics for GPR target injections. To interpret these GPR injection results a basic knowledge of the RISCV GPRs is helpful. In tab. 2.1 the GPRs and their fundamental usage is listed. The area making up the 32-bit hard-wired zero register (x0) is ignored, since the assumption was made that this component would be hard-wired, thus, not actually a sequential logic, i.e. flip flop, in real hardware. This leaves around 992 injectable bits or around one sixth of RI5CY’s total injection targets. Hang-ups, however only logic stalls, occur with a probability of 3.56 percent. System errors with mostly illegal instructions being the cause occur with 5.32 percent. Application errors happen with 2.69 percent probability, while mostly affecting the model output. Interestingly, injections not affecting the program rarely result in a complete mask (13.9 percent), while with three quarters of all injections most remain in the model. The GPR as a component seems to be more vulnerable to hang-ups and system errors than the core as a whole. The large amount of illegal instruction system errors can be traced back to bit-flips to the GPR area where the stack pointer and function return address is stored (x1 and x2). Furthermore, the high occurrence rate of not-masked injections might be related to a large portion of the register file not being used, thus, not regularly updated during run-time by the ALU test program.
The results for the MUL and AES test are varying from the ALU test, meaning that fault effects resulting from injections into the GPR seem to be application dependent. The AES test might be more resilient to application level faults, which may be explained by the longer test masking stack-related memory errors more easily due to the higher access occurrences (the output is compared only at the end of each evaluation). The numbers for MUL and AES can be found in tab. A.1 and tab. A.4.
62 6.1. Fault Effect Probability
Micro-architectural Targets
group count % key count % MSK Hang-Up Pipeline 4,374 0.168 HP Hang-Up Logic 3,043 0.117 HL 64.4 % SM 113,552 69.8 System Error 162,581 6.26 SI 49,029 30.2 0.29 % H* AO 81,799 74.8 6.26 % Application Error 109,363 4.21 4.21 % S* AP 62,535 57.2 24.9 % Not Masked 646,566 24.9 NSK A* Masked 1,672,240 64.6 MSK NSK P 2,598,167
Table 6.6.: Fault effect probability, ALU test - micro-architectural targets
At last, micro-architectural-exclusive injections for the ALU software can be examined in tab 6.6. In contrast to GPR injections, micro-architectural injections show pipeline stalling hang- ups (0.172 percent), however, both, application and system level fault rates are higher with 4.2 and 6.3 percent respectively. While error free runs occur mostly at the same rate as they do with GPR injections, the probability of complete masking is with 66 percent higher in micro-architectural injections than in GPRs.
Compared to the ALU test, the AES result is not much different for micro-architectural injec- tions. On the other hand, for the MUL test, a higher rate of application level faults can be observed. This might be explainable by the additional micro-architectural hardware (multiplier units) used in the MUL compared to ALU and AES test which solely utilize the ALU of the RI5CY core. In addition, AES has with 0.55 percent a much higher rate of logical hang-ups than its counterparts (0.117 for ALU and 0.119 for MUL). Again, the much longer execution time, thus, number of branching and jumps, resulting from the high repetitiveness of the crypto algorithm seem to increase the risk for logical hang-ups. The results can be found in tab. A.3 and A.6 for MUL and AES respectively.
63 6. Results
6.2. Fault Effect Causation
The fault effect causes are examined according to the data processing ideas presented in sec. 5.2.2. Primarily, this survey focuses on causes for fault effects in the ALU test, however discrepancies between the ALU and the MUL or AES are taken into consideration. For better visibility, all causation cluster figures are scaled to the weighted fault effect proportion, while tables listing influential targets show both, weighted and unweighted values.
6.2.1. Hang-up Errors
The overwhelming portion of hang-ups are caused by injections in the GPR. In these cases the core’s pipeline still executes instructions, however, the application does not finish because of some loop body might be infinitely executed due to a failing exit check. Such logic errors can be caught by watchdog-like system components checking the application’s progress. More problematic are hang-ups caused by a stuck pipeline, i.e. no instructions propagate through the processing stages.
Hang-up - Pipeline Stall
ResInv_SP
cs_registers_i ResInv_SN div_i is_pcmr
RemSel_SP
Cnt_DP
is_pcer mcause_n ABComp_S
LoadEn_S RemSel_SN
PCCR_q
BRegEn_S PCER_n
priv_lvl_n CompInv_SP
ucause_q
AddMux_D cnt_l1
mtvec_n
State_SP
cnt_l3 AReg_DN State_SN
ucause_n mscratch_n dscratch1_q
exception_pc
OutMux_D
dscratch1_n
alu_i cnt_l2
Cnt_DN ResRegEn_S index_lut
PCCR_n
index_nodes
ResReg_DP
ResReg_DN shift_arithmetic
PCCR_inc alu_popcnt_i
mepc_q
ResReg_DP_rev shuffle_reg0_sel
is_pccr cnt_l4
pccr_all_sel sel_nodes
ARegEn_S AReg_DP f_is_nan alu_ff_i pmp_reg_n
AddTmp_D cmp_result
ff_input BReg_DP pmp_reg_q dcsr_n div_ready
radix_2_rev
div_shift BReg_DN
PCMPCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr R_n cnt_result
mepc_n CompInv_SN
mstatus_n shuffle_r1_in is_greater
operand_a_rev adder_op_b_negate adder_result_expanded
pmpcfg_we
shift_use_round
pmpaddr_we operand_a_neg_rev shift_amt_int dscratch0_n csr_wdata_int
PCER_q shift_result utvec_n csr_we_int
pack_result
perf_rdata cmp_signed
adder_in_a is_equal
dscratch0_q utvec_q shuffle_r0_in
uepc_q
shift_amt mscratch_q priv_lvl_q shuffle_through
shift_left_result
csr_rdata_int div_valid shift_op_a
mtvec_q
mstatus_q depc_q dcsr_q shuffle_result div_op_a_signed bmask
shuffle_r1
depc_n
bextins_result
PCCR_inc_q sel_minmax
shuffle_r0
id_valid_q is_equal_clip adder_op_a
PCMR_q shuffle_byte_sel mcause_q result_minmax
uepc_n
pccr_index radix_4_rev
shift_amt_left
radix_8_rev PCCR_in
is_equal_vec priv_lvl_q adder_result adder_op_b shift_left
adder_in_b
is_greater_vec minmax_b shuffle_reg_sel shift_right_result
shuffle_reg1_sel
bitop_result f_is_greater mult_i
short_subword ex_stage_i mulh_clearcarry riscv_core_i mulh_signed data_load_event_ex
mulh_NS dot_short_op_b
mulh_ready id_valid
csr_access_ex regfile_waddr_lsu mult_result
mulh_active
mult_clpx_img_ex dot_char_mul csr_save_ex top data_req_ex csr_save_id short_op_b regfile_we_lsu dot_short_result
dot_char_op_b mult_sel_subword_ex dot_char_op_a csr_restore_mret_id irq_sec_i data_req_pmp
mulh_save alu_result
regfile_alu_we_fw
data_gnt_pmp u_irq_enable pc_set short_mac instr_req_o data_gnt_i
regfile_we_wb clpx_shift_result dot_short_op_a
illegal_c_insn_id
mulh_shift_arith clk_i m_irq_enable
data_type_ex is_compressed_id
irq_id_o
csr_hwlp_we exc_pc_mux_id data_sign_ext_ex
instr_req_int
useincr_addr_ex
sec_lvl_o
short_result dot_short_mul ex_ready data_rvalid_i data_we_o mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rvalid_i
csr_save_if mulh_carry_q
data_misaligned_ex mult_operand_a_ex bmask_a_ex mult_signed_mode_ex branch_in_ex data_be_o instr_rdata_id csr_restore_uret_idcsr_restore_uret_id
irq_id_i short_op_a
bmask_b_ex mulh_subword core_ctrl_firstfetch mulh_CS
clk_en rstn_i data_rdata_i instr_gnt_i
top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id instr_valid_id is_compressed_id is_fetch_failed_id illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux is_decoding useincr_addr_ex data_misaligned mult_multicycle branch_in_ex ctrl_busy alu_en_ex alu_operator_ex bmask_a_ex bmask_b_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex mult_en_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex apu_en_ex apu_lat_ex regfile_waddr_ex regfile_we_ex regfile_we_wb regfile_alu_waddr_ex regfile_alu_we_ex regfile_alu_we_fw csr_op_ex data_we_ex data_type_ex data_sign_ext_ex data_reg_offset_ex data_req_ex data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb instr_req_int m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id regfile_alu_we_ex mult_clpx_shift_ex
alu_clpx_shift_ex mult_dot_op_c_ex
debug_csr_save
core_clock_gate_i regfile_alu_wdata_fw data_addr_o
alu_operand_b_ex
short_shift_arith alu_operand_a_ex
data_req_o
mult_dot_signed_ex
clear_instr_valid apu_en_ex debug_req_i csr_addr_int instr_addr_o alu_is_subrot_ex
data_wdata_o csr_cause perf_pipeline_stall
csr_rdata pc_ex irq_ack_o
pc_id
regfile_alu_waddr_ex
id_ready core_busy_o data_reg_offset_ex
irq_i is_hwlp_id trap_addr_mux
lsu_rdata
fetch_enable_i alu_operand_c_ex
mult_dot_op_b_ex imm_vec_ext_ex instr_valid_id
mult_imm_ex
lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp
ctrl_busy mem mult_operand_c_ex
mult_operand_b_ex
exc_cause pc_mux_id alu_vec_mode_ex riscv_register_file_i
is_decoding
data_err_ack alu_operator_ex
is_fetch_failed_id data_misaligned
debug_cause
regfile_waddr_ex data_we_id hwlp_dec_cnt_id csr_op_ex
if_valid halt_if
csr_hwlp_regid mult_operator_ex
rega_used_dec
csr_status
offset_fsm_cs hwlp_dec_cnt regfile_we_ex ebrk_insn
alu_is_clpx_ex
apu_lat_ex
lsu_ready_ex fencei_insn_dec we_a_dec mult_multicycle valid we_b_dec
j csr_save_cause hwloop_regid
ex_valid
mult_is_clpx_ex reg_d_wb_is_reg_a_id hwloop_we
hwloop_start_mux_sel fetch_addr_n mult_dot_signed
hwloop_controller_i hwlp_target csr_restorcsr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int instr_rdata_id pc_id pc_ex alu_operand_a_ex alu_operand_b_ex alu_operand_c_ex mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 e_dret_id rdata_offset_q fetch_ready clk
data_we_ex
data_type_id operand_a_fw_mux_sel registers_i
instr_req_pmp alu_en_ex
data_rdata_ext fetch_rdata exc_kill alu_op_a_mux_sel
mult_en_ex bmask_b_mux
pc_is_end_addr uret_insn_dec
fetch_is_hwlp hwloop_cnt_int
mult_operator
CS instr_gnt_pmp instr_decompressed rdata_q mult_imm_mux
data_addr_int bmask_b_id_imm
hwlp_dec_cnt_if operand_c_fw_mux_sel
uret_dec hwloop_we_masked
exc_pc alu_op_b_mux_sel
trap_base_addr
reg_d_ex_is_reg_a_id regfile_data_ra_id
is_hwlp_id_q data_sign_ext_q operand_a_fw_id
bmask_a_mux illegal_c_insn alu_vec_mode
hwloop_cnt branch_taken_ex rdata_b_ext jump_target_mux_sel data_type_q id_stage_i
CS jump_in_id branch_req
rdata_h_ext fetch_valid
imm_b_mux_sel
alu_operand_b
offset_fsm_ns imm_b
mret_dec data_sign_ext_id mult_int_en deassert_we imm_i_type wdata_offset data_we_q csr_access
compressed_decoder_i alu_operand_a NNS data_addr_int rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n S
imm_vu_type
load_store_unit_i regb_used_dec operand_b
scalar_replication ecall_insn_dec mult_dot_en
operand_c is_subrot hwloop_start_int if_stage_i alu_operator mult_signed_mode
jump_target
operand_b_fw_mux_sel
regc_used_dec load_stall operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel hwloop_target pipe_flush_dec
alu_en
regfile_alu_waddr_id
MODE_rule is_clpx regfile_addr_rc_id mret_insn_dec mask_addr
regfile_alu_we_id operand_b_vec R_rule
dret_insn_dec data_err_state_q
alu_op_c_mux_sel mult_sel_subword
bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall
reg_d_ex_is_reg_b_id dret_dec
illegal_insn_dec
data_req_id data_err_state_n alu_bmask_a_mux_sel
hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id
stop_addr start_addr prepost_useincr
data_load_event_id regfile_alu_waddr_mux_sel
fetch_valid hwloop_valid
halt_id
exc_ack
CS hwlp_start_q instr_match_region alu_bmask_b_mux_sel
use_hwlp regc_mux hwlp_end_q next_valid
data_match_region
W_rule hwloop_cnt_mux_sel rdata_unaligned
hwlp_counter_n CS imm_a_mux_sel do_fetch jump_in_id int_controller_i addr_n hwloop_regs_i next_is_crossword pmp_unit_i
rdata
EN_rule exc_ctrl_cs X_rule
mult_dot_en csr_op
addr_real_next
irq_id_q
hwlp_counter_q
do_hwlp
valid
addr_int irq_sec_q rdata_last_q
regfile_alu_we
hwloop_we
NNS do_fetch do_hwlp do_hwlp_int use_last save_rdata_last use_hwlp save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid addr_q addr_n addr_int addr_real_next rdata_last_q rdata rdata_unaligned L0_buffer_i S
use_last
data_req
regfile_mem_we
addr_q
hwlp_is_crossword
csr_illegal save_rdata_last L0_buffer_i busy_L0
mult_int_en
do_hwlp_int
is_hwlp_q
CS
addr_q instr_addr_int decoder_i save_rdata_hwlp
is_crossword
illegal_insn_n
next_upper_compressed CSis_hwlp_n L0_buffer ebrk_force_debug_mode
ctrl_fsm_ns
jump_done_q
NNS L0_buffer addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec ebrk_insn mret_insn_dec uret_insn_dec dret_insn_dec ecall_insn_dec pipe_flush_dec fencei_insn_dec rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id regfile_alu_waddr_id regfile_alu_we_id alu_en alu_operator alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel imm_b_mux_sel jump_target_mux_sel mult_operator mult_int_en mult_sel_subword mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_alu_waddr_mux _sel data_we_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_start_mux_sel hwloop_cnt_mux_sel hwloop_valid csr_access csr_status prepost_useincr operand_a_fw_mux_se operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux bmask_b_mux alu_bmask_a_mux_se alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm bmask_b_id_imm alu_vec_mode scalar_replication reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec imm_i_type imm_vu_type imm_b jump_target regfile_data_ra_id hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i mem we_a_dec we_b_dec decoder_i regfile_mem_we regfile_alu_we data_req csr_illegal csr_op controller_i ctrl_fsm_cs ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i regfile_we_lsu regfile_waddr_lsu alu_result mult_result alu_i div_shift div_valid adder_op_b_negate shift_left shift_use_round shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int shift_op_a shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev adder_in_a adder_in_b adder_result_expanded alu_popcnt_i cnt_l1 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN State_SP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready mulh_CS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q rdata_offset_q data_sign_ext_q data_we_q wdata_offset S
irq_enable_int
ctrl_fsm_cs
instr_valid_irq_flush_q
branch_in_id
illegal_insn_q
jump_done prefetch_buffer_i instr_valid_irq_flush_n
debug_mode_q
debug_mode_n
controller_i data_err_q jump_in_dec
Figure 6.1.: Hang-up pipeline stall, ALU test - causation cluster
64 6.2. Fault Effect Causation
Fig. 6.1 shows the weighted causation cluster evaluation for pipeline stalling hang-up effects in the RI5CY core (ALU test). The intensity of (red) coloration and label size of each node or rather target indicate its proportional share in overall pipeline stalling hang-up faults. There is not much difference between the weighted and unweighted statistic which means that these hang-up errors mostly depend on the individual target, i.e. its function in the RISC-V core. With the exception of the MUL test, where the FSM in the utilized multiplier unit might cause additional pipeline stalls, the results are test independent.
un- /weighted [%] target module function ALU MUL AES RISC-V privilege priv lvl q cs registers i 37.0/39.0 36.2/37.8 35.1/36.8 level CS load store unit i 23.1/24.4 21.9/22.8 23.7/24.8 current state FSM CS L0 buffer i 22.2/21.3 22.2/21.5 21.9/20.9 current state FSM CS prefetch buffer i 17.5/15.1 17.1/15.3 15.7/13.4 current state FSM mulh CS mult i 0/0 1.74/1.69 0/0 current state FSM restore PC (user- csr restore uret id riscv core i 0.23/0.26 0.83/0.93 3.59/4.11 mode handling)
Table 6.7.: Hang-up pipeline stall - influential targets
Tab. 6.7 lists the most influential injection targets with their respective causation ratio. These hang-ups are produced by injections into delicate registers, e.g. finite state machine (FSM) current state storage and the core’s privilege level. For the FSM cases, the system does not seem to be able to regenerate by itself and, in some instances, gets stuck at fetching new instructions. Even worse is an injection in the privilege level register, since here an injection always leads to a stuck pipeline. Reason might be that the test program normally stays in machine mode and a flip changes either to supervised mode or sets the level to the reserved, or rather undefined, mode (see. tab. 2.2). The privilege level has crucial influence on the systems pipeline as it may result in failing instruction fetch attempts due to the memory protection unit blocking access.
Fig. A.21 shows the pipeline stall effect heat map for the ALU test. The lower line contains the FSM registers for the Prefetch Buffer and L0 Buffer. The upper line is built from data regarding the privilege level register and LSU FSM. Overall, both lines seem to be more or less continuous which indicates that these hang-up effects are not application/time dependent. However, further, more fine-grained, analysis of those targets’ fault effect might reveal things like cycle or value-dependency. For example, injections in the current state register of these FSMs might only result in stalls if a certain state is active and then corrupted.
65 6. Results
Hang-up - Logic Stall
Logic or application level stalls mostly result from injection into the GPRs memory elements (see tab. 6.8). Fig. 6.2 shows the causation cluster, while the heat map in fig. A.22 displays a more irregular pattern compared to pipeline stalling hang-ups. A closer inspection of the responsible simulations reveals that mostly the return address, stack and global pointer register regions are the causing sectors in the register file. In the heat map, some of the traces are discontinuous which suggests that their respective targets make the core vulnerable only at specific moments, thus, are influenced by the application code and application progress.
ResInv_SP
cs_registers_i ResInv_SN div_i is_pcmr
RemSel_SP
Cnt_DP
is_pcer mcause_n ABComp_S
LoadEn_S RemSel_SN
PCCR_q
BRegEn_S PCER_n
priv_lvl_n CompInv_SP
ucause_q
AddMux_D cnt_l1
mtvec_n
State_SP
cnt_l3 AReg_DN State_SN
ucause_n mscratch_n dscratch1_q
exception_pc
OutMux_D
dscratch1_n
alu_i cnt_l2
Cnt_DN ResRegEn_S index_lut
PCCR_n
index_nodes
ResReg_DP alu_popcnt_i cnt_l1 cnt_l2 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN State_SP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready mulh_CS mulh_NS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q rdata_offset_q data_sign_ext_q data_we_q wdata_offset CS NS data_addr_int rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q id_valid_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_q uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr
ResReg_DN shift_arithmetic
PCCR_inc alu_popcnt_i
mepc_q
ResReg_DP_rev shuffle_reg0_sel
is_pccr cnt_l4
pccr_all_sel sel_nodes
ARegEn_S AReg_DP f_is_nan alu_ff_i pmp_reg_n
AddTmp_D cmp_result
ff_input BReg_DP pmp_reg_q dcsr_n div_ready
radix_2_rev
div_shift BReg_DN PCMR_n cnt_result
mepc_n CompInv_SN
mstatus_n shuffle_r1_in is_greater
operand_a_rev adder_op_b_negate adder_result_expandedadder_result_expanded
pmpcfg_we
shift_use_round
pmpaddr_we operand_a_neg_rev shift_amt_int dscratch0_n csr_wdata_int
PCER_q shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev shift_result utvec_n csr_we_int
pack_result
perf_rdata cmp_signed
adder_in_aadder_in_a is_equal
dscratch0_q utvec_q shuffle_r0_in
uepc_q
shift_amt mscratch_q priv_lvl_q shuffle_through
shift_left_result
csr_rdata_int div_valid shift_op_ashift_op_a
mtvec_q
mstatus_q depc_q dcsr_q shuffle_result div_op_a_signed bmask
shuffle_r1
depc_n
bextins_result
PCCR_inc_q sel_minmax
shuffle_r0
id_valid_q is_equal_clip adder_op_a
PCMR_q shuffle_byte_sel mcause_q result_minmax
uepc_n
pccr_index radix_4_rev
shift_amt_left
radix_8_rev PCCR_in
is_equal_vec adder_result adder_op_b shift_left
adder_in_badder_in_b
is_greater_vec minmax_b shuffle_reg_sel shift_right_result
shuffle_reg1_sel
bitop_result f_is_greater mult_i
short_subword ex_stage_i mulh_clearcarry riscv_core_i mulh_signed data_load_event_ex
mulh_NS dot_short_op_b
mulh_ready id_valid
csr_access_ex regfile_waddr_lsu mult_result
mulh_active
mult_clpx_img_ex dot_char_mul csr_save_ex top data_req_ex csr_save_id short_op_b regfile_we_lsu dot_short_result
dot_char_op_b mult_sel_subword_ex dot_char_op_a csr_restore_mret_id irq_sec_i data_req_pmp
mulh_save alu_result
regfile_alu_we_fw
data_gnt_pmp u_irq_enable pc_set short_mac instr_req_o data_gnt_i
regfile_we_wb clpx_shift_result dot_short_op_a
illegal_c_insn_id
mulh_shift_arith clk_i m_irq_enable
data_type_ex is_compressed_id
irq_id_o
csr_hwlp_we exc_pc_mux_id data_sign_ext_ex
instr_req_int
useincr_addr_ex
sec_lvl_o
short_result dot_short_mul ex_ready data_rvalid_i data_we_o mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rvalid_i
csr_save_if mulh_carry_q
data_misaligned_ex mult_operand_a_ex mult_signed_mode_ex bmask_a_ex data_be_o branch_in_ex csr_restore_uret_id instr_rdata_idinstr_rdata_id
irq_id_i short_op_a
bmask_b_ex mulh_subword core_ctrl_firstfetch mulh_CS
clk_en rstn_i data_rdata_i instr_gnt_i top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id instr_valid_id is_compressed_id is_fetch_failed_id illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux is_decoding data_misaligned mult_multicycle branch_in_ex ctrl_busy alu_en_ex alu_operator_ex bmask_a_ex bmask_b_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex mult_en_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex apu_en_ex apu_lat_ex regfile_waddr_ex regfile_we_ex regfile_we_wb regfile_alu_we_ex regfile_alu_we_fw csr_access_ex csr_op_ex data_we_ex data_type_ex data_sign_ext_ex data_reg_offset_ex data_req_ex data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb instr_req_int m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int regfile_alu_we_ex mult_clpx_shift_ex
alu_clpx_shift_ex mult_dot_op_c_ex
debug_csr_save
core_clock_gate_i regfile_alu_wdata_fw data_addr_o
alu_operand_b_exalu_operand_b_ex
short_shift_arith alu_operand_a_exalu_operand_a_ex
data_req_o
mult_dot_signed_ex
clear_instr_valid apu_en_ex debug_req_i csr_addr_int instr_addr_o alu_is_subrot_ex
data_wdata_o csr_cause perf_pipeline_stall
csr_rdata pc_ex irq_ack_o pc_id pc_ex pc_id
regfile_alu_waddr_exregfile_alu_waddr_ex
id_ready core_busy_o data_reg_offset_ex
irq_i is_hwlp_id trap_addr_mux
lsu_rdata alu_operand_c_ex mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 fetch_enable_i alu_operand_c_ex
mult_dot_op_b_ex imm_vec_ext_ex instr_valid_id
mult_imm_ex
lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp
ctrl_busy mem mult_operand_c_ex
mult_operand_b_ex
exc_cause pc_mux_id alu_vec_mode_ex riscv_register_file_i
is_decoding
data_err_ack alu_operator_ex
is_fetch_failed_id data_misaligned
debug_cause
regfile_waddr_ex data_we_id hwlp_dec_cnt_id csr_op_ex
if_valid halt_if
csr_hwlp_regid mult_operator_ex
rega_used_dec
csr_status
offset_fsm_cs hwlp_dec_cnt regfile_we_ex ebrk_insn
alu_is_clpx_ex
apu_lat_ex fencei_insn_dec memwe_a_dec lsu_ready_ex mult_multicycle valid we_a_dec we_b_decwe_b_dec j csr_save_cause hwloop_regid
ex_valid
mult_is_clpx_ex reg_d_wb_is_reg_a_id hwloop_we
hwloop_start_mux_sel fetch_addr_n mult_dot_signed
hwloop_controller_i hwlp_target csr_restore_dret_id rdata_offset_q fetch_ready clk
data_we_ex
data_type_id operand_a_fw_mux_sel registers_i
instr_req_pmp alu_en_ex
data_rdata_ext fetch_rdata exc_kill alu_op_a_mux_sel
mult_en_ex bmask_b_mux
pc_is_end_addr uret_insn_dec
fetch_is_hwlp hwloop_cnt_int
mult_operator
CS instr_gnt_pmp instr_decompressed rdata_q mult_imm_mux
data_addr_int bmask_b_id_imm
hwlp_dec_cnt_if operand_c_fw_mux_sel
uret_dec hwloop_we_masked
exc_pc alu_op_b_mux_sel
trap_base_addr
reg_d_ex_is_reg_a_id regfile_data_ra_idregfile_data_ra_id
is_hwlp_id_q data_sign_ext_q operand_a_fw_id
bmask_a_mux illegal_c_insn alu_vec_mode
hwloop_cnt branch_taken_ex rdata_b_ext jump_target_mux_sel data_type_q id_stage_i
jump_in_id branch_req
rdata_h_ext fetch_valid
imm_b_mux_sel
alu_operand_b
imm_b offset_fsm_ns imm_b
mret_dec data_sign_ext_id mult_int_en deassert_we imm_i_typeimm_i_type wdata_offset data_we_q csr_access
compressed_decoder_i alu_operand_a NS imm_vu_type imm_vu_type
load_store_unit_i regb_used_dec operand_b
scalar_replication ecall_insn_dec mult_dot_en
operand_c is_subrot hwloop_start_int if_stage_i alu_operator mult_signed_mode
jump_targetjump_target
operand_b_fw_mux_sel
regc_used_dec load_stall operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i hwloop_target pipe_flush_dec
alu_en
regfile_alu_waddr_idregfile_alu_waddr_id
MODE_rule is_clpx regfile_addr_rc_id mret_insn_dec mask_addr regfile_alu_we_id alu_en alu_operator alu_op_a_mux_sel alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel imm_b_mux_sel jump_target_mux_sel mult_operator mult_int_en mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_alu_waddr_mux _sel data_we_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_cnt_mux_sel hwloop_valid csr_access csr_status prepost_useincr operand_a_fw_mux_se operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux bmask_b_mux alu_bmask_a_mux_se alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm bmask_b_id_imm alu_vec_mode scalar_replication reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec regfile_alu_we_id operand_b_vec R_rule
dret_insn_dec data_err_state_q
alu_op_c_mux_sel mult_sel_subword
bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall
reg_d_ex_is_reg_b_id dret_dec
illegal_insn_dec
data_req_id data_err_state_n alu_bmask_a_mux_sel
hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id
stop_addr start_addr prepost_useincr
data_load_event_id regfile_alu_waddr_mux_sel
fetch_valid hwloop_valid
halt_id
exc_ack
CS CS hwlp_start_q instr_match_region alu_bmask_b_mux_sel
use_hwlp regc_mux hwlp_end_q next_valid
data_match_region
W_rule hwloop_cnt_mux_sel rdata_unaligned
hwlp_counter_n imm_a_mux_sel do_fetch jump_in_idjump_in_id int_controller_i addr_n addr_int addr_real_next rdata_last_q rdata rdata_unaligned L0_buffer_i CS NS addr_n hwloop_regs_i next_is_crossword pmp_unit_i
rdata
EN_rule exc_ctrl_cs X_rule
mult_dot_en csr_op mult_int_en mult_dot_en controller_i ctrl_fsm_cs ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i regfile_we_lsu regfile_waddr_lsu alu_result mult_result alu_i div_shift div_valid adder_op_b_negate shift_left shift_use_round shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int csr_op
addr_real_next
irq_id_q decoder_i regfile_mem_we regfile_alu_we data_req hwloop_we csr_illegal
hwlp_counter_q
do_hwlp
valid
addr_int irq_sec_q rdata_last_q
regfile_alu_we
NS do_fetch do_hwlp do_hwlp_int use_last save_rdata_last use_hwlp save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid hwloop_we NS
use_last
data_req
regfile_mem_we addr_qaddr_q
hwlp_is_crossword
csr_illegal save_rdata_last L0_buffer_i busy_L0
mult_int_en
do_hwlp_int
is_hwlp_q
CS addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec ebrk_insn mret_insn_dec uret_insn_dec dret_insn_dec ecall_insn_dec pipe_flush_dec fencei_insn_dec rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id addr_q instr_addr_int decoder_i save_rdata_hwlp
is_crossword
illegal_insn_n
next_upper_compressed
is_hwlp_n
L0_bufferL0_buffer ebrk_force_debug_mode
ctrl_fsm_ns
jump_done_q
NS
irq_enable_int
ctrl_fsm_cs
instr_valid_irq_flush_q
branch_in_id
illegal_insn_q
jump_done prefetch_buffer_i instr_valid_irq_flush_n
debug_mode_q
debug_mode_n
controller_i data_err_q jump_in_dec
Figure 6.2.: Hang-up logic stall, ALU test - causation cluster
un- /weighted [%] target module function ALU MUL AES mem register file i 90.4/80.8 91.6/83.6 56.4/38.8 register file memory reg. file write we a dec register file i 2.43/4.90 2.37/4.66 2.46/3.48 enable port a addr q prefetch buffer i 1.62/3.26 1.55/3.04 5.18/7.31 prefetch address reg. file write we b dec register file i 1.35/2.72 1.60/3.16 2.07/2.92 enable port a L0 buffer L0 buffer i 1.17/2.22 0.54/1.01 6.87/9.21 128-bit instr. cache
Table 6.8.: Hang-up logic stall - influential targets
66 6.2. Fault Effect Causation
6.2.2. System Errors
Fig. 6.3 shows the ALU evaluation’s system error causation cluster. Fig. A.10 focuses on memory access errors and fig A.9 illustrates illegal instruction fault causes. Again, the GPR register and components related to the instruction fetch have a high influence on this fault effect (see tab. 6.9). The corresponding heat map for the ALU test is depicted in fig. A.23.
ResInv_SP
cs_registers_i ResInv_SN div_i is_pcmr
RemSel_SP
Cnt_DP
is_pcer mcause_n ABComp_S
LoadEn_S RemSel_SN
PCCR_q
BRegEn_S PCER_n
priv_lvl_n CompInv_SP
ucause_q
AddMux_D cnt_l1
mtvec_n
SState_SPtate_SP
cnt_l3 AReg_DN State_SN
ucause_n mscratch_n dscratch1_q
exception_pc
OutMux_D
dscratch1_n
alu_i cnt_l2
Cnt_DN ResRegEn_S index_lut
PCCR_n
index_nodes
ResReResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready g_DP alu_popcnt_i cnt_l1 cnt_l2 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN ResReg_DN
shift_arishift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed thmetic
PCCR_inc alu_popcnt_i
mepc_q
ResReg_DP_rev shuffle_reg0_sel
is_pccr cnt_l4
pccr_all_sel sel_nodes
ARegEn_S AReg_DP f_is_nan alu_ff_i pmp_reg_n
AddTmp_D cmp_result
ff_input BReg_DP pmp_reg_q
dcsrdcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule _n div_ready
radix_2_rev
div_shift BReg_DN PCMR_n cnt_result
mepc_n CompInv_SN
mstatus_n shuffle_r1_in is_greater
operand_a_rev adder_op_adder_op_b_negate b_negate operand_a_rev adder_result_expanded pmpcfg_we adder_result_expanded
sshift_use_roundhift_use_round pmpaddr_we
operand_aoperand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int _neg_rev shift_amt_int dscratch0_n csr_wdata_int
PCER_q
shift_rshift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev esult utvec_n csr_we_int
pack_result
perf_rdata cmp_signed
adder_in_a is_equal
dscratch0_q utvec_q shuffle_r0_in
uepc_q adder_in_a
shift_amt mscratch_q priv_lvl_q shuffle_through
shift_left_result
csr_rdata_int ddiv_validiv_valid shift_op_a
mtvec_q
mstatus_q shift_op_a depc_q dcsr_q dcsr_q shuffle_result div_op_a_signed bmask
shuffle_r1
depc_n
bextins_result
PCCR_inc_q sel_minmax
shuffle_r0
id_valid_q is_equal_clip adder_op_a
PCMR_q shuffle_byte_sel mcause_q result_minmax
uepc_n
pccr_index radix_4_rev
shift_amt_left
radix_8_rev PCCR_in
is_equal_vec adder_result adder_op_b
sshift_lefthift_left
adder_in_b
is_greater_vec minmax_b shuffle_reg_sel adder_in_b shift_right_result
shuffle_reg1_sel
bitop_result f_is_greater mult_i
short_subword ex_stage_i mulh_clearcarry mulh_signed
riscv_coredata_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb _i data_load_event_ex
mulhmulh_NS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i _NS dot_short_op_b
mulh_ready id_valid
regfile_waddr_lsu ccsr_access_exsr_access_ex regfile_waddr_lsu mult_result
mulh_active
mult_clpx_img_ex dot_char_mul csr_save_ex top data_req_exdata_req_ex csr_save_id short_op_b rregfile_we_lsuegfile_we_lsu dot_short_result
dot_char_op_b mult_sel_subword_ex dot_char_op_a csr_restore_mret_id irq_sec_i data_req_pmp
mulh_save
alu_realu_result mult_result alu_i div_shift sult
rregfile_alu_we_fwegfile_alu_we_fw
data_gnt_pmp u_irq_enable pc_set short_mac instr_req_o data_gnt_i
regfile_regfile_we_wb we_wb clpx_shift_result dot_short_op_a illegal_c_insn_idillegal_c_insn_id clk_i mulh_shift_arith m_irq_em_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id nable
data_type_ex
is_compreis_compressed_id ssed_id data_type_ex
irq_id_o
csr_hwlp_we exc_pc_mux_id
data_signdata_sign_ext_ex data_reg_offset_ex _ext_ex
iinstr_req_intnstr_req_int
uuseincr_addr_exseincr_addr_ex
sec_lvl_o
short_result dot_short_mul ex_ready data_rvalid_i data_we_o mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rvalid_i
csr_save_if mulh_carry_q
data_misaligned_ex mult_operand_a_ex bmask_a_ex mult_signedmult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex _mode_ex bmask_a_ex data_be_o branch_in_ex csr_restore_uret_idcsr_restore_uret_id instr_rdata_id branch_in_ex
irq_id_i short_op_a
bmask_b_ex mulh_subword bmask_b_ex core_ctrl_firstfetch mmulh_CSulh_CS
clk_en rstn_i data_rdata_i instr_gnt_i
top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id rregfile_alu_we_exegfile_alu_we_ex mult_clpx_shift_ex
alu_clpx_alu_clpx_shift_ex mult_operator_ex shift_ex mult_dot_op_c_ex instr_rdata_iddebug_csr_save
core_clock_gate_i regfile_alu_wdata_fw data_addr_o
alu_operand_b_ex
short_shift_arith alu_operand_a_ex
data_req_o
mult_dot_signed_ex
apu_en_ex clear_insclear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux tr_valid apu_en_ex debug_req_i csr_addr_int instr_addr_o aalu_is_subrot_exlu_is_subrot_ex
data_wdata_o alu_operand_b_excsr_cause perf_pipeline_stall
csr_rdata
pc_pc_ex ex irq_ack_o
pc_id regfile_alu_waddr_exregfile_alu_waddr_ex pc_id id_ready core_busy_o data_reg_offset_ex
irq_i is_hwlp_id trap_addr_mux
alu_operand_a_exlsu_rdata
fetch_enable_i alu_operaalu_operand_c_ex mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 nd_c_ex
mult_dot_op_b_ex
imm_vecimm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex _ext_ex iinstr_valid_idnstr_valid_id
mult_imm_ex
lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmpdata_err_pmp
ctrl_bctrl_busy usy mem mult_operand_c_ex
mult_operand_b_ex
exc_cause pc_mux_id alu_vec_mode_ex riscv_register_file_i
iis_decodings_decoding
data_edata_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int rr_ack alu_operator_exalu_operator_ex is_fetch_failed_id
is_fetch_failed_id data_misdata_misaligned aligned
debug_cause
regfile_waddr_ex regfile_waddr_ex data_we_id hwlp_dec_cnt_id data_we_id
csr_ocsr_op_ex p_ex
if_valid halt_if mem csr_hwlp_regid mult_operator_ex
rega_usrega_used_dec regb_used_dec regc_used_dec ed_dec
csr_scsr_status tatus
hwlp_dec_cnt ebrk_insn offset_fsm_cs rregfile_we_exegfile_we_ex ebrk_insn
alu_is_clpx_ex
apu_laapu_lat_ex t_ex we_a_dec lsu_ready_ex ffencei_insn_decencei_insn_dec mmult_multicycleult_multicycle valid we_b_dec
jj compressed_decoder_ i id_stage_i deassert_we csr_save_cause we_a_dec hwloop_regid we_b_dec ex_valid
mult_is_clpx_ex reg_d_wb_is_reg_a_id hwloop_we
hwloop_start_mux_sel fetch_addr_n mult_dot_signed
hwloop_controller_i hwlp_target csr_restorcsr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp e_dret_id rrdata_offset_qdata_offset_q fetch_ready clk
ddata_we_exata_we_ex
data_tydata_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_cnt_mux_sel hwloop_valid pe_id operand_a_fw_mux_seloperand_a_fw_mux_sel registers_i
instr_req_pmp aalu_en_exlu_en_ex
data_rdata_ext fetch_rdata exc_kill alu_op_a_mux_sel
mult_en_ex mult_en_ex bbmask_b_muxmask_b_mux alu_op_a_mux_sel
pc_is_end_addr uuret_insn_decret_insn_dec
fetch_is_hwlp pc_is_end_addr hwloop_cnt_int
mult_operator
CCSS instr_gnt_pmp
instr_decompressed rdatardata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q id_valid_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_q uepc_n _q
mult_immult_imm_mux bmask_a_id_imm m_mux
data_addr_int bmask_b_id_imm
hwlp_dec_cnt_if operand_c_fw_mux_sel bmask_b_id_imm
uret_dec hwloop_we_masked
exc_pc data_addr_int aalu_op_b_mux_sellu_op_b_mux_sel trap_base_addr
reg_d_ex_isreg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx _reg_a_id regfile_data_ra_id
is_hwlp_id_q data_sign_ext_q data_we_q wdata_offset data_sign_ext_q operand_a_fw_id
bmask_a_mux illegal_c_insn regfile_data_ra_id alu_vecalu_vec_mode _mode
hwloop_cnt branch_taken_ex rdata_b_ext jump_targejump_target_mux_sel mult_operator mult_int_en mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id t_mux_sel data_type_q id_stage_i data_type_q branch_taken_ex
jump_jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id in_id branch_req
rdata_h_ext fetch_valid
imm_b_mux_selimm_b_mux_sel
alu_operand_b
offset_fsm_ns imm_b
mret_mret_dec uret_dec dret_dec dec data_sign_ext_id mult_int_en deassert_we imm_i_type wdata_offset data_we_q ccsr_accesssr_access
compressed_decoder_i alu_operand_a
NSNS
imm_bimm_vuimm_vu_type _type
load_store_unit_i imm_i_type regb_used_dec operand_b
scalar_replicationscalar_replication eecall_insn_deccall_insn_dec mult_dot_en
operand_c is_subrot hwloop_start_int is_subrot if_stage_i alu_opalu_operator erator mult_signed_mode jump_targetjump_target
operand_b_foperand_b_fw_mux_se l operand_c_fw_mux_se bmask_a_mux w_mux_sel
regc_used_dec load_stall operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel
hwloop_hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i target ppipe_flush_decipe_flush_dec
alu_enalu_en regfile_alu_waddr_id
is_clpx regfile_alu_waddr_id MODE_rule regfile_addr_rc_id mret_insn_dec mask_addr mret_insn_dec
regfile_alregfile_alu_we_id u_we_id operand_b_vec R_rule
dret_insn_dec data_err_state_qdata_err_state_q dret_insn_dec
alu_op_c_alu_op_c_mux_sel regc_mux imm_a_mux_sel mux_sel mult_sel_subword
bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall
reg_d_ex_is_reg_b_id dret_dec illegal_insn_decillegal_insn_dec data_req_id
data_err_data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr state_n
alu_bmask_alu_bmask_a_mux_se l a_mux_sel
hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id
stop_addr start_addr
pprepost_useincrrepost_useincr
data_load_event_id rregfile_alu_waddr_mux_selegfile_alu_waddr_mux_sel
fetch_valid hwloop_valid
halt_id
exc_ack
CS hwlp_start_q instr_match_region CS aalu_bmask_b_mux_sellu_bmask_b_mux_sel
use_hwlp use_hwlp regc_mux hwlp_end_q next_valid
data_match_region
W_rule hwloop_cnt_mux_sel rdata_unaligned
hwlp_counter_n imm_a_mux_sel do_fetch jump_in_idjump_in_id int_controller_i addaddr_n addr_int addr_real_next r_n hwloop_regs_i next_is_crossword pmp_unit_i
rdardata rdata_unaligned L0_buffer_i CS NS ta
EN_rule exc_ctrl_cs X_rule
mmult_dot_enult_dot_en
csr_csr_op op
addr_real_next
irq_id_q decoder_i regfile_mem_we regfile_alu_we
hwlp_counter_q
do_hwlp
valid
addr_int irq_sec_q rdata_last_qrdata_last_q regfile_alu_we
hwloohwloop_we csr_illegal p_we
NSNS do_fetch do_hwlp
uuse_lastse_last
ddata_reqata_req regfile_mem_we
addr_q
hwlp_is_crossword
csr_illegal
save_rdasave_rdata_last ta_last L0_buffer_i busy_L0
mmult_int_enult_int_en
do_hwlp_intdo_hwlp_int
is_hwlp_q
CS
addaddr_q instr_addr_int hwloop_controller_i r_q instr_addr_int
save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid decoder_i addr_qsave_rdata_hwlp
is_crossword
illegal_illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i insn_n
next_upper_compressed
is_hwlp_n
L0_buffer ebrk_force_debug_mode
ctrl_fsctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de m_ns
jump_done_q
NS controller_i irq_enable_int
ctrl_fsm_csctrl_fsm_cs
instr_valid_irq_flush_q
branch_in_id
illegal_insn_qillegal_insn_q
jump_done L0_bufferprefetch_buffer_i instr_valid_irq_flush_n debug_mode_q
debug_mode_n
controller_i data_err_q jump_in_dec
Figure 6.3.: System error, ALU test - causation cluster
System Error - Memory Access
Beside the LSU, IF, and ID pipeline components, ALU related targets as a part of the execution stage, show an additional high ratio of causation behavior for memory access violations by affecting potential load and store addresses. This can be related to the ALU being used to calculate memory addresses for storing the test values, thus, accessing invalid address spaces if the address value was corrupted.
67 6. Results
un- /weighted [%] target module function ALU MUL AES mem register file i 20.9/11.7 16.1/8.64 23.7/13.5 register file memory L0 buffer L0 buffer i 15.6/16.7 17.0/17.7 13.0/14.1 128-bit instr. cache addr q prefetch buffer i 9.65/10.8 10.2/10.9 10.9/12.4 prefetch address instr rdata id riscv core i 6.47/6.27 6.27/6.88 5.38/6.14 instr. data (IF) alu operand a ex riscv core i 5.47/5.14 5.14/5.65 4.57/5.20 ALU op. a (ID) alu operand b ex riscv core i 5.05/4.75 4.74/5.21 4.38/4.99 ALU op. b (ID) imm b id stage i 3.94/4.43 4.33/4.75 4.03/4.60 ALU immediate b data addr int load store unit i 2.90/3.26 3.31/3.64 3.20/3.65 LSU addr. (EX)
Table 6.9.: System error causation - influential targets
System Error - Illegal Instruction
For illegal instructions mostly GPR or instruction fetch and decode related targets are an issue, while executing modules are not.
6.2.3. Application Errors
Fig. 6.4 shows the evaluation’s application error causation cluster. Fig. A.15 focuses on targets silently corrupting the systems output and fig A.16 illustrates fault causes altering the application’s execution progress. The overall fault pattern is very similar to the system error one. However, these application level errors are not as easily detectable by the core itself. For example, a storage address might have been corrupted but the altered address value might still be in a region viable to the memory protection. More classically, the actual data written to system outputs varies from what should have been calculated by the application. Overall, almost every module or region of the system can produce an application error. The heat map is shown in fig. A.24. Most prominently a thick and continuous line around bit index 4,000 can be seen which corresponds to the program counter registers.
Application Error - Output
For output corruptions, the most parts of the system under test can have an affect. The comparison between MUL and ALU/AES test shows, that even though some hardware parts are not utilized by an application, they can still produce fault effects. For example, in the ALU and AES tests, the multiplier and division units are not used, however, are identified by the framework as causing application level faults. In this specific case, these faults were caused, like in pipeline stalling effects, by current state registers of FSMs.
68 6.2. Fault Effect Causation
ResInv_SP
cs_registers_i ResInv_SN div_i is_pcmr
RemSel_SP
Cnt_DP
is_pcer mcause_n ABComp_S
LoadEn_S RemSel_SN
PCCR_q
BRegEn_S PCER_n
priv_lvl_n CompInv_SP
ucause_q
AddMux_D cnt_l1
mtvec_n
State_SPState_SP
cnt_l3 AReg_DN State_SN
ucause_n mscratch_n dscratch1_q
exception_pc
OutMux_D
dscratch1_n
alu_i cnt_l2
Cnt_DN ResRegEn_S index_lut
PCCR_n
index_nodes ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready ResReg_DP alu_popcnt_i cnt_l1 cnt_l2 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN ResReg_DN shift_arithmeticshift_arithmetic
PCCR_inc alu_popcnt_i
mepc_q
ResReg_DP_rev shuffle_reg0_sel
is_pccr cnt_l4
pccr_all_sel sel_nodes
ARegEn_S AReg_DP f_is_nan alu_ff_i pmp_reg_n
AddTmp_D cmp_result
ff_input BReg_DP pmp_reg_q dcsr_n div_ready
radix_2_rev
div_shift BReg_DN PCMR_n cnt_result
mepc_n CompInv_SN
mstatus_n shuffle_r1_in is_greater adder_op_b_negate operand_a_rev adder_op_b_negate adder_result_expanded pmpcfg_we operand_a_revadder_result_expanded shift_use_roundshift_use_round
pmpaddr_we operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int operand_a_neg_rev shift_amt_int dscratch0_n csr_wdata_int
PCER_q shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev shift_result utvec_n csr_we_int
pack_result
perf_rdata cmp_signed
adder_in_a is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed is_equal
dscratch0_q utvec_q shuffle_r0_in uepc_q adder_in_a shift_amt mscratch_q priv_lvl_q shuffle_through
shift_left_result
csr_rdata_int div_validdiv_valid shift_op_a
mtvec_q
mstatus_q depc_q dcsr_q shift_op_a shuffle_result div_op_a_signed bmask
shuffle_r1
depc_n
bextins_result
PCCR_inc_q sel_minmax
shuffle_r0
id_valid_q is_equal_clip adder_op_a
PCMR_q shuffle_byte_sel mcause_q result_minmax
uepc_n
pccr_index radix_4_rev
shift_amt_left
radix_8_rev PCCR_in
is_equal_vec adder_result adder_op_b shift_leftshift_left
adder_in_b
is_greater_vec minmax_b shuffle_reg_sel adder_in_b shift_right_result
shuffle_reg1_sel
bitop_result f_is_greater mult_i
short_subword ex_stage_i mulh_clearcarry mulh_signed riscv_coredata_load_event_ex _i data_load_event_ex mulh_NS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i mulh_NS dot_short_op_b
mulh_ready id_valid
csr_access_excsr_access_ex regfile_waddr_lsu mult_result regfile_waddr_lsu
mulh_active
mult_clpx_img_ex dot_char_mul csr_save_ex top data_req_exdata_req_ex csr_save_id short_op_b regfile_we_lsuregfile_we_lsu dot_short_result
dot_char_op_b mult_sel_subword_ex dot_char_op_a csr_restore_mret_id irq_sec_i data_req_pmp
mulh_save alu_result mult_result alu_i div_shift alu_result
regfile_alu_we_fwregfile_alu_we_fw
data_gnt_pmp u_irq_enable pc_set short_mac instr_req_o data_gnt_i regfile_we_wb regfile_we_wb clpx_shift_result dot_short_op_a illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux illegal_c_insn_id
m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int mulh_shift_arith clk_i m_irq_enable
is_compressed_id data_type_exdata_type_ex is_compressed_id
irq_id_o
csr_hwlp_we
data_sign_ext_ex exc_pc_mux_id data_sign_ext_ex
instr_req_intinstr_req_int
useincr_addr_exuseincr_addr_ex
sec_lvl_o
short_result dot_short_mul ex_ready data_rvalid_i data_we_o mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rvalid_i
csr_save_if mulh_carry_q mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 data_misaligned_exdata_misaligned_ex mult_operand_a_ex bmask_a_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex mult_signed_mode_ex bmask_a_ex branch_in_ex ctrl_busy data_be_o branch_in_ex csr_restore_uret_id instr_rdata_id
irq_id_i short_op_a
bmask_b_exbmask_b_ex mulh_subword core_ctrl_firstfetch mulh_CSmulh_CS
clk_en rstn_i data_rdata_i instr_gnt_i top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id regfile_alu_we_exregfile_alu_we_ex mult_clpx_shift_ex alu_clpx_shift_ex mult_operator_ex alu_clpx_shift_ex instr_rdata_idmult_dot_op_c_ex debug_csr_save
core_clock_gate_i regfile_alu_wdata_fw data_addr_o
alu_operand_b_ex
short_shift_arith alu_operand_a_ex
data_req_o
mult_dot_signed_ex
apu_en_ex clear_instr_valid apu_en_ex debug_req_i csr_addr_int alu_is_subrot_ex instr_addr_o alu_is_subrot_ex
data_wdata_o csr_cause perf_pipeline_stall alu_operand_b_ex csr_rdata pc_ex pc_ex irq_ack_o
pc_idpc_id regfile_alu_waddr_exregfile_alu_waddr_ex data_reg_offset_ex id_ready core_busy_o data_reg_offset_ex
irq_i is_hwlp_id trap_addr_mux
lsu_rdata fetch_enable_i alu_operand_a_exalu_operand_c_ex mult_dot_op_b_ex
alu_operand_c_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex imm_vec_ext_ex instr_valid_idinstr_valid_id
mult_imm_ex
lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp
ctrl_busy mem mult_operand_c_ex
mult_operand_b_ex
exc_cause pc_mux_id alu_vec_mode_ex riscv_register_file_i
is_decodingis_decoding
data_err_ack alu_operator_ex
is_fetch_failed_id is_fetch_failed_id alu_operator_ex data_misaligneddata_misaligned
debug_cause
regfile_waddr_ex data_we_id data_we_id hwlp_dec_cnt_id csr_op_ex regfile_waddr_ex csr_op_ex mem
if_valid halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb halt_if
csr_hwlp_regid mult_operator_ex rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id rega_used_dec csr_status csr_status offset_fsm_cs hwlp_dec_cnt regfile_we_exregfile_we_ex ebrk_insnebrk_insn
alu_is_clpx_ex apu_lat_ex apu_lat_ex
lsu_ready_ex fencei_insn_dec we_a_decwe_a_dec mult_multicyclemult_multicycle fencei_insn_dec valid we_b_decwe_b_dec j csr_save_cause hwloop_regid
ex_valid
mult_is_clpx_ex reg_d_wb_is_reg_a_id hwloop_we
hwloop_start_mux_sel fetch_addr_n mult_dot_signed
hwloop_controller_i hwlp_target csr_restore_dret_id rdata_offset_qrdata_offset_q fetch_ready clk
data_we_exdata_we_ex
data_type_iddata_type_id operand_a_fw_mux_seloperand_a_fw_mux_sel registers_i
instr_req_pmp alu_en_exalu_en_ex
data_rdata_ext fetch_rdata exc_kill alu_op_a_mux_selalu_op_a_mux_sel mult_en_ex mult_en_ex bmask_b_muxbmask_b_mux
pc_is_end_addr uret_insn_decuret_insn_dec
fetch_is_hwlp hwloop_cnt_int
mult_operator CS NS CS instr_gnt_pmp rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q id_valid_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_q uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr instr_decompressed rdata_q mult_imm_mux
data_addr_int bmask_b_id_immbmask_b_id_imm operand_c_fw_mux_se l bmask_a_mux hwlp_dec_cnt_if operand_c_fw_mux_sel
uret_dec hwloop_we_masked
exc_pc data_addr_int alu_op_b_mux_selalu_op_b_mux_sel
trap_base_addr
reg_d_ex_is_reg_a_idreg_d_ex_is_reg_a_id regfile_data_ra_id
is_hwlp_id_q data_sign_ext_q data_we_q data_sign_ext_q operand_a_fw_id
bmask_a_mux
illegal_c_insn alu_vec_mode alu_vec_mode
jump_target_mux_sel mult_operator mult_int_en mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_data_ra_idhwloop_cnt branch_taken_ex rdata_b_ext jump_target_mux_sel data_type_qdata_type_q id_stage_i
jump_in_id branch_req
rdata_h_ext fetch_valid
imm_b_mux_selimm_b_mux_sel alu_operand_b
offset_fsm_ns imm_b mret_dec uret_dec dret_dec mret_dec data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_cnt_mux_sel hwloop_valid data_sign_ext_id mult_int_en deassert_we imm_i_type wdata_offsetwdata_offset data_we_q csr_accesscsr_access
compressed_decoder_i alu_operand_a NS imm_vu_type imm_i_typeimm_bimm_vu_type
load_store_unit_i regb_used_dec operand_b
scalar_replicationscalar_replication ecall_insn_dec ecall_insn_dec mult_dot_en
operand_c is_subrotis_subrot hwloop_start_int alu_operator if_stage_i alu_operator mult_signed_mode
jump_targetjump_target
operand_b_fw_mux_seloperand_b_fw_mux_sel
regc_used_dec load_stall operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i hwloop_target pipe_flush_decpipe_flush_dec
alu_enalu_en regfile_alu_waddr_idregfile_alu_waddr_id MODE_rule is_clpx regfile_addr_rc_id mret_insn_dec mask_addr mret_insn_dec regfile_alu_we_id regfile_alu_we_id operand_b_vec R_rule
dret_insn_dec data_err_state_q dret_insn_dec alu_op_c_mux_sel regc_mux imm_a_mux_sel alu_op_c_mux_sel mult_sel_subword
bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx reg_d_ex_is_reg_b_id dret_dec
illegal_insn_dec
data_req_id
data_err_state_n alu_bmask_a_mux_se l alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm alu_bmask_a_mux_sel
hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id
stop_addr start_addr prepost_useincrprepost_useincr
data_load_event_id regfile_alu_waddr_mux_selregfile_alu_waddr_mux_sel
fetch_valid hwloop_valid
halt_id
exc_ack
CSCS hwlp_start_q instr_match_region alu_bmask_b_mux_sel
use_hwlp use_hwlp regc_mux hwlp_end_q next_valid
data_match_region
W_rule hwloop_cnt_mux_sel rdata_unaligned
hwlp_counter_n imm_a_mux_sel do_fetch jump_in_id int_controller_i addr_n addr_int addr_real_next addr_n hwloop_regs_i next_is_crossword pmp_unit_i rdata rdata_unaligned L0_buffer_i CS NS rdata
EN_rule exc_ctrl_cs X_rule
mult_dot_enmult_dot_en csr_op
addr_real_next
irq_id_q decoder_i regfile_mem_we regfile_alu_we data_req hwloop_we csr_illegal jump_in_id csr_op
hwlp_counter_q
do_hwlp
valid
addr_int irq_sec_q rdata_last_qrdata_last_q
regfile_alu_we
hwloop_we NS do_fetch do_hwlp NS
use_lastuse_last data_req
regfile_mem_we
addr_q
hwlp_is_crossword
addr_q csr_illegal save_rdata_last save_rdata_last L0_buffer_i busy_L0
mult_int_enmult_int_en
do_hwlp_intdo_hwlp_int
is_hwlp_q
CS addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec addr_q instr_addr_int
save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid decoder_i save_rdata_hwlp
is_crossword
illegal_insn_n
next_upper_compressed
is_hwlp_n
L0_buffer ebrk_force_debug_mode ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i ctrl_fsm_ns
jump_done_q
NS controller_i
irq_enable_int
ctrl_fsm_csctrl_fsm_cs
instr_valid_irq_flush_q
branch_in_id
illegal_insn_q
jump_done L0_bufferprefetch_buffer_i instr_valid_irq_flush_n debug_mode_q
debug_mode_n
controller_i data_err_q jump_in_dec
Figure 6.4.: Application error, ALU test - causation cluster
Application Error - Program Flow
For program or execution flow corruption, the pattern resembles the output corruption pattern, however, parts of the CSR take over as most influential ones, e.g. the program counter registers. This phenomenon is described in sec. 6.1.
69 6. Results
un- /weighted [%] target module function ALU MUL AES PCCR q cs registers i 15.9/15.0 14.9/14.0 17.1/15.7 performance counters mem register file i 13.3/9.27 10.7/7.55 5.12/3.46 register file memory L0 buffer L0 buffer i 12.9/13.5 15.2/15.6 16.5/16.8 128-bit instr. cache instr rdata id riscv core i 4.57/4.94 4.34/4.63 5.67/5.967 instr. data (IF) alu operand a ex riscv core i 3.98/4.30 3.60/3.84 3.98/4.18 ALU op. a (ID) alu operand b ex riscv core i 3.85/4.16 3.21/3.42 3.73/3.92 ALU op. b (ID)
Table 6.10.: Application error causation - influential targets
70 6.3. Conclusion
6.3. Conclusion
Several consequences can be formulated for the evaluation results. The more statistical ap- proach observing the probability of a fault effect appearing considering random injections can show an overall vulnerability of the evaluated RISC-V core to soft errors. In case of RI5CY with a bare-metal test software evaluated without any additional resiliency methods applied, the RISC-V core has shown a good response, i.e. soft error resiliency. The overall number of hang-up effect (pipeline and logic stalls), for example, might seem quite high at around 0.8 percent, however, the majority of these errors could be either handled or avoided by mea- sures on the software level in the first place. For example, (Weinzierl 2017) explored multiple compiler-based solutions that check the control flow by software signatures or duplicate in- structions to introduce redundancy. These software measures could reduce the rate of logic hang-ups observed in this thesis’ evaluation.
Similarly, the system can handle the observed system errors itself provided its protecting com- ponents are configured in such a way and a defined state is reached by the system on its after a fault. However, the pipeline stalling faults would remain. This sub-group, which makes up about 0.1 percent of all evaluations results, has to be solved by hardware measures. In general, there are two approaches for this; Either resolving the fault effect or avoiding it in the first place.
Avoiding errors would require to increase the hardware’s resiliency against the causing effects, i.e. neutron and alpha particle effects on the chip. While random access memory (RAM), both static and dynamic, are frequently considered for radiation hardening, micro-architectural parts often are not. (Baze et al. 2000) proposed radiation hardening techniques for CMOS logic through placement of transistors in biased and isolated wells. Amongst other things the work showed examples for resilient inverters that, in form of cross-coupled pairs, are the basic components for sequential logic. Electronic suppliers also provide radiation tolerant SoC platforms that, for example, can be found in aerospace applications (Microchip Technology Inc. n.d.). Resolving, or rather detecting and correcting an error, could be done by some additional hardware performing continuous checks. This could either be a quite forceful action like resetting the system to a error free state, e.g. by a watchdog, or a more gentle one; Sequential logic paths are implemented multiple times, then, a majority vote decides what the correct value for each path has to be since multiple soft-errors on the same path are very unlikely (Baumann 2005). This and other redundancy methods increase area usage of the protected hardware, therefore, are sometimes not feasible for the whole digital system. Implementing the redundancy only on critical sections could pose a trade-off between cost and the gained soft error resiliency.
The results from this work’s evaluation process have shown some of these critical sections for the RI5CY core in form of vulnerable micro-architectural targets. Some form of majority vote could be added to the core’s various finite state machine registers that were showing an especially high ratio of pipeline-stalling hang-up effects.
71 6. Results
72 7. Summary
In this work, a fast, guaranteed fault injection framework based on the Verilator HDL simulator was developed. To enable Verilator’s output (VRTL) simulations of soft errors, its C++ sources had to be modified. Due to the size of the VRTL, manual modifications were not feasible. Additionally, two modification types were evaluated with source-transformation coming out on top. Therefore, a LLVM-based and model-agnostic source transformation tool was developed that inserts injection points in the source code. An API builder automatically generates an individual Injection API for a each modified VRTL, thus, allowing high compiler optimization capabilities for executable simulation.
A possible design flow was proposed through a toolchain that builds an efficient injection frame- work from hardware description to executable simulation. As proof-of-concept, the modified VRTL of a RISC-V ISA implementing core was extended to a fault injection simulation frame- work. The framework was fed with over 10 million random injection runs for three different test program. In each simulation run, one space- and time-random bit flip of the model’s sequential logic was applied and the effect on the core under test observed. From the mass of simulation run results, an evaluation for statistical probability of a certain fault effect was formulated. Furthermore, each fault effect was examined for causation in the model. Thus, existing vulnerabilities of certain parts of the core under test could be located.
Most fault effects can be handled either by additional features, like proper exception han- dling, of the examined core itself or by software-based resiliency enhancements. The remaining vulnerabilities, mostly pipeline stalling effects, would need further hardware-based measures.
In future works, the framework could be extended to support additional peripherals. Verila- tor’s SystemC capabilities could be utilized to integrate high-level models of such hardware components, thus, enabling more complex virtual prototypes with fault injection capability. Furthermore, while the work for this thesis was carried out, Verilator added multi-threaded simulation support. Spreading the high CPU load for the RTL model to multiple cores of the host machine could speed up the simulation even further. The framework currently allows uncomplicated modeling of soft errors through random injections, however, deliberate faults could be simulated and serve as a basis for a fault attack evaluation of RISC-V cores.
73 7. Summary
74 A. Appendix
ResInv_SP
cs_registers_i ResInv_SN div_i is_pcmr
RemSel_SP
Cnt_DP
is_pcer mcause_n ABComp_S
LoadEn_S RemSel_SN
PCCR_q
BRegEn_S PCER_n
priv_lvl_n CompInv_SP
ucause_q
AddMux_D cnt_l1
mtvec_n
State_SP
cnt_l3 AReg_DN State_SN
ucause_n mscratch_n dscratch1_q
exception_pc
OutMux_D
dscratch1_n
alu_i cnt_l2
Cnt_DN ResRegEn_S index_lut
PCCR_n
index_nodes
ResReg_DP
ResReg_DN shift_arithmetic
PCCR_inc alu_popcnt_i
mepc_q
ResReg_DP_rev shuffle_reg0_sel
is_pccr cnt_l4
pccr_all_sel sel_nodes
ARegEn_S AReg_DP f_is_nan alu_ff_i pmp_reg_n
AddTmp_D cmp_result
ff_input BReg_DP pmp_reg_q dcsr_n div_ready
radix_2_rev
div_shift BReg_DN PCMR_n cnt_result
mepc_n CompInv_SN
mstatus_n shuffle_r1_in is_greater
operand_a_rev adder_op_b_negate adder_result_expanded
pmpcfg_we
shift_use_round
pmpaddr_we operand_a_neg_rev shift_amt_int dscratch0_n csr_wdata_int
PCER_q shift_result utvec_n csr_we_int
pack_result
perf_rdata cmp_signed
adder_in_a is_equal
dscratch0_q utvec_q shuffle_r0_in
uepc_q
shift_amt mscratch_q priv_lvl_q shuffle_through
shift_left_result
csr_rdata_int div_valid shift_op_a
mtvec_q
mstatus_q depc_q dcsr_q shuffle_result div_op_a_signed bmask
shuffle_r1
depc_n
bextins_result
PCCR_inc_q sel_minmax
shuffle_r0
id_valid_q is_equal_clip adder_op_a
PCMR_q shuffle_byte_sel mcause_q result_minmax
uepc_n
pccr_index radix_4_rev
shift_amt_left
radix_8_rev PCCR_in
is_equal_vec adder_result adder_op_b shift_left
adder_in_b
is_greater_vec minmax_b shuffle_reg_sel shift_right_result
shuffle_reg1_sel
bitop_result f_is_greater mult_i
short_subword ex_stage_i mulh_clearcarry riscv_core_i mulh_signed data_load_event_ex
mulh_NS dot_short_op_b
mulh_ready id_valid
csr_access_ex regfile_waddr_lsu mult_result
mulh_active
mult_clpx_img_ex dot_char_mul csr_save_ex top data_req_ex csr_save_id short_op_b regfile_we_lsu dot_short_result
dot_char_op_b mult_sel_subword_ex dot_char_op_a csr_restore_mret_id irq_sec_i data_req_pmp
mulh_save alu_result
regfile_alu_we_fw
data_gnt_pmp u_irq_enable pc_set short_mac instr_req_o data_gnt_i
regfile_we_wb clpx_shift_result dot_short_op_a
illegal_c_insn_id
mulh_shift_arith clk_i m_irq_enable
data_type_ex is_compressed_id
irq_id_o
csr_hwlp_we exc_pc_mux_id data_sign_ext_ex
instr_req_int
useincr_addr_ex
sec_lvl_o
short_result dot_short_mul ex_ready data_rvalid_i data_we_o mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rvalid_i
csr_save_if mulh_carry_q
data_misaligned_ex mult_operand_a_ex mult_signed_mode_ex bmask_a_ex data_be_o branch_in_ex csr_restore_uret_id instr_rdata_id
irq_id_i short_op_a
bmask_b_ex mulh_subword core_ctrl_firstfetch mulh_CS
clk_en rstn_i data_rdata_i instr_gnt_i regfile_alu_we_ex mult_clpx_shift_ex
alu_clpx_shift_ex mult_dot_op_c_ex
debug_csr_save
core_clock_gate_i regfile_alu_wdata_fw data_addr_o
alu_operand_b_ex
short_shift_arith alu_operand_a_ex
data_req_o
mult_dot_signed_ex
clear_instr_valid apu_en_ex debug_req_i csr_addr_int instr_addr_o alu_is_subrot_ex
data_wdata_o csr_cause perf_pipeline_stall
csr_rdata pc_ex irq_ack_o
pc_id
regfile_alu_waddr_ex
id_ready core_busy_o data_reg_offset_ex
irq_i is_hwlp_id trap_addr_mux
lsu_rdata
fetch_enable_i alu_operand_c_ex
mult_dot_op_b_ex imm_vec_ext_ex instr_valid_id
mult_imm_ex
lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp
ctrl_busy mem mult_operand_c_ex
mult_operand_b_ex
exc_cause pc_mux_id alu_vec_mode_ex riscv_register_file_i
is_decoding
data_err_ack alu_operator_ex
is_fetch_failed_id data_misaligned
debug_cause
regfile_waddr_ex data_we_id hwlp_dec_cnt_id csr_op_ex
if_valid halt_if
csr_hwlp_regid mult_operator_ex
rega_used_dec
csr_status
offset_fsm_cs hwlp_dec_cnt regfile_we_ex ebrk_insn
alu_is_clpx_ex
apu_lat_ex
lsu_ready_ex fencei_insn_dec we_a_dec mult_multicycle valid we_b_dec
j csr_save_cause hwloop_regid
ex_valid
mult_is_clpx_ex reg_d_wb_is_reg_a_id hwloop_we
hwloop_start_mux_sel fetch_addr_n mult_dot_signed
hwloop_controller_i hwlp_target csr_restore_dret_id rdata_offset_q fetch_ready clk
data_we_ex
data_type_id operand_a_fw_mux_sel registers_i
instr_req_pmp alu_en_ex
data_rdata_ext fetch_rdata exc_kill alu_op_a_mux_sel
mult_en_ex bmask_b_mux
pc_is_end_addr uret_insn_dec
fetch_is_hwlp hwloop_cnt_int
mult_operator
CS instr_gnt_pmp instr_decompressed rdata_q mult_imm_mux
data_addr_int bmask_b_id_imm
hwlp_dec_cnt_if operand_c_fw_mux_sel
uret_dec hwloop_we_masked
exc_pc alu_op_b_mux_sel
trap_base_addr
reg_d_ex_is_reg_a_id regfile_data_ra_id
is_hwlp_id_q data_sign_ext_q operand_a_fw_id
bmask_a_mux illegal_c_insn alu_vec_mode
hwloop_cnt branch_taken_ex rdata_b_ext jump_target_mux_sel data_type_q id_stage_i
jump_in_id branch_req
rdata_h_ext fetch_valid
imm_b_mux_sel
alu_operand_b
offset_fsm_ns imm_b
mret_dec data_sign_ext_id mult_int_en deassert_we imm_i_type wdata_offset data_we_q csr_access
compressed_decoder_i alu_operand_a NS
imm_vu_type
load_store_unit_i regb_used_dec operand_b
scalar_replication ecall_insn_dec mult_dot_en
operand_c is_subrot hwloop_start_int if_stage_i alu_operator mult_signed_mode
jump_target
operand_b_fw_mux_sel
regc_used_dec load_stall operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel hwloop_target pipe_flush_dec
alu_en
regfile_alu_waddr_id
MODE_rule is_clpx regfile_addr_rc_id mret_insn_dec mask_addr
regfile_alu_we_id operand_b_vec R_rule
dret_insn_dec data_err_state_q
alu_op_c_mux_sel mult_sel_subword
bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall
reg_d_ex_is_reg_b_id dret_dec
illegal_insn_dec
data_req_id data_err_state_n alu_bmask_a_mux_sel
hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id
stop_addr start_addr prepost_useincr
data_load_event_id regfile_alu_waddr_mux_sel
fetch_valid hwloop_valid
halt_id
exc_ack
CS hwlp_start_q instr_match_region alu_bmask_b_mux_sel
use_hwlp regc_mux hwlp_end_q next_valid
data_match_region
W_rule hwloop_cnt_mux_sel rdata_unaligned
hwlp_counter_n imm_a_mux_sel do_fetch jump_in_id int_controller_i addr_n hwloop_regs_i next_is_crossword pmp_unit_i
rdata
EN_rule exc_ctrl_cs X_rule
mult_dot_en csr_op
addr_real_next
irq_id_q
hwlp_counter_q
do_hwlp
valid
addr_int irq_sec_q rdata_last_q
regfile_alu_we
hwloop_we NS
use_last
data_req
regfile_mem_we
addr_q
hwlp_is_crossword
csr_illegal save_rdata_last L0_buffer_i busy_L0
mult_int_en
do_hwlp_int
is_hwlp_q
CS
addr_q instr_addr_int decoder_i save_rdata_hwlp
is_crossword
illegal_insn_n
next_upper_compressed
is_hwlp_n
L0_buffer ebrk_force_debug_mode
ctrl_fsm_ns
jump_done_q
NS
irq_enable_int
ctrl_fsm_cs
instr_valid_irq_flush_q
branch_in_id
illegal_insn_q
jump_done prefetch_buffer_i instr_valid_irq_flush_n
debug_mode_q
debug_mode_n
controller_i data_err_q jump_in_dec
Figure A.1.: RI5CY injection target cluster
75 A. Appendix alu_ f alu_popcnt riscv_alu_div riscv_L0_bu f er riscv_register_ f le div_i f _i alu_ L0_bu f er_i alu_popcnt_i f le_i riscv_register_ riscv_alu riscv_mult riscv_decoder riscv_controller riscv_hwloop_regs riscv_int_controller register_ f le_test_wrap riscv_hwloop_controller riscv_prefetch_L0_bu f er riscv_compressed_decoder alu_i mult_i decoder_i registers_i controller_i hwloop_regs_i int_controller_i prefetch_bu f er_i hwloop_controller_i compressed_decoder_i riscv_pmp riscv_if_stage riscv_id_stage riscv_ex_stage riscv_cs_registers cluster_clock_gating riscv_load_store_unit if_stage_i id_stage_i ex_stage_i pmp_unit_i cs_registers_i load_store_unit_i core_clock_gate_i riscv_core riscv_core_i top
Figure A.2.: RI5CY hierarchy - modules and cell instances
76 Fault Effect Probability - MUL Test
group count % key count % Hang-Up Pipeline 0 0 HP Hang-Up Logic 26,796 4.19 HL MSK SM 2,042 8.25 System Error 24,766 3.87 12.4 % SI 22,724 91.75 77.3 % 4.19 % AO 13,774 94.3 NSK 3.87 % Application Error 14,609 2.28 2.28 % H* AP 9,797 67.1 S* Not Masked 494,589 77.3 NSK A* Masked 79,096 12.4 MSK P 639,856
Table A.1.: Fault effect probability, MUL test - GPR targets
group count % key count % Hang-Up Pipeline 0 0 HP Hang-Up Logic 0 0 HL MSK SM 0 0 System Error 0 0 11.9 % SI 0 0 2.76 % AO 0 0 85.4 % AP Application Error 27,291 2.76 AP 27,291 100.0 NSK Not Masked 845,367 85.4 NSK Masked 117,421 11.9 MSK P 990,079
Table A.2.: Fault effect probability, MUL test - CSR targets
group count % key count % MSK Hang-Up Pipeline 3,611 0.176 HP Hang-Up Logic 2,444 0.119 HL 67.1 % SM 90,189 69.9 System Error 129,001 6.28 SI 38,812 30.1 0.298 % H* AO 78,889 82.0 6.28 % Application Error 96,157 4.68 4.68 % S* AP 47,903 49.8 21.7 % Not Masked 444,918 21.7 NSK A* Masked 1,378,049 67.1 MSK P 2,054,180 NSK
Table A.3.: Fault effect probability, MUL test - micro-architectural targets
77 A. Appendix
Fault Effect Probability - AES Test
group count % key count % Hang-Up Pipeline 0 0 HP MSK Hang-Up Logic 9,487 2.12 HL SM 7,143 34.4 21.3 % System Error 20,782 4.65 SI 13,639 65.6 2.12 % AO 3,914 93.4 4.65 % Application Error 4,192 0.937 70.9 % 0.937 % H* AP 3,813 91.0 S* NSK A* Not Masked 317,342 70.9 NSK Masked 95,473 21.3 MSK P 447,276
Table A.4.: Fault effect probability, AES test - GPR targets
group count % key count % Hang-Up Pipeline 0 0 HP Hang-Up Logic 0 0 HL MSK SM 0 0 System Error 0 0 12.0 % SI 0 0 2.66 % AO 0 0 85.4 % AP Application Error 18,407 2.66 AP 18,407 100.0 NSK Not Masked 590,624 85.4 NSK Masked 82,903 12.0 MSK P 691,934
Table A.5.: Fault effect probability, AES test - CSR targets
group count % key count % MSK Hang-Up Pipeline 2,504 0.174 HP Hang-Up Logic 7,368 0.513 HL 65.5 % SM 37,110 55.5 System Error 66,927 4.66 SI 29,817 44.5 0.687 % H* AO 49,454 81.0 4.66 % Application Error 61,044 4.25 4.25 % S* AP 56,258 92.2 24.9 % Not Masked 357,192 24.9 NSK A* Masked 941,600 65.5 MSK P 1,436,635 NSK
Table A.6.: Fault effect probability, AES test - micro-architectural targets
78 Fault Effect Causation - Hang-up Error Clusters
ResInv_SP ResInv_SP
ResInv_SN cs_registers_i div_i ResInv_SN is_pcmr cs_registers_i div_i is_pcmr
RemSel_SP RemSel_SP
Cnt_DP Cnt_DP is_pcer mcause_n ABComp_S is_pcer mcause_n ABComp_S
LoadEn_S RemSel_SN LoadEn_S RemSel_SN
PCCR_q PCCR_q
BRegEn_S PCER_n BRegEn_S PCER_n
priv_lvl_n CompInv_SP priv_lvl_n CompInv_SP
ucause_q ucause_q
AddMux_D cnt_l1 AddMux_D cnt_l1 mtvec_n mtvec_n State_SP State_SP
cnt_l3 cnt_l3 AReg_DN State_SN AReg_DN State_SN
ucause_n mscratch_n dscratch1_q ucause_n mscratch_n dscratch1_q
exception_pc exception_pc
OutMux_D OutMux_D
dscratch1_n dscratch1_n
alu_i cnt_l2 alu_i cnt_l2 Cnt_DN ResRegEn_S index_lut Cnt_DN ResRegEn_S index_lut PCCR_n PCCR_n index_nodes index_nodes
ResReg_DP ResReg_DP alu_popcnt_i cnt_l1 cnt_l2 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN State_SP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready mulh_CS mulh_NS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q rdata_offset_q data_sign_ext_q data_we_q wdata_offset CS NS data_addr_int rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q id_valid_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_q uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr ResReg_DN shift_arithmetic ResReg_DN shift_arithmetic
PCCR_inc alu_popcnt_i PCCR_inc alu_popcnt_i mepc_q mepc_q
ResReg_DP_rev ResReg_DP_rev shuffle_reg0_sel shuffle_reg0_sel
is_pccr cnt_l4 is_pccr cnt_l4
pccr_all_sel sel_nodes pccr_all_sel sel_nodes ARegEn_S ARegEn_S AReg_DP AReg_DP f_is_nan alu_ff_i f_is_nan alu_ff_i pmp_reg_n pmp_reg_n AddTmp_D cmp_result AddTmp_D cmp_result
ff_input BReg_DP ff_input BReg_DP pmp_reg_q dcsr_n pmp_reg_q div_ready dcsr_n div_ready
radix_2_rev radix_2_rev div_shift div_shift BReg_DN BReg_DN PCMPCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr R_n cnt_result PCMR_n cnt_result
mepc_n mepc_n CompInv_SN CompInv_SN
mstatus_n shuffle_r1_in is_greater mstatus_n shuffle_r1_in is_greater
operand_a_rev adder_op_b_negate operand_a_rev adder_op_b_negate adder_result_expanded adder_result_expandedadder_result_expanded pmpcfg_we pmpcfg_we
shift_use_round shift_use_round pmpaddr_we pmpaddr_we operand_a_neg_rev shift_amt_int operand_a_neg_rev dscratch0_n shift_amt_int csr_wdata_int dscratch0_n csr_wdata_int
PCER_q shift_result PCER_q shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev utvec_n shift_result csr_we_int utvec_n csr_we_int pack_result pack_result perf_rdata cmp_signed perf_rdata cmp_signed
adder_in_a is_equal adder_in_aadder_in_a is_equal dscratch0_q utvec_q dscratch0_q utvec_q shuffle_r0_in shuffle_r0_in
uepc_q uepc_q
shift_amt shift_amt mscratch_q priv_lvl_q priv_lvl_q shuffle_through mscratch_q shuffle_through
shift_left_result shift_left_result csr_rdata_int div_valid csr_rdata_int div_valid shift_op_a shift_op_ashift_op_a
mtvec_q mtvec_q
mstatus_q depc_q mstatus_q dcsr_q depc_q dcsr_q shuffle_result div_op_a_signed shuffle_result div_op_a_signed bmask bmask shuffle_r1 shuffle_r1
depc_n depc_n
bextins_result bextins_result
PCCR_inc_q sel_minmax PCCR_inc_q sel_minmax shuffle_r0 shuffle_r0
id_valid_q is_equal_clip id_valid_q is_equal_clip adder_op_a adder_op_a PCMR_q shuffle_byte_sel PCMR_q mcause_q result_minmax shuffle_byte_sel mcause_q result_minmax
uepc_n uepc_n
pccr_index pccr_index radix_4_rev radix_4_rev
shift_amt_left shift_amt_left
radix_8_rev radix_8_rev PCCR_in PCCR_in is_equal_vec priv_lvl_q adder_result is_equal_vec adder_result adder_op_b adder_op_b shift_left shift_left
adder_in_b adder_in_badder_in_b
is_greater_vec is_greater_vec minmax_b shuffle_reg_sel minmax_b shift_right_result shuffle_reg_sel shift_right_result
shuffle_reg1_sel shuffle_reg1_sel
bitop_result bitop_result
f_is_greater mult_i f_is_greater mult_i
short_subword short_subword
mulh_clearcarry ex_stage_i ex_stage_i mulh_clearcarry mulh_signed riscv_core_i mulh_signed data_load_event_ex riscv_core_i data_load_event_ex
mulh_NS mulh_NS dot_short_op_b dot_short_op_b
mulh_ready mulh_ready id_valid id_valid
csr_access_ex regfile_waddr_lsu csr_access_ex regfile_waddr_lsu mult_result mult_result
mulh_active mulh_active
mult_clpx_img_ex dot_char_mul mult_clpx_img_ex dot_char_mul csr_save_ex data_req_ex csr_save_ex top data_req_ex csr_save_id short_op_b top regfile_we_lsu dot_short_result csr_save_id short_op_b regfile_we_lsu dot_short_result
dot_char_op_b dot_char_op_b mult_sel_subword_ex dot_char_op_a mult_sel_subword_ex dot_char_op_a csr_restore_mret_id csr_restore_mret_id irq_sec_i data_req_pmp irq_sec_i data_req_pmp
mulh_save mulh_save alu_result alu_result
regfile_alu_we_fw regfile_alu_we_fw
data_gnt_pmp data_gnt_pmp u_irq_enable pc_set u_irq_enable pc_set short_mac instr_req_o data_gnt_i short_mac instr_req_o data_gnt_i
regfile_we_wb clpx_shift_result dot_short_op_a regfile_we_wb clpx_shift_result dot_short_op_a
illegal_c_insn_id illegal_c_insn_id
clk_i mulh_shift_arith m_irq_enable mulh_shift_arith clk_i m_irq_enable data_type_ex is_compressed_id data_type_ex is_compressed_id
irq_id_o irq_id_o csr_hwlp_we exc_pc_mux_id csr_hwlp_we data_sign_ext_ex exc_pc_mux_id data_sign_ext_ex instr_req_int instr_req_int useincr_addr_ex useincr_addr_ex
sec_lvl_o sec_lvl_o dot_short_mul short_result dot_short_mul ex_ready short_result data_rvalid_i ex_ready data_rvalid_i data_we_o data_we_o mulh_imm short_signed mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rdata_i csr_irq_sec instr_rvalid_i instr_rvalid_i csr_save_if mulh_carry_q csr_save_if mulh_carry_q
data_misaligned_ex mult_operand_a_ex data_misaligned_ex mult_operand_a_ex bmask_a_ex mult_signed_mode_ex branch_in_ex data_be_o instr_rdata_id mult_signed_mode_ex bmask_a_ex csr_restore_uret_id data_be_o branch_in_ex csr_restore_uret_id csr_restore_uret_id instr_rdata_idinstr_rdata_id
irq_id_i short_op_a irq_id_i short_op_a
bmask_b_ex mulh_subword bmask_b_ex mulh_subword core_ctrl_firstfetch mulh_CS core_ctrl_firstfetch mulh_CS
clk_en rstn_i clk_en rstn_i data_rdata_i instr_gnt_i data_rdata_i instr_gnt_i top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id instr_valid_id is_compressed_id is_fetch_failed_id illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux is_decoding useincr_addr_ex data_misaligned mult_multicycle branch_in_ex ctrl_busy alu_en_ex alu_operator_ex bmask_a_ex bmask_b_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex mult_en_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex apu_en_ex apu_lat_ex regfile_waddr_ex regfile_we_ex regfile_we_wb regfile_alu_waddr_ex regfile_alu_we_ex regfile_alu_we_fw csr_op_ex data_we_ex data_type_ex data_sign_ext_ex data_reg_offset_ex data_req_ex data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb instr_req_int m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id instr_valid_id is_compressed_id is_fetch_failed_id illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux is_decoding data_misaligned mult_multicycle branch_in_ex ctrl_busy alu_en_ex alu_operator_ex bmask_a_ex bmask_b_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex mult_en_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex apu_en_ex apu_lat_ex regfile_waddr_ex regfile_we_ex regfile_we_wb regfile_alu_we_ex regfile_alu_we_ex regfile_alu_we_fw csr_access_ex csr_op_ex data_we_ex data_type_ex data_sign_ext_ex data_reg_offset_ex data_req_ex data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb instr_req_int m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int mult_clpx_shift_ex regfile_alu_we_ex mult_clpx_shift_ex
alu_clpx_shift_ex mult_dot_op_c_ex alu_clpx_shift_ex mult_dot_op_c_ex debug_csr_save debug_csr_save core_clock_gate_i regfile_alu_wdata_fw core_clock_gate_i data_addr_o regfile_alu_wdata_fw data_addr_o
alu_operand_b_ex alu_operand_b_exalu_operand_b_ex
short_shift_arith short_shift_arith alu_operand_a_ex alu_operand_a_exalu_operand_a_ex data_req_o data_req_o
mult_dot_signed_ex mult_dot_signed_ex
apu_en_ex clear_instr_valid apu_en_ex debug_req_i clear_instr_valid debug_req_i csr_addr_int instr_addr_o alu_is_subrot_ex csr_addr_int instr_addr_o alu_is_subrot_ex
data_wdata_o data_wdata_o csr_cause csr_cause perf_pipeline_stall perf_pipeline_stall
csr_rdata pc_ex csr_rdata irq_ack_o pc_ex irq_ack_o
pc_id pc_id pc_ex pc_id regfile_alu_waddr_ex regfile_alu_waddr_exregfile_alu_waddr_ex
data_reg_offset_ex id_ready core_busy_o id_ready core_busy_o data_reg_offset_ex
irq_i is_hwlp_id trap_addr_mux irq_i is_hwlp_id trap_addr_mux
lsu_rdata lsu_rdata
fetch_enable_i alu_operand_c_ex alu_operand_c_ex mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 fetch_enable_i alu_operand_c_ex
mult_dot_op_b_ex mult_dot_op_b_ex imm_vec_ext_ex imm_vec_ext_ex instr_valid_id instr_valid_id
mult_imm_ex mult_imm_ex lsu_ready_wb mult_dot_op_a_ex lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp core_busy_q data_err_pmp
ctrl_busy mem ctrl_busy mem mult_operand_c_ex mult_operand_c_ex
mult_operand_b_ex mult_operand_b_ex
pc_mux_id exc_cause alu_vec_mode_ex riscv_register_file_i pc_mux_id exc_cause alu_vec_mode_ex riscv_register_file_i
is_decoding is_decoding
data_err_ack data_err_ack alu_operator_ex alu_operator_ex is_fetch_failed_id data_misaligned is_fetch_failed_id data_misaligned
debug_cause debug_cause
regfile_waddr_ex data_we_id regfile_waddr_ex hwlp_dec_cnt_id data_we_id hwlp_dec_cnt_id csr_op_ex csr_op_ex
if_valid halt_if if_valid halt_if csr_hwlp_regid mult_operator_ex csr_hwlp_regid mult_operator_ex
rega_used_dec rega_used_dec
csr_status csr_status offset_fsm_cs hwlp_dec_cnt regfile_we_ex ebrk_insn offset_fsm_cs hwlp_dec_cnt regfile_we_ex ebrk_insn
alu_is_clpx_ex alu_is_clpx_ex
apu_lat_ex apu_lat_ex fencei_insn_dec we_a_dec lsu_ready_ex fencei_insn_dec memwe_a_dec mult_multicycle lsu_ready_ex mult_multicycle valid we_b_dec valid we_b_dec j csr_save_cause we_a_dec we_b_dec hwloop_regid j csr_save_cause hwloop_regid
ex_valid ex_valid
mult_is_clpx_ex reg_d_wb_is_reg_a_id mult_is_clpx_ex hwloop_we reg_d_wb_is_reg_a_id hwloop_we hwloop_start_mux_sel fetch_addr_n hwloop_start_mux_sel fetch_addr_n mult_dot_signed mult_dot_signed
csr_restorcsr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int instr_rdata_id pc_id pc_ex alu_operand_a_ex alu_operand_b_ex alu_operand_c_ex mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 e_dret_id hwloop_controller_i hwlp_target csr_restore_dret_id hwloop_controller_i hwlp_target rdata_offset_q fetch_ready rdata_offset_q clk fetch_ready clk
data_we_ex data_we_ex data_type_id operand_a_fw_mux_sel registers_i data_type_id operand_a_fw_mux_sel registers_i
instr_req_pmp alu_en_ex instr_req_pmp alu_en_ex
data_rdata_ext data_rdata_ext fetch_rdata exc_kill alu_op_a_mux_sel fetch_rdata exc_kill alu_op_a_mux_sel
mult_en_ex bmask_b_mux mult_en_ex bmask_b_mux
pc_is_end_addr uret_insn_dec pc_is_end_addr uret_insn_dec
fetch_is_hwlp hwloop_cnt_int fetch_is_hwlp hwloop_cnt_int
mult_operator mult_operator
CS instr_gnt_pmp CS instr_gnt_pmp instr_decompressed rdata_q instr_decompressed rdata_q mult_imm_mux mult_imm_mux
data_addr_int bmask_b_id_imm data_addr_int bmask_b_id_imm hwlp_dec_cnt_if operand_c_fw_mux_sel hwlp_dec_cnt_if operand_c_fw_mux_sel uret_dec uret_dec hwloop_we_masked hwloop_we_masked
exc_pc exc_pc alu_op_b_mux_sel alu_op_b_mux_sel
trap_base_addr trap_base_addr reg_d_ex_is_reg_a_id regfile_data_ra_id reg_d_ex_is_reg_a_id regfile_data_ra_idregfile_data_ra_id
is_hwlp_id_q data_sign_ext_q operand_a_fw_id is_hwlp_id_q data_sign_ext_q operand_a_fw_id
bmask_a_mux bmask_a_mux illegal_c_insn alu_vec_mode illegal_c_insn alu_vec_mode
hwloop_cnt branch_taken_ex rdata_b_ext jump_target_mux_sel hwloop_cnt branch_taken_ex data_type_q id_stage_i rdata_b_ext jump_target_mux_sel data_type_q id_stage_i
CS jump_in_id branch_req jump_in_id branch_req rdata_h_ext rdata_h_ext fetch_valid fetch_valid
imm_b_mux_sel imm_b_mux_sel
alu_operand_b alu_operand_b
offset_fsm_ns imm_b imm_b offset_fsm_ns imm_b
mret_dec mret_dec data_sign_ext_id mult_int_en deassert_we imm_i_type data_sign_ext_id mult_int_en wdata_offset deassert_we imm_i_typeimm_i_type data_we_q wdata_offset data_we_q csr_access csr_access
compressed_decoder_i alu_operand_a NNS data_addr_int rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n S compressed_decoder_i alu_operand_a NS
imm_vu_type imm_vu_type imm_vu_type
regb_used_dec load_store_unit_i load_store_unit_i regb_used_dec operand_b operand_b
scalar_replication scalar_replication ecall_insn_dec ecall_insn_dec mult_dot_en mult_dot_en
operand_c operand_c is_subrot hwloop_start_int is_subrot hwloop_start_int
alu_operator if_stage_i if_stage_i alu_operator mult_signed_mode mult_signed_mode
jump_target jump_targetjump_target
operand_b_fw_mux_sel operand_b_fw_mux_sel
regc_used_dec load_stall regc_used_dec operand_c_fw_id load_stall operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel operand_b_fw_id hwloop_target_mux_sel hwloop_target hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i pipe_flush_dec hwloop_target pipe_flush_dec
alu_en alu_en regfile_alu_waddr_id regfile_alu_waddr_idregfile_alu_waddr_id
MODE_rule is_clpx regfile_addr_rc_id MODE_rule is_clpx regfile_addr_rc_id mret_insn_dec mret_insn_dec mask_addr mask_addr
regfile_alu_we_id regfile_alu_we_id alu_en alu_operator alu_op_a_mux_sel alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel imm_b_mux_sel jump_target_mux_sel mult_operator mult_int_en mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_alu_waddr_mux _sel data_we_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_cnt_mux_sel hwloop_valid csr_access csr_status prepost_useincr operand_a_fw_mux_se operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux bmask_b_mux alu_bmask_a_mux_se alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm bmask_b_id_imm alu_vec_mode scalar_replication reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec operand_b_vec regfile_alu_we_id operand_b_vec R_rule R_rule
dret_insn_dec data_err_state_q dret_insn_dec data_err_state_q
alu_op_c_mux_sel mult_sel_subword alu_op_c_mux_sel mult_sel_subword
bmask_a_id_imm bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall reg_d_alu_is_reg_a_id jr_stall reg_d_ex_is_reg_b_id dret_dec reg_d_ex_is_reg_b_id dret_dec illegal_insn_dec illegal_insn_dec
data_req_id data_err_state_n data_req_id alu_bmask_a_mux_sel data_err_state_n alu_bmask_a_mux_sel
hwloop_mask hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id regfile_we_id reg_d_ex_is_reg_c_id
stop_addr stop_addr start_addr start_addr prepost_useincr prepost_useincr
data_load_event_id regfile_alu_waddr_mux_sel data_load_event_id regfile_alu_waddr_mux_sel
fetch_valid hwloop_valid fetch_valid hwloop_valid halt_id halt_id
exc_ack exc_ack
CS hwlp_start_q CS instr_match_region CS hwlp_start_q alu_bmask_b_mux_sel instr_match_region alu_bmask_b_mux_sel
use_hwlp regc_mux use_hwlp regc_mux hwlp_end_q next_valid hwlp_end_q next_valid
data_match_region data_match_region
W_rule hwloop_cnt_mux_sel W_rule hwloop_cnt_mux_sel rdata_unaligned rdata_unaligned
hwlp_counter_n CS imm_a_mux_sel hwlp_counter_n imm_a_mux_sel do_fetch jump_in_id do_fetch int_controller_i jump_in_idjump_in_id int_controller_i
addr_n addr_n addr_int addr_real_next rdata_last_q rdata rdata_unaligned L0_buffer_i CS NS hwloop_regs_i addr_n hwloop_regs_i next_is_crossword pmp_unit_i next_is_crossword pmp_unit_i rdata rdata
EN_rule exc_ctrl_cs X_rule EN_rule exc_ctrl_cs X_rule
mult_dot_en mult_dot_en csr_op csr_op mult_int_en mult_dot_en controller_i ctrl_fsm_cs ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i regfile_we_lsu regfile_waddr_lsu alu_result mult_result alu_i div_shift div_valid adder_op_b_negate shift_left shift_use_round shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int csr_op addr_real_next addr_real_next irq_id_q irq_id_q decoder_i regfile_mem_we regfile_alu_we data_req hwloop_we csr_illegal
hwlp_counter_q hwlp_counter_q
do_hwlp do_hwlp
valid valid addr_int addr_int irq_sec_q rdata_last_q irq_sec_q rdata_last_q
regfile_alu_we regfile_alu_we
hwloop_we
NNS do_fetch do_hwlp do_hwlp_int use_last save_rdata_last use_hwlp save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid addr_q addr_n addr_int addr_real_next rdata_last_q rdata rdata_unaligned L0_buffer_i S NS do_fetch do_hwlp do_hwlp_int use_last save_rdata_last use_hwlp save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid hwloop_we NS
use_last use_last data_req data_req regfile_mem_we regfile_mem_we addr_q addr_qaddr_q
hwlp_is_crossword hwlp_is_crossword
csr_illegal csr_illegal save_rdata_last busy_L0 save_rdata_last L0_buffer_i L0_buffer_i busy_L0
mult_int_en mult_int_en
do_hwlp_int do_hwlp_int
is_hwlp_q is_hwlp_q CS CS
addr_q addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec ebrk_insn mret_insn_dec uret_insn_dec dret_insn_dec ecall_insn_dec pipe_flush_dec fencei_insn_dec rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id addr_q instr_addr_int decoder_i instr_addr_int save_rdata_hwlp decoder_i save_rdata_hwlp
is_crossword is_crossword
illegal_insn_n illegal_insn_n next_upper_compressed next_upper_compressed
is_hwlp_n CS is_hwlp_n L0_buffer L0_buffer ebrk_force_debug_mode L0_buffer ebrk_force_debug_mode
ctrl_fsm_ns ctrl_fsm_ns
jump_done_q jump_done_q
NNS L0_buffer addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec ebrk_insn mret_insn_dec uret_insn_dec dret_insn_dec ecall_insn_dec pipe_flush_dec fencei_insn_dec rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id regfile_alu_waddr_id regfile_alu_we_id alu_en alu_operator alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel imm_b_mux_sel jump_target_mux_sel mult_operator mult_int_en mult_sel_subword mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_alu_waddr_mux _sel data_we_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_start_mux_sel hwloop_cnt_mux_sel hwloop_valid csr_access csr_status prepost_useincr operand_a_fw_mux_se operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux bmask_b_mux alu_bmask_a_mux_se alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm bmask_b_id_imm alu_vec_mode scalar_replication reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec imm_i_type imm_vu_type imm_b jump_target regfile_data_ra_id hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i mem we_a_dec we_b_dec decoder_i regfile_mem_we regfile_alu_we data_req csr_illegal csr_op controller_i ctrl_fsm_cs ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i regfile_we_lsu regfile_waddr_lsu alu_result mult_result alu_i div_shift div_valid adder_op_b_negate shift_left shift_use_round shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int shift_op_a shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev adder_in_a adder_in_b adder_result_expanded alu_popcnt_i cnt_l1 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN State_SP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready mulh_CS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q rdata_offset_q data_sign_ext_q data_we_q wdata_offset S NS irq_enable_int irq_enable_int
ctrl_fsm_cs ctrl_fsm_cs
instr_valid_irq_flush_q instr_valid_irq_flush_q
branch_in_id branch_in_id
illegal_insn_q illegal_insn_q
jump_done jump_done instr_valid_irq_flush_n prefetch_buffer_i prefetch_buffer_i instr_valid_irq_flush_n
debug_mode_q debug_mode_q
debug_mode_n debug_mode_n
data_err_q controller_i controller_i data_err_q jump_in_dec jump_in_dec
Figure A.3.: (HP) Pipeline stall, ALU test Figure A.4.: (HL) Logic stall, ALU test
ResInv_SP ResInv_SP
cs_registers_i ResInv_SN div_i cs_registers_i ResInv_SN div_i is_pcmr is_pcmr
RemSel_SP RemSel_SP
Cnt_DP Cnt_DP
is_pcer is_pcer mcause_n ABComp_S mcause_n ABComp_S
LoadEn_S LoadEn_S RemSel_SN RemSel_SN
PCCR_q PCCR_q
BRegEn_S BRegEn_S PCER_n PCER_n
priv_lvl_n priv_lvl_n CompInv_SP CompInv_SP
ucause_q ucause_q
AddMux_D cnt_l1 AddMux_D cnt_l1
mtvec_n mtvec_n
State_SP State_SP
cnt_l3 cnt_l3 AReg_DN State_SN AReg_DN State_SN
ucause_n mscratch_n dscratch1_q ucause_n mscratch_n dscratch1_q
exception_pc exception_pc
OutMux_D OutMux_D
dscratch1_n dscratch1_n
alu_i cnt_l2 alu_i cnt_l2
Cnt_DN ResRegEn_S index_lut Cnt_DN ResRegEn_S index_lut
PCCR_n PCCR_n
index_nodes index_nodes
ResReg_DP ResReg_DP alu_popcnt_i cnt_l1 cnt_l2 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN State_SP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready mulh_CS mulh_NS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q rdata_offset_q data_sign_ext_q data_we_q wdata_offset CS NS data_addr_int rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q id_valid_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_q uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr ResReg_DN ResReg_DN shift_arithmetic shift_arithmetic
PCCR_inc alu_popcnt_i PCCR_inc alu_popcnt_i
mepc_q mepc_q
ResReg_DP_rev ResReg_DP_rev shuffle_reg0_sel shuffle_reg0_sel
is_pccr is_pccr cnt_l4 cnt_l4
pccr_all_sel pccr_all_sel sel_nodes sel_nodes
ARegEn_S ARegEn_S AReg_DP AReg_DP f_is_nan alu_ff_i f_is_nan alu_ff_i pmp_reg_n pmp_reg_n
AddTmp_D cmp_result AddTmp_D cmp_result
ff_input ff_input BReg_DP BReg_DP pmp_reg_q pmp_reg_q dcsr_n dcsr_n div_ready div_ready
radix_2_rev radix_2_rev
div_shift div_shift BReg_DN BReg_DN PCMR_n PCMR_n cnt_result cnt_result
mepc_n mepc_n CompInv_SN CompInv_SN
mstatus_n mstatus_n shuffle_r1_in is_greater shuffle_r1_in is_greater
operand_a_rev adder_op_b_negate operand_a_rev adder_op_b_negate adder_result_expanded adder_result_expandedadder_result_expanded
pmpcfg_we pmpcfg_we
shift_use_round shift_use_round
pmpaddr_we pmpaddr_we operand_a_neg_rev operand_a_neg_rev shift_amt_int shift_amt_int dscratch0_n dscratch0_n csr_wdata_int csr_wdata_int
PCER_q PCER_q shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev shift_result shift_result utvec_n utvec_n csr_we_int csr_we_int
pack_result pack_result
perf_rdata perf_rdata cmp_signed cmp_signed
adder_in_a adder_in_aadder_in_a is_equal is_equal
dscratch0_q utvec_q dscratch0_q utvec_q shuffle_r0_in shuffle_r0_in
uepc_q uepc_q
shift_amt shift_amt mscratch_q priv_lvl_q mscratch_q priv_lvl_q shuffle_through shuffle_through
shift_left_result shift_left_result
csr_rdata_int csr_rdata_int div_valid div_valid shift_op_a shift_op_ashift_op_a
mtvec_q mtvec_q
mstatus_q mstatus_q depc_q depc_q dcsr_q dcsr_q shuffle_result div_op_a_signed shuffle_result div_op_a_signed bmask bmask
shuffle_r1 shuffle_r1
depc_n depc_n
bextins_result bextins_result
PCCR_inc_q sel_minmax PCCR_inc_q sel_minmax
shuffle_r0 shuffle_r0
id_valid_valid_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_q uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr id_q is_equal_clip id_valid_q is_equal_clip adder_op_a adder_op_a
PCMR_q PCMR_q shuffle_byte_sel shuffle_byte_sel mcause_q result_minmax mcause_q result_minmax
uepc_n uepc_n
pccr_index pccr_index radix_4_rev radix_4_rev
shift_amt_left shift_amt_left
radix_8_rev radix_8_rev PCCR_in PCCR_in priv_lvl_q is_equal_vec is_equal_vec adder_result adder_result adder_op_b adder_op_b shift_left shift_left
adder_in_b adder_in_badder_in_b
is_greater_vec is_greater_vec minmax_b minmax_b shuffle_reg_sel shuffle_reg_sel shift_right_result shift_right_result
shuffle_reg1_sel shuffle_reg1_sel
bitop_result bitop_result f_is_greater mult_i f_is_greater mult_i
short_subword short_subword ex_stage_i mulh_clearcarry ex_stage_i mulh_clearcarry riscv_core_i mulh_signed riscv_core_i mulh_signed data_load_event_ex data_load_event_ex
mulh_mulh_NS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q rdata_offset_q data_sign_ext_q data_we_q wdata_offset NS mulh_NS dot_short_op_b dot_short_op_b
mulh_ready mulh_ready id_valid id_valid
csr_access_ex regfile_waddr_lsu csr_access_ex regfile_waddr_lsu mult_result mult_result
mulh_active mulh_active
mult_clpx_img_ex dot_char_mul mult_clpx_img_ex dot_char_mul csr_save_ex csr_save_ex top data_req_ex top data_req_ex csr_save_id short_op_b csr_save_id short_op_b regfile_we_lsu dot_short_result regfile_we_lsu dot_short_result
dot_char_op_b dot_char_op_b mult_sel_subword_ex dot_char_op_a mult_sel_subword_ex dot_char_op_a csr_restore_mret_id csr_restore_mret_id irq_sec_i irq_sec_i data_req_pmp data_req_pmp
mulh_save mulh_save alu_result alu_result
regfile_alu_we_fw regfile_alu_we_fw
data_gnt_pmp data_gnt_pmp u_irq_enable u_irq_enable pc_set pc_set short_mac short_mac instr_req_o data_gnt_i instr_req_o data_gnt_i
regfile_we_wb regfile_we_wb clpx_shift_result dot_short_op_a clpx_shift_result dot_short_op_a
illegal_c_insn_id illegal_c_insn_id
mulh_shift_arith mulh_shift_arith clk_i m_irq_enable clk_i m_irq_enable
data_type_ex data_type_ex is_compressed_id is_compressed_id
irq_id_o irq_id_o
csr_hwlp_we csr_hwlp_we exc_pc_mux_id exc_pc_mux_id data_sign_ext_ex data_sign_ext_ex
instr_req_int instr_req_int
useincr_addr_ex useincr_addr_ex
sec_lvl_o sec_lvl_o
short_result dot_short_mul short_result dot_short_mul ex_ready ex_ready data_rvalid_i data_rvalid_i data_we_o data_we_o mulh_imm short_signed mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rdata_i csr_irq_sec instr_rvalid_i instr_rvalid_i
csr_save_if csr_save_if mulh_carry_q mulh_carry_q mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 CS NS do_fetch do_hwlp do_hwlp_int use_last save_rdata_last use_hwlp save_rdata_hwlp hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n data_misaligned_ex mult_operand_a_ex data_misaligned_ex mult_operand_a_ex mult_signed_mode_ex bmask_a_ex mult_signed_mode_ex bmask_a_ex data_be_o branch_in_ex data_be_o branch_in_ex csr_restore_uret_idcsr_restore_uret_id instr_rdata_id csr_restore_uret_id instr_rdata_idinstr_rdata_id
irq_id_i short_op_a irq_id_i short_op_a
bmask_b_ex mulh_subword bmask_b_ex mulh_subword core_ctrl_firstfetch mulh_CSmulh_CS core_ctrl_firstfetch mulh_CS clk_en clk_en rstn_i rstn_i data_rdata_i instr_gnt_i data_rdata_i instr_gnt_i top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id instr_valid_id is_compressed_id is_fetch_failed_id illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux is_decoding data_misaligned mult_multicycle branch_in_ex ctrl_busy alu_en_ex alu_operator_ex bmask_a_ex bmask_b_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex mult_en_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex apu_en_ex apu_lat_ex regfile_waddr_ex regfile_we_ex regfile_we_wb regfile_alu_waddr_ex regfile_alu_we_ex regfile_alu_we_fw csr_access_ex csr_op_ex data_we_ex data_type_ex data_sign_ext_ex data_reg_offset_ex data_req_ex data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb instr_req_int m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id regfile_alu_we_ex top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id instr_valid_id is_compressed_id is_fetch_failed_id illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux is_decoding data_misaligned mult_multicycle branch_in_ex ctrl_busy alu_en_ex alu_operator_ex bmask_a_ex bmask_b_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex mult_en_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex apu_en_ex apu_lat_ex regfile_waddr_ex regfile_we_ex regfile_we_wb regfile_alu_waddr_ex regfile_alu_we_ex regfile_alu_we_fw csr_access_ex csr_op_ex data_we_ex data_type_ex data_sign_ext_ex data_reg_offset_ex data_req_ex data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb instr_req_int m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int regfile_alu_we_ex mult_clpx_shift_ex mult_clpx_shift_ex
alu_clpx_shift_ex alu_clpx_shift_ex mult_dot_op_c_ex mult_dot_op_c_ex
debug_csr_save debug_csr_save
core_clock_gate_i regfile_alu_wdata_fw core_clock_gate_i regfile_alu_wdata_fw data_addr_o data_addr_o
alu_operand_b_ex alu_operand_b_exalu_operand_b_ex
short_shift_arith short_shift_arith alu_operand_a_ex alu_operand_a_exalu_operand_a_ex
data_req_o data_req_o
mult_dot_signed_ex mult_dot_signed_ex
clear_instr_valid apu_en_ex clear_instr_valid apu_en_ex debug_req_i debug_req_i csr_addr_int csr_addr_int instr_addr_o alu_is_subrot_ex instr_addr_o alu_is_subrot_ex
data_wdata_o data_wdata_o csr_cause csr_cause perf_pipeline_stall perf_pipeline_stall
csr_rdata csr_rdata pc_ex pc_pc_ex ex irq_ack_o irq_ack_o
pc_id pc_idpc_id
regfile_alu_waddr_ex regfile_alu_waddr_ex
id_ready id_ready core_busy_o data_reg_offset_ex core_busy_o data_reg_offset_ex
irq_i is_hwlp_id trap_addr_mux irq_i is_hwlp_id trap_addr_mux
lsu_rdata lsu_rdata
fetch_enable_i alu_operand_c_ex fetch_enable_i alu_operand_c_exalu_operand_c_ex
mult_dot_op_b_ex mult_dot_op_b_ex imm_vec_ext_ex imm_vec_ext_ex instr_valid_id instr_valid_id
mult_imm_ex mult_imm_ex
lsu_ready_wb mult_dot_op_a_ex lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp core_busy_q data_err_pmp
ctrl_busy mem ctrl_busy mem mult_operand_c_ex mult_operand_c_ex
mult_operand_b_ex mult_operand_b_ex
exc_cause exc_cause pc_mux_id alu_vec_mode_ex riscv_register_file_i pc_mux_id alu_vec_mode_ex riscv_register_file_i
is_decoding is_decoding
data_err_ack data_err_ack alu_operator_ex alu_operator_ex
is_fetch_failed_id is_fetch_failed_id data_misaligned data_misaligned
debug_cause debug_cause
regfile_waddr_ex regfile_waddr_ex data_we_id data_we_id hwlp_dec_cnt_id hwlp_dec_cnt_id csr_op_ex csr_op_ex
if_valid if_valid halt_if halt_if
csr_hwlp_regid csr_hwlp_regid mult_operator_ex mult_operator_ex
rega_used_dec rega_used_dec
csr_status csr_status
offset_fsm_cs hwlp_dec_cnt regfile_we_ex ebrk_insn offset_fsm_cs hwlp_dec_cnt regfile_we_ex ebrk_insn
alu_is_clpx_ex alu_is_clpx_ex
apu_lat_ex apu_lat_ex lsu_ready_ex fencei_insn_dec we_a_dec lsu_ready_ex fencei_insn_dec memwe_a_dec mult_multicycle mult_multicycle valid we_b_dec valid we_a_dec we_b_dec j csr_save_cause j csr_save_cause we_b_dec hwloop_regid hwloop_regid
ex_valid ex_valid
mult_is_clpx_ex mult_is_clpx_ex reg_d_wb_is_reg_a_id reg_d_wb_is_reg_a_id hwloop_we hwloop_we
hwloop_start_mux_sel hwloop_start_mux_sel fetch_addr_n fetch_addr_n mult_dot_signed mult_dot_signed csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int instr_rdata_id pc_id pc_ex alu_operand_a_ex alu_operand_b_ex alu_operand_c_ex mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 hwloop_controller_i hwlp_target csr_restore_dret_id hwloop_controller_i hwlp_target csr_restore_dret_id rdata_offset_q rdata_offset_q fetch_ready fetch_ready clk clk
data_we_ex data_we_ex
data_type_id data_type_id operand_a_fw_mux_sel registers_i operand_a_fw_mux_sel registers_i
instr_req_pmp instr_req_pmp alu_en_ex alu_en_ex
data_rdata_ext data_rdata_ext fetch_rdata fetch_rdata exc_kill alu_op_a_mux_sel exc_kill alu_op_a_mux_sel
mult_en_ex bmask_b_mux mult_en_ex bmask_b_mux
pc_is_end_addr uret_insn_dec pc_is_end_addr uret_insn_dec
fetch_is_hwlp fetch_is_hwlp hwloop_cnt_int hwloop_cnt_int
mult_operator mult_operator
CS instr_gnt_pmp CS instr_gnt_pmp instr_decompressed rdata_q instr_decompressed rdata_q mult_imm_mux mult_imm_mux
data_addr_int bmask_b_id_imm data_addr_int bmask_b_id_imm
hwlp_dec_cnt_if operand_c_fw_mux_sel hwlp_dec_cnt_if operand_c_fw_mux_sel
uret_dec uret_dec hwloop_we_masked hwloop_we_masked
exc_pc exc_pc alu_op_b_mux_sel alu_op_b_mux_sel
trap_base_addr trap_base_addr
reg_d_ex_is_reg_a_id regfile_data_ra_id hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i reg_d_ex_is_reg_a_id regfile_data_ra_id regfile_data_ra_id
is_hwlp_id_q data_sign_ext_q is_hwlp_id_q operand_a_fw_id data_sign_ext_q operand_a_fw_id
bmask_a_mux bmask_a_mux illegal_c_insn illegal_c_insn alu_vec_mode alu_vec_mode
hwloop_cnt branch_taken_ex hwloop_cnt branch_taken_ex rdata_b_ext jump_target_mux_sel rdata_b_ext jump_target_mux_sel CS data_type_q id_stage_i data_type_q id_stage_i jump_in_id jump_in_id branch_req branch_req
rdata_h_ext rdata_h_ext fetch_valid fetch_valid
imm_b_mux_sel imm_b_mux_sel
alu_operand_b alu_operand_b
offset_fsm_ns imm_b offset_fsm_ns imm_bimm_b
mret_dec mret_dec data_sign_ext_id mult_int_en data_sign_ext_id mult_int_en deassert_we imm_i_type deassert_we imm_i_typeimm_i_type wdata_offset wdata_offset data_we_q data_we_q csr_access csr_access
compressed_decoder_i alu_operand_a compressed_decoder_i alu_operand_a NSNS data_addr_int rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n NS
imm_vu_type imm_vimm_vu_type u_type
load_store_unit_i regb_used_dec load_store_unit_i regb_used_dec operand_b operand_b
scalar_replication scalar_replication ecall_insn_dec ecall_insn_dec mult_dot_en mult_dot_en
operand_c operand_c is_subrot is_subrot hwloop_start_int hwloop_start_int if_stage_i alu_operator if_stage_i alu_operator mult_signed_mode mult_signed_mode
jump_target jump_targetjump_target
operand_b_fw_mux_sel operand_b_fw_mux_sel
regc_used_dec load_stall regc_used_dec load_stall operand_c_fw_id operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel operand_b_fw_id hwloop_target_mux_sel hwloop_target hwloop_target pipe_flush_dec pipe_flush_dec
alu_en alu_en
regfile_alu_waddr_id regfile_alu_waddr_id
MODE_rule is_clpx regfile_addr_rc_id MODE_rule is_clpx regfile_addr_rc_id mret_insn_dec mret_insn_dec mask_addr mask_addr
regfile_alu_we_id regfile_alu_we_id operand_b_vec operand_b_vec R_rule R_rule
dret_insn_dec dret_insn_dec data_err_state_q data_err_state_q
alu_op_c_mux_sel alu_op_c_mux_sel mult_sel_subword mult_sel_subword
bmask_a_id_imm bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall reg_d_alu_is_reg_a_id jr_stall
reg_d_ex_is_reg_b_id reg_d_ex_is_reg_b_id dret_dec dret_dec
illegal_insn_dec illegal_insn_dec
data_req_id data_req_id data_err_state_n data_err_state_n alu_bmask_a_mux_sel alu_bmask_a_mux_sel
hwloop_mask hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id regfile_we_id reg_d_ex_is_reg_c_id
stop_addr stop_addr start_addr start_addr prepost_useincr prepost_useincr
data_load_event_id data_load_event_id regfile_alu_waddr_mux_sel regfile_alu_waddr_mux_sel
fetch_valid hwloop_valid fetch_valid hwloop_valid
halt_id halt_id
exc_ack exc_ack
CS hwlp_start_q CS hwlp_start_q instr_match_region instr_match_region alu_bmask_b_mux_sel alu_bmask_b_mux_sel
use_hwlp use_hwlp regc_mux regc_mux hwlp_end_q hwlp_end_q next_valid next_valid
data_match_region data_match_region
W_rule W_rule hwloop_cnt_mux_sel hwloop_cnt_mux_sel rdata_unaligned rdata_unaligned
hwlp_counter_n hwlp_counter_n CS imm_a_mux_sel imm_a_mux_sel do_fetch do_fetch jump_in_id int_controller_i jump_in_id int_controller_i addr_n hwloop_regs_i addaddr_n addr_int addr_real_next rdata_last_q rdata rdata_unaligned L0_buffer_i CS NS r_n hwloop_regs_i next_is_crossword pmp_unit_i next_is_crossword pmp_unit_i
rdata rdata
EN_rule exc_ctrl_cs EN_rule exc_ctrl_cs X_rule X_rule
mult_dot_en mult_dot_en csr_op csr_op
addr_real_next addr_real_next
irq_id_q irq_id_q decoder_i
hwlp_counter_q hwlp_counter_q
do_hwlp do_hwlp
valid valid
addr_int addr_int irq_sec_q irq_sec_q rdata_last_q rdata_last_q
regfile_alu_we regfile_regfile_alu_we data_req hwloop_we csr_illegal jump_in_id csr_op mult_int_en mult_dot_en controller_i ctrl_fsm_cs ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i regfile_we_lsu regfile_waddr_lsu alu_result mult_result alu_i div_shift div_valid adder_op_b_negate shift_left shift_use_round shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int alu_we
hwloop_we hwloop_we NSNS do_fetch do_hwlp do_hwlp_int use_last save_rdata_last use_hwlp save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid addr_q addr_n addr_int addr_real_next rdata_last_q rdata rdata_unaligned L0_buffer_i NS
use_last use_last
data_req data_req
regfile_mem_we regfile_mem_weregfile_mem_we addr_q addr_qaddr_q
hwlp_is_crossword hwlp_is_crossword
csr_illegal csr_illegal save_rdata_last save_rdata_last L0_buffer_i busy_L0 L0_buffer_i busy_L0
mult_int_en mult_int_en
do_hwlp_int do_hwlp_int
is_hwlp_q is_hwlp_q
CS CS
addr_q addaddr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec ebrk_insn mret_insn_dec uret_insn_dec dret_insn_dec ecall_insn_dec pipe_flush_dec fencei_insn_dec rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id regfile_alu_waddr_id regfile_alu_we_id alu_en alu_operator alu_op_a_mux_sel alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel imm_b_mux_sel jump_target_mux_sel mult_operator mult_int_en mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_alu_waddr_mux _sel data_we_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_cnt_mux_sel hwloop_valid csr_access csr_status prepost_useincr operand_a_fw_mux_se operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux bmask_b_mux alu_bmask_a_mux_se alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm bmask_b_id_imm alu_vec_mode scalar_replication reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec r_q instr_addr_int decoder_i instr_addr_int decoder_i save_rdata_hwlp save_rdata_hwlp
is_crossword is_crossword
illegal_insn_n illegal_insn_n
next_upper_compressed next_upper_compressed CSis_hwlp_n is_hwlp_n L0_buffer L0_bufferL0_buffer ebrk_force_debug_mode ebrk_force_debug_mode
ctrl_fsm_ns ctrl_fsm_ns
jump_done_q jump_done_q
NSNS L0_buffer addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec ebrk_insn mret_insn_dec uret_insn_dec dret_insn_dec ecall_insn_dec pipe_flush_dec fencei_insn_dec rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id regfile_alu_waddr_id regfile_alu_we_id alu_en alu_operator alu_op_a_mux_sel alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel imm_b_mux_sel jump_target_mux_sel mult_operator mult_int_en mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_alu_waddr_mux _sel data_we_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_cnt_mux_sel hwloop_valid csr_access csr_status prepost_useincr operand_a_fw_mux_se operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux bmask_b_mux alu_bmask_a_mux_se alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm bmask_b_id_imm alu_vec_mode scalar_replication reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec imm_i_type imm_vu_type imm_b jump_target regfile_data_ra_id hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i mem we_a_dec we_b_dec decoder_i regfile_mem_we regfile_alu_we data_req csr_illegal csr_op controller_i ctrl_fsm_cs ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i regfile_we_lsu regfile_waddr_lsu alu_result mult_result alu_i div_shift div_valid adder_op_b_negate shift_left shift_use_round shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int shift_op_a shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev adder_in_a adder_in_b adder_result_expanded alu_popcnt_i cnt_l1 cnt_l2 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN State_SP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready NS
irq_enable_int irq_enable_int
ctrl_fsm_cs ctrl_fsm_cs
instr_valid_irq_flush_q instr_valid_irq_flush_q
branch_in_id branch_in_id
illegal_insn_q illegal_insn_q
jump_done jump_done prefetch_buffer_i instr_valid_irq_flush_n prefetch_buffer_i instr_valid_irq_flush_n
debug_mode_q debug_mode_q
debug_mode_n debug_mode_n
controller_i data_err_q controller_i data_err_q jump_in_dec jump_in_dec
Figure A.5.: (HP) Pipeline stall, MUL test Figure A.6.: (HL) Logic stall, MUL test
ResInv_SP ResInv_SP
cs_registers_i ResInv_SN div_i ResInv_SN div_i is_pcmr cs_registers_i is_pcmr
RemSel_SP RemSel_SP
Cnt_DP Cnt_DP
mcause_n is_pcer is_pcer ABComp_S mcause_n ABComp_S
LoadEn_S LoadEn_S RemSel_SN RemSel_SN
PCCR_q PCCR_q
BRegEn_S BRegEn_S PCER_n PCER_n
priv_lvl_n priv_lvl_n CompInv_SP CompInv_SP
ucause_q ucause_q
AddMux_D cnt_l1 AddMux_D cnt_l1
mtvec_n mtvec_n
State_SP State_SP
cnt_l3 cnt_l3 AReg_DN State_SN AReg_DN State_SN
dscratch1_q ucause_n mscratch_n ucause_n mscratch_n dscratch1_q
exception_pc exception_pc
OutMux_D OutMux_D
dscratch1_n dscratch1_n
alu_i cnt_l2 alu_i cnt_l2
Cnt_DN ResRegEn_S index_lut Cnt_DN ResRegEn_S index_lut
PCCR_n PCCR_n
index_nodes index_nodes
ResReg_DP ResReg_DP alu_popcnt_i cnt_l1 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN State_SP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready ResReg_DN ResReg_DN shift_arithmetic shift_arithmetic
PCCR_inc alu_popcnt_i PCCR_inc alu_popcnt_i
mepc_q mepc_q
ResReg_DP_rev ResReg_DP_rev shuffle_reg0_sel shuffle_reg0_sel
is_pccr is_pccr cnt_l4 cnt_l4
pccr_all_sel pccr_all_sel sel_nodes sel_nodes
ARegEn_S ARegEn_S AReg_DP AReg_DP f_is_nan alu_ff_i f_is_nan alu_ff_i pmp_reg_n pmp_reg_n cmp_result AddTmp_D AddTmp_D cmp_result
ff_input ff_input BReg_DP BReg_DP pmp_reg_q pmp_reg_q dcsr_n dcsr_n div_ready div_ready
radix_2_rev radix_2_rev
div_shift div_shift BReg_DN BReg_DN PCMR_n PCMR_n cnt_result cnt_result
mepc_n mepc_n CompInv_SN CompInv_SN
mstatus_n is_greater mstatus_n shuffle_r1_in shuffle_r1_in is_greater
operand_a_rev adder_op_b_negate operand_a_rev adder_op_adder_op_b_negate shift_left shift_use_round shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int b_negate adder_result_expanded adder_result_expanded pmpcfg_we pmpcfg_we adder_result_expanded
shift_use_round shift_use_round
pmpaddr_we pmpaddr_we operand_a_neg_rev operand_a_neg_rev shift_amt_int shift_amt_int dscratch0_n dscratch0_n csr_wdata_int csr_wdata_int
PCER_q PCER_q shift_result shift_shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev result utvec_n utvec_n csr_we_int csr_we_int
pack_result pack_result
perf_rdata perf_rdata cmp_signed cmp_signed
adder_in_a adder_in_a is_equal is_equal
dscratch0_q utvec_q dscratch0_q utvec_q adder_in_a shuffle_r0_in shuffle_r0_in
uepc_q uepc_q
shift_amt shift_amt mscratch_q priv_lvl_q mscratch_q priv_lvl_q shuffle_through shuffle_through
shift_left_result shift_left_result
csr_rdata_int csr_rdata_int div_valid div_validdiv_valid shift_op_a shift_op_ashift_op_a
mtvec_q mtvec_q
mstatus_q mstatus_q depc_q depc_q dcsr_q dcsr_q shuffle_result div_op_a_signed shuffle_result div_op_a_signed bmask bmask
shuffle_r1 shuffle_r1
depc_n depc_n
bextins_result bextins_result
PCCR_inc_q sel_minmax PCCR_inc_q sel_minmax
shuffle_r0 shuffle_r0
id_valid_valid_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_q uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr id_q is_equal_clip id_valid_q is_equal_clip adder_op_a adder_op_a
PCMR_q PCMR_q shuffle_byte_sel shuffle_byte_sel mcause_q result_minmax mcause_q result_minmax
uepc_n uepc_n
pccr_index pccr_index radix_4_rev radix_4_rev
shift_amt_left shift_amt_left
radix_8_rev radix_8_rev PCCR_in PCCR_in
is_equal_vec is_equal_vec priv_lvl_q adder_result adder_result adder_op_b adder_op_b shift_left shift_left
adder_in_b adder_in_b
is_greater_vec is_greater_vec adder_in_b minmax_b minmax_b shuffle_reg_sel shuffle_reg_sel shift_right_result shift_right_result
shuffle_reg1_sel shuffle_reg1_sel
bitop_result bitop_result f_is_greater mult_i f_is_greater mult_i
short_subword short_subword ex_stage_i mulh_clearcarry ex_stage_i mulh_clearcarry riscv_core_i mulh_signed mulh_signed data_load_event_ex riscv_core_i data_load_event_ex
mulh_NS mulh_NS dot_short_op_b dot_short_op_b
mulh_ready mulh_ready id_valid id_valid
csr_access_ex regfile_waddr_lsu csr_access_ex regfile_waddr_lsuregfile_waddr_lsu mult_result mult_result
mulh_active mulh_active
mult_clpx_img_ex dot_char_mul mult_clpx_img_ex dot_char_mul csr_save_ex csr_save_ex top data_req_ex top data_rdata_req_ex data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb instr_req_int m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int eq_ex csr_save_id short_op_b csr_save_id short_op_b regfile_we_lsu dot_short_result regfile_we_lsuregfile_we_lsu dot_short_result
dot_char_op_b dot_char_op_b mult_sel_subword_ex dot_char_op_a mult_sel_subword_ex dot_char_op_a csr_restore_mret_id csr_restore_mret_id irq_sec_i irq_sec_i data_req_pmp data_req_pmp
mulh_save mulh_save
alu_result alu_ralu_result mult_result alu_i div_shift esult
regfile_alu_we_fw regfile_alu_we_fw
data_gnt_pmp data_gnt_pmp u_irq_enable u_irq_enable pc_set pc_set short_mac short_mac instr_req_o data_gnt_i instr_req_o data_gnt_i
regfile_we_wb regfile_we_wb clpx_shift_result dot_short_op_a regfile_we_wb clpx_shiclpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q ft_result dot_short_op_a
illegal_c_insn_id illegal_cillegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux _insn_id
clk_i mulh_shift_arith mulh_shift_arith m_irq_enable clk_i m_irq_enable
data_type_ex data_type_ex is_compressed_id is_compris_compressed_id essed_id data_type_ex
irq_id_o irq_id_o
csr_hwlp_we csr_hwlp_we exc_pc_mux_id exc_pc_mux_id data_sign_ext_ex data_signdata_sign_ext_ex _ext_ex
instr_req_int instr_req_int
useincr_addr_ex useincr_addr_exuseincr_addr_ex
sec_lvl_o sec_lvl_o
short_result dot_short_mul short_result dot_short_mul ex_ready ex_ready data_rvalid_i data_rvalid_i data_we_o data_we_o mulh_imm short_signed mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rdata_i csr_irq_sec instr_rvalid_i instr_rvalid_i
csr_save_if csr_save_if mulh_carry_q mulh_carry_q
data_misaligned_ex mult_operand_a_ex data_misaligned_ex mult_opermult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 and_a_ex
bmask_a_ex bmaskbmask_a_ex _a_ex mult_signed_mode_ex branch_in_ex mult_signed_mode_ex branch_in_ex ctrl_busy alu_en_ex data_be_o instr_rdata_id data_be_o branch_in_ex csr_restore_uret_id csr_restore_uret_id instr_rdata_idinstr_rdata_id
csr_restore_uret_id short_op_a irq_id_i irq_id_i short_op_a
bmask_b_ex mulh_subword bmask_b_exbmask_b_ex mulh_subword mulh_CS core_ctrl_firstfetch core_ctrl_firstfetch mulh_CSmulh_CS
clk_en clk_en rstn_i rstn_i data_rdata_i instr_gnt_i data_rdata_i instr_gnt_i top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id instr_valid_id is_compressed_id is_fetch_failed_id illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux is_decoding data_misaligned mult_multicycle branch_in_ex ctrl_busy alu_en_ex alu_operator_ex bmask_a_ex bmask_b_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex mult_en_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex apu_en_ex apu_lat_ex regfile_waddr_ex regfile_we_ex regfile_we_wb regfile_alu_waddr_ex regfile_alu_we_ex regfile_alu_we_fw csr_access_ex csr_op_ex data_we_ex data_type_ex data_sign_ext_ex data_reg_offset_ex data_req_ex data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb instr_req_int m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id regfile_alu_we_ex regfile_alregfile_alu_we_ex regfile_alu_we_fw csr_op_ex u_we_ex mult_clpx_shift_ex mult_clpx_shift_ex
alu_clpx_shift_ex alu_clpx_alu_clpx_shift_ex mult_operator_ex mult_en_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex apu_en_ex apu_lat_ex shift_ex mult_dot_op_c_ex mult_dot_op_c_ex
debug_csr_save debug_csr_save core_clock_gate_i regfile_alu_wdata_fw core_clock_gate_i regfile_alu_wdata_fw data_addr_o data_addr_o
alu_operand_b_ex alu_operand_b_ex
short_shift_arith short_shift_arith alu_operand_a_ex alu_operand_b_ex alu_operand_a_ex
data_req_o data_req_o mult_dot_signed_ex mult_dot_signed_ex alu_operand_a_ex
clear_instr_valid apu_en_ex clear_instr_valid apu_en_ex debug_req_i debug_req_i csr_addr_int csr_addr_int instr_addr_o alu_is_subrot_ex instr_addr_o alu_is_subrot_exalu_is_subrot_ex
data_wdata_o data_wdata_o csr_cause csr_cause perf_pipeline_stall perf_pipeline_stall
csr_rdata csr_rdata pc_ex pc_pc_ex ex irq_ack_o irq_ack_o
pc_id pc_idpc_id
regfile_alu_waddr_ex regfile_alu_waddr_exregfile_alu_waddr_ex
id_ready id_ready core_busy_o data_reg_offset_ex core_busy_o data_reg_offset_exdata_reg_offset_ex
trap_addr_mux irq_i is_hwlp_id irq_i is_hwlp_id trap_addr_mux
lsu_rdata lsu_rdata fetch_enable_i alu_operand_c_ex fetch_enable_i alu_operand_c_exalu_operand_c_ex
mult_dot_op_b_ex mult_dot_op_b_ex
imm_vec_ext_ex imm_vecimm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex _ext_ex instr_valid_id instr_valid_idinstr_valid_id
mult_imm_ex mult_imm_ex
lsu_ready_wb mult_dot_op_a_ex lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp core_busy_q data_err_pmp
ctrl_busy mem ctrl_busy mem mult_operand_c_ex mult_operand_c_ex
mult_operand_b_ex mult_operand_b_ex
pc_mux_id exc_cause exc_cause alu_vec_mode_ex riscv_register_file_i pc_mux_id alu_vec_mode_ex riscv_register_file_i
is_decoding is_decodingis_decoding
data_err_ack data_err_ack
alu_operator_ex alu_operator_exalu_operator_ex
is_fetch_failed_id is_fetch_failed_id
is_fetch_failed_id data_misaligned data_misaligned data_misaligned
debug_cause debug_cause
regfile_waddr_ex regfile_waddr_ex data_we_id regfile_waddr_ex data_we_id hwlp_dec_cnt_id hwlp_dec_cnt_id csr_op_ex csr_op_ex
if_valid if_valid halt_if halt_if
csr_hwlp_regid csr_hwlp_regid mult_operator_ex mult_operator_ex
rega_used_dec rega_used_dec
csr_status csr_status hwlp_dec_cnt hwlp_dec_cnt offset_fsm_cs regfile_we_ex ebrk_insn offset_fsm_cs regfile_we_exregfile_we_ex ebrk_insnebrk_insn
alu_is_clpx_ex alu_is_clpx_ex
apu_lat_ex apu_lat_ex
fencei_insn_dec we_a_dec fencei_insn_dec rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id lsu_ready_ex lsu_ready_ex fencei_insn_dec memwe_a_dec mult_multicycle mult_multicyclemult_multicycle valid we_b_dec valid we_b_dec
j csr_save_cause j csr_save_cause hwloop_regid hwloop_regid we_a_decwe_b_dec ex_valid ex_valid
mult_is_clpx_ex mult_is_clpx_ex reg_d_wb_is_reg_a_id reg_d_wb_is_reg_a_id hwloop_we hwloop_we
hwloop_start_mux_sel hwloop_start_mux_sel fetch_addr_n fetch_addr_n mult_dot_signed mult_dot_signed
hwloop_controller_i hwlp_target csr_restorecsr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int instr_rdata_id pc_id pc_ex alu_operand_a_ex alu_operand_b_ex alu_operand_c_ex mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 _dret_id hwloop_controller_i hwlp_target csr_restore_dret_id rdata_offset_q rdata_offset_qrdata_offset_q fetch_ready fetch_ready clk clk
data_we_ex data_we_exdata_we_ex data_type_id data_type_id operand_a_fw_mux_sel registers_i operand_a_fw_mux_seloperand_a_fw_mux_sel registers_i
instr_req_pmp instr_req_pmp alu_en_ex alu_en_ex
data_rdata_ext data_rdata_ext fetch_rdata exc_kill fetch_rdata exc_kill alu_op_a_mux_sel alu_op_a_mux_selalu_op_a_mux_sel
mult_en_ex bmask_b_mux mult_en_ex bmask_b_mux
pc_is_end_addr uret_insn_dec pc_is_end_addr uret_insn_decuret_insn_dec
fetch_is_hwlp fetch_is_hwlp hwloop_cnt_int hwloop_cnt_int
mult_operator mult_operator
CS instr_gnt_pmp CCS NS S instr_gnt_pmp
instr_decompressed rdata_q instr_decompressed rdatrdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr a_q mult_imm_mux mult_imm_mux
data_addr_int bmask_b_id_imm data_addr_intdata_addr_int bmask_b_id_immbmask_b_id_imm hwlp_dec_cnt_if operand_c_fw_mux_sel hwlp_dec_cnt_if operand_c_operand_c_fw_mux_se l bmask_a_mux bmask_b_mux alu_bmask_a_mux_se alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm fw_mux_sel
uret_dec uret_dec hwloop_we_masked hwloop_we_masked
exc_pc exc_pc
alu_op_b_mux_sel alu_op_b_alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel mux_sel
trap_base_addr trap_base_addr
reg_d_ex_is_reg_a_id reg_d_ex_ireg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx s_reg_a_id regfile_data_ra_id regfile_data_ra_idregfile_data_ra_id
is_hwlp_id_q data_sign_ext_q is_hwlp_id_q data_sign_ext_q data_we_q operand_a_fw_id data_sign_ext_q operand_a_fw_id
bmask_a_mux bmask_a_mux illegal_c_insn illegal_c_insn alu_vec_mode alu_vecalu_vec_mode _mode
hwloop_cnt hwloop_cnt jump_target_mux_sel branch_taken_ex jump_target_mux_sel mult_operator mult_int_en mult_sel_subword mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_alu_waddr_mux _sel data_we_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_start_mux_sel hwloop_cnt_mux_sel hwloop_valid csr_access csr_status branch_taken_ex rdata_b_ext rdata_b_ext jump_target_mux_sel data_type_q id_stage_i data_type_q id_stage_i
jump_in_id jump_in_id branch_req branch_req CS rdata_h_ext rdata_h_ext fetch_valid fetch_valid
imm_b_mux_sel imm_b_mux_selimm_b_mux_sel
alu_operand_b alu_operand_b
offset_fsm_ns imm_b offset_fsm_ns imm_b
mret_dec mret_mret_dec uret_dec dret_dec dec data_sign_ext_id mult_int_en data_sign_ext_id mult_int_en deassert_we imm_i_type deassert_we imm_i_type wdata_offset imm_b wdata_offset data_we_q data_we_q wdata_offset csr_access imm_i_type csr_access compressed_decoder_i alu_operand_a compressed_decoder_i alu_operand_a NSNS data_addr_int rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n NS
imm_vu_type imm_vimm_vu_type u_type
load_store_unit_i regb_used_dec load_store_unit_i regb_used_dec operand_b operand_b
scalar_replication scalar_replicationscalar_replication ecall_insn_dec ecall_insn_dececall_insn_dec mult_dot_en mult_dot_en
operand_c operand_c is_subrot is_subrotis_subrot hwloop_start_int hwloop_start_int if_stage_i alu_operator if_stage_i alu_operator mult_signed_mode mult_signed_mode
jump_target jump_targetjump_target
operand_b_fw_mux_sel operand_b_fw_mux_seloperand_b_fw_mux_sel
regc_used_dec load_stall regc_used_dec load_stall operand_c_fw_id operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel operand_b_fw_id hwloop_target_mux_sel
hwloop_target hwloophwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i _target pipe_flush_dec pipe_flush_decpipe_flush_dec
alu_en alu_en
regfile_alu_waddr_id regfile_alu_waddr_idregfile_alu_waddr_id
is_clpx MODE_rule regfile_addr_rc_id MODE_rule is_clpx regfile_addr_rc_id mret_insn_dec mret_insn_decmret_insn_dec mask_addr mask_addr
regfile_alu_we_id regfile_aregfile_alu_we_id alu_en alu_operator lu_we_id operand_b_vec operand_b_vec R_rule R_rule
dret_insn_dec dret_insn_decdret_insn_dec data_err_state_q data_err_state_q
alu_op_c_mux_sel alu_op_c_mux_sel mult_sel_subword mult_sel_subword
bmask_a_id_imm bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall reg_d_alu_is_reg_a_id jr_stall
reg_d_ex_is_reg_b_id reg_d_ex_is_reg_b_id dret_dec dret_dec
illegal_insn_dec illegal_insn_dec
data_req_id data_req_id data_err_state_n data_err_state_n alu_bmask_a_mux_sel alu_bmask_a_mux_sel
hwloop_mask hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id regfile_we_id reg_d_ex_is_reg_c_id
stop_addr stop_addr start_addr start_addr prepost_useincr prepost_useincrprepost_useincr
data_load_event_id data_load_event_id regfile_alu_waddr_mux_sel regfile_alu_waddr_mux_sel
fetch_valid hwloop_valid fetch_valid hwloop_valid
halt_id halt_id
exc_ack exc_ack
CS hwlp_start_q CSCS hwlp_start_q instr_match_region instr_match_region alu_bmask_b_mux_sel alu_bmask_b_mux_sel
use_hwlp use_hwlpuse_hwlp regc_mux regc_mux hwlp_end_q hwlp_end_q next_valid next_valid
data_match_region data_match_region
W_rule W_rule hwloop_cnt_mux_sel hwloop_cnt_mux_sel CSrdata_unaligned rdata_unaligned hwlp_counter_n hwlp_counter_n imm_a_mux_sel imm_a_mux_sel do_fetch do_fetch jump_in_id int_controller_i jump_in_idjump_in_id int_controller_i addr_n hwloop_regs_i addaddr_n addr_int addr_real_next r_n hwloop_regs_i next_is_crossword pmp_unit_i next_is_crossword pmp_unit_i
rdata rdardata rdata_unaligned L0_buffer_i CS NS ta
EN_rule exc_ctrl_cs EN_rule exc_ctrl_cs X_rule X_rule
mult_dot_en mult_dot_en
csr_op csr_csr_op mult_int_en mult_dot_en controller_i op
addr_real_next addr_real_next
irq_id_q irq_id_q decoder_i regfile_mem_we regfile_alu_we data_req hwloop_we csr_illegal
hwlp_counter_q hwlp_counter_q
do_hwlp do_hwlp
valid valid
addr_int addr_int irq_sec_q irq_sec_q rdata_last_q rdata_last_qrdata_last_q
regfile_alu_we regfile_alu_we
hwloop_we hwloop_we
NSNS do_fetch do_hwlp do_hwlp_int use_last save_rdata_last use_hwlp save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid addr_q addr_n addr_int addr_real_next rdata_last_q rdata rdata_unaligned L0_buffer_i NNS do_fetch do_hwlp S
use_last use_lastuse_last data_req data_req
regfile_mem_we regfile_mem_we
addr_q addr_q
hwlp_is_crossword hwlp_is_crossword
csr_illegal csr_illegal
save_rdata_last save_rdsave_rdata_last ata_last L0_buffer_i busy_L0 L0_buffer_i addr_q busy_L0
mult_int_en mult_int_en
do_hwlp_int do_hwlp_intdo_hwlp_int
is_hwlp_q is_hwlp_q
CS CS
addr_q addaddr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec r_q instr_addr_int instr_addr_int
decoder_i save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid decoder_i save_rdata_hwlp save_rdata_hwlp
is_crossword is_crossword
illegal_insn_n illegal_insn_n
next_upper_compressed next_upper_compressed CSis_hwlp_n is_hwlp_n L0_buffer L0_buffer ebrk_force_debug_mode ebrk_force_debug_mode ctrl_fsm_ns L0_buffer ctrl_fsctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i m_ns
jump_done_q jump_done_q
NSNS L0_buffer addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec ebrk_insn mret_insn_dec uret_insn_dec dret_insn_dec ecall_insn_dec pipe_flush_dec fencei_insn_dec rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id regfile_alu_waddr_id regfile_alu_we_id alu_en alu_operator alu_op_a_mux_sel alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel imm_b_mux_sel jump_target_mux_sel mult_operator mult_int_en mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_alu_waddr_mux _sel data_we_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_cnt_mux_sel hwloop_valid csr_access csr_status prepost_useincr operand_a_fw_mux_se operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux bmask_b_mux alu_bmask_a_mux_se alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm bmask_b_id_imm alu_vec_mode scalar_replication reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec imm_i_type imm_vu_type imm_b jump_target regfile_data_ra_id hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i mem we_a_dec we_b_dec decoder_i regfile_mem_we regfile_alu_we data_req csr_illegal csr_op controller_i ctrl_fsm_cs ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i regfile_we_lsu regfile_waddr_lsu alu_result mult_result alu_i div_shift div_valid adder_op_b_negate shift_left shift_use_round shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int shift_op_a shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev adder_in_a adder_in_b adder_result_expanded alu_popcnt_i cnt_l1 cnt_l2 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN State_SP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready mulh_CS mulh_NS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q rdata_offset_q data_sign_ext_q data_we_q wdata_offset NS
irq_enable_int irq_enable_int
ctrl_fsm_cs ctrl_fsm_csctrl_fsm_cs
instr_valid_irq_flush_q instr_valid_irq_flush_q
branch_in_id branch_in_id
illegal_insn_q illegal_insn_q
jump_done jump_done prefetch_buffer_i instr_valid_irq_flush_n prefetch_buffer_i instr_valid_irq_flush_n
debug_mode_q debug_mode_q
debug_mode_n debug_mode_n
controller_i data_err_q controller_i data_err_q jump_in_dec jump_in_dec
Figure A.7.: (HP) Pipeline stall, AES test Figure A.8.: (HL) Logic stall, AES test 79 A. Appendix
Fault Effect Causation - System Error Clusters
ResInv_SP ResInv_SP
ResInv_SN cs_registers_i div_i ResInv_SN is_pcmr cs_registers_i div_i is_pcmr
RemSel_SP RemSel_SP
Cnt_DP Cnt_DP is_pcer mcause_n ABComp_S is_pcer mcause_n ABComp_S
LoadEn_S RemSel_SN LoadEn_S RemSel_SN
PCCR_q PCCR_q
BRegEn_S PCER_n BRegEn_S PCER_n
priv_lvl_n CompInv_SP priv_lvl_n CompInv_SP
ucause_q ucause_q
AddMux_D cnt_l1 AddMux_D cnt_l1 mtvec_n mtvec_n State_SP State_SPState_SP
cnt_l3 cnt_l3 AReg_DN State_SN AReg_DN State_SN
ucause_n mscratch_n dscratch1_q ucause_n mscratch_n dscratch1_q
exception_pc exception_pc
OutMux_D OutMux_D
dscratch1_n dscratch1_n
alu_i cnt_l2 alu_i cnt_l2 Cnt_DN ResRegEn_S index_lut Cnt_DN ResRegEn_S index_lut PCCR_n PCCR_n index_nodes index_nodes
ResReg_DP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready ResReg_DP alu_popcnt_i cnt_l1 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN State_SP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready mulh_CS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q rdata_offset_q data_sign_ext_q data_we_q wdata_offset CS NS alu_popcnt_i cnt_l1 cnt_l2 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN ResReg_DN
shift_arithmetic ResReg_DN shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed shift_arithmetic
PCCR_inc alu_popcnt_i PCCR_inc alu_popcnt_i mepc_q mepc_q
ResReg_DP_rev ResReg_DP_rev shuffle_reg0_sel shuffle_reg0_sel
is_pccr cnt_l4 is_pccr cnt_l4
pccr_all_sel sel_nodes pccr_all_sel sel_nodes ARegEn_S ARegEn_S AReg_DP AReg_DP f_is_nan alu_ff_i f_is_nan alu_ff_i pmp_reg_n pmp_reg_n AddTmp_D cmp_result AddTmp_D cmp_result
ff_input BReg_DP ff_input BReg_DP pmp_reg_q pmp_reg_q dcsrdcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule _n div_ready dcsr_n div_ready
radix_2_rev radix_2_rev div_shift div_shift BReg_DN PCMR_n BReg_DN cnt_result PCMR_n cnt_result
mepc_n mepc_n CompInv_SN CompInv_SN
mstatus_n shuffle_r1_in is_greater mstatus_n shuffle_r1_in is_greater
operand_a_rev adder_op_b_negate adder_op_b_negate operand_a_rev adder_op_b_negate adder_result_expanded adder_result_expanded adder_result_expanded pmpcfg_we pmpcfg_we operand_a_rev
shift_use_round adder_result_expanded shift_use_roundshift_use_round pmpaddr_we pmpaddr_we
operand_a_neg_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int shift_amt_int operand_a_neg_rev dscratch0_n shift_amt_int dscratch0_n csr_wdata_int csr_wdata_int
PCER_q shift_rshift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev esult PCER_q shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev utvec_n shift_result utvec_n csr_we_int csr_we_int pack_result pack_result perf_rdata cmp_signed perf_rdata cmp_signed
adder_in_a adder_in_a is_equal adder_in_a is_equal dscratch0_q utvec_q dscratch0_q utvec_q shuffle_r0_in shuffle_r0_in
uepc_q uepc_q
shift_amt shift_amt mscratch_q priv_lvl_q adder_in_a priv_lvl_q shuffle_through mscratch_q shuffle_through
shift_left_result shift_left_result csr_rdata_int div_valid csr_rdata_int div_validdiv_valid shift_op_a shift_op_a shift_op_a
mtvec_q mtvec_q
mstatus_q depc_q mstatus_q dcsr_q depc_q dcsr_q shuffle_result div_op_a_signed shuffle_result div_op_a_signed dcsr_q bmask shift_op_a bmask shuffle_r1 shuffle_r1
depc_n depc_n
bextins_result bextins_result
PCCR_inc_q sel_minmax PCCR_inc_q sel_minmax shuffle_r0 shuffle_r0
id_valid_q is_equal_clip id_valid_q is_equal_clip adder_op_a adder_op_a PCMR_q shuffle_byte_sel PCMR_q mcause_q result_minmax shuffle_byte_sel mcause_q result_minmax
uepc_n uepc_n
pccr_index pccr_index radix_4_rev radix_4_rev
shift_amt_left shift_amt_left
radix_8_rev radix_8_rev PCCR_in PCCR_in is_equal_vec adder_result is_equal_vec adder_result adder_op_b adder_op_b shift_left shift_leftshift_left
adder_in_b adder_in_b adder_in_b
is_greater_vec is_greater_vec minmax_b shuffle_reg_sel minmax_b shift_right_result shuffle_reg_sel shift_right_result
shuffle_reg1_sel adder_in_b shuffle_reg1_sel
bitop_result bitop_result
f_is_greater mult_i f_is_greater mult_i
short_subword short_subword
mulh_clearcarry ex_stage_i ex_stage_i mulh_clearcarry mulh_signed mulh_signed
riscv_coredata_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb instr_req_int m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id _i data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb data_load_event_ex riscv_core_i data_load_event_ex
mulh_NS mulh_NS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i mulh_NS dot_short_op_b dot_short_op_b
mulh_ready mulh_ready id_valid id_valid
csr_access_ex regfile_waddr_lsu csr_access_excsr_access_ex regfile_waddr_lsu mult_result regfile_waddr_lsu mult_result
mulh_active mulh_active
mult_clpx_img_ex dot_char_mul mult_clpx_img_ex dot_char_mul csr_save_ex data_req_ex csr_save_ex top data_req_ex data_req_exdata_req_ex csr_save_id short_op_b top regfile_we_lsu dot_short_result csr_save_id short_op_b regfile_we_lsuregfile_we_lsu dot_short_result
dot_char_op_b dot_char_op_b mult_sel_subword_ex dot_char_op_a mult_sel_subword_ex dot_char_op_a csr_restore_mret_id csr_restore_mret_id irq_sec_i data_req_pmp irq_sec_i data_req_pmp
mulh_save mulh_save
alu_result alu_result mult_result alu_i div_shift alu_result
regfile_alu_we_fw regfile_alu_we_fwregfile_alu_we_fw
data_gnt_pmp data_gnt_pmp u_irq_enable pc_set u_irq_enable pc_set short_mac instr_req_o data_gnt_i short_mac instr_req_o data_gnt_i
regfile_we_wb regfile_we_wb clpx_shift_result dot_short_op_a regfile_we_wb clpx_shift_result dot_short_op_a
illegal_c_insn_id illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux illegal_c_insn_id illegal_c_insn_id clk_i mulh_shift_arith m_irq_enable m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int mulh_shift_arith clk_i m_irq_enable data_type_ex is_compressed_id is_compressed_id data_type_exdata_type_ex is_compressed_id
irq_id_o irq_id_o csr_hwlp_we exc_pc_mux_id csr_hwlp_we
data_sign_ext_ex data_sign_ext_ex data_reg_offset_ex exc_pc_mux_id data_sign_ext_ex instr_req_int instr_req_intinstr_req_int
useincr_addr_ex useincr_addr_exuseincr_addr_ex
sec_lvl_o sec_lvl_o dot_short_mul short_result dot_short_mul ex_ready short_result data_rvalid_i ex_ready data_rvalid_i data_we_o data_we_o mulh_imm short_signed mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rdata_i csr_irq_sec instr_rvalid_i instr_rvalid_i csr_save_if mulh_carry_q csr_save_if mulh_carry_q
data_misaligned_ex mult_operamult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 nd_a_ex data_misaligned_ex mult_operand_a_ex bmask_a_ex mult_signed_mode_ex bmask_a_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex branch_in_ex branch_in_ex ctrl_busy data_be_o instr_rdata_id branch_in_ex mult_signed_mode_ex bmask_a_ex csr_restore_uret_id data_be_o branch_in_ex csr_restore_uret_id csr_restore_uret_id instr_rdata_id
irq_id_i short_op_a irq_id_i short_op_a
bmask_b_ex mulh_subword bmask_b_ex mulh_subword mulh_CS core_ctrl_firstfetch bmask_b_ex mulh_CSmulh_CS core_ctrl_firstfetch
clk_en rstn_i clk_en rstn_i data_rdata_i instr_gnt_i data_rdata_i instr_gnt_i top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id instr_valid_id is_compressed_id is_fetch_failed_id top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id regfile_aluregfile_alu_we_ex regfile_alu_we_fw csr_op_ex data_we_ex data_type_ex data_sign_ext_ex data_reg_offset_ex _we_ex mult_clpx_shift_ex regfile_alu_we_exregfile_alu_we_ex instr_rdata_id mult_clpx_shift_ex alu_clpx_shift_ex alu_clpx_shift_ex mult_operator_ex mult_dot_op_c_ex alu_clpx_shift_ex mult_dot_op_c_ex debug_csr_save debug_csr_save core_clock_gate_i instr_rdata_id regfile_alu_wdata_fw core_clock_gate_i data_addr_o regfile_alu_wdata_fw data_addr_o
alu_operand_b_ex alu_operand_b_ex alu_operand_b_ex
short_shift_arith short_shift_arith alu_operand_a_ex alu_operand_a_ex alu_operand_a_ex data_req_o data_req_o
mult_dot_signed_ex mult_dot_signed_ex
clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux is_decoding useincr_addr_ex data_misaligned mult_multicycle apu_en_ex clear_instr_valid apu_en_exapu_en_ex debug_req_i clear_instr_valid debug_req_i csr_addr_int csr_addr_int instr_addr_o alu_is_subrot_ex alu_is_subrot_ex instr_addr_o alu_is_subrot_ex
data_wdata_o data_wdata_o csr_cause csr_cause perf_pipeline_stall perf_pipeline_stall
csr_rdata
pc_ex csr_rdata pc_ex irq_ack_o pc_ex irq_ack_o alu_operand_b_ex
pc_pc_id pc_ex id pc_id regfile_alu_waddr_ex regfile_alu_waddr_ex regfile_alu_waddr_exregfile_alu_waddr_ex id_ready core_busy_o data_reg_offset_ex id_ready core_busy_o data_reg_offset_ex pc_id irq_i is_hwlp_id trap_addr_mux irq_i is_hwlp_id trap_addr_mux
lsu_rdata lsu_rdata
fetch_enable_i aalu_operand_c_exlu_operand_c_ex alu_operand_c_ex mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 fetch_enable_i alu_operand_c_ex
mult_dot_op_b_ex mult_dot_op_b_ex
imm_vec_ext_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex imm_vec_ext_ex instr_valid_id instr_valid_idinstr_valid_id
mult_imm_ex mult_imm_ex lsu_ready_wb mult_dot_op_a_ex lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp calu_operand_a_exore_busy_q data_err_pmp
ctrl_busy alu_en_ex alu_operator_ex bmask_a_ex bmask_b_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex mult_en_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex apu_en_ex apu_lat_ex regfile_waddr_ex regfile_we_ex regfile_we_wb data_err_pmp ctrl_busy mem ctrl_busy mem mult_operand_c_ex mult_operand_c_ex
mult_operand_b_ex mult_operand_b_ex
pc_mux_id exc_cause alu_vec_mode_ex riscv_register_file_i pc_mux_id exc_cause alu_vec_mode_ex riscv_register_file_i mem
is_decoding is_decodingis_decoding
data_erdata_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int r_ack data_err_ack alu_operator_ex alu_operator_ex is_fetch_failed_id alu_operator_ex data_misaligned is_fetch_failed_id data_misaligned is_fetch_failed_id data_misaligned
debug_cause debug_cause
regfile_waddr_ex regfile_waddr_ex data_wdata_we_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_start_mux_sel hwloop_cnt_mux_sel hwloop_valid csr_access csr_status prepost_useincr operand_a_fw_mux_se operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux bmask_b_mux alu_bmask_a_mux_se alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm bmask_b_id_imm alu_vec_mode scalar_replication reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec e_id hwlp_dec_cnt_id regfile_waddr_ex data_we_iddata_we_id hwlp_dec_cnt_id
csr_op_ex csr_op_ex csr_op_ex
if_valid halt_if if_valid halt_if csr_hwlp_regid mult_operator_ex csr_hwlp_regid mult_operator_ex
rega_used_dec rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id rega_used_dec
csr_status csr_status csr_status
offset_fsm_cs hwlp_dec_cnt regfile_we_ex ebrk_ebrk_insn mret_insn_dec uret_insn_dec dret_insn_dec ecall_insn_dec pipe_flush_dec fencei_insn_dec rega_used_dec regb_used_dec regc_used_dec insn offset_fsm_cs hwlp_dec_cnt regfile_we_exregfile_we_ex ebrk_insnebrk_insn
alu_is_clpx_ex mem alu_is_clpx_ex
apu_lat_ex apu_lat_ex apu_lat_ex lsu_ready_ex fencei_insn_dec we_a_dec mult_multicycle lsu_ready_ex fencei_insn_decfencei_insn_dec we_a_dec mult_multicycle valid we_b_dec mult_multicycle we_a_dec valid we_b_dec
j j compressed_decoder_ i id_stage_i deassert_we csr_save_cause j we_b_dec hwloop_regid csr_save_cause we_a_dec hwloop_regid ex_valid we_b_dec ex_valid
mult_is_clpx_ex reg_d_wb_is_reg_a_id mult_is_clpx_ex hwloop_we reg_d_wb_is_reg_a_id hwloop_we hwloop_start_mux_sel fetch_addr_n hwloop_start_mux_sel fetch_addr_n mult_dot_signed mult_dot_signed
csr_restorecsr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp _dret_id hwloop_controller_i hwlp_target csr_restore_dret_id hwloop_controller_i hwlp_target rdata_offset_q rdata_offset_q fetch_ready rdata_offset_q clk fetch_ready clk
data_we_ex data_we_exdata_we_ex
data_type_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_cnt_mux_sel hwloop_valid operand_a_fw_mux_sel registers_i data_type_id operand_a_fw_mux_seloperand_a_fw_mux_sel registers_i
instr_req_pmp alu_en_ex instr_req_pmp alu_en_exalu_en_ex
data_rdata_ext data_rdata_ext fetch_rdata exc_kill alu_op_a_mux_sel fetch_rdata alu_op_a_mux_sel exc_kill alu_op_a_mux_sel
mult_en_ex bmask_b_mux mult_en_ex mult_en_ex bmask_b_muxbmask_b_mux alu_op_a_mux_sel pc_is_end_addr uret_insn_dec pc_is_end_addr uret_insn_decuret_insn_dec
fetch_is_hwlp hwloop_cnt_int fetch_is_hwlp pc_is_end_addr hwloop_cnt_int
mult_opmult_operator mult_int_en mult_sel_subword mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id erator mult_operator
CS instr_gnt_pmp CSCS instr_gnt_pmp instr_decompressed rdatardata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_n _q rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q id_valid_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_q uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr instr_decompressed rdata_q
mult_imm_mux mult_imm_mux bmask_a_id_imm mult_imm_mux
ddata_addr_intata_addr_int bmask_b_id_imm data_addr_int bmask_b_id_imm hwlp_dec_cnt_if operand_c_fw_mux_sel hwlp_dec_cnt_if operand_c_fw_mux_sel bmask_b_id_imm uret_dec uret_dec hwloop_we_masked hwloop_we_masked
exc_pc exc_pc
alu_op_b_alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel imm_b_mux_sel mux_sel alu_op_b_mux_selalu_op_b_mux_sel
trap_base_addr trap_base_addr
reg_d_ex_is_reg_a_id reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx regfile_data_ra_id reg_d_ex_is_reg_a_id regfile_data_ra_id data_addr_int regfile_data_ra_id
is_hwlp_id_q data_sign_ext_q data_sign_ext_q data_we_q wdata_offset operand_a_fw_id is_hwlp_id_q data_sign_ext_q operand_a_fw_id
bmask_a_mux bmask_a_mux illegal_c_insn
alu_vec_mode illegal_c_insn alu_vec_mode alu_vec_mode
hwloop_cnt branch_taken_ex jump_target_mux_sel mult_operator mult_int_en mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id hwloop_cnt rdata_b_ext jjump_target_mux_selump_target_mux_sel branch_taken_ex data_type_q id_stage_i rdata_b_ext jump_target_mux_sel data_type_qdata_type_q id_stage_i regfile_data_ra_id branch_taken_ex
jump_jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id in_id branch_req jump_in_id branch_req rdata_h_ext rdata_h_ext fetch_valid fetch_valid
imm_b_mux_sel imm_b_mux_selimm_b_mux_sel alu_operand_b alu_operand_b
offset_fsm_ns iimm_bmm_b offset_fsm_ns imm_b
mret_dec mret_dec uret_dec dret_dec mret_dec data_sign_ext_id mult_int_en deassert_we imm_i_type data_sign_ext_id mult_int_en wdata_offset imm_i_type deassert_we imm_i_type data_we_q wdata_offset data_we_q csr_access csr_accesscsr_access
compressed_decoder_i alu_operand_a
NS compressed_decoder_i NS alu_operand_a NS
imm_vuimm_vu_type _type imm_vu_type imm_bimm_vu_type regb_used_dec load_store_unit_i load_store_unit_i regb_used_dec operand_b operand_b
scalar_replication scalar_replication ecall_insn_dec scalar_replication ecall_insn_dec mult_dot_en ecall_insn_dec mult_dot_en
operand_c operand_c is_subrot hwloop_start_int is_subrotis_subrot imm_i_type hwloop_start_int
alu_operator alu_operator if_stage_i if_stage_i alu_operator mult_signed_mode mult_signed_mode
jump_target jump_target jump_targetjump_target
operand_b_fw_mux_sel operand_b_fw_mux_se l operand_c_fw_mux_se bmask_a_mux operand_b_fw_mux_sel
regc_used_dec load_stall regc_used_dec operand_c_fw_id load_stall operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel operand_b_fw_id hwloop_target_mux_sel
hwloop_hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i target hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i pipe_flush_dec hwloop_target pipe_flush_decpipe_flush_dec
alu_en alu_en regfile_alu_waddr_id alu_en regfile_alu_waddr_id regfile_alu_waddr_id
MODE_rule is_clpx regfile_addr_rc_id MODE_rule is_clpx regfile_addr_rc_id regfile_alu_waddr_id mret_insn_dec mret_insn_decmret_insn_dec mask_addr mask_addr
regfile_aluregfile_alu_we_id alu_en alu_operator _we_id regfile_alu_we_id operand_b_vec regfile_alu_we_id operand_b_vec R_rule R_rule
dret_insn_dec data_err_state_q dret_insn_decdret_insn_dec data_err_state_q
data_err_state_q alu_op_c_mux_sel regc_mux imm_a_mux_sel alu_op_c_mux_sel mult_sel_subword alu_op_c_mux_sel mult_sel_subword
bmask_a_id_imm bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall reg_d_alu_is_reg_a_id jr_stall reg_d_ex_is_reg_b_id dret_dec reg_d_ex_is_reg_b_id dret_dec illegal_insn_dec illegal_insn_dec illegal_insn_dec data_req_id data_req_id data_err_data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr state_n
alu_bmask_a_mux_sel data_err_state_n alu_bmask_a_mux_se l alu_bmask_a_mux_sel
hwloop_mask hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id regfile_we_id reg_d_ex_is_reg_c_id
stop_addr stop_addr start_addr start_addr prepost_useincr prepost_useincrprepost_useincr
data_load_event_id regfile_alu_waddr_mux_sel data_load_event_id regfile_alu_waddr_mux_sel regfile_alu_waddr_mux_selregfile_alu_waddr_mux_sel
fetch_valid hwloop_valid fetch_valid hwloop_valid halt_id halt_id
exc_ack exc_ack
CS hwlp_start_q instr_match_region CSCS hwlp_start_q alu_bmask_b_mux_sel instr_match_region CS alu_bmask_b_mux_selalu_bmask_b_mux_sel
use_hwlp regc_mux use_hwlp use_hwlp regc_mux hwlp_end_q next_valid hwlp_end_q next_valid
data_match_region data_match_region
W_rule hwloop_cnt_mux_sel W_rule hwloop_cnt_mux_sel rdata_unaligned rdata_unaligned
hwlp_counter_n imm_a_mux_sel hwlp_counter_n imm_a_mux_sel do_fetch jump_in_id do_fetch int_controller_i jump_in_id int_controller_i
addraddr_n addr_int addr_real_next _n jump_in_id addr_n addr_int addr_real_next hwloop_regs_i addr_n hwloop_regs_i next_is_crossword pmp_unit_i next_is_crossword pmp_unit_i
rdardata rdata_unaligned L0_buffer_i CS NS ta rdata rdata_unaligned L0_buffer_i CS NS rdata
EN_rule exc_ctrl_cs X_rule EN_rule exc_ctrl_cs X_rule
mult_dot_en mult_dot_enmult_dot_en
csr_csr_op mult_int_en mult_dot_en controller_i op csr_op addr_real_next addr_real_next irq_id_q irq_id_q decoder_i regfile_mem_we regfile_alu_we data_req hwloop_we csr_illegal decoder_i regfile_mem_we regfile_alu_we
hwlp_counter_q hwlp_counter_q
do_hwlp do_hwlp
valid valid addr_int addr_int irq_sec_q rdata_last_q irq_sec_q rdata_last_q rdata_last_qrdata_last_q regfile_alu_we regfile_alu_we
hwloop_we hwloop_we csr_illegal jump_in_id csr_op hwloop_we NSNS do_fetch do_hwlp do_hwlp_int use_last save_rdata_last use_hwlp save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid NS do_fetch do_hwlp NS
use_last use_lastuse_last data_req data_reqdata_req regfile_mem_we regfile_mem_we addr_q addr_q
hwlp_is_crossword hwlp_is_crossword addr_q
csr_illegal csr_illegal
save_rdata_last save_rdata_last busy_L0 save_rdata_last L0_buffer_i L0_buffer_i busy_L0
mult_int_en mult_int_enmult_int_en
do_hwlp_int do_hwlp_intdo_hwlp_int
is_hwlp_q is_hwlp_q CS CS
addraddr_q instr_addr_int hwloop_controller_i _q addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec addr_q instr_addr_int instr_addr_int
decoder_i save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid save_rdata_hwlp decoder_i save_rdata_hwlp
is_crossword is_crossword
illegal_iillegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i regfile_we_lsu regfile_waddr_lsu alu_result mult_result alu_i div_shift div_valid adder_op_b_negate shift_left shift_use_round shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int nsn_n illegal_insn_n next_upper_compressed next_upper_compressed
is_hwlp_n is_hwlp_n
addr_qL0_buffer L0_buffer ebrk_force_debug_mode ebrk_force_debug_mode
ctrl_fsmctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de _ns ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i ctrl_fsm_ns
jump_done_q jump_done_q
NS
NS controller_i irq_enable_int irq_enable_int
ctrl_fsm_cs L0_buffer ctrl_fsm_cs ctrl_fsm_csctrl_fsm_cs instr_valid_irq_flush_q instr_valid_irq_flush_q
branch_in_id branch_in_id
illegal_insn_q illegal_insn_q illegal_insn_q
jump_done jump_done instr_valid_irq_flush_n prefetch_buffer_i L0_bufferprefetch_buffer_i instr_valid_irq_flush_n debug_mode_q debug_mode_q
debug_mode_n debug_mode_n
data_err_q controller_i controller_i data_err_q jump_in_dec jump_in_dec
Figure A.9.: (SI) Illegal instruction, ALU test Figure A.10.: (SM) Memory access, ALU test
ResInv_SP ResInv_SP
cs_registers_i ResInv_SN div_i ResInv_SN div_i is_pcmr cs_registers_i is_pcmr
RemSel_SP RemSel_SP
Cnt_DP Cnt_DP
mcause_n is_pcer is_pcer ABComp_S mcause_n ABComp_S
LoadEn_S LoadEn_S RemSel_SN RemSel_SN
PCCR_q PCCR_q
BRegEn_S BRegEn_S PCER_n PCER_n
priv_lvl_n priv_lvl_n CompInv_SP CompInv_SP
ucause_q ucause_q
AddMux_D cnt_l1 AddMux_D cnt_l1
mtvec_n mtvec_n
State_SP SState_SPtate_SP
cnt_l3 cnt_l3 AReg_DN State_SN AReg_DN State_SN
dscratch1_q ucause_n mscratch_n ucause_n mscratch_n dscratch1_q
exception_pc exception_pc
OutMux_D OutMux_D
dscratch1_n dscratch1_n
alu_i cnt_l2 alu_i cnt_l2 ResRegEn_S Cnt_DN index_lut Cnt_DN ResRegEn_S index_lut
PCCR_n PCCR_n
index_nodes index_nodes
ResReg_DP ResRegResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry _DP alu_popcnt_i cnt_l1 cnt_l2 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN State_SP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready mulh_CS mulh_NS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q rdata_offset_q data_sign_ext_q data_we_q wdata_offset CS NS alu_popcnt_i cnt_l1 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN ResReg_DN ResReg_DN
shift_arithmetic shift_arithshift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed metic
PCCR_inc alu_popcnt_i PCCR_inc alu_popcnt_i
mepc_q mepc_q
ResReg_DP_rev ResReg_DP_rev shuffle_reg0_sel shuffle_reg0_sel
is_pccr is_pccr cnt_l4 cnt_l4
pccr_all_sel pccr_all_sel sel_nodes sel_nodes
ARegEn_S ARegEn_S AReg_DP AReg_DP f_is_nan alu_ff_i f_is_nan alu_ff_i pmp_reg_n pmp_reg_n cmp_result AddTmp_D AddTmp_D cmp_result
ff_input ff_input BReg_DP BReg_DP pmp_reg_q pmp_reg_q
dcsrdcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule _n dcsr_n div_ready div_ready
radix_2_rev radix_2_rev
div_shift div_shift BReg_DN BReg_DN PCMR_n PCMR_n cnt_result cnt_result
mepc_n mepc_n CompInv_SN CompInv_SN
mstatus_n is_greater mstatus_n shuffle_r1_in shuffle_r1_in is_greater
operand_a_rev adder_op_b_negate operand_a_rev adder_op_badder_op_b_negate _negate
aadder_result_expandeddder_result_expanded adder_result_expanded pmpcfg_we operand_a_rev pmpcfg_we adder_result_expanded shift_use_round sshift_use_roundhift_use_round pmpaddr_we pmpaddr_we
operand_a_neg_rev operand_a_operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int neg_rev shift_amt_int shift_amt_int dscratch0_n dscratch0_n csr_wdata_int csr_wdata_int
PCER_q PCER_q shift_rshift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev esult shift_reshift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev sult utvec_n utvec_n csr_we_int csr_we_int
pack_result pack_result
perf_rdata perf_rdata cmp_signed cmp_signed
adder_in_a adder_in_a adder_in_a is_equal is_equal
dscratch0_q utvec_q dscratch0_q utvec_q shuffle_r0_in shuffle_r0_in uepc_q uepc_q adder_in_a shift_amt shift_amt mscratch_q priv_lvl_q mscratch_q priv_lvl_q shuffle_through shuffle_through
shift_left_result shift_left_result
csr_rdata_int csr_rdata_int div_valid ddiv_validiv_valid sshift_op_ahift_op_a shift_op_a
mtvec_q mtvec_q
mstatus_q mstatus_q depc_q depc_q dcsr_q dcsr_q shuffle_result div_op_a_signed shift_op_a shuffle_result div_op_a_signed dcsr_q bmask bmask
shuffle_r1 shuffle_r1
depc_n depc_n
bextins_result bextins_result
PCCR_inc_q sel_minmax PCCR_inc_q sel_minmax
shuffle_r0 shuffle_r0
is_equal_clip id_valid_q id_valid_q is_equal_clip adder_op_a adder_op_a
PCMR_q PCMR_q shuffle_byte_sel shuffle_byte_sel mcause_q result_minmax mcause_q result_minmax
uepc_n uepc_n
pccr_index pccr_index radix_4_rev radix_4_rev
shift_amt_left shift_amt_left
radix_8_rev radix_8_rev PCCR_in PCCR_in
is_equal_vec is_equal_vec adder_result adder_result adder_op_b adder_op_b shift_left sshift_lefthift_left
aadder_in_bdder_in_b adder_in_b
is_greater_vec is_greater_vec minmax_b minmax_b shuffle_reg_sel shuffle_reg_sel shift_right_result adder_in_b shift_right_result shuffle_reg1_sel shuffle_reg1_sel
bitop_result bitop_result f_is_greater mult_i f_is_greater mult_i
short_subword short_subword ex_stage_i mulh_clearcarry ex_stage_i mulh_clearcarry mulh_signed mulh_signed
riscv_core_i data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb data_load_event_ex riscv_core_i data_load_event_ex
mulh_NS mulh_NS dot_short_op_b dot_short_op_b
mulh_ready mmulh_readyulh_ready id_valid id_valid
regfile_waddr_lsu regfile_waddr_lsu csr_access_ex ccsr_access_exsr_access_ex regfile_waddr_lsu mult_result mult_result
mulh_active mulh_active
mult_clpx_img_ex dot_char_mul mult_clpx_img_ex dot_char_mul csr_save_ex csr_save_ex top data_req_ex top data_req_exdata_req_ex csr_save_id short_op_b csr_save_id short_op_b regfile_we_lsu dot_short_result reregfile_we_lsugfile_we_lsu dot_short_result
dot_char_op_b dot_char_op_b mult_sel_subword_ex dot_char_op_a mult_sel_subword_ex dot_char_op_a csr_restore_mret_id csr_restore_mret_id irq_sec_i irq_sec_i data_req_pmp data_req_pmp
mulh_save mulh_save
alu_result alu_realu_result mult_result alu_i div_shift sult
regfile_alu_we_fw reregfile_alu_we_fwgfile_alu_we_fw
data_gnt_pmp data_gnt_pmp u_irq_enable u_irq_enable pc_set pc_set short_mac short_mac instr_req_o data_gnt_i instr_req_o data_gnt_i
regfile_we_wb dot_short_op_a regfile_wregfile_we_wb e_wb clpx_shift_result clpx_shiftclpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i _result dot_short_op_a illegal_c_insn_idillegal_c_insn_id illegal_c_illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux insn_id clk_i mulh_shift_arith clk_i mulh_shift_arith m_irq_enable m_irq_em_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int nable
data_type_ex data_type_ex is_compressed_id is_compreis_compressed_id ssed_id data_type_ex
irq_id_o irq_id_o
csr_hwlp_we csr_hwlp_we exc_pc_mux_id exc_pc_mux_id data_sign_ext_ex data_sign_data_sign_ext_ex data_reg_offset_ex ext_ex
instr_req_int ininstr_req_intstr_req_int
useincr_addr_ex uuseincr_addr_exseincr_addr_ex
sec_lvl_o sec_lvl_o
short_result dot_short_mul short_result dot_short_mul ex_ready ex_ready data_rvalid_i data_rvalid_i data_we_o data_we_o mulh_imm short_signed mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rdata_i csr_irq_sec instr_rvalid_i instr_rvalid_i
csr_save_if csr_save_if mulh_carry_q mulh_carry_q
mult_operamult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 nd_a_ex mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 data_misaligned_ex data_misaligned_ex mult_operand_a_ex bmask_a_ex mult_signed_mode_ex bmask_a_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex bmask_a_ex branch_in_ex mult_signed_mode_ex branch_in_ex ctrl_busy data_be_o instr_rdata_id data_be_o branch_in_ex csr_restore_uret_idcsr_restore_uret_id branch_in_ex csr_restore_uret_id instr_rdata_id
irq_id_i short_op_a irq_id_i short_op_a
bmask_b_ex mulh_subword bmask_b_ex mulh_subword mulh_CS core_ctrl_firstfetch bmask_b_ex core_ctrl_firstfetch mulh_CSmulh_CS
clk_en clk_en rstn_i instr_rdata_id rstn_i data_rdata_i instr_gnt_i data_rdata_i instr_gnt_i
top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id instr_valid_id is_compressed_id is_fetch_failed_id regfile_alu_we_ex top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id reregfile_alu_we_exgfile_alu_we_ex mult_clpx_shift_ex mult_clpx_shift_ex
alu_clpx_shift_ex alu_clpx_salu_clpx_shift_ex mult_operator_ex hift_ex mult_dot_op_c_ex instr_rdata_idmult_dot_op_c_ex debug_csr_save debug_csr_save core_clock_gate_i regfile_alu_wdata_fw core_clock_gate_i regfile_alu_wdata_fw data_addr_o data_addr_o
aalu_operand_b_exlu_operand_b_ex alu_operand_b_ex
short_shift_arith short_shift_arith aalu_operand_a_exlu_operand_a_ex alu_operand_a_ex
data_req_o data_req_o
mult_dot_signed_ex mult_dot_signed_ex
apu_en_ex clear_insclear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux is_decoding data_misaligned mult_multicycle tr_valid clear_instr_valid aapu_en_expu_en_ex debug_req_i debug_req_i csr_addr_int csr_addr_int instr_addr_o alu_is_subrot_ex instr_addr_o aalu_is_subrot_exlu_is_subrot_ex
data_wdata_o data_wdata_o csr_cause csr_cause perf_pipeline_stall perf_pipeline_stall
csr_rdata csr_rdata
pc_pc_ex ex pc_epc_ex x irq_ack_o irq_ack_o alu_operand_b_ex
ppc_idc_id pc_id regfile_alu_waddr_ex regfile_alu_waddr_exregfile_alu_waddr_ex data_reg_offset_ex id_ready id_ready core_busy_o core_busy_o data_reg_offset_ex
trap_addr_mux irq_i is_hwlp_id irq_i is_hwlp_id pc_id trap_addr_mux
lsu_rdata lsu_rdata fetch_enable_i alu_operand_c_exalu_operand_c_ex fetch_enable_i aalu_operand_c_exlu_operand_c_ex
mult_dot_op_b_ex mult_dot_op_b_ex
imm_vec_ext_ex imm_vec_imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex ext_ex instr_valid_id instr_valid_idinstr_valid_id
mult_imm_ex mult_imm_ex
lsu_ready_wb mult_dot_op_a_ex lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp core_busy_q alu_operand_a_exdata_err_pmp
ctrl_busy alu_en_ex alu_operator_ex bmask_a_ex bmask_b_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex mult_en_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex apu_en_ex apu_lat_ex regfile_waddr_ex regfile_we_ex regfile_we_wb regfile_alu_waddr_ex regfile_alu_we_ex regfile_alu_we_fw csr_access_ex csr_op_ex data_we_ex data_type_ex data_sign_ext_ex data_reg_offset_ex data_req_ex data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb instr_req_int m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id data_err_pmp ctrl_busy mem ctrl_busy mem mult_operand_c_ex mult_operand_c_ex mem mult_operand_b_ex mult_operand_b_ex
pc_mux_id exc_cause exc_cause alu_vec_mode_ex riscv_register_file_i pc_mux_id alu_vec_mode_ex riscv_register_file_i
is_decoding is_decodingis_decoding
data_erdata_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int r_ack data_err_ack alu_operator_ex alu_operator_ex
is_fetch_failed_id is_fetch_failed_id alu_operator_ex data_misaligned is_fetch_failed_id data_misadata_misaligned ligned
debug_cause debug_cause
regfile_waddr_ex regfile_waddr_ex data_wdata_we_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_cnt_mux_sel hwloop_valid csr_access csr_status prepost_useincr operand_a_fw_mux_se operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux bmask_b_mux alu_bmask_a_mux_se alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm bmask_b_id_imm alu_vec_mode scalar_replication reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec e_id ddata_we_idata_we_id hwlp_dec_cnt_id hwlp_dec_cnt_id regfile_waddr_ex
csr_op_ex csr_opcsr_op_ex _ex
if_valid if_valid halt_if halt_if
csr_hwlp_regid csr_hwlp_regid mult_operator_ex mem mult_operator_ex
rega_used_dec rega_userega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id d_dec
csr_status csr_stacsr_status tus hwlp_dec_cnt ebrk_ebrk_insn mret_insn_dec uret_insn_dec dret_insn_dec ecall_insn_dec pipe_flush_dec fencei_insn_dec rega_used_dec regb_used_dec regc_used_dec insn hwlp_dec_cnt offset_fsm_cs regfile_we_ex offset_fsm_cs reregfile_we_exgfile_we_ex ebrk_insnebrk_insn
alu_is_clpx_ex alu_is_clpx_ex
apu_lat_ex apu_laapu_lat_ex t_ex fencei_insn_dec we_a_dec lsu_ready_ex lsu_ready_ex fencei_insn_dec we_a_dec mult_multicycle fencei_insn_dec mmult_multicycleult_multicycle we_a_dec valid we_b_dec valid we_b_decwe_b_dec
j j compressed_decoder_ i id_stage_i deassert_we csr_save_cause j csr_save_cause hwloop_regid we_a_decwe_b_dec hwloop_regid ex_valid ex_valid
mult_is_clpx_ex mult_is_clpx_ex reg_d_wb_is_reg_a_id reg_d_wb_is_reg_a_id hwloop_we hwloop_we
hwloop_start_mux_sel hwloop_start_mux_sel fetch_addr_n fetch_addr_n mult_dot_signed mult_dot_signed
csr_restorecsr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp _dret_id hwloop_controller_i hwlp_target hwloop_controller_i hwlp_target csr_restore_dret_id rdata_offset_q rdata_offset_q fetch_ready fetch_ready rdata_offset_q clk clk
data_we_ex ddata_we_exata_we_ex
data_type_id data_typdata_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_start_mux_sel hwloop_cnt_mux_sel hwloop_valid e_id operand_a_fw_mux_sel registers_i operand_a_fw_mux_seloperand_a_fw_mux_sel registers_i
instr_req_pmp instr_req_pmp alu_en_ex aalu_en_exlu_en_ex
data_rdata_ext data_rdata_ext fetch_rdata exc_kill fetch_rdata exc_kill aalu_op_a_mux_sellu_op_a_mux_sel alu_op_a_mux_sel
mult_en_ex mult_en_ex bmask_b_mux mult_en_ex bbmask_b_muxmask_b_mux alu_op_a_mux_sel pc_is_end_addr uret_insn_dec pc_is_end_addr uret_insn_decuret_insn_dec
fetch_is_hwlp fetch_is_hwlp pc_is_end_addr hwloop_cnt_int hwloop_cnt_int mult_operator mult_operator
CS instr_gnt_pmp CS instr_gnt_pmp
instr_decompressed rdatardata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q id_valid_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_q uepc_n _q instr_decompressed rdatardata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr _q
mult_imm_mux mult_immmult_imm_mux bmask_a_id_imm _mux
ddata_addr_intata_addr_int bmask_b_id_imm data_addr_int bmask_b_id_imm hwlp_dec_cnt_if operand_c_fw_mux_sel hwlp_dec_cnt_if operand_c_fw_mux_sel bmask_b_id_imm uret_dec uret_dec hwloop_we_masked hwloop_we_masked
exc_pc exc_pc
alu_op_b_alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel imm_b_mux_sel jump_target_mux_sel mult_operator mult_int_en mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id mux_sel alu_op_b_alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel mux_sel
trap_base_addr trap_base_addr
reg_d_ex_is_reg_a_id reg_d_ex_isreg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx _reg_a_id regfile_daregfile_data_ra_id hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i ta_ra_id data_addr_int regfile_data_ra_id
is_hwlp_id_q data_sign_ext_q is_hwlp_id_q data_sign_ext_q data_we_q wdata_offset CS NS operand_a_fw_id data_sign_ext_q operand_a_fw_id
bmask_a_mux bmask_a_mux illegal_c_insn illegal_c_insn
alu_vec_mode alu_vec_alu_vec_mode mode
hwloop_cnt branch_taken_ex hwloop_cnt branch_taken_ex jump_target_mux_sel jump_target_mux_sel mult_operator mult_int_en mult_sel_subword mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id rdata_b_ext rdata_b_ext jump_target_mux_sel data_type_q id_stage_i data_type_q id_stage_i data_type_q regfile_data_ra_id branch_taken_ex
jump_jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id regfile_alu_waddr_id regfile_alu_we_id alu_en alu_operator in_id jump_in_id branch_req branch_req
rdata_h_ext rdata_h_ext fetch_valid fetch_valid
imm_b_mux_sel imm_b_mux_selimm_b_mux_sel
alu_operand_b alu_operand_b
offset_fsm_ns iimm_bmm_b offset_fsm_ns imm_b
mret_dec mret_mret_dec uret_dec dret_dec dec data_sign_ext_id mult_int_en data_sign_ext_id mult_int_en deassert_we imm_i_type deassert_we imm_i_type wdata_offset imm_i_type wdata_offset data_we_q data_we_q csr_access ccsr_accesssr_access
compressed_decoder_i alu_operand_a compressed_decoder_i alu_operand_a NS NS imm_vuimm_vu_type _type imm_bimm_vuimm_vu_type _type load_store_unit_i regb_used_dec load_store_unit_i regb_used_dec operand_b operand_b
scalar_replication scalar_replicationscalar_replication ecall_insn_dec ecall_insn_dececall_insn_dec mult_dot_en imm_i_type mult_dot_en operand_c operand_c is_subrot is_subrot hwloop_start_int hwloop_start_int is_subrot if_stage_i alu_operator if_stage_i alu_opealu_operator rator mult_signed_mode mult_signed_mode
jump_targetjump_target jujump_targetmp_target
operand_b_fw_mux_sel operand_b_fwoperand_b_fw_mux_se l operand_c_fw_mux_se bmask_a_mux _mux_sel
regc_used_dec load_stall regc_used_dec load_stall operand_c_fw_id operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel operand_b_fw_id hwloop_target_mux_sel
hwloop_target hwloop_hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i target pipe_flush_dec pipe_flush_decpipe_flush_dec
alu_en alu_enalu_en regfile_alu_waddr_id regfile_alu_waddr_id
is_clpx MODE_rule regfile_addr_rc_id MODE_rule is_clpx regfile_addr_rc_id regfile_alu_waddr_id mret_insn_dec mret_insn_dec mask_addr mask_addr mret_insn_dec
regfile_alu_we_id regfile_aluregfile_alu_we_id _we_id operand_b_vec operand_b_vec R_rule R_rule
dret_insn_dec dret_insn_dec data_err_state_qdata_err_state_q data_err_state_q dret_insn_dec alu_op_c_mux_sel alu_op_c_mux_sel mult_sel_subword mult_sel_subword
bmask_a_id_imm bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall reg_d_alu_is_reg_a_id jr_stall
reg_d_ex_is_reg_b_id reg_d_ex_is_reg_b_id dret_dec dret_dec illegal_insn_decillegal_insn_dec illegal_insn_dec data_req_id data_req_id
data_err_data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr state_n data_err_state_n
alu_bmask_a_mux_sel alu_bmask_aalu_bmask_a_mux_se l _mux_sel
hwloop_mask hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id regfile_we_id reg_d_ex_is_reg_c_id
stop_addr stop_addr start_addr start_addr prepost_useincr pprepost_useincrrepost_useincr
data_load_event_id data_load_event_id rregfile_alu_waddr_mux_selegfile_alu_waddr_mux_sel reregfile_alu_waddr_mux_selgfile_alu_waddr_mux_sel
fetch_valid hwloop_valid fetch_valid hwloop_valid
halt_id halt_id
exc_ack exc_ack
CS hwlp_start_q CS hwlp_start_q instr_match_region CS instr_match_region CS alu_bmask_b_mux_sel aalu_bmask_b_mux_sellu_bmask_b_mux_sel
use_hwlp use_hwlp regc_mux use_hwlp regc_mux hwlp_end_q hwlp_end_q next_valid next_valid
data_match_region data_match_region
W_rule W_rule hwloop_cnt_mux_sel hwloop_cnt_mux_sel rdata_unaligned rdata_unaligned
hwlp_counter_n hwlp_counter_n imm_a_mux_sel imm_a_mux_sel do_fetch do_fetch jump_in_id int_controller_i jump_in_id int_controller_i addraddr_n addr_int addr_real_next _n jump_in_id hwloop_regs_i addraddr_n addr_int addr_real_next _n hwloop_regs_i next_is_crossword pmp_unit_i next_is_crossword pmp_unit_i
rdardata rdata_unaligned L0_buffer_i CS NS ta rdatrdata rdata_unaligned L0_buffer_i CS NS a
EN_rule exc_ctrl_cs EN_rule exc_ctrl_cs X_rule X_rule
mult_dot_en mmult_dot_enult_dot_en
csr_csr_op mult_int_en mult_dot_en controller_i op csr_op
addr_real_next addr_real_next
irq_id_q irq_id_q decoder_i regfile_mem_we regfile_alu_we data_req hwloop_we csr_illegal decoder_i regfile_mem_we regfile_alu_we
hwlp_counter_q hwlp_counter_q
do_hwlp do_hwlp
valid valid
addr_int addr_int irq_sec_q irq_sec_q rdata_last_qrdata_last_q rdata_last_q regfile_alu_we rdata_last_q regfile_alu_we
hwloop_we hwloophwloop_we csr_illegal jump_in_id csr_op _we
NSNS do_fetch do_hwlp do_hwlp_int use_last save_rdata_last use_hwlp save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid NSNS do_fetch do_hwlp
use_last use_lastuse_last data_req ddata_reqata_req regfile_mem_we regfile_mem_we
addr_q addr_q
hwlp_is_crossword hwlp_is_crossword addr_q
csr_illegal csr_illegal
save_rdata_last save_rdasave_rdata_last ta_last L0_buffer_i busy_L0 L0_buffer_i busy_L0
mult_int_en mmult_int_enult_int_en
do_hwlp_int do_hwlp_intdo_hwlp_int
is_hwlp_q is_hwlp_q
CS CS
addraddr_q instr_addr_int hwloop_controller_i _q addraddr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec _q instr_addr_int instr_addr_int
decoder_i save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid decoder_i save_rdata_hwlp save_rdata_hwlp
is_crossword is_crossword
illegal_iillegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i regfile_we_lsu regfile_waddr_lsu alu_result mult_result alu_i div_shift div_valid adder_op_b_negate shift_left shift_use_round shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int nsn_n illegal_insn_n
next_upper_compressed next_upper_compressed
is_hwlp_n is_hwlp_n
addr_qL0_buffer L0_buffer ebrk_force_debug_mode ebrk_force_debug_mode
ctrl_fsmctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de _ns ctrl_fsmctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i _ns
jump_done_q jump_done_q
NS NS controller_i irq_enable_int irq_enable_int
L0_buffer ctrl_fsm_csctrl_fsm_cs ctrl_fsm_csctrl_fsm_cs instr_valid_irq_flush_q instr_valid_irq_flush_q
branch_in_id branch_in_id
illegal_insn_qillegal_insn_q illegal_insn_q
jump_done jump_done prefetch_buffer_i instr_valid_irq_flush_n L0_bufferprefetch_buffer_i instr_valid_irq_flush_n debug_mode_q debug_mode_q
debug_mode_n debug_mode_n
controller_i data_err_q controller_i data_err_q jump_in_dec jump_in_dec
Figure A.11.: (SI) Illegal instruction, MUL test Figure A.12.: (SM) Memory access, MUL test
ResInv_SP ResInv_SP
ResInv_SN ResInv_SN cs_registers_i div_i cs_registers_i div_i is_pcmr is_pcmr
RemSel_SP RemSel_SP
Cnt_DP Cnt_DP
is_pcer is_pcer mcause_n ABComp_S mcause_n ABComp_S
LoadEn_S LoadEn_S RemSel_SN RemSel_SN
PCCR_q PCCR_q
BRegEn_S BRegEn_S PCER_n PCER_n
priv_lvl_n priv_lvl_n CompInv_SP CompInv_SP
ucause_q ucause_q
AddMux_D cnt_l1 AddMux_D cnt_l1 mtvec_n mtvec_n State_SP State_SP State_SP
cnt_l3 cnt_l3 AReg_DN State_SN AReg_DN State_SN
ucause_n mscratch_n dscratch1_q ucause_n mscratch_n dscratch1_q
exception_pc exception_pc
OutMux_D OutMux_D
dscratch1_n dscratch1_n
alu_i cnt_l2 alu_i cnt_l2 Cnt_DN ResRegEn_S index_lut Cnt_DN ResRegEn_S index_lut PCCR_n PCCR_n index_nodes index_nodes
ResReResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready g_DP ResReg_DP alu_popcnt_i cnt_l1 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN State_SP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready mulh_CS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q rdata_offset_q data_sign_ext_q data_we_q wdata_offset CS NS alu_popcnt_i cnt_l1 cnt_l2 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN ResReg_DN ResReg_DN
shift_arishift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed thmetic shift_arithmetic
PCCR_inc PCCR_inc alu_popcnt_i alu_popcnt_i mepc_q mepc_q
ResReg_DP_rev ResReg_DP_rev shuffle_reg0_sel shuffle_reg0_sel
is_pccr is_pccr cnt_l4 cnt_l4
pccr_all_sel pccr_all_sel sel_nodes sel_nodes
ARegEn_S ARegEn_S AReg_DP AReg_DP f_is_nan f_is_nan alu_ff_i alu_ff_i pmp_reg_n pmp_reg_n AddTmp_D cmp_result AddTmp_D cmp_result
ff_input ff_input BReg_DP BReg_DP pmp_reg_q pmp_reg_q
dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule dcsr_n dcsr_n div_ready div_ready
radix_2_rev radix_2_rev div_shift div_shift BReg_DN BReg_DN PCMR_n PCMR_n cnt_result cnt_result
mepc_n mepc_n CompInv_SN CompInv_SN
mstatus_n mstatus_n shuffle_r1_in is_greater shuffle_r1_in is_greater
operand_a_rev adder_op_adder_op_b_negate b_negate operand_a_rev adder_op_b_negate adder_result_expanded adder_result_expanded operand_a_rev pmpcfg_we pmpcfg_we adder_result_expanded
shift_use_round shift_use_round adder_result_expanded shift_use_round pmpaddr_we pmpaddr_we
operand_aoperand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int _neg_rev operand_a_neg_rev shift_amt_int shift_amt_int dscratch0_n dscratch0_n csr_wdata_int csr_wdata_int
PCER_q
PCER_q shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev shift_rshift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev esult shift_result utvec_n utvec_n csr_we_int csr_we_int pack_result pack_result perf_rdata perf_rdata cmp_signed cmp_signed
adder_in_a adder_in_a is_equal is_equal dscratch0_q utvec_q dscratch0_q utvec_q adder_in_a shuffle_r0_in shuffle_r0_in
uepc_q uepc_q
shift_amt shift_amt adder_in_a mscratch_q priv_lvl_q mscratch_q priv_lvl_q shuffle_through shuffle_through
shift_left_result shift_left_result csr_rdata_int csr_rdata_int div_valid div_valid div_valid shift_op_a shift_op_ashift_op_a
mtvec_q mtvec_q
mstatus_q mstatus_q depc_q depc_q dcsr_q dcsr_q shift_op_a shuffle_result div_op_a_signed shuffle_result div_op_a_signed bmask dcsr_q bmask shuffle_r1 shuffle_r1
depc_n depc_n
bextins_result bextins_result
PCCR_inc_q sel_minmax PCCR_inc_q sel_minmax shuffle_r0 shuffle_r0
id_valid_q is_equal_clip id_valid_q is_equal_clip adder_op_a adder_op_a PCMR_q PCMR_q shuffle_byte_sel shuffle_byte_sel mcause_q result_minmax mcause_q result_minmax
uepc_n uepc_n
pccr_index pccr_index radix_4_rev radix_4_rev
shift_amt_left shift_amt_left
radix_8_rev radix_8_rev PCCR_in PCCR_in is_equal_vec is_equal_vec adder_result adder_result adder_op_b adder_op_b shift_left shift_left shift_left
adder_in_b adder_in_badder_in_b is_greater_vec is_greater_vec minmax_b minmax_b shuffle_reg_sel shuffle_reg_sel shift_right_result shift_right_result adder_in_b shuffle_reg1_sel shuffle_reg1_sel
bitop_result bitop_result
f_is_greater f_is_greater mult_i mult_i
short_subword short_subword
mulh_clearcarry ex_stage_i mulh_clearcarry ex_stage_i mulh_signed mulh_signed
riscv_coredata_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb _i riscv_core_i data_load_event_ex data_load_event_ex
mulhmulh_NS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i _NS mulh_NS dot_short_op_b dot_short_op_b
mulh_ready mulh_ready id_valid id_valid
csr_access_ex regfile_waddr_lsu ccsr_access_exsr_access_ex regfile_waddr_lsu csr_access_ex regfile_waddr_lsu mult_result mult_result
mulh_active mulh_active
mult_clpx_img_ex dot_char_mul mult_clpx_img_ex dot_char_mul csr_save_ex csr_save_ex data_req_ex data_req_ex top data_req_ex top csr_save_id short_op_b csr_save_id short_op_b regfile_we_lsu dot_short_result regfile_we_lsu dot_short_result regfile_we_lsu
dot_char_op_b dot_char_op_b mult_sel_subword_ex dot_char_op_a mult_sel_subword_ex dot_char_op_a csr_restore_mret_id csr_restore_mret_id irq_sec_i irq_sec_i data_req_pmp data_req_pmp
mulh_save mulh_save
alu_ralu_result mult_result alu_i div_shift esult alu_result
regfile_alu_we_fw regfile_alu_we_fw regfile_alu_we_fw
data_gnt_pmp data_gnt_pmp u_irq_enable u_irq_enable pc_set pc_set short_mac short_mac instr_req_o data_gnt_i instr_req_o data_gnt_i
regfile_we_wb regfile_we_wb regfile_we_wb clpx_shift_result dot_short_op_a clpx_shift_result dot_short_op_a
illegal_c_illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux insn_id illegal_c_insn_id
clk_i mulh_shift_arith
illegal_c_insn_id m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int mulh_shift_arith m_irq_enable clk_i m_irq_enable data_type_ex
data_type_ex is_compris_compressed_id essed_id data_type_ex is_compressed_id
irq_id_o irq_id_o csr_hwlp_we csr_hwlp_we exc_pc_mux_id exc_pc_mux_id data_signdata_sign_ext_ex data_reg_offset_ex _ext_ex data_sign_ext_ex instr_req_int instr_req_int instr_req_int
useincr_addr_ex useincr_addr_ex useincr_addr_ex
sec_lvl_o sec_lvl_o short_result dot_short_mul short_result dot_short_mul ex_ready ex_ready data_rvalid_i data_rvalid_i data_we_o data_we_o mulh_imm short_signed mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rdata_i csr_irq_sec instr_rvalid_i instr_rvalid_i csr_save_if csr_save_if mulh_carry_q mulh_carry_q
mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 data_misaligned_ex mult_opermult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 and_a_ex data_misaligned_ex mult_operand_a_ex
bmask_a_ex bmaskbmask_a_ex _a_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex apu_en_ex apu_lat_ex regfile_waddr_ex regfile_we_ex regfile_we_wb mult_signedmult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex _mode_ex mult_signed_mode_ex bmask_a_ex data_be_o branchbranch_in_ex ctrl_busy _in_ex data_be_o bbranch_in_exranch_in_ex csr_restore_uret_id instr_rdata_id csr_restore_uret_idcsr_restore_uret_id instr_rdata_id
irq_id_i short_op_a irq_id_i short_op_a
bmask_b_ex mulh_subword bbmask_b_exmask_b_ex mulh_subword mulh_CS core_ctrl_firstfetch mulh_CS core_ctrl_firstfetch mulh_CS bmask_b_ex
clk_en clk_en rstn_i rstn_i data_rdata_i instr_gnt_i data_rdata_i instr_gnt_i top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id instr_valid_id is_compressed_id is_fetch_failed_id top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id regfile_alu_we_ex regfile_alu_we_fw regfile_alu_we_ex regfile_alu_we_ex regfile_alu_we_ex mult_clpx_shift_ex instr_rdata_id mult_clpx_shift_ex instr_rdata_id alu_clpx_alu_clpx_shift_ex mult_operator_ex shift_ex alu_clpx_shift_ex mult_dot_op_c_ex mult_dot_op_c_ex debug_csr_save debug_csr_save
core_clock_gate_i core_clock_gate_i regfile_alu_wdata_fw regfile_alu_wdata_fw data_addr_o data_addr_o
alu_operand_b_ex alu_operand_b_exalu_operand_b_ex short_shift_arith short_shift_arith alu_operand_a_ex alu_operand_a_ex data_req_o data_req_o alu_operand_a_ex mult_dot_signed_ex mult_dot_signed_ex
apu_en_ex clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux is_decoding useincr_addr_ex data_misaligned mult_multicycle clear_instr_valid clear_instr_valid apu_en_ex apu_en_ex debug_req_i debug_req_i csr_addr_int csr_addr_int instr_addr_o alu_is_subrot_ex instr_addr_o alu_is_subrot_ex alu_is_subrot_ex
data_wdata_o data_wdata_o csr_cause csr_cause perf_pipeline_stall perf_pipeline_stall
csr_rdata csr_rdata pc_ex pc_pc_ex ex pc_ex irq_ack_o irq_ack_o
pc_id pc_id pc_id regfile_alu_waddr_ex pc_id rregfile_alu_waddr_exegfile_alu_waddr_ex regfile_alu_waddr_ex id_ready id_ready core_busy_o data_reg_offset_ex core_busy_o data_reg_offset_ex
irq_i is_hwlp_id trap_addr_mux irq_i is_hwlp_id trap_addr_mux alu_operand_b_ex
lsu_rdata lsu_rdata fetch_enable_i alu_operand_c_ex fetch_enable_i alu_operand_c_exalu_operand_c_ex alu_operand_c_ex
mult_dot_op_b_ex mult_dot_op_b_ex
imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex imm_vecimm_vec_ext_ex _ext_ex imm_vec_ext_ex instr_valid_id instr_valid_id instr_valid_id
mult_imm_ex mult_imm_ex lsu_ready_wb mult_dot_op_a_ex lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp core_busy_q data_err_pmp
ctrl_busy alu_en_ex data_err_pmp ctrl_busy ctrl_busy mem mem mult_operand_c_ex mult_operand_c_ex
mult_operand_b_ex mult_operand_b_ex
exc_cause exc_cause pc_mux_id alu_vec_mode_ex pc_mux_id alu_vec_mode_ex riscv_register_file_i alu_vec_mode_ex riscv_register_file_i
is_decoding is_decoding is_decoding
data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int data_err_ack data_err_ack alu_operator_ex aalu_operator_exlu_operator_ex is_fetch_failed_id alu_operator_ex is_fetch_failed_id is_fetch_failed_id data_misdata_misaligned aligned data_misaligned
debug_cause debug_cause
regfile_waddr_ex regfile_waddr_ex regfile_waddr_ex data_we_id data_we_id hwlp_dec_cnt_id data_we_id hwlp_dec_cnt_id
csr_op_ex data_we_ex data_type_ex data_sign_ext_ex data_reg_offset_ex data_req_ex data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb instr_req_int m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_ocsr_op_ex p_ex csr_op_ex alu_operand_a_ex
if_valid if_valid halt_if halt_if mem csr_hwlp_regid csr_hwlp_regid mult_operator_ex mult_operator_ex mem
rega_usrega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id ed_dec rega_used_dec
csr_status prepost_useincr operand_a_fw_mux_se l operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux csr_scsr_status tatus csr_status hwlp_dec_cnt ebrk_insn mret_insn_dec uret_insn_dec dret_insn_dec ecall_insn_dec pipe_flush_dec fencei_insn_dec rega_used_dec regb_used_dec regc_used_dec offset_fsm_cs regfile_we_ex ebrk_insn offset_fsm_cs hwlp_dec_cnt regfile_we_ex ebrk_insn regfile_we_ex ebrk_insn alu_is_clpx_ex alu_is_clpx_ex alu_is_clpx_ex
apu_laapu_lat_ex t_ex apu_lat_ex fencei_insn_dec we_a_dec fencei_insn_dec we_a_dec lsu_ready_ex fencei_insn_dec lsu_ready_ex mult_multicycle mult_multicycle mult_multicycle valid we_b_dec valid we_a_dec we_b_dec we_a_dec j compressed_decoder_ i id_stage_i deassert_we j csr_save_cause j csr_save_cause we_b_dec hwloop_regid hwloop_regid we_b_dec ex_valid ex_valid
mult_is_clpx_ex mult_is_clpx_ex reg_d_wb_is_reg_a_id reg_d_wb_is_reg_a_id hwloop_we hwloop_we hwloop_start_mux_sel hwloop_start_mux_sel fetch_addr_n fetch_addr_n mult_dot_signed mult_dot_signed
csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp hwlp_target csr_restore_dret_id hwloop_controller_i hwlp_target csr_restore_dret_id hwloop_controller_i rdata_offset_q rdata_offset_q rdata_offset_q fetch_ready fetch_ready clk clk
data_we_ex data_we_ex data_we_ex
data_tydata_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_cnt_mux_sel hwloop_valid pe_id data_type_id operand_a_fw_mux_sel operand_a_fw_mux_sel registers_i registers_i
instr_req_pmp operand_a_fw_mux_sel instr_req_pmp alu_en_ex alu_en_ex alu_en_ex
data_rdata_ext data_rdata_ext fetch_rdata fetch_rdata exc_kill alu_op_a_mux_sel exc_kill aalu_op_a_mux_sellu_op_a_mux_sel
mult_en_ex bmask_b_mux mmult_en_exult_en_ex bbmask_b_muxmask_b_mux mult_en_ex bmask_b_mux pc_is_end_addr uret_insn_dec pc_is_end_addr uret_insn_dec alu_op_a_mux_seluret_insn_dec fetch_is_hwlp fetch_is_hwlp hwloop_cnt_int pc_is_end_addr hwloop_cnt_int mult_operator mult_operator
CCS NS S instr_gnt_pmp CS instr_gnt_pmp
rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_n instr_decompressed rdatrdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q id_valid_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_q uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr a_q instr_decompressed rdata_q
mult_immult_imm_mux bmask_a_id_imm m_mux mult_imm_mux
data_addr_int bmask_b_id_imm ddata_addr_intata_addr_int bbmask_b_id_immmask_b_id_imm
hwlp_dec_cnt_if operand_c_foperand_c_fw_mux_se l bmask_a_mux w_mux_sel hwlp_dec_cnt_if operand_c_fw_mux_sel bmask_b_id_imm uret_dec uret_dec hwloop_we_masked hwloop_we_masked
exc_pc exc_pc
alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel alu_op_b_alu_op_b_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel mux_sel alu_op_b_mux_sel
trap_base_addr trap_base_addr
reg_d_ex_isreg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx _reg_a_id reg_d_ex_is_reg_a_id regfile_data_ra_id regfile_data_ra_idregfile_data_ra_id
is_hwlp_id_q data_sign_ext_q data_we_q is_hwlp_id_q data_sign_ext_q operand_a_fw_id data_sign_ext_q operand_a_fw_id
bmask_a_mux bmask_a_mux illegal_c_insn illegal_c_insn alu_vec_mode scalar_replication reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec alu_vec_mode alu_vec_mode alu_vec_mode hwloop_cnt hwloop_cnt branch_taken_ex jump_target_mux_sel mult_operator mult_int_en mult_sel_subword mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_alu_waddr_mux _sel data_we_id data_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_start_mux_sel hwloop_cnt_mux_sel hwloop_valid jump_targejump_target_mux_sel mult_operator mult_int_en mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id t_mux_sel jump_target_mux_sel branch_taken_ex rdata_b_ext rdata_b_ext data_type_q id_stage_i data_type_q id_stage_i data_type_q branch_taken_ex
jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id jump_in_id jump_in_id branch_req branch_req rdata_h_ext rdata_h_ext data_addr_int fetch_valid fetch_valid
imm_b_mux_sel iimm_b_mux_selmm_b_mux_sel
alu_operand_b imm_b_mux_sel alu_operand_b
offset_fsm_ns imm_b offset_fsm_ns imm_b regfile_data_ra_id imm_b mret_mret_dec uret_dec dret_dec dec mret_dec data_sign_ext_id mult_int_en data_sign_ext_id mult_int_en deassert_we deassert_we imm_i_type imm_i_type wdata_offset wdata_offset data_we_q wdata_offset data_we_q csr_access imm_i_type ccsr_accesssr_access csr_access
compressed_decoder_i alu_operand_a compressed_decoder_i alu_operand_a NS NS
imm_vu_type imm_vuimm_vu_type _type imm_vu_type
regb_used_dec load_store_unit_i regb_used_dec load_store_unit_i operand_b operand_b
scalar_replication scalar_replication ecall_insn_dec ecall_insn_dec ecall_insn_dec scalar_replication mult_dot_en mult_dot_en
operand_c operand_c is_subrot is_subrot hwloop_start_int is_subrot hwloop_start_int
alu_operator alu_opalu_operator erator if_stage_i alu_operator if_stage_i imm_b mult_signed_mode mult_signed_mode
jump_target jump_targetjump_target jump_target operand_b_fw_mux_sel operand_b_fw_mux_sel operand_b_fw_mux_sel
regc_used_dec regc_used_dec load_stall load_stall operand_c_fw_id operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel operand_b_fw_id hwloop_target_mux_sel
hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i hwloophwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i _target hwloop_target pipe_flush_dec pipe_flush_dec imm_i_typepipe_flush_dec
alu_en aalu_enlu_en alu_en regfile_alu_waddr_id rregfile_alu_waddr_idegfile_alu_waddr_id
MODE_rule is_clpx regfile_addr_rc_id MODE_rule is_clpx regfile_addr_rc_id regfile_alu_waddr_id mret_insn_dec mret_insn_dec mret_insn_dec mask_addr mask_addr
regfile_alu_we_id regfile_alregfile_alu_we_id u_we_id regfile_alu_we_id operand_b_vec operand_b_vec R_rule R_rule
dret_insn_dec dret_insn_dec data_err_state_q dret_insn_dec data_err_state_qdata_err_state_q alu_op_c_mux_sel alu_op_c_mux_sel mult_sel_subword mult_sel_subword
bmask_a_id_imm bmask_a_id_imm
reg_d_alu_is_reg_a_id jr_stall reg_d_alu_is_reg_a_id jr_stall reg_d_ex_is_reg_b_id reg_d_ex_is_reg_b_id dret_dec dret_dec illegal_insn_dec illegal_insn_decillegal_insn_dec data_req_id data_req_id
data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr data_err_state_n data_err_state_n
alu_bmask_a_mux_se l alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm alu_bmask_alu_bmask_a_mux_se l a_mux_sel alu_bmask_a_mux_sel
hwloop_mask hwloop_mask regfile_we_id reg_d_ex_is_reg_c_id regfile_we_id reg_d_ex_is_reg_c_id
stop_addr stop_addr start_addr start_addr prepost_useincr prepost_useincr prepost_useincr
data_load_event_id data_load_event_id regfile_alu_waddr_mux_sel regfile_alu_waddr_mux_sel regfile_alu_waddr_mux_sel
fetch_valid hwloop_valid fetch_valid hwloop_valid halt_id halt_id
exc_ack exc_ack
CS CS hwlp_start_q hwlp_start_q CS instr_match_region instr_match_region alu_bmask_b_mux_sel CS alu_bmask_b_mux_sel alu_bmask_b_mux_sel
use_hwlp uuse_hwlpse_hwlp regc_mux regc_mux use_hwlp hwlp_end_q hwlp_end_q next_valid next_valid
data_match_region data_match_region
W_rule W_rule hwloop_cnt_mux_sel hwloop_cnt_mux_sel rdata_unaligned rdata_unaligned
hwlp_counter_n hwlp_counter_n imm_a_mux_sel imm_a_mux_sel do_fetch do_fetch jump_in_id jump_in_id int_controller_i int_controller_i
addr_n addr_int addr_real_next addaddr_n addr_int addr_real_next r_n addr_n jump_in_id hwloop_regs_i hwloop_regs_i next_is_crossword pmp_unit_i next_is_crossword pmp_unit_i
rdata rdata_unaligned L0_buffer_i CS NS rdardata rdata_unaligned L0_buffer_i CS NS ta rdata
EN_rule exc_ctrl_cs EN_rule exc_ctrl_cs X_rule X_rule
mult_dot_en controller_i mult_dot_en mult_dot_en mult_dot_en
csr_op csr_op csr_op addr_real_next addr_real_next
irq_id_q irq_id_q decoder_i regfile_mem_we regfile_alu_we data_req hwloop_we csr_illegal decoder_i
hwlp_counter_q hwlp_counter_q
do_hwlp do_hwlp
valid valid addr_int addr_int irq_sec_q irq_sec_q rdata_last_q rrdata_last_qdata_last_q rdata_last_q
regfile_regfile_alu_we alu_we regfile_alu_we
hwloohwloop_we csr_illegal jump_in_id csr_op p_we hwloop_we
NS do_fetch do_hwlp do_hwlp_int NNS do_fetch do_hwlp S NS
use_last uuse_lastse_last use_last data_req data_req regfile_mem_we data_req regfile_mem_we regfile_mem_we addr_q addr_q
hwlp_is_crossword hwlp_is_crossword addr_q
csr_illegal csr_illegal
save_rdata_last save_rdsave_rdata_last ata_last save_rdata_last busy_L0 L0_buffer_i busy_L0 L0_buffer_i
mult_int_en mmult_int_enult_int_en mult_int_en
do_hwlp_int do_hwlp_int do_hwlp_int
is_hwlp_q is_hwlp_q
CS CS
addr_q instr_addr_int hwloop_controller_i addaddr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec r_q addr_q instr_addr_int instr_addr_int
save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid decoder_i decoder_i save_rdata_hwlp save_rdata_hwlp
is_crossword is_crossword
illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i regfile_we_lsu regfile_waddr_lsu alu_result mult_result alu_i div_shift div_valid adder_op_b_negate shift_left shift_use_round shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int illegal_insn_n illegal_insn_n next_upper_compressed next_upper_compressed
is_hwlp_n is_hwlp_n
addr_q L0_buffer L0_buffer ebrk_force_debug_mode ebrk_force_debug_mode
ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de ctrl_fsctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i m_ns ctrl_fsm_ns
jump_done_q jump_done_q
NS NS controller_i irq_enable_int irq_enable_int
ctrl_fsm_cs ctrl_fsm_csctrl_fsm_cs ctrl_fsm_cs
instr_valid_irq_flush_q L0_buffer instr_valid_irq_flush_q branch_in_id branch_in_id
illegal_insn_q illegal_insn_qillegal_insn_q
jump_done jump_done instr_valid_irq_flush_n prefetch_buffer_i instr_valid_irq_flush_n L0_bufferprefetch_buffer_i debug_mode_q debug_mode_q
debug_mode_n debug_mode_n
data_err_q controller_i data_err_q controller_i jump_in_dec jump_in_dec
Figure A.13.: (SI) Illegal instruction, AES test Figure A.14.: (SM) Memory access, AES test 80 Fault Effect Causation - Application Error Clusters
ResInv_SP ResInv_SP
ResInv_SN cs_registers_i ResInv_SN div_i cs_registers_i div_i is_pcmr is_pcmr
RemSel_SP RemSel_SP
Cnt_DP Cnt_DP
is_pcer mcause_n is_pcer mcause_n ABComp_S ABComp_S
LoadEn_S LoadEn_S RemSel_SN RemSel_SN
PCCR_q PCCR_q
BRegEn_S BRegEn_S PCER_n PCER_nPCER_n priv_lvl_n priv_lvl_n CompInv_SP CompInv_SP
ucause_q ucause_q
AddMux_D cnt_l1 AddMux_D cnt_l1
mtvec_n mtvec_n State_SPState_SP State_SPState_SP
cnt_l3 cnt_l3 AReg_DN State_SN AReg_DN State_SN
dscratch1_q ucause_n mscratch_n dscratch1_q ucause_n mscratch_n
exception_pc exception_pc
OutMux_D OutMux_D
dscratch1_n dscratch1_n
alu_i cnt_l2 alu_i cnt_l2 ResRegEn_S Cnt_DN ResRegEn_S index_lut Cnt_DN index_lut
PCCR_n PCCR_n
index_nodes index_nodes ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready ResReg_DP ResReg_DP alu_popcnt_i cnt_l1 cnt_l2 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN alu_popcnt_i cnt_l1 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN ResReg_DN
ResReg_DN shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int shift_arithmeticshift_arithmetic shift_arithmetic
PCCR_inc alu_popcnt_i PCCR_inc alu_popcnt_i mepc_q PCCR_qmepc_q ResReg_DP_rev ResReg_DP_rev shuffle_reg0_sel shuffle_reg0_sel
is_pccr is_pccr cnt_l4 cnt_l4
pccr_all_sel pccr_all_sel sel_nodes sel_nodes
ARegEn_S ARegEn_S AReg_DP AReg_DP f_is_nan alu_ff_i f_is_nan alu_ff_i pmp_reg_n pmp_reg_n cmp_result AddTmp_D cmp_result AddTmp_D
ff_input ff_input BReg_DP BReg_DP pmp_reg_q pmp_reg_q dcsr_n dcsr_n div_ready div_ready
radix_2_rev radix_2_rev
div_shift div_shift BReg_DN BReg_DN PCMR_n PCMR_n cnt_result PCMR_n cnt_result
mepc_n mepc_n CompInv_SN CompInv_SN
mstatus_n mstatus_n is_greater shuffle_r1_in is_greater shuffle_r1_in adder_op_b_negate adder_op_b_negate operand_a_rev adder_op_b_negate operand_a_rev adder_op_b_negate adder_result_expanded adder_result_expanded pmpcfg_we operand_a_revadder_result_expanded pmpcfg_we adder_result_expanded shift_use_roundshift_use_round shift_use_roundshift_use_round
pmpaddr_we pmpaddr_we operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int operand_a_neg_rev operand_a_neg_rev shift_amt_int shift_amt_int dscratch0_n dscratch0_n csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q csr_wdata_int csr_wdata_int
PCER_q shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev PCER_q shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev shift_result shift_result utvec_n utvec_n csr_we_int PCER_q csr_we_int pack_result pack_result perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr perf_rdata perf_rdata cmp_signed cmp_signed
adder_in_a is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed adder_in_a is_equal is_equal utvec_q adder_in_a dscratch0_q utvec_q dscratch0_q shuffle_r0_in shuffle_r0_in uepc_q adder_in_a uepc_q shift_amt shift_amt mscratch_q priv_lvl_q mscratch_q priv_lvl_q shuffle_through shuffle_through
shift_left_result shift_left_result
csr_rdata_int csr_rdata_int div_validdiv_valid div_valid shift_op_a div_valid shift_op_a shift_op_a
mtvec_q mtvec_q
mstatus_q mstatus_q depc_q depc_q dcsr_q dcsr_q shift_op_a shuffle_result div_op_a_signed shuffle_result div_op_a_signed bmask bmask
shuffle_r1 shuffle_r1
depc_n depc_n
bextins_result bextins_result
PCCR_inc_q PCCR_inc_q sel_minmax PCCR_inc_q sel_minmax shuffle_r0 shuffle_r0
is_equal_clip id_valid_q is_equal_clip id_valid_q adder_op_a adder_op_a
PCMR_q PCMR_q shuffle_byte_sel shuffle_byte_sel mcause_q mcause_q result_minmax PCMR_q result_minmax
uepc_n uepc_n pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc pccr_index pccr_index radix_4_rev radix_4_rev
shift_amt_left shift_amt_left
radix_8_rev radix_8_rev PCCR_in PCCR_in
is_equal_vec is_equal_vec adder_result adder_result adder_op_b adder_op_b shift_leftshift_left shift_leftshift_left
adder_in_b adder_in_badder_in_b is_greater_vec is_greater_vec minmax_b minmax_b shuffle_reg_sel shuffle_reg_sel adder_in_b shift_right_result shift_right_result
shuffle_reg1_sel shuffle_reg1_sel
bitop_result bitop_result f_is_greater mult_i f_is_greater mult_i
short_subword short_subword ex_stage_i mulh_clearcarry ex_stage_i mulh_clearcarry mulh_signed mulh_signed data_load_event_ex riscv_coredata_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb _i riscv_core_i data_load_event_ex data_load_event_ex mulh_NS clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i mulh_NS mulh_NS dot_short_op_b dot_short_op_b
mulh_ready mulh_ready id_valid id_valid
csr_access_excsr_access_ex regfile_waddr_lsu csr_access_excsr_access_ex regfile_waddr_lsuregfile_waddr_lsu mult_result regfile_waddr_lsu mult_result
mulh_active mulh_active
mult_clpx_img_ex dot_char_mul mult_clpx_img_ex dot_char_mul csr_save_ex csr_save_ex top data_req_exdata_req_ex top data_req_exdata_req_ex csr_save_id short_op_b csr_save_id short_op_b regfile_we_lsuregfile_we_lsu dot_short_result regfile_we_lsuregfile_we_lsu dot_short_result
dot_char_op_b dot_char_op_b mult_sel_subword_ex dot_char_op_a mult_sel_subword_ex dot_char_op_a csr_restore_mret_id csr_restore_mret_id irq_sec_i irq_sec_i data_req_pmp data_req_pmp
mulh_save mulh_save alu_result mult_result alu_i div_shift alu_result mult_result alu_i div_shift alu_result alu_result
regfile_alu_we_fwregfile_alu_we_fw regfile_alu_we_fwregfile_alu_we_fw
data_gnt_pmp data_gnt_pmp u_irq_enable u_irq_enable pc_set pc_set short_mac short_mac instr_req_o data_gnt_i instr_req_o data_gnt_i regfile_we_wb regfile_we_wb
regfile_we_wb regfile_we_wb clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q clpx_shift_result dot_short_op_a clpx_shift_result dot_short_op_a illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux illegal_c_insn_id illegal_c_insn_id
m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int mulh_shift_arith clk_i m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int mulh_shift_arith clk_i m_irq_enable m_irq_enable data_type_ex data_sign_ext_ex
is_compressed_id data_type_exdata_type_ex is_compressed_id data_type_ex is_compressed_id is_compressed_id
irq_id_o irq_id_o
csr_hwlp_we csr_hwlp_we
data_sign_ext_ex exc_pc_mux_id exc_pc_mux_id data_sign_ext_ex data_sign_ext_ex instr_req_intinstr_req_int instr_req_intinstr_req_int useincr_addr_exuseincr_addr_ex useincr_addr_exuseincr_addr_ex
sec_lvl_o sec_lvl_o
short_result dot_short_mul short_result dot_short_mul ex_ready ex_ready data_rvalid_i data_rvalid_i data_we_o data_we_o mulh_imm short_signed mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rdata_i csr_irq_sec instr_rvalid_i instr_rvalid_i
csr_save_if csr_save_if mulh_carry_q mulh_carry_q
mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 mult_opermult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i and_a_ex data_misaligned_exdata_misaligned_ex mult_operand_a_ex data_misaligned_ex bmask_a_ex bmask_a_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex
branch_in_ex ctrl_busy bmask_a_ex branch_in_ex ctrl_busy mult_signed_mode_ex bmask_a_ex mult_signed_mode_ex branch_in_ex data_be_o branch_in_ex data_be_o instr_rdata_id csr_restore_uret_id instr_rdata_id csr_restore_uret_id
irq_id_i short_op_a irq_id_i short_op_a
bmask_b_ex instr_rdata_id bmask_b_ex bmask_b_ex mulh_subword bmask_b_ex mulh_subword mulh_CS core_ctrl_firstfetch mulh_CSmulh_CS core_ctrl_firstfetch
clk_en mulh_CS clk_en rstn_i rstn_i data_rdata_i instr_gnt_i data_rdata_i instr_gnt_i top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id regfile_alu_we_exregfile_alu_we_ex regfile_alu_we_exregfile_alu_we_ex mult_clpx_shift_ex mult_clpx_shift_ex alu_clpx_shift_ex mult_operator_ex alu_clpx_shift_ex alu_clpx_shift_ex instr_rdata_idmult_dot_op_c_ex mult_dot_op_c_ex debug_csr_save debug_csr_save core_clock_gate_i core_clock_gate_i regfile_alu_wdata_fw regfile_alu_wdata_fw data_addr_o data_addr_o
alu_operand_b_ex alu_operand_b_ex
short_shift_arith short_shift_arith alu_operand_a_ex alu_operand_a_ex data_req_o data_req_o alu_operand_b_ex mult_dot_signed_ex mult_dot_signed_ex
apu_en_ex apu_en_exapu_en_ex clear_instr_valid apu_en_ex clear_instr_valid debug_req_i debug_req_i csr_addr_int csr_addr_int alu_is_subrot_ex alu_is_subrot_ex instr_addr_o alu_is_subrot_ex instr_addr_o alu_operand_a_ex
data_wdata_o data_wdata_o csr_cause csr_cause perf_pipeline_stall alu_operand_b_ex perf_pipeline_stall csr_rdata pc_ex csr_rdata pc_ex pc_ex pc_ex irq_ack_o irq_ack_o
pc_idpc_id pc_idpc_id regfile_alu_waddr_exregfile_alu_waddr_ex regfile_alu_waddr_exregfile_alu_waddr_ex data_reg_offset_ex id_ready data_reg_offset_exdata_reg_offset_ex id_ready core_busy_o data_reg_offset_ex core_busy_o
is_hwlp_id trap_addr_mux irq_i is_hwlp_id trap_addr_mux irq_i
lsu_rdata lsu_rdata fetch_enable_i alu_operand_c_ex fetch_enable_i alu_operand_c_exalu_operand_c_ex
alu_operand_a_ex mult_dot_op_b_ex mult_dot_op_b_ex
alu_operand_c_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex mult_en_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex imm_vec_ext_ex imm_vec_ext_ex instr_valid_idinstr_valid_id instr_valid_idinstr_valid_id
mult_imm_ex mult_imm_ex
lsu_ready_wb mult_dot_op_a_ex lsu_ready_wb mult_dot_op_a_ex
core_busy_q data_err_pmp core_busy_q data_err_pmp
ctrl_busy mem ctrl_busy mem mult_operand_c_ex mult_operand_c_ex
mult_operand_b_ex mult_operand_b_ex
exc_cause pc_mux_id exc_cause pc_mux_id alu_vec_mode_ex riscv_register_file_i alu_vec_mode_ex riscv_register_file_i
is_decodingis_decoding is_decodingis_decoding mem
data_err_ack data_err_ack alu_operator_ex alu_operator_exalu_operator_ex
is_fetch_failed_id is_fetch_failed_id is_fetch_failed_id alu_operator_ex data_misaligneddata_misaligned is_fetch_failed_id data_misaligneddata_misaligned debug_cause debug_cause
regfile_waddr_ex
regfile_waddr_ex data_we_id data_we_id regfile_waddr_ex data_we_iddata_we_id hwlp_dec_cnt_id hwlp_dec_cnt_id csr_op_ex csr_op_ex regfile_waddr_ex csr_op_ex mem csr_op_ex
if_valid halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb if_valid halt_if halt_if
csr_hwlp_regid csr_hwlp_regid mult_operator_ex mult_operator_ex rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id rega_used_dec rega_used_dec csr_status csr_status csr_status hwlp_dec_cnt csr_status offset_fsm_cs hwlp_dec_cnt regfile_we_exregfile_we_ex ebrk_insnebrk_insn offset_fsm_csoffset_fsm_cs regfile_we_exregfile_we_ex ebrk_insnebrk_insn alu_is_clpx_ex alu_is_clpx_ex apu_lat_ex apu_lat_ex apu_lat_ex apu_lat_ex fencei_insn_dec we_awe_a_dec _dec lsu_ready_ex fencei_insn_dec we_a_decwe_a_dec lsu_ready_ex mult_multicycle fencei_insn_dec mult_multicycle fencei_insn_dec mult_multicycle mult_multicycle we_b_decwe_b_dec valid we_b_decwe_b_dec valid j j csr_save_cause csr_save_cause hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_start_mux_sel hwloop_cnt_mux_sel hwloop_valid hwloop_regid hwloop_regid
ex_valid ex_valid
mult_is_clpx_ex
mult_is_clpx_ex reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec reg_d_wb_is_reg_a_id reg_d_wb_is_reg_a_id hwloop_we hwloop_we
hwloop_start_mux_sel hwloop_start_mux_sel fetch_addr_n fetch_addr_n mult_dot_signed mult_dot_signed
csr_restore_dret_id hwloop_controller_i hwlp_target csr_restore_dret_id hwloop_controller_i hwlp_target rdata_offset_qrdata_offset_q rdata_offset_qrdata_offset_q fetch_ready fetch_ready clk clk
data_we_exdata_we_ex data_we_exdata_we_ex
data_type_id data_tdata_type_id data_sign_ext_id data_req_id ype_id
data_type_id operand_a_fw_mux_se l operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux operand_a_fw_mux_seloperand_a_fw_mux_sel registers_i operand_a_fw_mux_sel registers_i
instr_req_pmp instr_req_pmp alu_en_exalu_en_ex alu_en_exalu_en_ex
data_rdata_ext data_rdata_ext fetch_rdata fetch_rdata exc_kill exc_kill alu_op_a_mux_selalu_op_a_mux_sel alu_op_a_mux_selalu_op_a_mux_sel mult_en_ex mult_en_ex mult_en_ex bmask_b_muxbmask_b_mux bmask_b_muxbmask_b_mux
uret_insn_dec pc_is_end_addr uret_insn_decuret_insn_dec pc_is_end_addr uret_insn_dec
fetch_is_hwlp fetch_is_hwlp hwloop_cnt_int hwloop_cnt_int
mult_operator mult_operator CS NS CS NS CS instr_gnt_pmp CS instr_gnt_pmp rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q id_valid_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_q uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q instr_decompressed rdata_q instr_decompressed rdata_q mult_imm_mux bmask_a_id_imm mult_imm_mux mult_imm_mux
data_addr_int data_addr_int bmask_b_id_immbmask_b_id_imm bmask_b_id_immbmask_b_id_imm
operand_c_fw_mux_se l bmask_a_mux data_addr_int hwlp_dec_cnt_if operand_c_fw_mux_sel hwlp_dec_cnt_if operand_c_fw_mux_sel
uret_dec uret_dec hwloop_we_masked hwloop_we_masked
exc_pc data_addr_int exc_pc alu_op_b_mux_selalu_op_b_mux_sel alu_op_b_mux_selalu_op_b_mux_sel
trap_base_addr trap_base_addr
reg_d_ex_is_reg_a_idreg_d_ex_is_reg_a_id reg_d_ex_is_reg_a_idreg_d_ex_is_reg_a_id regfile_data_ra_id regfile_data_ra_idregfile_data_ra_id
is_hwlp_id_q data_sign_ext_q data_we_q is_hwlp_id_q data_sigdata_sign_ext_q data_we_q n_ext_q data_sign_ext_q operand_a_fw_id operand_a_fw_id
bmask_a_mux bmask_a_mux
illegal_c_insn alu_vec_mode illegal_c_insn alu_vec_mode scalar_replication alu_vec_mode alu_vec_mode
hwloop_cnt jump_target_mux_sel mult_operator mult_int_en mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_data_ra_idhwloop_cnt jump_target_mux_sel mult_operator mult_int_en mult_sel_subword mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id branch_taken_ex jump_target_mux_sel branch_taken_ex rdata_b_ext jump_target_mux_sel rdata_b_ext data_type_qdata_type_q id_stage_i data_type_q id_stage_i
jump_in_id jump_in_id branch_req branch_req
rdata_h_ext rdata_h_ext fetch_valid fetch_valid
imm_b_mux_selimm_b_mux_sel imm_b_mux_selimm_b_mux_sel alu_operand_b alu_operand_b
offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 imm_b offset_fsm_ns imm_b offset_fsm_ns mret_dec uret_dec dret_dec mret_dec mret_dec data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_cnt_mux_sel hwloop_valid data_sign_ext_id mult_int_en data_sign_ext_id mult_int_en deassert_we deassert_we imm_i_type imm_i_type wdata_offsetwdata_offset wdata_offsetwdata_offset imm_b data_we_q data_we_q csr_accesscsr_access imm_i_type csr_accesscsr_access compressed_decoder_i alu_operand_a compressed_decoder_i alu_operand_a NS NS imm_vu_type imm_vu_type imm_i_typeimm_bimm_vu_type imm_vu_type
load_store_unit_i regb_used_dec load_store_unit_i regb_used_dec operand_b operand_b
scalar_replicationscalar_replication scalar_replication ecall_insn_dec ecall_insn_dec ecall_insn_dec mult_dot_en ecall_insn_dec mult_dot_en
operand_c operand_c is_subrotis_subrot is_subrot hwloop_start_int hwloop_start_int alu_operator alu_operator if_stage_i alu_operator if_stage_i alu_operator mult_signed_mode mult_signed_mode
jump_targetjump_target jump_targetjump_target
operand_b_fw_mux_seloperand_b_fw_mux_sel operand_b_fw_mux_sel
regc_used_dec load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id regc_used_dec load_stall load_stall operand_c_fw_id operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel operand_b_fw_id hwloop_target_mux_sel hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i hwloop_target hwloop_target pipe_flush_decpipe_flush_dec pipe_flush_decpipe_flush_dec
alu_enalu_en alu_enalu_en regfile_alu_waddr_idregfile_alu_waddr_id regfile_alu_waddr_idregfile_alu_waddr_id is_clpx MODE_rule is_clpx regfile_addr_rc_id MODE_rule regfile_addr_rc_id mret_insn_dec mret_insn_dec mask_addr mret_insn_dec mask_addr mret_insn_dec regfile_alu_we_id regfile_alu_we_id regfile_alu_we_id regfile_alu_we_id operand_b_vec operand_b_vec R_rule R_rule
dret_insn_dec dret_insn_dec data_err_state_q dret_insn_dec data_err_state_q dret_insn_dec alu_op_c_mux_sel regc_mux imm_a_mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel alu_op_c_mux_sel alu_op_c_mux_sel mult_sel_subword mult_sel_subword
bmask_a_id_imm bmask_a_id_imm
jr_stall reg_d_alu_is_reg_a_id jr_stall reg_d_alu_is_reg_a_id
reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx jr_stall reg_d_ex_is_reg_b_id reg_d_ex_is_reg_b_idreg_d_ex_is_reg_b_id dret_dec dret_dec
illegal_insn_dec illegal_insn_dec
data_req_id data_req_id data_err_state_n
data_err_state_n alu_bmask_a_mux_se l alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm alu_bmask_a_mux_se l alu_bmask_a_mux_sel alu_bmask_a_mux_sel
hwloop_mask hwloop_mask reg_d_ex_is_reg_c_id regfile_we_id reg_d_ex_is_reg_c_id regfile_we_id reg_d_ex_is_reg_c_id
stop_addr stop_addr start_addr start_addr prepost_useincrprepost_useincr prepost_useincrprepost_useincr
data_load_event_id data_load_event_id regfile_alu_waddr_mux_selregfile_alu_waddr_mux_sel regfile_alu_waddr_mux_selregfile_alu_waddr_mux_sel data_load_event_id
fetch_valid hwloop_valid fetch_valid hwloop_valid
halt_id halt_id
exc_ack exc_ack
CSCS hwlp_start_q CS hwlp_start_q instr_match_region instr_match_region CS alu_bmask_b_mux_sel alu_bmask_b_mux_sel alu_bmask_b_mux_sel
use_hwlp use_hwlpuse_hwlp use_hwlp regc_mux regc_mux hwlp_end_q hwlp_end_q next_valid next_valid
data_match_region data_match_region
W_rule W_rule hwloop_cnt_mux_sel hwloop_cnt_mux_sel rdata_unaligned rdata_unaligned
hwlp_counter_n hwlp_counter_n imm_a_mux_sel imm_a_mux_sel do_fetch do_fetch jump_in_id int_controller_i jump_in_idjump_in_id int_controller_i addr_n addr_int addr_real_next addr_n addr_int addr_real_next addr_n hwloop_regs_i addr_n hwloop_regs_i next_is_crossword pmp_unit_i next_is_crossword pmp_unit_i rdata rdata_unaligned L0_buffer_i CS NS rdata rdata_unaligned L0_buffer_i rdata rdata
EN_rule exc_ctrl_cs EN_rule exc_ctrl_cs X_rule X_rule mult_dot_en controller_i mult_dot_enmult_dot_en mult_dot_en csr_op csr_op csr_op
addr_real_next addr_real_next
irq_id_q irq_id_q decoder_i regfile_mem_we regfile_alu_we data_req hwloop_we csr_illegal jump_in_id csr_op decoder_i regfile_mem_we regfile_alu_we data_req hwloop_we csr_illegal
hwlp_counter_q hwlp_counter_q
do_hwlp do_hwlp
valid valid
addr_int addr_int irq_sec_q irq_sec_q rdata_last_qrdata_last_q rdata_last_qrdata_last_q
regfile_alu_we regfile_alu_we
hwloop_we hwloop_we NS do_fetch do_hwlp NS do_fetch do_hwlp NS NS
use_lastuse_last use_lastuse_last data_req data_req
regfile_mem_we regfile_mem_we
addr_q addr_q
hwlp_is_crossword hwlp_is_crossword
addr_q csr_illegal csr_illegal save_rdata_last addr_q save_rdata_last save_rdata_last save_rdata_last L0_buffer_i busy_L0 L0_buffer_i busy_L0
mult_int_enmult_int_en mult_int_enmult_int_en
do_hwlp_intdo_hwlp_int do_hwlp_intdo_hwlp_int
is_hwlp_q is_hwlp_q
CS CSCS addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec addr_q addr_q instr_addr_int instr_addr_int
save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid decoder_i decoder_i save_rdata_hwlp save_rdata_hwlp
is_crossword is_crossword
illegal_insn_n illegal_insn_n
next_upper_compressed next_upper_compressed
is_hwlp_n is_hwlp_n
L0_buffer L0_buffer ebrk_force_debug_mode ebrk_force_debug_mode ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i ctrl_fsm_ns ctrl_fsm_ns
jump_done_q jump_done_q
NNS S
NS controller_i irq_enable_int L0_buffer irq_enable_int ctrl_fsm_csctrl_fsm_cs ctrl_fsm_cs
instr_valid_irq_flush_q ctrl_fsm_cs instr_valid_irq_flush_q
branch_in_id branch_in_id
illegal_insn_q illegal_insn_q
jump_done jump_done L0_bufferprefetch_buffer_i instr_valid_irq_flush_n prefetch_buffer_i instr_valid_irq_flush_n debug_mode_q debug_mode_q
debug_mode_n debug_mode_n
controller_i data_err_q controller_i data_err_q jump_in_dec jump_in_dec
Figure A.15.: (AO) Output, ALU test Figure A.16.: (AP) Program flow, ALU test
ResInv_SP
cs_registers_i ResInv_SN div_i is_pcmr
ResInv_SP RemSel_SP cs_registers_i ResInv_SN div_i is_pcmr
RemSel_SP
Cnt_DP
is_pcer mcause_n ABComp_S
LoadEn_S RemSel_SN
Cnt_DP
PCCR_q is_pcer mcause_n ABComp_S
BRegEn_S LoadEn_S PCER_n PCER_n RemSel_SN priv_lvl_n CompInv_SP
PCCR_q
BRegEn_S PCER_n
ucause_q priv_lvl_n CompInv_SP
AddMux_D cnt_l1
mtvec_n SState_SPtate_SP State_SP ucause_q
cnt_l3 AReg_DN State_SN AddMux_D cnt_l1
mtvec_n
State_SP ucause_n mscratch_n dscratch1_q
exception_pc cnt_l3 OutMux_D AReg_DN State_SN
dscratch1_n
ucause_n mscratch_n dscratch1_q
exception_pc alu_i cnt_l2 OutMux_D Cnt_DN ResRegEn_S index_lut dscratch1_n PCCR_n
index_nodes
ResReResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith g_DP ResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready cnt_l2
alu_popcnt_i cnt_l1 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN alu_i alu_popcnt_i cnt_l1 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN ResReg_DN ResRegEn_S shift_arishift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed thmetic Cnt_DN shift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed operand_a_rev operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int index_lut
PCCR_n PCCR_inc alu_popcnt_i index_nodes mepc_q PCCR_q ResReg_DP ResReg_DP_rev ResReg_DN shift_arithmetic shuffle_reg0_sel
is_pccr cnt_l4 PCCR_inc alu_popcnt_i
pccr_all_sel mepc_q sel_nodes
ARegEn_S ResReg_DP_rev AReg_DP shuffle_reg0_sel f_is_nan is_pccr alu_ff_i cnt_l4 pmp_reg_n pccr_all_sel sel_nodes AddTmp_D cmp_result ARegEn_S AReg_DP ff_input BReg_DP f_is_nan pmp_reg_q alu_ff_i dcsr_n div_ready pmp_reg_n
AddTmp_D cmp_result radix_2_rev
div_shift ff_input BReg_DN BReg_DP PCMR_n cnt_result pmp_reg_q dcsr_n PCMR_n div_ready
mepc_n radix_2_rev
CompInv_SN div_shift BReg_DN mstatus_n PCMR_n shuffle_r1_in is_greater cnt_result
operand_a_rev adder_op_adder_op_b_negate b_negate adder_op_b_negate operand_a_rev adder_result_expanded mepc_n pmpcfg_we CompInv_SN adder_result_expanded mstatus_n adder_result_expanded shuffle_r1_in is_greater
operand_a_rev adder_op_b_negate sshift_use_roundhift_use_round shift_use_round adder_result_expanded pmpaddr_we
operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int pmpcfg_we operand_a_neg_rev shift_amt_int dscratch0_n csr_wdata_int csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q
PCER_q shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev shift_use_round shift_result utvec_n PCER_q csr_we_int pmpaddr_we operand_a_neg_rev pack_result shift_amt_int dscratch0_n perf_rdata perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr csr_wdata_int cmp_signed
PCER_q shift_result adder_in_a utvec_n is_equal csr_we_int adder_in_a utvec_q dscratch0_q pack_result shuffle_r0_in adder_in_a perf_rdata cmp_signed
uepc_q
shift_amt adder_in_a mscratch_q priv_lvl_q is_equal shuffle_through dscratch0_q utvec_q shuffle_r0_in
shift_left_result uepc_q csr_rdata_int ddiv_validiv_valid shift_op_a div_valid shift_amt mscratch_q priv_lvl_q shift_op_a shuffle_through
mtvec_q shift_op_a shift_left_result csr_rdata_int div_valid mstatus_q depc_q shift_op_a dcsr_q shuffle_result div_op_a_signed bmask
shuffle_r1 mtvec_q
depc_n mstatus_q depc_q dcsr_q shuffle_result div_op_a_signed bmask bextins_result shuffle_r1
PCCR_inc_q sel_minmax depc_n shuffle_r0 PCCR_inc_q
id_valid_q is_equal_clip adder_op_a bextins_result
PCMR_q PCCR_inc_q shuffle_byte_sel sel_minmax mcause_q result_minmax PCMR_q shuffle_r0
uepc_n id_valid_q is_equal_clip adder_op_a
PCMR_q shuffle_byte_sel
pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc mcause_q pccr_index result_minmax radix_4_rev
uepc_n shift_amt_left
radix_8_rev PCCR_in pccr_index is_equal_vec radix_4_rev adder_result adder_op_b sshift_lefthift_left shift_left shift_amt_left
radix_8_rev PCCR_in
is_equal_vec adder_result adder_op_b shift_left
adder_in_b adder_in_b is_greater_vec minmax_b adder_in_b shuffle_reg_sel shift_right_result
adder_in_b
shuffle_reg1_sel is_greater_vec minmax_b shuffle_reg_sel shift_right_result
shuffle_reg1_sel
bitop_result
f_is_greater
bitop_result mult_i f_is_greater mult_i
short_subword
mulh_clearcarry
short_subword ex_stage_i mulh_clearcarry mulh_signed
riscv_coredata_load_event_ex _i data_load_event_ex data_misaligned_ex halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb data_load_event_ex
mulh_NS dot_short_op_b ex_stage_i riscv_core_i mulh_signed mulh_ready data_load_event_ex id_valid
mulh_NS dot_short_op_b
ccsr_access_exsr_access_ex regfile_waddr_lsu regfile_waddr_lsu mult_result regfile_waddr_lsu mulh_ready mmulh_activeulh_active id_valid
mult_clpx_img_ex dot_chadot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i r_mul csr_access_ex regfile_waddr_lsu csr_save_ex ddata_req_exata_req_ex data_req_ex mult_result top mulh_active csr_save_id short_op_b regfile_we_lsuregfile_we_lsu short_op_b dot_short_result mult_clpx_img_ex regfile_we_lsu dot_char_mul csr_save_ex data_req_ex
dot_char_op_b mult_sel_subword_ex dot_char_op_a csr_restore_mret_id irq_sec_i top data_req_pmp csr_save_id short_op_b regfile_we_lsu dot_short_result
mulh_mulh_save mulh_clearcarry mulh_ready save alu_ralu_result mult_result alu_i div_shift esult alu_result mult_result alu_i div_shift dot_char_op_b mult_sel_subword_ex dot_char_op_a regfile_alu_we_fw regfile_alu_we_fw regfile_alu_we_fw csr_restore_mret_id irq_sec_i data_gnt_pmp data_req_pmp u_irq_enable pc_set instr_req_o short_mac data_gnt_i mulh_save alu_result
regfile_alu_we_fw regfile_we_wb regfile_we_wb
regfile_we_wb clpx_shift_result dot_char_op_a dot_char_op_b clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q clpx_shift_result dot_short_op_a data_gnt_pmp u_irq_enable pc_set illegal_c_illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux insn_id illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux short_mac instr_req_o data_gnt_i
m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int mulh_shift_arith m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int clk_i m_irq_enable data_type_ex data_sign_ext_ex
is_compressed_id data_type_ex is_compressed_id is_compressed_id data_type_ex regfile_we_wb clpx_shift_result dot_short_op_a
irq_id_o illegal_c_insn_id csr_hwlp_we exc_pc_mux_id data_signdata_sign_ext_ex _ext_ex mulh_shift_arith clk_i m_irq_enable iinstr_req_intnstr_req_int instr_req_int data_type_ex uuseincr_addr_exseincr_addr_ex is_compressed_id useincr_addr_ex
irq_id_o sec_lvl_o csr_hwlp_we dot_short_mul exc_pc_mux_id short_result data_sign_ext_ex ex_ready data_rvalid_i instr_req_int data_we_o mmulh_immulh_imm short_signed useincr_addr_ex instr_rdata_i csr_irq_sec instr_rvalid_i sec_lvl_o csr_save_if mmulh_carry_qulh_carry_q short_result dot_short_mul ex_ready data_rvalid_i data_we_o
mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i mulh_imm short_signed ddata_misaligned_exata_misaligned_ex mult_operand_a_ex
bmask_a_ex instr_rdata_i csr_irq_sec bmask_a_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex
mult_signed_mode_ex bmask_a_ex branch_in_ex ctrl_busy branch_in_ex ctrl_busy data_be_o branch_in_ex instr_rvalid_i csr_restore_uret_id instr_rdata_id mult_operand_a_ex csr_save_if mulh_carry_q
data_misaligned_ex mult_operand_a_ex irq_id_i short_op_a bmask_a_ex mult_signed_mode_ex branch_in_ex short_op_a data_be_o instr_rdata_id csr_restore_uret_id
bbmask_b_exmask_b_ex mulh_sumulh_subword mulh_signed mulh_shift_arith bword instr_rdata_id bmask_b_ex core_ctrl_firstfetch mulh_CSmulh_CS
clk_en mulh_CS rstn_i irq_id_i short_op_a data_rdata_i instr_gnt_i top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id regfile_alu_we_ex instr_rdata_id top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id regfile_alu_we_ex regfile_alu_we_ex mult_clpx_shift_ex bmask_b_ex mulh_subword mulh_CS alu_clpx_shift_ex core_ctrl_firstfetch mult_dot_op_c_ex
debug_csr_save clk_en rstn_i core_clock_gate_i regfile_alu_wdata_fw data_rdata_i instr_gnt_i data_addr_o regfile_alu_we_ex mult_clpx_shift_ex alu_operand_b_ex alu_clpx_shift_ex mult_dot_op_c_ex
short_shift_arith debug_csr_save alu_operand_a_ex alu_operand_b_ex core_clock_gate_i regfile_alu_wdata_fw data_req_o data_addr_o
mult_dot_signed_ex alu_operand_b_ex
clear_instr_valid aapu_en_expu_en_ex alu_operand_a_ex apu_en_ex short_shift_arith debug_req_i alu_operand_b_ex alu_operand_a_ex csr_addr_int alu_is_subrot_ex instr_addr_o data_req_o
data_wdata_o mult_dot_signed_ex csr_cause perf_pipeline_stall clear_instr_valid apu_en_ex csr_rdata debug_req_i pc_pc_ex ex pc_ex irq_ack_o csr_addr_int instr_addr_o alu_is_subrot_ex
data_wdata_o csr_cause perf_pipeline_stall
csr_rdata pc_ex pc_idpc_id irq_ack_o pc_id regfile_alu_waddr_ex alu_operand_a_ex regfile_alu_waddr_ex regfile_alu_waddr_ex id_ready core_busy_o ddata_reg_offset_exata_reg_offset_ex data_reg_offset_ex
irq_i is_hwlp_id trap_addr_mux
pc_id
regfile_alu_waddr_ex
lsu_rdata id_ready core_busy_o data_reg_offset_ex fetch_enable_i alu_operand_c_ex alu_operand_c_ex irq_i is_hwlp_id trap_addr_mux
mult_dot_op_b_ex alu_operand_c_ex imm_vecimm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex _ext_ex imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex instr_valid_idinstr_valid_id lsu_rdata instr_valid_id fetch_enable_i alu_operand_c_ex
mult_imm_ex
lsu_ready_wb mult_dot_mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i offset_fsm_cs offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 op_a_ex mult_dot_op_b_ex imm_vec_ext_ex instr_valid_id
core_busy_q data_err_pmp
mult_imm_ex ctrl_busy mem lsu_ready_wb mult_dot_op_a_ex mult_operand_c_exmult_operand_c_ex mult_operand_b_ex core_busy_q data_err_pmp exc_cause pc_mux_id alu_vec_mode_ex riscv_register_file_i mult_operand_b_ex ctrl_busy mem mult_operand_c_ex
mult_operand_b_ex is_decodingis_decoding is_decoding exc_cause pc_mux_id alu_vec_mode_ex riscv_register_file_imem data_err_ack alu_operator_exalu_operator_ex alu_operator_ex is_fetch_failed_id mem ddata_misalignedata_misaligned is_fetch_failed_id is_fetch_failed_id is_decoding data_misaligned debug_cause
data_err_ack
regfile_waddr_ex alu_operator_ex data_we_id hwlp_dec_cnt_id regfile_waddr_ex is_fetch_failed_id regfile_waddr_ex csr_ocsr_op_ex p_ex csr_op_ex data_misaligned
debug_cause
if_valid halthalt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb _if
csr_hwlp_regid regfile_waddr_ex mmult_operator_exult_operator_ex mult_operator_ex data_we_id hwlp_dec_cnt_id csr_op_ex rega_usrega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id ed_dec rega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id
csr_scsr_status tatus if_valid hwlp_dec_cnt halt_if csr_status offset_fsm_cs regfile_we_exregfile_we_ex ebrk_insnebrk_insn regfile_we_ex ebrk_insn offset_fsm_cs csr_hwlp_regid alu_is_clpx_ex mult_operator_ex
rega_used_dec
apu_laapu_lat_ex t_ex apu_lat_ex csr_status fencei_insn_dec wwe_a_dece_a_dec we_a_dec lsu_ready_ex fencei_insn_dec hwlp_dec_cnt mult_multicyclemult_multicycle offset_fsm_cs mult_multicycle regfile_we_ex ebrk_insn fencei_insn_dec valid we_b_decwe_b_dec we_b_dec j csr_save_cause alu_is_clpx_ex hwloop_regid hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_start_mux_sel hwloop_cnt_mux_sel hwloop_valid csr_access
ex_valid apu_lat_ex
lsu_ready_ex fencei_insn_dec we_a_dec mult_is_clpx_ex mult_multicycle reg_d_wb_is_reg_a_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec we_b_dec hwloop_we valid j hwloop_start_mux_sel csr_save_cause fetch_addr_n hwloop_regid mult_dot_signed ex_valid
hwloop_controller_i hwlp_target csr_restore_dret_id rdata_offset_qrdata_offset_q rdata_offset_q mult_is_clpx_ex fetch_ready reg_d_wb_is_reg_a_id clk hwloop_we
hwloop_start_mux_sel ddata_we_exata_we_ex fetch_addr_n data_we_ex mult_dot_signed ddata_type_idata_type_id ooperand_a_fw_mux_selperand_a_fw_mux_sel registers_i operand_a_fw_mux_se l operand_b_fw_mux_se operand_c_fw_mux_se bmask_a_mux hwloop_controller_i hwlp_target csr_restore_dret_id instr_req_pmp rdata_offset_q aalu_en_exlu_en_ex alu_en_ex fetch_ready clk
data_rdata_ext fetch_rdata exc_kill alu_op_a_mux_selalu_op_a_mux_sel data_we_ex alu_op_a_mux_sel data_type_id mmult_en_exult_en_ex bmask_b_mux mult_en_ex operand_a_fw_mux_sel bmask_b_mux registers_i
uret_insn_dec pc_is_end_addr instr_req_pmp uret_insn_dec alu_en_ex uret_insn_dec
fetch_is_hwlp hwloop_cnt_int data_rdata_ext fetch_rdata exc_kill alu_op_a_mux_sel
mult_operator mult_en_ex bmask_b_mux
CSCS NS instr_gnt_pmp pc_is_end_addr CS NS uret_insn_dec instr_decompressed rdatardata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr _q rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q mult_imm_mux fetch_is_hwlp hwloop_cnt_int data_addr_int bbmask_b_id_immmask_b_id_imm data_addr_int bmask_b_id_imm hwlp_dec_cnt_if operand_c_foperand_c_fw_mux_se l bmask_a_mux bmask_b_mux alu_bmask_a_mux_se alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm w_mux_sel mult_operator
uret_dec hwloop_we_masked CS instr_gnt_pmp instr_decompressed rdata_q data_addr_int mult_imm_mux exc_pc data_addr_int bmask_b_id_imm aalu_op_b_mux_sellu_op_b_mux_sel alu_op_b_mux_sel hwlp_dec_cnt_if operand_c_fw_mux_sel
trap_base_addr uret_dec hwloop_we_masked
reg_d_ex_isreg_d_ex_is_reg_a_id _reg_a_id regfile_data_ra_id reg_d_ex_is_reg_a_id
exc_pc regfile_data_ra_id alu_op_b_mux_sel
is_hwlp_id_q data_sign_ext_q data_we_q data_sign_ext_q data_we_q data_sign_ext_q operand_a_fw_id trap_base_addr
bmask_a_mux reg_d_ex_is_reg_a_id regfile_data_ra_id illegal_c_insn alu_vecalu_vec_mode _mode regfile_data_ra_id alu_vec_mode hwloop_cnt
jump_target_mux_sel mult_operator mult_int_en mult_sel_subword mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_alu_waddr_mux _sel data_we_id branch_taken_ex jump_target_mux_sel mult_operator mult_int_en mult_sel_subword mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id regfile_alu_waddr_mux _sel data_we_id data_type_id data_sign_ext_id data_req_id rdata_b_ext jump_target_mux_sel ddata_type_qata_type_q id_stage_i is_hwlp_id_q data_sign_ext_q operand_a_fw_id jump_in_id branch_req bmask_a_mux rdata_h_ext illegal_c_insn alu_vec_mode fetch_valid hwloop_cnt branch_taken_ex rdata_b_ext jump_target_mux_sel data_type_q id_stage_i imm_b_mux_sel imm_b_mux_sel imm_b_mux_sel jump_in_id branch_req alu_operand_b rdata_h_ext fetch_valid
offset_fsm_ns imm_b offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0
mret_dec data_signdata_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_start_mux_sel hwloop_cnt_mux_sel hwloop_valid _ext_id mult_int_en imm_b_mux_sel deassert_we imm_i_type imm_b wdata_offset data_we_q wdata_offset wdata_offset ccsr_accesssr_access imm_i_type alu_operand_b compressed_decoder_i alu_operand_a imm_b NS imm_b offset_fsm_ns mret_dec imm_i_type imm_vuimm_vu_type _type imm_vu_type data_sign_ext_id mult_int_en deassert_we imm_i_type wdata_offset data_we_q csr_access
compressed_decoder_i alu_operand_a load_store_unit_i regb_used_dec NS imm_vu_type operand_b
sscalar_replicationcalar_replication scalar_replication ecall_insn_dec ecall_insn_dec ecall_insn_dec regb_used_dec mult_dot_en load_store_unit_i operand_c operand_b is_subrot hwloop_start_int
alu_opalu_operator erator alu_operator scalar_replication ecall_insn_dec mult_dot_en
if_stage_i operand_c mult_signed_mode is_subrot hwloop_start_int
jjump_targetump_target alu_operator jump_target
ooperand_b_fw_mux_selperand_b_fw_mux_sel if_stage_i mult_signed_mode
regc_used_dec load_stall jump_target load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id operand_c_fw_id
operand_b_fw_mux_sel operand_b_fw_id hwloop_target_mux_sel
hwloop_hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i target hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i pipe_flush_decpipe_flush_dec pipe_flush_dec regc_used_dec load_stall operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel hwloop_target pipe_flush_dec
aalu_enlu_en alu_en regfile_alu_waddr_idregfile_alu_waddr_id regfile_alu_waddr_id MODE_rule is_clpx regfile_addr_rc_id mret_insn_dec mask_addr mret_insn_dec mret_insn_dec regfile_alu_we_id regfile_alu_we_id regfile_alu_we_id alu_en operand_b_vec R_rule regfile_alu_waddr_id
MODE_rule is_clpx regfile_addr_rc_id dret_insn_dec data_err_state_q mret_insn_dec dret_insn_dec mask_addr dret_insn_dec
alu_op_c_alu_op_c_mux_sel regc_mux imm_a_mux_sel mux_sel alu_op_c_mux_sel regc_mux imm_a_mux_sel mult_sel_subword regfile_alu_we_id operand_b_vec R_rule
dret_insn_dec data_err_state_q
alu_op_c_mux_sel bmask_a_id_imm mult_sel_subword reg_d_alu_is_reg_a_id jr_stall jr_stall rreg_d_ex_is_reg_b_ideg_d_ex_is_reg_b_id reg_d_ex_is_reg_b_id dret_dec
illegal_insn_dec
bmask_a_id_imm data_req_id data_err_state_n alu_bmask_a_mux_sel alu_bmask_a_mux_se l alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm reg_d_alu_is_reg_a_id jr_stall
reg_d_ex_is_reg_b_id dret_dec
hwloop_mask illegal_insn_dec
regfile_we_id reg_d_ex_isreg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx is_subrot mret_dec uret_dec dret_dec _reg_c_id reg_d_ex_is_reg_c_id
data_req_id data_err_state_n alu_bmask_a_mux_sel stop_addr start_addr hwloop_mask pprepost_useincrrepost_useincr prepost_useincr regfile_we_id reg_d_ex_is_reg_c_id
data_load_event_id regfile_alu_waddr_mux_sel data_load_event_id stop_addr start_addr prepost_useincr
fetch_valid hwloop_valid
halt_id data_load_event_id regfile_alu_waddr_mux_sel
exc_ack
CS hwlp_start_q CS instr_match_region fetch_valid hwloop_valid alu_bmask_b_mux_sel CS halt_id
exc_ack
use_hwlp use_hwlp use_hwlp regc_mux CS hwlp_start_q hwlp_end_q instr_match_region next_valid alu_bmask_b_mux_sel
data_match_region
W_rule hwloop_cnt_mux_sel use_hwlp rdata_unaligned regc_mux hwlp_end_q next_valid
hwlp_counter_n data_match_region imm_a_mux_sel do_fetch jump_in_id jump_in_id W_rule int_controller_i hwloop_cnt_mux_sel rdata_unaligned addaddr_n addr_int addr_real_next r_n hwloop_regs_i addr_n addr_int addr_real_next hwlp_counter_n next_is_crossword pmp_unit_i imm_a_mux_sel do_fetch jump_in_id rdardata rdata_unaligned L0_buffer_i CS NS ta rdata rdata_unaligned L0_buffer_i int_controller_i
addr_n
EN_rule exc_ctrl_cs hwloop_regs_i X_rule next_is_crossword pmp_unit_i mult_dmult_dot_en controller_i ot_en mult_dot_en controller_i csr_op csr_op rdata
addr_real_next
irq_id_q
EN_rule exc_ctrl_cs X_rule decoder_i regfile_mem_we regfile_alu_we data_req hwloop_we csr_illegal jump_in_id csr_op decoder_i regfile_mem_we regfile_alu_we data_req hwloop_we csr_illegal mult_dot_en csr_op hwlp_counter_q addr_real_next
irq_id_q
do_hwlp
valid hwlp_counter_q
addr_int irq_sec_q rdata_last_qrdata_last_q rdata_last_q
regfile_alu_we do_hwlp
valid
addr_int
hwloop_we irq_sec_q
NS do_fetch do_hwlp rdata_last_q NS do_fetch do_hwlp NS
regfile_alu_we
use_lastuse_last use_last data_req
regfile_mem_we hwloop_we addr_q NS
hwlp_is_crossword use_last data_req addr_q regfile_mem_we addr_q csr_illegal
save_rdata_last addr_q save_rdata_last save_rdata_last L0_buffer_i busy_L0 hwlp_is_crossword
mmult_int_enult_int_en mult_int_en
do_hwlp_int csr_illegal do_hwlp_int do_hwlp_int save_rdata_last L0_buffer_i busy_L0
mult_int_en
is_hwlp_q do_hwlp_int
CS CS
addaddr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec r_q addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec instr_addr_int
is_hwlp_q
save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid decoder_i save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid save_rdata_hwlp CS
addr_q instr_addr_int is_crossword decoder_i save_rdata_hwlp
illegal_insn_n
next_upper_compressed is_crossword
is_hwlp_n
illegal_insn_n
next_upper_compressed L0_buffer ebrk_force_debug_mode
is_hwlp_n
ctrl_fsctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i m_ns ctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i
L0_buffer ebrk_force_debug_mode
ctrl_fsm_ns
jump_done_q
NS NS
irq_enable_int
jump_done_q
NS
irq_enable_int ctrl_fsm_cs L0_buffer ctrl_fsm_cs
instr_valid_irq_flush_q ctrl_fsm_cs
branch_in_id ctrl_fsm_cs
instr_valid_irq_flush_q
illegal_insn_q branch_in_id
jump_done illegal_insn_q L0_bufferprefetch_buffer_i instr_valid_irq_flush_n debug_mode_q
jump_done prefetch_buffer_i instr_valid_irq_flush_n
debug_mode_q
debug_mode_n
controller_i data_err_q jump_in_dec debug_mode_n
controller_i data_err_q jump in dec Figure A.17.: (AO) Output, MUL test Figure A.18.: (AP) Program Flow, MUL test
ResInv_SP ResInv_SP
ResInv_SN cs_registers_i ResInv_SN div_i cs_registers_i div_i is_pcmr is_pcmr
RemSel_SP RemSel_SP
Cnt_DP Cnt_DP
is_pcer mcause_n is_pcer mcause_n ABComp_S ABComp_S
LoadEn_S LoadEn_S RemSel_SN RemSel_SN
PCCR_q PCCR_q
BRegEn_S BRegEn_S PCER_n PCER_nPCER_n priv_lvl_n priv_lvl_n CompInv_SP CompInv_SP
ucause_q ucause_q
AddMux_D cnt_l1 AddMux_D cnt_l1
mtvec_n mtvec_n SState_SPtate_SP State_SPState_SP
cnt_l3 cnt_l3 AReg_DN State_SN AReg_DN State_SN
mscratch_n dscratch1_q ucause_n mscratch_n dscratch1_q ucause_n
exception_pc exception_pc
OutMux_D OutMux_D
dscratch1_n dscratch1_n
alu_i cnt_l2 alu_i cnt_l2 ResRegEn_S Cnt_DN ResRegEn_S index_lut Cnt_DN index_lut
PCCR_n PCCR_n
index_nodes index_nodes
ResReResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready g_DP ResRegResReg_DP ResReg_DN ResReg_DP_rev AReg_DP AReg_DN BReg_DP BReg_DN AddMux_D AddTmp_D OutMux_D mult_i short_subword short_signed short_shift_arith mulh_imm mulh_subword mulh_signed mulh_shift_arith mulh_carry_q mulh_active mulh_save mulh_clearcarry mulh_ready _DP alu_popcnt_i cnt_l1 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN alu_popcnt_i cnt_l1 cnt_l3 cnt_l4 alu_ff_i index_lut index_nodes sel_nodes div_i RemSel_SN RemSel_SP CompInv_SN CompInv_SP ResInv_SN ResInv_SP Cnt_DP Cnt_DN ARegEn_S BRegEn_S ResRegEn_S ABComp_S LoadEn_S State_SN ResReg_DN ResReg_DN shift_arishift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed thmetic shift_arithshift_arithmetic is_equal is_greater f_is_greater cmp_signed is_equal_vec is_greater_vec is_equal_clip cmp_result f_is_nan sel_minmax shuffle_byte_sel shuffle_reg_sel shuffle_reg1_sel shuffle_reg0_sel shuffle_through cnt_result bitop_result div_ready div_op_a_signed metic
PCCR_inc alu_popcnt_i PCCR_inc alu_popcnt_i mepc_q PCCR_qmepc_q ResReg_DP_rev ResReg_DP_rev shuffle_reg0_sel shuffle_reg0_sel
is_pccr is_pccr cnt_l4 cnt_l4
pccr_all_sel pccr_all_sel sel_nodes sel_nodes
ARegEn_S ARegEn_S AReg_DP AReg_DP f_is_nan alu_ff_i f_is_nan alu_ff_i pmp_reg_n pmp_reg_n cmp_result AddTmp_D cmp_result AddTmp_D
ff_input ff_input BReg_DP BReg_DP pmp_reg_q pmp_reg_q dcsr_n dcsr_n div_ready div_ready
radix_2_rev radix_2_rev
div_shift div_shift BReg_DN BReg_DN PCMR_n PCMR_n cnt_result PCMR_n cnt_result
mepc_n mepc_n CompInv_SN CompInv_SN
mstatus_n mstatus_n is_greater shuffle_r1_in is_greater shuffle_r1_in
operand_a_revoperand_a_rev adder_op_adder_op_b_negate b_negate operand_a_revoperand_a_rev adder_op_badder_op_b_negate _negate adder_result_expanded adder_result_expanded pmpcfg_we adder_result_expanded pmpcfg_we adder_result_expanded
sshift_use_roundhift_use_round shshift_use_roundift_use_round
pmpaddr_we pmpaddr_we operand_aoperand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int _neg_rev operand_a_operand_a_neg_rev bmask adder_op_a adder_op_b adder_result shift_amt_left shift_amt shift_amt_int neg_rev shift_amt_int shift_amt_int dscratch0_n dscratch0_n csr_wdata_int csr_wdacsr_wdata_int csr_rdata_int mepc_q mepc_n uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q ta_int
PCER_q
PCER_q shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev shift_result shift_right_result shift_left_result result_minmax minmax_b shuffle_r1 shuffle_r0 shuffle_r1_in shuffle_r0_in shuffle_result pack_result ff_input bextins_result radix_2_rev radix_4_rev radix_8_rev shift_result shift_result utvec_n utvec_n csr_we_int PCER_q csr_we_int pack_result pack_result
perf_rdata perf_rdperf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr ata cmp_signed cmp_signed
adder_in_a adder_in_a is_equal is_equal utvec_q dscratch0_q utvec_q dscratch0_q shuffle_r0_in adder_in_a shuffle_r0_in adder_in_a
uepc_q uepc_q
shift_amt shift_amt priv_lvl_q mscratch_q priv_lvl_q mscratch_q shuffle_through shuffle_through
shift_left_result shift_left_result
csr_rdata_int csr_rdata_int ddiv_validiv_valid div_valid shift_op_ashift_op_a shift_op_ashift_op_a div_valid mtvec_q mtvec_q
mstatus_q mstatus_q depc_q depc_q dcsr_q dcsr_q shuffle_result shuffle_result div_op_a_signed div_op_a_signed bmask bmask
shuffle_r1 shuffle_r1
depc_n depc_n
bextins_result bextins_result
PCCR_inc_q PCCR_inc_q sel_minmax PCCR_inc_q sel_minmax shuffle_r0 shuffle_r0
is_equal_clip id_valid_q is_equal_clip id_valid_q adder_op_a adder_op_a
PCMR_q PCMR_q shuffle_byte_sel shuffle_byte_sel mcause_q mcause_q result_minmax PCMR_q result_minmax
uepc_n uepc_n
pccr_index pccr_inpccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc dex radix_4_rev radix_4_rev
shift_amt_left shift_amt_left
radix_8_rev radix_8_rev PCCR_in PCCR_in
is_equal_vec is_equal_vec adder_result adder_result adder_op_b adder_op_b sshift_lefthift_left shshift_leftift_left
adder_in_b adder_in_b
is_greater_vec is_greater_vec minmax_b minmax_b adder_in_b shuffle_reg_sel adder_in_b shuffle_reg_sel shift_right_result shift_right_result
shuffle_reg1_sel shuffle_reg1_sel
bitop_result bitop_result f_is_greater mult_i f_is_greater mult_i
short_subword short_subword ex_stage_i mulh_clearcarry ex_stage_i mulh_clearcarry mulh_signed mulh_signed
data_load_event_ex riscv_coredata_load_event_ex _i riscv_core_i data_load_event_ex data_load_event_ex
mulh_NS mulh_NS dot_short_op_b dot_short_op_b
mulh_ready mulh_ready id_valid id_valid
ccsr_access_exsr_access_ex regfile_waddr_lsu cscsr_access_exr_access_ex regfile_waddr_lsu mult_result regfile_waddr_lsu mult_result regfile_waddr_lsu
mulh_active mulh_active
dot_char_mul mult_clpx_img_ex dot_char_mul mult_clpx_img_ex csr_save_ex csr_save_ex ddata_req_exata_req_ex top ddata_req_exata_req_ex top csr_save_id short_op_b csr_save_id short_op_b rregfile_we_lsuegfile_we_lsu dot_short_result reregfile_we_lsugfile_we_lsu dot_short_result
dot_char_op_b dot_char_op_b mult_sel_subword_ex dot_char_op_a mult_sel_subword_ex dot_char_op_a csr_restore_mret_id csr_restore_mret_id irq_sec_i irq_sec_i data_req_pmp data_req_pmp
mulh_save mulh_save alu_realu_result mult_result alu_i div_shift sult alu_realu_result mult_result alu_i div_shift sult
rregfile_alu_we_fwegfile_alu_we_fw reregfile_alu_we_fwgfile_alu_we_fw
data_gnt_pmp data_gnt_pmp u_irq_enable u_irq_enable pc_set pc_set short_mac instr_req_o short_mac instr_req_o data_gnt_i data_gnt_i
regfile_we_wb regfile_wregfile_we_wb e_wb regfile_we_wb clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i clpx_shift_result dot_char_op_a dot_char_op_b short_op_a short_op_b dot_char_mul dot_short_op_a dot_short_op_b short_mac short_result dot_short_result dot_short_mul load_store_unit_i data_type_q dot_short_op_a clpx_shift_result dot_short_op_a clpx_shift_result
illegal_c_illegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux insn_id illegal_c_iillegal_c_insn_id clear_instr_valid pc_set pc_mux_id exc_pc_mux_id exc_cause trap_addr_mux nsn_id
clk_i mulh_shift_arith m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int mulh_shift_arith m_irq_enable u_irq_enable csr_irq_sec csr_save_cause csr_save_if csr_save_id csr_save_ex csr_cause csr_restore_mret_id csr_restore_uret_id csr_restore_dret_id debug_cause debug_csr_save csr_hwlp_regid csr_hwlp_we perf_pipeline_stall core_ctrl_firstfetch core_busy_q data_req_pmp data_gnt_pmp data_err_pmp data_err_ack instr_req_pmp instr_gnt_pmp mult_is_clpx_ex csr_addr_int clk_i m_irq_enable m_irq_enable
data_type_ex
is_compressed_id ddata_type_exata_type_ex is_compressed_id data_type_ex is_compressed_id is_compressed_id
irq_id_o irq_id_o
csr_hwlp_we csr_hwlp_we exc_pc_mux_id exc_pc_mux_id data_signdata_sign_ext_ex _ext_ex data_sign_data_sign_ext_ex ext_ex iinstr_req_intnstr_req_int instr_req_intinstr_req_int uuseincr_addr_exseincr_addr_ex uuseincr_addr_exseincr_addr_ex
sec_lvl_o sec_lvl_o dot_short_mul short_result dot_short_mul short_result ex_ready ex_ready data_rvalid_i data_rvalid_i data_we_o data_we_o mulh_imm short_signed mulh_imm short_signed instr_rdata_i csr_irq_sec instr_rdata_i csr_irq_sec instr_rvalid_i instr_rvalid_i
csr_save_if csr_save_if mulh_carry_q mulh_carry_q
mult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i mult_operamult_operand_a_ex mult_operand_b_ex mult_operand_c_ex mult_dot_op_a_ex mult_dot_op_b_ex mult_dot_op_c_ex regfile_alu_wdata_fw csr_rdata lsu_rdata core_clock_gate_i clk_en if_stage_i nd_a_ex ddata_misaligned_exata_misaligned_ex mult_operand_a_ex ddata_misaligned_exata_misaligned_ex bmask_a_ex bmask_a_ex
mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex mult_signed_mode_ex mult_imm_ex mult_dot_signed_ex mult_clpx_shift_ex mult_clpx_img_ex bmask_a_ex mult_signed_mode_ex bmask_a_ex branch_in_ex ctrl_busy mult_signed_mode_ex branch_branch_in_ex ctrl_busy in_ex data_be_o branch_in_ex data_be_o instr_rdata_id csr_restore_uret_id instr_rdata_id csr_restore_uret_id
irq_id_i short_op_a irq_id_i short_op_a
bmask_b_exbmask_b_ex mulh_subword bmask_b_exbmask_b_ex mulh_subword mulh_CS mulh_CS core_ctrl_firstfetch mulh_CS core_ctrl_firstfetch
clk_en clk_en rstn_i rstn_i mulh_CS data_rdata_i instr_gnt_i data_rdata_i instr_gnt_i top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id regfile_alu_we_ex top clk_i rstn_i instr_gnt_i instr_rvalid_i data_gnt_i data_rvalid_i irq_i irq_id_i irq_sec_i debug_req_i fetch_enable_i instr_rdata_i data_rdata_i instr_req_o data_req_o data_we_o data_be_o irq_ack_o irq_id_o sec_lvl_o core_busy_o instr_addr_o data_addr_o data_wdata_o riscv_core_i clk is_hwlp_id hwlp_dec_cnt_id regfile_alu_we_ex regfile_alu_we_ex mult_clpx_shift_ex regfile_alu_we_ex mult_clpx_shift_ex
alu_clpx_shift_ex alu_clpx_shift_ex instr_rdata_idmult_dot_op_c_ex instr_rdata_idmult_dot_op_c_ex debug_csr_save debug_csr_save core_clock_gate_i core_clock_gate_i regfile_alu_wdata_fw regfile_alu_wdata_fw data_addr_o data_addr_o
alu_operand_b_ex alu_operand_b_ex
short_shift_arith short_shift_arith alu_operand_a_ex alu_operand_a_ex
data_req_o data_req_o
mult_dot_signed_ex mult_dot_signed_ex
apu_en_ex clear_instr_valid aapu_en_expu_en_ex clear_instr_valid apu_en_ex debug_req_i debug_req_i alu_operand_b_ex csr_addr_int csr_addr_int alu_is_subrot_ex instr_addr_o alu_operand_b_ex alu_is_subrot_ex instr_addr_o
data_wdata_o data_wdata_o csr_cause alu_operand_a_excsr_cause perf_pipeline_stall perf_pipeline_stall
csr_rdata csr_rdata pc_pc_ex ex pc_epc_ex x irq_ack_o irq_ack_o
ppc_idc_id ppc_idc_id regfile_alu_waddr_ex regfile_alu_waddr_exregfile_alu_waddr_ex regfile_alu_waddr_ex id_ready data_reg_offset_ex id_ready ddata_reg_offset_exata_reg_offset_ex alu_operand_a_ex core_busy_o data_reg_offset_ex core_busy_o
is_hwlp_id trap_addr_mux irq_i is_hwlp_id trap_addr_mux irq_i
lsu_rdata lsu_rdata fetch_enable_i alu_operand_c_exalu_operand_c_ex fetch_enable_i alu_operand_c_exalu_operand_c_ex
mult_dot_op_b_ex mult_dot_op_b_ex
imm_vecimm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex _ext_ex imm_vec_imm_vec_ext_ex alu_vec_mode_ex alu_is_clpx_ex alu_is_subrot_ex alu_clpx_shift_ex mult_operator_ex ext_ex instr_valid_idinstr_valid_id instr_valid_idinstr_valid_id
mult_imm_ex mult_imm_ex
lsu_ready_wb mult_dot_op_a_ex lsu_ready_wb mult_dot_op_a_ex
core_busy_q core_busy_q data_err_pmp data_err_pmp
ctrl_busy mem ctrl_busy mem mult_operand_c_ex mult_operand_c_ex
mult_operand_b_ex mult_operand_b_ex
exc_cause pc_mux_id exc_cause pc_mux_id alu_vec_mode_ex riscv_register_file_i mem alu_vec_mode_ex riscv_register_file_i mem
is_decodingis_decoding is_decodingis_decoding
data_err_ack data_err_ack alu_operator_ex alu_operator_ex
is_fetch_failed_id is_fetch_failed_id is_fetch_failed_id alu_operator_ex ddata_misalignedata_misaligned is_fetch_failed_id alu_operator_ex data_misaligneddata_misaligned debug_cause debug_cause
regfile_waddr_ex regfile_waddr_ex ddata_we_idata_we_id ddata_we_idata_we_id hwlp_dec_cnt_id regfile_waddr_ex hwlp_dec_cnt_id
csr_op_ex regfile_waddr_ex csr_op_ex csr_op_ex csr_op_ex
if_valid if_valid halthalt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb _if halt_halt_if id_ready ex_ready id_valid ex_valid lsu_ready_ex lsu_ready_wb if
csr_hwlp_regid csr_hwlp_regid mult_operator_ex mult_operator_ex
rega_usrega_used_dec regb_used_dec regc_used_dec branch_taken_ex jump_in_id jr_stall load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id ed_dec rega_userega_used_dec regb_used_dec regc_used_dec d_dec
csr_scsr_status tatus csr_status hwlp_dec_cnt csr_status offset_fsm_csoffset_fsm_cs hwlp_dec_cnt rregfile_we_exegfile_we_ex ebrk_insnebrk_insn offset_fsm_csoffset_fsm_cs reregfile_we_exgfile_we_ex ebrk_insnebrk_insn alu_is_clpx_ex alu_is_clpx_ex
apu_laapu_lat_ex t_ex apu_laapu_lat_ex t_ex fencei_insn_dec we_a_dec lsu_ready_ex fencei_insn_dec we_a_decwe_a_dec lsu_ready_ex we_a_dec mult_multicycle fencei_insn_dec mult_multicycle mult_multicycle fencei_insn_dec we_b_dec valid we_b_decwe_b_dec valid mult_multicycle we_b_dec j j csr_save_cause csr_save_cause hwloop_regid hwloop_hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_start_mux_sel hwloop_cnt_mux_sel hwloop_valid regid
ex_valid ex_valid
mult_is_clpx_ex mult_is_clpx_ex reg_d_wb_is_reg_a_id reg_d_wb_isreg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx _reg_a_id hwloop_we hwloop_we
hwloop_start_mux_sel hwloop_start_mux_sel fetch_addr_n fetch_addr_n mult_dot_signed mult_dot_signed
csr_restore_dret_id hwloop_controller_i hwlp_target csr_restore_dret_id hwloop_controller_i hwlp_target rrdata_offset_qdata_offset_q rdrdata_offset_qata_offset_q fetch_ready fetch_ready clk clk
ddata_we_exata_we_ex ddata_we_exata_we_ex
data_tydata_type_id data_sign_ext_id data_req_id data_load_event_id hwloop_regid hwloop_we hwloop_we_masked hwloop_target_mux_se l hwloop_start_mux_sel hwloop_cnt_mux_sel hwloop_valid pe_id data_typdata_type_id data_sign_ext_id data_req_id e_id ooperand_a_fw_mux_selperand_a_fw_mux_sel registers_i ooperand_a_fw_mux_selperand_a_fw_mux_sel registers_i
instr_req_pmp instr_req_pmp aalu_en_exlu_en_ex aalu_en_exlu_en_ex
data_rdata_ext data_rdata_ext fetch_rdata fetch_rdata exc_kill exc_kill alu_op_a_mux_selalu_op_a_mux_sel alu_op_a_mux_selalu_op_a_mux_sel mult_en_ex mmult_en_exult_en_ex bbmask_b_muxmask_b_mux mult_en_ex bbmask_b_muxmask_b_mux
uret_insn_dec pc_is_end_addr uret_insn_decuret_insn_dec pc_is_end_addr uret_insn_dec fetch_is_hwlp fetch_is_hwlp hwloop_cnt_int hwloop_cnt_int
mult_operator mult_operator
CCSS instr_gnt_pmp CCSS instr_gnt_pmp
rdata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q PCMR_n PCMR_q pccr_index pccr_all_sel is_pccr is_pcer is_pcmr pmpaddr_we pmpcfg_we PCCR_in PCCR_inc PCCR_inc_q PCER_n PCER_q csr_wdata_int csr_rdata_int mepc_q mepc_n uepc_n dcsr_q dcsr_n depc_q depc_n dscratch0_q dscratch0_n dscratch1_q dscratch1_n mscratch_q mscratch_n exception_pc mtvec_n mtvec_q utvec_n utvec_q PCCR_q PCCR_n perf_rdata pmp_reg_q pmp_reg_n pmp_unit_i MODE_rule data_err_state_q data_err_state_n EN_rule R_rule W_rule X_rule data_match_region instr_match_region mask_addr start_addr stop_addr rdatardata_q data_rdata_ext rdata_h_ext rdata_b_ext cs_registers_i csr_we_int mstatus_q mstatus_n mcause_q mcause_n ucause_q ucause_n priv_lvl_n priv_lvl_q _q instr_decompressed rdata_q instr_decompressed mult_imm_mux mult_imm_mux
data_addr_int data_addr_int bmask_b_id_immbmask_b_id_imm bmask_b_id_immbmask_b_id_imm hwlp_dec_cnt_if operand_c_foperand_c_fw_mux_se l bmask_a_mux w_mux_sel hwlp_dec_cnt_if operand_c_fwoperand_c_fw_mux_se l bmask_a_mux _mux_sel
uret_dec uret_dec data_addr_int hwloop_we_masked data_addr_int hwloop_we_masked
exc_pc exc_pc alu_op_b_mux_selalu_op_b_mux_sel aalu_op_b_mux_sellu_op_b_mux_sel
trap_base_addr trap_base_addr
reg_d_ex_is_reg_a_id rereg_d_ex_is_reg_a_idg_d_ex_is_reg_a_id regfile_data_ra_id regfile_data_ra_id
is_hwlp_id_q data_sign_ext_q data_we_q is_hwlp_id_q data_signdata_sign_ext_q data_we_q _ext_q data_sign_ext_q operand_a_fw_id operand_a_fw_id regfile_data_ra_id bmask_a_mux regfile_data_ra_id bmask_a_mux illegal_c_insn illegal_c_insn alu_vecalu_vec_mode scalar_replication reg_d_ex_is_reg_a_id reg_d_ex_is_reg_b_id reg_d_ex_is_reg_c_id reg_d_wb_is_reg_a_id reg_d_alu_is_reg_a_id is_clpx _mode alu_vec_alu_vec_mode scalar_replication mode
hwloop_cnt hwloop_cnt jump_target_mux_sel mult_operator mult_int_en mult_sel_subword mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id branch_taken_ex jump_target_mux_sel mult_operator mult_int_en mult_sel_subword mult_signed_mode mult_dot_en mult_dot_signed regfile_we_id bbranch_taken_exranch_taken_ex jump_target_mux_sel rdata_b_ext jump_target_mux_sel rdata_b_ext data_type_q id_stage_i ddata_type_qata_type_q id_stage_i
jump_in_id jump_injump_in_id _id branch_req branch_req
rdata_h_ext rdata_h_ext fetch_valid fetch_valid
imm_b_mux_selimm_b_mux_sel imm_b_mux_selimm_b_mux_sel alu_operand_b alu_operand_b
offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 offset_fsm_ns if_valid valid branch_req fetch_valid fetch_ready is_hwlp_id_q fetch_is_hwlp hwlp_dec_cnt hwlp_dec_cnt_if illegal_c_insn fetch_addr_n fetch_rdata exc_pc hwlp_target trap_base_addr instr_decompressed prefetch_buffer_i busy_L0 imm_b offset_fsm_ns imm_b offset_fsm_ns
mret_mret_dec uret_dec dret_dec dec mret_dmret_dec uret_dec dret_dec ec data_sign_ext_id mult_int_en data_sign_ext_id mult_int_en deassert_we deassert_we imm_i_type imm_i_type wwdata_offsetdata_offset wwdata_offsetdata_offset data_we_q data_we_q ccsr_accesssr_access cscsr_accessr_access
alu_operand_a compressed_decoder_i alu_operand_a
compressed_decoder_i NS NS NS imm_b NS imm_b imm_i_type imm_vuimm_vu_type _type imm_i_type imm_vu_imm_vu_type type
load_store_unit_i regb_used_dec load_store_unit_i regb_used_dec operand_b operand_b
scalar_replication scalar_replication ecall_insn_dec ecall_insn_dec ecall_insn_dec mult_dot_en ecall_insn_dec mult_dot_en
operand_c operand_c iis_subrots_subrot isis_subrot_subrot hwloop_start_int hwloop_start_int if_stage_i alu_opalu_operator erator if_stage_i alu_opealu_operator rator mult_signed_mode mult_signed_mode
jjump_targetump_target jujump_targetmp_target
ooperand_b_fw_mux_selperand_b_fw_mux_sel ooperand_b_fw_mux_selperand_b_fw_mux_sel
regc_used_dec load_stall hwloop_mask halt_id exc_ack exc_kill regfile_addr_rc_id regc_used_dec load_stall load_stall operand_c_fw_id operand_c_fw_id
operand_b_fw_id hwloop_target_mux_sel operand_b_fw_id hwloop_target_mux_sel hwloop_hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i target hwloop_hwloop_target hwloop_start_int hwloop_cnt hwloop_cnt_int operand_a_fw_id operand_b_fw_id operand_c_fw_id operand_b operand_b_vec operand_c alu_operand_a alu_operand_b registers_i riscv_register_file_i target pipe_flush_decpipe_flush_dec pipe_flush_decpipe_flush_dec
alu_enalu_en aalu_enlu_en regfile_alu_waddr_id regfile_alu_waddr_id
is_clpx MODE_rule is_clpx regfile_addr_rc_id regfile_alu_waddr_id MODE_rule regfile_addr_rc_id regfile_alu_waddr_id mret_insn_dec mret_insn_dec mask_addr mret_insn_dec mask_addr mret_insn_dec
regfile_alregfile_alu_we_id u_we_id regfile_aluregfile_alu_we_id _we_id operand_b_vec operand_b_vec R_rule R_rule
dret_insn_dec dret_insn_dec data_err_state_q dret_insn_dec data_err_state_q dret_insn_dec
alu_op_c_alu_op_c_mux_sel regc_mux imm_a_mux_sel mux_sel alu_op_c_malu_op_c_mux_sel regc_mux imm_a_mux_sel ux_sel mult_sel_subword mult_sel_subword
bmask_a_id_imm bmask_a_id_imm
jr_stall reg_d_alu_is_reg_a_id jr_stall reg_d_alu_is_reg_a_id reg_d_ex_is_reg_b_id jr_stall reg_d_ex_is_reg_b_id reg_d_ex_is_reg_b_id dret_dec dret_dec
illegal_insn_dec illegal_insn_dec
data_req_id data_req_id data_err_state_n data_err_state_n alu_bmask_alu_bmask_a_mux_se l alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm a_mux_sel alu_bmask_aalu_bmask_a_mux_se l alu_bmask_b_mux_se mult_imm_mux bmask_a_id_imm _mux_sel
hwloop_mask hwloop_mask reg_d_ex_is_reg_c_id regfile_we_id reg_d_ex_is_reg_c_id regfile_we_id reg_d_ex_is_reg_c_id
stop_addr stop_addr start_addr start_addr pprepost_useincrrepost_useincr pprepost_useincrrepost_useincr
data_load_event_id data_load_event_id rregfile_alu_waddr_mux_selegfile_alu_waddr_mux_sel reregfile_alu_waddr_mux_selgfile_alu_waddr_mux_sel data_load_event_id
fetch_valid hwloop_valid fetch_valid hwloop_valid
halt_id halt_id
exc_ack exc_ack
CS CSCS hwlp_start_q hwlp_start_q instr_match_region instr_match_region CS alu_bmask_b_mux_sel alu_bmask_b_mux_sel
uuse_hwlpse_hwlp use_hwlp regc_mux use_hwlp regc_mux hwlp_end_q hwlp_end_q next_valid next_valid
data_match_region data_match_region
W_rule W_rule hwloop_cnt_mux_sel hwloop_cnt_mux_sel rdata_unaligned rdata_unaligned
hwlp_counter_n hwlp_counter_n imm_a_mux_sel imm_a_mux_sel do_fetch do_fetch jump_in_id int_controller_i jujump_in_idmp_in_id int_controller_i addaddr_n addr_int addr_real_next r_n hwloop_regs_i addr_addr_n addr_int addr_real_next n hwloop_regs_i next_is_crossword pmp_unit_i next_is_crossword pmp_unit_i
rdardata rdata_unaligned L0_buffer_i CS NS ta rdatrdata rdata_unaligned L0_buffer_i a
EN_rule exc_ctrl_cs EN_rule exc_ctrl_cs X_rule X_rule
mmult_dot_enult_dot_en mmult_dot_enult_dot_en
csr_op csr_ocsr_op p
addr_real_next addr_real_next
irq_id_q irq_id_q decoder_i decoder_i
hwlp_counter_q hwlp_counter_q
do_hwlp do_hwlp
valid valid
addr_int addr_int irq_sec_q irq_sec_q rdata_last_qrdata_last_q rdata_last_qrdata_last_q
regfile_aregfile_alu_we data_req hwloop_we csr_illegal jump_in_id csr_op lu_we regfile_aregfile_alu_we data_req hwloop_we csr_illegal lu_we
hwloop_we hwloop_we NSNS do_fetch do_hwlp NSNS do_fetch do_hwlp
use_lastuse_last use_lastuse_last data_req data_req
rregfile_mem_weegfile_mem_we reregfile_mem_wegfile_mem_we
addr_q addr_q hwlp_is_crossword addr_q hwlp_is_crossword csr_illegal csr_illegal
save_rdata_last addr_q save_rdata_last save_rdata_last save_rdata_last L0_buffer_i busy_L0 L0_buffer_i busy_L0
mmult_int_enult_int_en mmult_int_enult_int_en
do_hwlp_intdo_hwlp_int do_hwlp_intdo_hwlp_int
is_hwlp_q is_hwlp_q
CS CCSS
addaddr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec r_q addr_addr_q instr_addr_int hwloop_controller_i pc_is_end_addr j compressed_decoder_ i id_stage_i deassert_we illegal_insn_dec q instr_addr_int instr_addr_int
save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid save_rdata_hwlp valid hwlp_is_crossword is_crossword next_is_crossword next_valid next_upper_compresse d is_hwlp_q is_hwlp_n fetch_valid decoder_i decoder_i save_rdata_hwlp save_rdata_hwlp
is_crossword is_crossword
illegal_insn_n illegal_insn_n
next_upper_compressed next_upper_compressed
is_hwlp_n is_hwlp_n
L0_buffer L0_buffer ebrk_force_debug_mode ebrk_force_debug_mode
ctrl_fsctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i m_ns ctrl_fsmctrl_fsm_ns jump_done jump_done_q jump_in_dec branch_in_id irq_enable_int data_err_q debug_mode_q debug_mode_n ebrk_force_debug_mo de illegal_insn_q illegal_insn_n instr_valid_irq_flush_n instr_valid_irq_flush_q int_controller_i exc_ctrl_cs irq_id_q irq_sec_q hwloop_regs_i hwlp_start_q hwlp_end_q hwlp_counter_q hwlp_counter_n ex_stage_i _ns
jump_done_q jump_done_q
NS NSNS controller_i controller_i
irq_enable_int irq_enable_int
ctrl_fsm_csctrl_fsm_cs ctrl_fsm_cs instr_valid_irq_flush_q ctrl_fsm_cs instr_valid_irq_flush_q branch_in_id branch_in_id
illegal_insn_q illegal_insn_q
jump_done jump_done L0_bufferprefetch_buffer_i instr_valid_irq_flush_n L0_bufferprefetch_buffer_i instr_valid_irq_flush_n debug_mode_q debug_mode_q
debug_mode_n debug_mode_n
controller_i data_err_q controller_i data_err_q jump_in_dec jump_in_dec
Figure A.19.: (AO) Output, AES test Figure A.20.: (AP) Program flow, AES test 81 A. Appendix
Fault Effect Causation - Heat Maps
normed effect count 1 5000
0.8 4000
0.6 3000
0.4
space [targetbit] 2000
0.2 1000
0 0 0 1000 2000 3000 4000 5000
time [exe. cycle] Figure A.21.: Hang-up pipeline stall, ALU test - heat map
normed effect count 1 5000
0.8 4000
0.6 3000
0.4
space [targetbit] 2000
0.2 1000
0 0 0 1000 2000 3000 4000 5000
time [exe. cycle] Figure A.22.: Hang-up logic stall, ALU test - heat map
82 normed effect count 1 5000
0.8 4000
0.6 3000
0.4
space [targetbit] 2000
0.2 1000
0 0 0 1000 2000 3000 4000 5000
time [exe. cycle] Figure A.23.: System errors, ALU test - heat map
normed effect count 1 5000
0.8 4000
0.6 3000
0.4
space [targetbit] 2000
0.2 1000
0 0 0 1000 2000 3000 4000 5000
time [exe. cycle] Figure A.24.: Application errors, ALU test - heat map
83 A. Appendix
84 Bibliography
Baumann, R. (2005): Soft errors in advanced computer systems, IEEE Design Test of Com- puters 22(3): 258–266.
Baze, M. P., Buchner, S. P. & McMorrow, D. (2000): A digital cmos design technique for seu hardening, IEEE Transactions on Nuclear Science 47(6): 2603–2608.
Cho, Hyungmin, Mirkhani, Shahrzad, Cher, Chen-Yong, Abraham, Jacob A. & Mitra, Subha- sish (2013): Quantitative evaluation of soft error injection techniques for robust system design, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) S. 1.
Dittrich, Martin (2017): Schnelle Fehlereffektsimulation f¨urSoft-Errors in der Pipeline von RISC-Prozessoren, Master’s thesis, TUM.
ETH Z¨urich, University of Bologna (n.d.a): PULP platform. https://pulp-platform.org/
ETH Z¨urich, University of Bologna (n.d.b): RI5C-Y: RISC-V core. https://github.com/pulp-platform/riscv
Geier, Johannes (2019): Automated extraction and categorization of signals in register transfer level simulators, Student report, TUM.
Gephi (n.d.): Gephi force atlas 2. https://github.com/gephi/gephi/wiki/Force-Atlas-2
IEEE Computer Society (2001): IEEE Standard Verilog hardware description language, Bd. 2005.
IEEE Computer Society (2009): IEEE Standard for SystemVerilog - Unified hardware de- sign, specification, and verification language, IEEE Standards Association 2012(Novem- ber): 1285.
Krste Asanovic, Rimas Avizienis, Jacob Bachmeyer, Christopher F. Batten, Allen, J. Baum, Alex Bradbury, Scott Beamer, Preston Briggs, Christopher Celio, David Chisnall, Paul, Clayton, Palmer Dabbelt, Stefan Freudenberger, Jan Gray, Michael Hamburg, John Hauser, David, Horner, Olof Johansson, Ben Keller, Yunsup Lee, Joseph Myers, Rishiyur Nikhil, Stefan O’Rear, Albert Ou, John Ousterhout, David Patterson, Colin Schmidt, Michael Taylor, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray VanDeWalker,
85 Bibliography
Megan Wachs, Andrew Waterman, Robert Wat, Son & Zandijk., Reinoud (2017): The RISC-V Instruction Set Manual v2.2, 2012 IEEE International Conference on Industrial Technology, ICIT 2012, Proceedings I: 1–32.
Leveugle, R., Calvez, A., Maistri, P. & Vanhauwaert, P. (2009): Statistical fault injection: Quantified error and confidence, 2009 Design, Automation Test in Europe Conference Exhibition, S. 502–506.
LLVM Foundation (n.d.): The LLVM compiler infrastructure. https://llvm.org/
Maniatakos, Michail, Karimi, Naghmeh, Tirumurti, Chandra, Jas, Abhijit & Makris, Yiorgos (2011): Instruction-level impact analysis of low-level faults in a modern microprocessor controller, IEEE Transactions on Computers 60(9): 1260–1273.
Microchip Technology Inc. (n.d.): Radiation tolerant devices. https://www.microchip.com/design-centers/aerospace-and-defense/ radiation-tolerant
RISC-V (n.d.): RISC-V GNU toolchain. https://github.com/riscv/riscv-gnu-toolchain
SiFive (n.d.): RISC-V QEMU part 1: Privileged ISA v1.10, HiFive1 and VirtIO. https://www.sifive.com/blog/risc-v-qemu-part-1-privileged-isa-hifive1-virtio
Traber, Andreas, Gautschi, Michael & Schiavone, Pasquale Davide (2019): RI5CY : User Manual, (August): 1–57. https://www.pulp-platform.org/docs/ri5cy{_}user{_}manual.pdf
TUM EI EDA (n.d.): ETISS repository. https://github.com/tum-ei-eda/etiss
Veripool (n.d.): Introduction to Verilator. https://www.veripool.org/wiki/verilator
Waterman, Andrew, Lee, Yunsup & Patterson, David (2014): The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, I.
Weinzierl, Josef (2017): Cross-layer resilience against soft errors for embedded control systems, Master’s thesis, TUM.
86