Cell Design and Layout

Kenneth Yun UC San Diego

Adapted from EE271 notes, Stanford University Overview n Wires n FPGA n n Standard Cell n Datapath Cells n Cell Layout n Reading

n W&E 6.3-6.3.6, 5.3 Wires n Part of capacitive load

n Need to know the length to size (driver) gates

n Need to plan for it n Resistance

n Long wires have RC time constants n Special wires

n Power, ground, and clock

n Need to have low resistance Wire Properties

Layer Resistance Capacitance Connects to M2 Low Low M1 M1 Low Low diff,poly,M2 poly Medium Low gate,M1 ndiff Medium High S/D,M1 pdiff Medium High S/D,M1 Wire Characteristics

r L L Layer R• R•/Rtrans R = = Rsq t W W metal 0.1W 1/1.5x105 poly 5W 1/3000 L ndiff 5W 1/3000 W t pdiff 5W 1/3000 nMOS 15KW 1 pMOS 30KW 2 Wire Usage n Diffusion

n Bad wire (high capacitance)

n Only used to connect to n Poly

n Resistance high: good for short, local interconnects

n Do not use to route outside cells or as jumpers in long wires n Metal

n M1: only conductor that can connect to poly and diff

n M1,…,Mn-1 for general wiring n Mn for Vdd, Ground, and clock routing Cell Implementation Technologies n Field programmable gate arrays (FPGA)

n Chips prefabricated; program fuses/anti-fuses n Gate arrays (mask programmable)

n Transistors prefabricated; customize metal to generate cells n Standard cells

n All cells have fixed height

n Wiring may be restricted to channels n Macro cells

n Similar to standard cells but

n Wiring done over cells n Memory (2D array) FPGA n Logic is programmed into chip after fabrication n Programming done using

n Memory cells and CMOS switches

n Fuse/anti-fuse

n EPROM cells hold values for 10 years n Customizing wires

n To program connections, need switches

n Switches have R and C; slows down signals on wires n Completely prefabricated in large volume

n Cost effective for certain applications FPGA Wiring n Standard cell like wiring (with channels)

n Each channel has wires of different length

n How many of each length determined by design statistics

n Use logic blocks as repeaters when necessary

n Problem: switches in wires (high resistance) Gate Array n Transistors predefined

n W/L all the same (or choice limited)

n Transistors prefabricated

n Chip covered with transistors (sea of gates) n Designer provides metal patterns that form logic gates by connecting transistors

n Transistors under wiring channels not used. Why? n Cheaper and faster to manufacture than standard cells. Why? Gate Array Layout

Vdd A B Vdd

out

Gnd Gnd 2-input NAND Standard Cell

n Appropriate for all or part of a custom chip n All cells have the same height (with abutting power and ground) n Cells tiled into rows n Rows separated by routing channels

n Channel height variable

Cell Height (includes

Vdd, Gnd) Channel height Standard Cell Layout Example Macro Cell reg mux n Standard cell with wiring done inside cell

n 1D – datapath bit slice n 2D – memory n Wires kept short and regular

n Less wiring area

n Less wire load (drivers can be smaller) bit line

n Order cells to minimize wire lengths

control (word line) Datapath n Fixed height cells with bit pitch set to

n height of tallest cell

n accommodate the total number of over-the-cell wires per bit

n 128l a good choice

n Often, cells are mirrored (every other cell is

flipped vertically) to share Vdd and Gnd rails. Why? n Some cells take up multiple bit pitches

n E.g., 4-bit Manchester carry chain n Variable width

n Depends on functionality of cells Datapath (continued) n Wires over cells

n Bit lines for data

n Word lines for control, clock n Place cells to minimize number of horizontal tracks and wire lengths

FB FA FB FA

Registers Adder

Slice Plan

R R R R LA LB MX LB LA Add Requires 3 Tracks Basic Layout Guidelines n Do wire planning before cell layout

n Assign preferred direction to each layer

n Group p’s and n’s

n Determine input/output port locations

n Power, ground, and clock wires must be wide n Determine cell pitch

n Height of tallest cell

n Number of over-the-cell tracks and wire lengths n Use metal for wiring

n Use poly for intra-cell wiring only

n Use diffusion for connection to transistors only n Do stick diagram first! Basic Cell Layout Guidelines n P-N spacing is large, so keep pMOS together and nMOS together

n Mirror cells, if necessary. How does it help? n Vdd and ground distribution must be in wide metal

n Vdd runs near pMOS groups n Ground runs near nMOS groups n Layers in alternate directions

n M1 and M2 should run in (predominantly) orthogonal directions. Why? Layout

Good bad bad bad n Transistors should be at least as wide as contacts (4l) n Use as many contacts as possible for wider transistors n Don’t use 3l device except for weak devices Transistor Folding n Better aspect ratio for large transistors n Reduces diffusion area

8/2 8/2 8/2 8/2

16/2 16/2

32/2 32/2 16/2 16/2 8/2 8/2 8/2 8/2 Folding Series Gates n Fold the whole stack, not individual transistors Example: Standard Cell Latch n Static design n F’ generated internally n Feedback isolated from output

F in out Standard Cell Stick Diagram

Transistors share diffusion Local poly routing

Vdd

Room for M2 track over cell

Gnd clk in out Standard Cell Layout Datapath Cell Layout Options n Data/control

n Data bus in M1 and control in M2

n Data bus in M2 and control in M1 n Power/Ground

n in control direction (vertical)

n in data direction (horizontal) Stick Diagram (1) n Start with just wires

ST ST’ RD RD’

Vdd

DIN

DOUT

Gnd Stick Diagram (2) n Draw transistors connected to inputs and outputs ST ST’ RD RD’

Vdd

DIN

DOUT

Gnd Stick Diagram (3) n Draw remaining transistors

ST ST’ RD RD’

Vdd

DIN

DOUT

Gnd Power and Ground n Resistance of power supply line must be very small

n If too large, then the voltage supplied to gates will drop (why?), which may cause malfunction of gates

n So, power supply lines must be wide metal

n Rtrans >> Rmetal

n Not so easy since wires are long and transistors are large Power IR Drop n Example: for 100K gate chip

n Each gate drives 1mm wire (200fF) in 500ps

n I = C dV/dt = 200fF x 2.5V / 500ps = 1mA

n If all switch at once, 100A!

n Even if only 10% switch at once, still 10A peak current!

n Considerable IR drop!

n Need many supply pins, wide power supply wires

n Grids are good for low R Power Distribution n Distribute power on thickest metal

local buses

Gnd

Vdd