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Eindhoven University of Technology MASTER From RTL to layout using blast chip Postma, D. Award date: 2002 Link to publication Disclaimer This document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain T U/ e technische unh",,,,it.it eindhoven Faculty of Electrical Engineering Section Design Technology For Electronic Systems (ICStES) ICS-ES 802 Master's Thesis FROM RTL TO LAYOUT USING BLAST CHIP. D. Postma Supervisor: prof.dr.ir. P.R. Groeneveld Date: August 2002 The Faculty of Electrical Engineering of the Eindhoven University of Technology does not accept any responsibility regarding the contents of Master's Theses T U/ e technische universiteit eindhoven Faculty of Electrical Engineering Section Design Technology (ICS/ES) Master's Thesis From RTL to Layout using Blast Chip D. Postma (414407) Supervisor: prof. dr. ir. P. Groeneveld Date: August 2002 The faculty of Electrical Engineering of the Eindhoven University of Technology does not accept any responsibility regarding the contents of Master's Theses. Contents 1 Introduction 5 2 RTL to Layout 7 2.1 'Traditional Design Flow 7 2.2 Fixed Timing . 9 2.3 Logical Effort Methodology 10 2.4 Gain Based Synthesis flow . 11 2.5 Practical 'Training Assignments 12 2.5.1 Generating a Layout .. 12 2.5.2 Timing versus Area trade-off 14 2.5.3 Hierarchical Area Report 15 2.5.4 Example: FIR Filter 18 3 VLSI Power Analysis 21 3.1 Hot chips ..... 21 3.2 Power Consumption Model 21 3.2.1 Terms ....... 22 3.2.2 Switching Power . 22 3.3 Low Power Design Methodologies . 24 3.4 Power Analysis in Blast Chip 3.1 . 25 3.5 Standard Cell Library Experiments . 26 3.6 Importing Standard Cell library ... 28 3.7 Power Analysis Experiments. 28 3.7.1 Switching Activity of an Inverter 28 3.7.2 Supply-voltage Scaling of a 32-bit Multiplier 29 3.7.3 Power Consumption of an 1D-IDCT 31 4 Conclusions and recommendations 33 A From Idea to Chiplayout in 15 minutes 37 A.1 Introduction ...... 37 A.I.1 Requirements .. 37 A.I.2 Getting Started 38 A.2 Blast Chip Reports ... 40 A.3 Blast CHip 'Hello world' 40 3 4 CONTENTS B Magma TCL scripts 43 B.1 Main Flow: run.tel ......... 43 B.2 General Functions: procedures.tel .. 44 B.3 Hierarchical Area Report: hierarea.tcl 47 B.4 Import Standard Cell Library 49 C C++ source of a FIR filter 51 D Power Tests 53 D.I General Sources. 53 D.LI Verilog 53 D.L2 power.tel 53 D.L3 run.tel 53 D.2 Library Without Power Characteristics 53 D.2.1 Liberty Source ......... 53 D.2.2 Relevant lines of Magma Logfile 54 D.2.3 Results of Power Analysis .. 54 D.3 default_ceIUeakage_power Attribute 55 D.3.1 Liberty Source ..... 55 D.3.2 Results of Power Analysis 55 D.4 leakage_power_unit Attribute .. 55 D.4.1 Liberty Source ..... 55 D.4.2 Results of Power Analysis 56 D.5 celLleakage_power Attribute .. 56 D.5.1 Liberty Source ..... 56 D.5.2 Results of Power Analysis 56 D.6 leakage_power Group ..... 57 D.6.1 Liberty Source ..... 57 D.6.2 Results of Power Analysis 57 D.7 Derating Factors ........ 58 D.7.1 Liberty Source ..... 58 D.7.2 Results of Power Analysis 59 D.8 1D Lookup Table totaLoutput..neLcapacitance 60 D.8.1 Liberty Source ......... 60 D.8.2 Results of Power Analysis ... 61 D.9 ID Lookup Table inpuLtransition_time 61 D.9.1 Liberty Source ..... 61 D.9.2 Results of Power Analysis 62 E Switching Activity of an Invertor 63 E.I Verilog Source: design. v .... 63 E.2 Testbench: testbench.v ..... 63 E.3 Icarus Verilog batchfile: icarus.bat 64 E.4 Icarus Simulation result . 64 E.5 Library: simple. lib . 64 E.6 TCL script to import VCD: power.tel 65 Chapter 1 Introduction At the Eindhoven University of Technology, department of Electrical Engineer­ ing, section Information and Communication Systems (rCS), research chair De­ sign Automation (ES), students can perform a practical training VLSI Design. Until recently, the goal of the practical training was to show students the various steps of digital system ~, from algorithm specific level to Register Trans­ fer level. ARIT Designer of Adelante Technologies is the tool that is used to generate an RTL description. Input to ARIT Designer is an algorithm written in C++ and a chip architecture the algorithm should be mapped on. Students should be able to explore various design alternatives and evaluate them using criteria such as performance, area and power consumption. In order to be able to get better understanding of the consequences of choices made at high level and in order to obtain numerical estimates of the criteria mentioned above (speed, area and power), it is desirable to extend the practical training with the steps from RTL to layout (see Figure 1.1). Figure 1.1: Extended flow of practical training. This report discusses this extension of the practical training using the RTL to layout tool 'Blast Chip' of Magma Design Automation. Chapter 2 gives an introduction of the flow from RTL to layout. First, the traditional flow is sum­ marized and afterwards, the flow that Blast Chip uses is explained. Chapter 3 discusses power analysis of VLSI designs and the way this can be done using Blast Chip. At the end of both chapters, some possible related practical as­ signments for the students are given. The last chapter provides conclusions and recommendations. 5 Chapter 2 RTL to Layout 2.1 Traditional Design Flow Figure 2.1 shows a traditional VLSII design flow from RTL2 to physical layout. Starting with an RTL description, the design is synthesized into a gate level netlist using a standard cell library. After creating a floorplan by defining the locations of macro cells, memory blocks, bond cells, pads and main power wires, the logic gates are placed and routed. Figure 2.1: Traditional VLSI design flow from RTL to physical layout. The final step of the flow is checking the timing constraints; if timing con­ straints are not met, adjustments have to be made in previous steps, e.g. chang- 1 Very Large Scale Integration 2Register Transfer Level 7 8 CHAPTER 2. RTL TO LAYOUT ing some drive strengths of logic gates, restructuring logic of the worst timing path or even changing the RTL (e.g. pipelining). After these adjustments, the design needs to be placed, routed and checked for timing constraints again. Un­ fortunately, the adjustments to optimize the worst timing path often introduce new worst case timing paths, which might even be worse. Therefore, many slow iterations might be needed before all timing constraints are met. The main problem of this traditional flow is the fact that during synthesis, drive strengths for each logic gate are estimated using statistical (inaccurate) wire delay models. In early days of VLSI design, these inaccuracies were not a problem because path delay was mainly caused by the delay of individual gates. However, as feature sizes decrease, the timing problem moves more and more from a gate delay problem to a wire delay problem, as shown in Figure 2.2. Gate delay versus wire delay 45 40 Q -I-Gate Delay 35 -\ ~WJreDelay ..... 30 \\ ~ Sum of delays III 25 \~ .e:>- .!! 20 X"-. ,,~ a 15 ""~ 10 ~ :::::::---r ~J --r 5 ..,..- o o 100 200 300 400 500 Feature size (nm) Figure 2.2: As feature sizes decrease, the timing problem moves from a gate delay problem to a wire delay problem (source: [1]). The reason for this is the fact that wire delay does not scale down as well as gate delay when dimensions shrink. Reducing sizes leads to decreased wire height and width, which results in a larger wire resistance (slower). Although the increased delay due to increased resistance is cancelled out by the decreased wire capacitance to ground, increased wire density leads to smaller distances between neighboring wires, which results in larger coupling capacitances between wires. Furthermore, for power and electromigration reasons, the aspect ratio of wires is changed such that wires become taller than they are wide. This leads to even higher coupling capacitances. Thus, the RC delay of the wire does not scale down as much as gate delay. Another problem concerning wire delay is the fact that wire delay is quadratic with wire length. When using a simple RC wire delay model, this is shown by the following equation: 2.2. FIXED TIMING 9 Here, R is the wire resistance, C is the wire capacitance, L is the wire length and W is the wire width. Before placement and routing, wire lengths are unknown. Therefore, esti­ mating path delay in advance to determine optimal drive strengths of the logic gates becomes a very difficult task when a traditional RTL to layout flow is used.

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