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SolbourneComputer ~Solbourne Computer Series4 and Series5 Theory of Operations Solbourne Confidential· Do Not Reproduce Solboume Computer, Inc. 303-772-3400 1900 Pike Road Longmont, Colorado 80501 For Solbourne support call: 1-800-447-2861 SoIbourne, Series4, SeriesS, Virtual Desktop, Kbus, OSIMP, Object Interface Library (01), and the Solboume logo are trademarks of Solboume Computer, Inc. SPARC, SunOS, and Sun-4 are trademarks of Sun Microsystems. UNIX is a trademark of the AT&T Bell Laboratories. Zilog is a trademark of Zilog Corporation. Exabyte is a trademark of Exabyte Corporation. Ciprico is a trademark of Ciprico Corporation. Xylogics is a trademark of Xylogics Corporation. VMEbus is a trademark of VMEbus Manufacturers' Association. This document contains highly-sensitive confidential information that may only be viewed by employees of Solbourne Computer, Inc. DO NOT COPY OR DISTRIBUTE THIS MANUAL. Part Number: 101250-AB February 1990 Copyright © 1990 by Solboume Computer, Inc. All rights reserved. No part of this publication may be reproduced, stored in any media or in any type of retrieval system, transmitted in any form (e.g., electronic, mechanical, photocopying, recording) or translated into any language or computer language without the prior written permission of Solboume Computer, Inc., 1900 Pike Road, Longmont, Colorado 80501. There is no right to reverse engineer, decompile, or disassemble the information contained herein or in the accompanying software. Solboume Computer, Inc. reserves the right to revise this publication and to make changes from time to time without obligation to notify any person of such revisions or changes. Preface This manual covers the theory of operation of the Solbourne Series4 and SeriesS systems. Theory of operations deals with the function of the major hardware components of the Series4 and Series5 systems. The difference between Series4 and Series5 is the design and performance of the CPU Boards in each system; otherwise the systems are identical in hardware functions. The theory of operation of each of these CPU Boards is detailed in this document. The Series4 and 5 theory of operations applies to two implementations of each series-the Series4 and Series5/500 (or desktop) model and the Series4 or Series5/600 (or deskside) model. The. major difference between the desktop and deskside model is the inclusion of the VMEbus backplane in the deskside, an interface not provided in the desktop model. The material dealing with the VMEbus interface in the System Board section applies only to Series4 and Series5/600 systems. The System Board of the Series4 and Series5/500 is identical to that used in the Series4 and Series5/600, but the VMEbus connections are not used. Theory of operation covers the functional blocks on each board, how they interface to the larger system and what their inputs and outputs are. This manual is divided into nine sections, as follows: Section 1 - System Overview This section introduces each of the components that is described in this manual. Section 2 - Kbus Operation This section describes the Kbus, which is the main communication link among the components detailed in this manual. It provides the name and description of each bus signal. Section 3 - Series4 CPU Operation This section describes the Series4 CPU Board, giving diagrams and descriptions of major internal buses, functional blocks, and external interfaces. Section 4 - Series5 CPU Operation This section describes the Series5 CPU Board, giving diagrams and deSCriptions of major internal buses, functional blocks, and external interfaces. Section 5 - System Board Operation This section describes the System Board, giving diagrams and descriptions of major internal buses, functional blocks and external interfaces. The System Board is the communications hub for I/O in the system. Section 6 - 16 Mbyte Memory Board Operation This section describes the 16 Mbyte Memory Board, gIVIng diagrams and descriptions of major internal buses, functional blocks, and external interfaces. Section 7 - 32 Mbyte Memory Board Operation This section describes the 32 Mbyte Memory Board, gIvmg diagrams and descriptions of major internal buses, functional blocks, and external interfaces. Section 8 - CG 40 Color Board Operation This section describes the CG 40 Color Board, giving diagrams and deSCriptions of iii major internal buses, functional blocks, and external interfaces. The CG 40 was the original color frame buffer designed by Solbourne. Section 9 - CG 30 Color Board Operation This section describes the CG 30 Color Board, giving diagrams and descriptions of major internal buses, functional blocks, and external interfaces. The CG 30 provides a performance improvement over the CG 40. iv Table of Contents Section 1: System Overview ......................................................................................................................... 1-1 1.1 Introduction .................................................................................................................................... 1-1 1.1.2 Series4 and Series5 CPU Boards ......................................................................................... 1-1 1.1.3 Series4 and Series5 Implementations ................................................................................ 1-1 1.2 Major System Functions ............................................................................................................... 1-2 1.3 Kbus .................................................................................................................................................. 1-5 1.4 VMEbus ........................................................................................................................................... 1-5 1.S CPU Boards ..................................................................................................................................... 1-6 1.6 System Board .................................................................................................................................. 1-6 1.7 CG 30 Color Board ......................................................................................................................... 1-7 1.8 Memory Boards .............................................................................................................................. 1-8 1.9 Peripherals ....................................................................................................................................... 1-8 Section 2: Kbus Operation ............................................................................................................................. 2-1 2.1 Introduction .................................................................................................................................... 2-1 2.2 Kbus Organization ........................................................................................................................ 2-2 2.3 Bus Arbitration ............................................................................................................................... 2-5 2.4 Transactions .................................................................................................................................... 2-6 2.4.1 Cache Memory Transactions ............................................................................................... 2-6 2.4.2 RIO Transactions ................................................................................................................... 2-7 2.4.3 Other Transactions ................................................................................................................ 2-7 2.5 Cache Protocol ................................................................................................................................ 2-7 2.6 System Interrupts .......................................................................................................................... 2-8 Section 3: Series4 CPU Board Operation .................................................................................................... 3-1 3.1 Introduction .................................................................................................................................... 3-1 3.2 CPU Board Address, Data, and Control Buses ........................................................................ 3-2 3.3 CPU Section .................................................................................................................................... 3-8 3.3.1 CPU Subsection ...................................................................................................................... 3-9 3.3.2 MMU Subsection ................................................................................................................... 3-11 3.3.3 Cache Tag Subsection ........................................................................................................... 3-12 3.3.4 Cache Subsection ................................................................................................................... 3-13 3.4 Kbus Interface Section .................................................................................................................. 3-13 3.4.1 ROM Subsection ........................................................................ ;........................................... 3-14 3.4.2 Bus Launcher Subsection ............. ;......................................................................................
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