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Validated Products List, 1995 No. 3: Programming Languages, Database
NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 QC 100 NIST .056 NO. 5693 1995 NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 (Supersedes April 1995 issue) U.S. DEPARTMENT OF COMMERCE Ronald H. Brown, Secretary TECHNOLOGY ADMINISTRATION Mary L. Good, Under Secretary for Technology NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY Arati Prabhakar, Director FOREWORD The Validated Products List (VPL) identifies information technology products that have been tested for conformance to Federal Information Processing Standards (FIPS) in accordance with Computer Systems Laboratory (CSL) conformance testing procedures, and have a current validation certificate or registered test report. The VPL also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The VPL includes computer language processors for programming languages COBOL, Fortran, Ada, Pascal, C, M[UMPS], and database language SQL; computer graphic implementations for GKS, COM, PHIGS, and Raster Graphics; operating system implementations for POSIX; Open Systems Interconnection implementations; and computer security implementations for DES, MAC and Key Management. -
Overview of the SPEC Benchmarks
9 Overview of the SPEC Benchmarks Kaivalya M. Dixit IBM Corporation “The reputation of current benchmarketing claims regarding system performance is on par with the promises made by politicians during elections.” Standard Performance Evaluation Corporation (SPEC) was founded in October, 1988, by Apollo, Hewlett-Packard,MIPS Computer Systems and SUN Microsystems in cooperation with E. E. Times. SPEC is a nonprofit consortium of 22 major computer vendors whose common goals are “to provide the industry with a realistic yardstick to measure the performance of advanced computer systems” and to educate consumers about the performance of vendors’ products. SPEC creates, maintains, distributes, and endorses a standardized set of application-oriented programs to be used as benchmarks. 489 490 CHAPTER 9 Overview of the SPEC Benchmarks 9.1 Historical Perspective Traditional benchmarks have failed to characterize the system performance of modern computer systems. Some of those benchmarks measure component-level performance, and some of the measurements are routinely published as system performance. Historically, vendors have characterized the performances of their systems in a variety of confusing metrics. In part, the confusion is due to a lack of credible performance information, agreement, and leadership among competing vendors. Many vendors characterize system performance in millions of instructions per second (MIPS) and millions of floating-point operations per second (MFLOPS). All instructions, however, are not equal. Since CISC machine instructions usually accomplish a lot more than those of RISC machines, comparing the instructions of a CISC machine and a RISC machine is similar to comparing Latin and Greek. 9.1.1 Simple CPU Benchmarks Truth in benchmarking is an oxymoron because vendors use benchmarks for marketing purposes. -
SPARC64-III User's Guide
SPARC64-III User’s Guide HAL Computer Systems, Inc. Campbell, California May 1998 Copyright © 1998 HAL Computer Systems, Inc. All rights reserved. This product and related documentation are protected by copyright and distributed under licenses restricting their use, copying, distribution, and decompilation. No part of this product or related documentation may be reproduced in any form by any means without prior written authorization of HAL Computer Systems, Inc., and its licensors, if any. Portions of this product may be derived from the UNIX and Berkeley 4.3 BSD Systems, licensed from UNIX System Laboratories, Inc., a wholly owned subsidiary of Novell, Inc., and the University of California, respectively. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii), FAR 52.227-19, and NASA FAR Supplement. The product described in this book may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS HAL, the HAL logo, HyperScalar, and OLIAS are registered trademarks and HAL Computer Systems, Inc. HALstation 300, and Ishmail are trademarks of HAL Computer Systems, Inc. SPARC64 and SPARC64/OS are trademarks of SPARC International, Inc., licensed by SPARC International, Inc., to HAL Computer Systems, Inc. Fujitsu and the Fujitsu logo are trademarks of Fujitsu Limited. All SPARC trademarks, including the SCD Compliant Logo, are trademarks or registered trademarks of SPARC International, Inc. SPARCstation, SPARCserver, SPARCengine, SPARCstorage, SPARCware, SPARCcenter, SPARCclassic, SPARCcluster, SPARCdesign, SPARC811 SPARCprinter, UltraSPARC, microSPARC, SPARCworks, and SPARCompiler are licensed exclusively to Sun Microsystems, Inc. -
The Conference Program Booklet
Austin Convention Center Conference Austin, TX Program http://sc15.supercomputing.org/ Conference Dates: Exhibition Dates: The International Conference for High Performance Nov. 15 - 20, 2015 Nov. 16 - 19, 2015 Computing, Networking, Storage and Analysis Sponsors: SC15.supercomputing.org SC15 • Austin, Texas The International Conference for High Performance Computing, Networking, Storage and Analysis Sponsors: 3 Table of Contents Welcome from the Chair ................................. 4 Papers ............................................................... 68 General Information ........................................ 5 Posters Research Posters……………………………………..88 Registration and Conference Store Hours ....... 5 ACM Student Research Competition ........ 114 Exhibit Hall Hours ............................................. 5 Posters SC15 Information Booth/Hours ....................... 5 Scientific Visualization/ .................................... 120 Data Analytics Showcase SC16 Preview Booth/Hours ............................. 5 Student Programs Social Events ..................................................... 5 Experiencing HPC for Undergraduates ...... 122 Registration Pass Access .................................. 7 Mentor-Protégé Program .......................... 123 Student Cluster Competition Kickoff ......... 123 SCinet ............................................................... 8 Student-Postdoc Job & ............................. 123 Convention Center Maps ................................. 12 Opportunity Fair Daily Schedules -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Energy-Effective Issue Logic
Energy-Effective Issue Logic Daniele Folegnani and Antonio GonzaJez Departament d'Arquitectura de Computadors Universitat Politecnica de Catalunya Jordi Girona, 1-3 Mbdul D6 08034 Barcelona, Spain [email protected] Abstract require an increasing computing power, which sometimes is achieved through higher clock frequencies and more sophisticated Tile issue logic of a dynamically-scheduled superscalar processor architectural techniques, with an obvious impact on power is a complex mechanism devoted to start the execution of multiple consumption. instructions eveo' cycle. Due to its complexity, it is responsible for a significant percentage of the energy consumed by a With the fast increase in design complexity and reduction in microprocessor. The energy consumption of the issue logic design time, new generation CAD tools for VLSI design like depends on several architectural parameters, the instruction issue PowerMill [13] and QuickPower [12] are crucial to evaluate the queue size being one of the most important. In this paper we energy consumption at different points of the design, helping to present a technique to reduce the energy consumption of the issue make important decisions early in the design process. The logic of a high-performance superscalar processor. The proposed importance of a continuous feedback between the functional technique is based on the observation that the conventional issue system description and the power impact requires better and faster logic wastes a significant amount of energy for useless activio,. In evaluation tools and models to introduce changes rapidly through particular, the wake-up of empty entries and operands that are various design scenarios. Recent research has shown how read)' represents an important source of energy waste. -
Solaris X Window System Reference Manual
Solaris X Window System Reference Manual Sun Microsystems, Inc. 2550 Garcia Avenue Mountain View, CA 94043 U.S.A. 1995 Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, California 94043-1100 USA. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX system, licensed from UNIX System Laboratories, Inc., a wholly owned subsidiary of Novell, Inc., and from the Berkeley 4.3 BSD system, licensed from the University of California. Third- party software, including font technology in this product, is protected by copyright and licensed from Sun's Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, SunSoft, the SunSoft logo, Solaris, SunOS, OpenWindows, DeskSet, ONC, ONC+, and NFS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. OPEN LOOK is a registered trademark of Novell, Inc. -
Openwindows Reference Manual
OpenWindows Reference Manual Sun Microsystems, Inc. 2550 Garcia Avenue Mountain View, CA 94043 U.S.A. 1994 Sun Microsystems, Inc. All rights reserved. 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A. This product and related documentation are protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or related documentation may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX and Berkeley 4.3 BSD systems, licensed from UNIX Systems Laboratories, Inc., a wholly owned subsidiary of Novell, Inc., and the University of California, respectively. Third-party software, including font technology, in this product is protected by copyright and licensed from Sun's Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. This product or the products described herein may be protected by one or more U.S., foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun Logo, SunSoft, Sun Microsystems Computer Corporation and Solaris, are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and certain other countries. UNIX is a registered trademark of Novell, Inc., in the United States and other countries; X/Open Company, Ltd., is the exclusive licensor of such trademark. OPEN LOOK is a registered trademark of Novell, Inc. -
Japanese Semiconductor Industry Service
Japanese Semiconductor Industry Service Volume II Technology & Government Dataquest nn a company of The Dun & Bradstreet Corporation 1290 Ridder Park Drive San Jose, California 95131-2398 (408) 437-8000 Telex: 171973 Fax: (408) 437-0292 Sales/Service offices: UNITED KINGDOM GERMANY Dataquest UK Limited Dataquest GmbH 13th Floor, Centrepoint Rosenkavalierplatz 17 103 New Oxford Street D-8000 Munich 81 London WCIA IDD West Germany England (089)91 10 64 01-379-6257 Telex: 5218070 Telex: 266195 Fax: (089)91 21 89 Fax: 01-240-3653 FRANCE JAPAN Dataquest SARL Dataquest Japan, Ltd. 100, avenue Charles de Gaulle Taiyo Ginza Building/2nd Floor 92200 Neuilly-sur-Seine 7-14-16 Ginza, Chuo-ku France Tokyo 104 Japan (01)4738.13.12 (03)546-3191 Telex: 611982 Telex: 32768 Fax: (01)4738.11.23 Fax: (03)546-3198 The content of this report represents our interpretation and analysis of information generally available to the public or released by responsible individuals in the subject com panies, but is not guaranteed as to accuracy or completeness. It does not contain material provided to us in confidence by our clients. This information is not furnished in connection with a sale or offer to sell securities, or in connection with the solicitation of an offer to buy securities. This firm and its par ent and/or their officers, stockholders, or members of their families may, from time to time, have a long or short position in the securities mentioned and may sell or buy such securities. Printed in the United States of America. All rights reserved. -
Data Locality Optimizations for Multigrid Methods on Structured Grids
Data Locality Optimizations for Multigrid Methods on Structured Grids Christian Weiß Technische Universitat¨ Munchen¨ Institut fur¨ Informatik Lehrstuhl fur¨ Rechnertechnik und Rechnerorganisation Data Locality Optimizations for Multigrid Methods on Structured Grids Christian Weiß Vollst¨andiger Abdruck der von der Fakult¨at f¨ur Informatik der Technischen Universit¨at M¨unchen zur Erlangung des akademischen Grades eines Doktors der Naturwissenschaften (Dr. rer. nat.) genehmigten Dissertation. Vorsitzender: Univ.-Prof. Dr. Hans Michael Gerndt Pr¨ufer der Dissertation: 1. Univ.-Prof. Dr. Arndt Bode 2. Univ.-Prof. Dr. Ulrich R¨ude Friedrich-Alexander-Universit¨at Erlangen-N¨urnberg 3. Univ.-Prof. (komm.) Dr.-Ing. Eike Jessen, em. Die Dissertation wurde am 26. September 2001 bei der Technischen Universit¨at M¨unchen eingereicht und durch die Fakult¨at f¨ur Informatik am 06. Dezember 2001 angenommen. Abstract Beside traditional direct solvers iterative methods offer an efficient alternative for the solution of systems of linear equations which arise in the solution of partial differen- tial equations (PDEs). Among them, multigrid algorithms belong to the most efficient methods based on the number of operations required to achieve a good approximation of the solution. The relevance of the number of arithmetic operations performed by an application as a metric for the complexity of an algorithm wanes since the performance of modern computing systems nowadays is limited by memory latency and bandwidth. Consequently, almost all computer manufacturers nowadays equip their computers with cache–based hierarchical memory systems. Thus, the efficiency of multigrid methods is rather determined by good data locality, i.e. good utilization of data caches, than by the number of arithmetic operations. -
The Spare ™ Architecture Manual Version 7
The SPARe™ Architecture Manual Version 7 SOLBOURNE COMPUTER, Inc. 2190 Miller Drive Longmont, Colorado 80501 303 772·3400 For Solboume Support Call: 1·800-447·2861 The X Window System is a trademark of MIT. Sun Mlcrosystems and Sun Workstation are registered trademarks of Sun Microsystems, Inc. Sun-3, Sun-4, SPARe, and DVMA are trademarks of Sun Microsystems, Inc. Part Number: 101482-00 September 1988 Reprinted by permission. Copyright 1988 by Solbourne Computer, Inc. All rights reserved. No part of this publication may be reproduced, stored in any media or in any type of retrieval system, transmitted in any form (e.g., electronic, mechanical, photocopying, recording) or translated into any language or computer language without the prior written permission of Solbourne Computer, Inc., 2190 Miller Drive, Longmont, Colorado 80501. There is no right to reverse engineer, decompile, or disassemble the information contained herein or in the accompanying software. Solbourne Computer, Inc. reserves the right to revise this publication and to make changes from time to time without obligation to notify any person of such reviSions or changes. TABLE OF CONTENTS SECTION 1: INTRODUCTION •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1-1 1.1 Introduction 1-1 1.2 Architecture and Implementation ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1-1 1.3 Features •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1-1 1.4 Using This Manual ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• -
Full Program
The International Conference for High Performance Computing, Networking, Storage and Analysis Conference Program http://sc16.supercomputing.org/ Salt Lake City Convention Center Salt Lake City, Utah Conference: November 13-18, 2016 Exhibition: November 14-17, 2016 Sponsors: SC16.supercomputing.org SC16 • Salt Lake City, Utah The International Conference for High Performance Computing, Networking, Storage and Analysis The International Conference for High Performance Computing, Networking, Storage and Analysis Sponsors: Sponsors 3 Table of Contents Welcome from the Chair ................................. 2 Panels ............................................................... 69 General Information ........................................ 4 Papers ............................................................... 73 Registration and Conference Store Hours ....... 4 Posters Posters ....................................................... 98 Exhibit Hall Hours ............................................. 4 Research Posters……………………………………..105 SC16 Information Booth/Hours ....................... 4 ACM Student Research Competition SC17 Preview Booth/Hours ............................. 4 Scientific Visualization/ Data Analytics Showcase ................................. 135 Social Events ..................................................... 5 Student Programs ............................................ 136 Registration Pass Access .................................. 7 Experiencing HPC for Undergraduates ...... 137 SCinet ..............................................................